ST7038

ST
Sitronix
ST7038
Dot Matrix LCD Controller/Driver
FEATURES
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5 x 8 dot matrix possible
Support low voltage single power operation:
Ø
VDD, VDD2: 1.8 to 3.3V (typical)
LCD Voltage Operation Range (V0/Vout)
Ø
Programmable V0: 3 to 7V(V0)
Ø
External power applied: Max. 12V(Vout)
Interface
Ø
6800-4bit / 8bit interface
Ø
8080-4bit / 8bit interface
Ø
3-line serial interface
Ø
4-line serial interface
2
Ø
I C interface
Support display mode:
Ø
8-COM x 100-SEG and 80 ICON
Ø
16-COM x 100-SEG and 80 ICON
Ø
24-COM x 80-SEG and 80 ICON
10,240-bit Character Generator ROM
(CGROM) stores 256 character fonts
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64 x 8-bit Character Generator RAM
(CGRAM)
80 x 8-bit Display RAM (80 characters max.)
16 x 5 bit ICON RAM
Variable instruction functions:
clear display, return home, display ON/OFF,
cursor ON/OFF, character blink, cursor shift,
display shift, double height font, ICON control
and character generation RAM
Reset circuit through an external reset pin
Internal oscillator or external clock
Built-in low power consumption voltage
booster, regulator and follower circuit
Built-in high-accuracy voltage regulator:
Ø
Programmable output range: 3~7V
COM/SEG direction selectable by instruction
Selectable CGRAM/CGROM size
Package Type: COG
GENERAL DESCRIPTION
ST7038 dot-matrix liquid crystal display controller can
display alphanumeric, Japanese kana characters and
symbols. It can be configured to drive a dot-matrix liquid
crystal display under the control of a microprocessor with
2
4/8-bit 6800-series or 8080-series, 3/4-line serial or fast I C
interface. Since all the functions (such as display RAM,
character generator ROM/RAM and liquid crystal driver)
required for driving a dot-matrix liquid crystal display are
internally embedded in this chip, a minimal system can be
used with this controller/driver.
ST7038 is suitable for low voltage supply (1.8V to 3.3V) and
is perfectly suitable for any portable product which is driven
by the battery and requires low power consumption.
The display resolution of ST7038 dot-matrix LCD driver can
be either 1-line x 20 characters, 2-line x 20 characters or
3-line x 16 characters with 80-bit ICON.
ST7038 works alone without extra cascaded drivers.
The Character Generator ROM of ST7038 has 256 5x8dot
cells and stores 256 different character fonts (5x8dot).
Product Name
Character generator ROM Size
Support Character
ST7038-0B
256
English / Europe / Japan
Ver 1.1
ST7038
6800-4bit / 8bit interface
8080-4bit / 8bit interface
3-line/4-line serial interface
(without I2C interface)
ST7038i
I2C interface
1/61
2007/01/25
ST7038
PAD ARRANGEMENT
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Chip Size:
Bump Pitch:
I/O PAD:
COM/SEG PAD:
Bump size:
PAD No. 001 ~ 057:
PAD No. 058 ~ 175:
Bump Height:
Chip Thickness:
Ver 1.1
5476.2um X 906.2 um
73um
45um
55um X 60um
30um X 80um
17um
480um
2/61
2007/01/25
ST7038
PAD CENTER COORDINATES
PAD No.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
Ver 1.1
PIN Name
XRESET
OSC
VDD
A0(RS)
CSB
/WR(RW)
/RD(E)
DB[0]
DB[1]
DB[2]
DB[3]
DB[4]
DB[5]
DB[6]
DB[7]
VSS
VSS
VSS
VSS
PS0
PS1
PS2
CLS
TEST[0]
TEST[1]
TEST[2]
TEST[3]
TEST[4]
TEST[5]
VDD
VDD
VDD
VDD2
VDD2
VDD2
VOUT
VOUT
VOUT
CAP3P
CAP3P
CAP1P
CAP1P
CAP1N
CAP1N
CAP1N
CAP2P
CAP2P
CAP2N
CAP2N
CAP4P
CAP4P
VRS
V0
V1
X
2543.915
2424.915
2350.675
2276.575
2157.575
2084.575
1965.575
1892.575
1773.575
1700.575
1581.575
1508.575
1389.575
1316.575
1197.575
1124.575
1051.575
978.575
905.575
830.945
711.945
638.945
519.945
447.945
298.945
223.945
48.945
-26.055
-201.055
-276.94
-349.94
-422.94
-495.94
-568.94
-641.94
-714.94
-787.94
-860.94
-933.94
-1006.94
-1079.94
-1152.94
-1225.94
-1298.94
-1371.94
-1444.94
-1517.94
-1590.94
-1663.94
-1736.71
-1809.94
-1892.1
-1965.26
-2053.56
(3-line & 2-line with double height)
Y
379
379
379
379
379
379
379
379
379
379
379
379
379
379
379
379
379
379
379
379
379
379
379
379
379
379
379
379
379
379
379
379
379
379
379
379
379
379
379
379
379
379
379
379
379
379
379
379
379
379
379
379
379
379
PAD No.
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
3/61
PIN Name
V2
V3
V4
COM[12]
COM[11]
COM[10]
COM[9]
COM[8]
COM[7]
COM[6]
COM[5]
NC
COM[4]
COM[3]
COM[2]
COM[1]
NC
NC
NC
NC
NC
NC
SEG[1]
SEG[2]
SEG[3]
SEG[4]
SEG[5]
SEG[6]
SEG[7]
SEG[8]
SEG[9]
SEG[10]
SEG[11]
SEG[12]
SEG[13]
SEG[14]
SEG[15]
SEG[16]
SEG[17]
SEG[18]
SEG[19]
SEG[20]
SEG[21]
SEG[22]
SEG[23]
SEG[24]
SEG[25]
SEG[26]
SEG[27]
SEG[28]
SEG[29]
SEG[30]
SEG[31]
SEG[32]
X
-2126.56
-2199.56
-2272.56
-2611.93
-2566.93
-2521.93
-2476.93
-2431.93
-2386.93
-2341.93
-2296.93
-2251.93
-2206.93
-2161.93
-2116.93
-2071.93
-2026.93
-1981.93
-1936.93
-1891.93
-1846.93
-1801.93
-1756.93
-1711.93
-1666.93
-1621.93
-1576.93
-1531.93
-1486.93
-1441.93
-1396.93
-1351.93
-1306.93
-1261.93
-1216.93
-1171.93
-1126.93
-1081.93
-1036.93
-991.93
-946.93
-901.93
-856.93
-811.93
-766.93
-721.93
-676.93
-631.93
-586.93
-541.93
-496.93
-451.93
-406.93
-361.93
Unit: um
Y
379
379
379
-369
-369
-369
-369
-369
-369
-369
-369
-369
-369
-369
-369
-369
-369
-369
-369
-369
-369
-369
-369
-369
-369
-369
-369
-369
-369
-369
-369
-369
-369
-369
-369
-369
-369
-369
-369
-369
-369
-369
-369
-369
-369
-369
-369
-369
-369
-369
-369
-369
-369
-369
2007/01/25
ST7038
PAD No.
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
Ver 1.1
PIN Name
SEG[33]
SEG[34]
SEG[35]
SEG[36]
SEG[37]
SEG[38]
SEG[39]
SEG[40]
SEG[41]
SEG[42]
SEG[43]
SEG[44]
SEG[45]
SEG[46]
SEG[47]
SEG[48]
SEG[49]
SEG[50]
SEG[51]
SEG[52]
SEG[53]
SEG[54]
SEG[55]
SEG[56]
SEG[57]
SEG[58]
SEG[59]
SEG[60]
SEG[61]
SEG[62]
SEG[63]
SEG[64]
SEG[65]
SEG[66]
SEG[67]
SEG[68]
SEG[69]
SEG[70]
SEG[71]
SEG[72]
SEG[73]
SEG[74]
SEG[75]
SEG[76]
SEG[77]
SEG[78]
SEG[79]
SEG[80]
NC
NC
NC
NC
NC
NC
COM[13]
X
-316.93
-271.93
-226.93
-181.93
-136.93
-91.93
-46.93
-1.93
43.07
88.07
133.07
178.07
223.07
268.07
313.07
358.07
403.07
448.07
493.07
538.07
583.07
628.07
673.07
718.07
763.07
808.07
853.07
898.07
943.07
988.07
1033.07
1078.07
1123.07
1168.07
1213.07
1258.07
1303.07
1348.07
1393.07
1438.07
1483.07
1528.07
1573.07
1618.07
1663.07
1708.07
1753.07
1798.07
1843.07
1888.07
1933.07
1978.07
2023.07
2068.07
2113.07
Y
-369
-369
-369
-369
-369
-369
-369
-369
-369
-369
-369
-369
-369
-369
-369
-369
-369
-369
-369
-369
-369
-369
-369
-369
-369
-369
-369
-369
-369
-369
-369
-369
-369
-369
-369
-369
-369
-369
-369
-369
-369
-369
-369
-369
-369
-369
-369
-369
-369
-369
-369
-369
-369
-369
-369
PAD No.
164
165
166
167
168
169
170
171
172
173
174
175
4/61
PIN Name
COM[14]
COM[15]
COM[16]
COM[17]
COM[18]
COM[19]
COM[20]
COM[21]
COM[22]
COM[23]
COM[24]
COMI2
X
2158.07
2203.07
2248.07
2293.07
2338.07
2383.07
2428.07
2473.07
2518.07
2563.07
2608.07
2653.07
Y
-369
-369
-369
-369
-369
-369
-369
-369
-369
-369
-369
-369
2007/01/25
ST7038
PAD CENTER COORDINATES
PAD No.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
Ver 1.1
PIN Name
XRESET
OSC
VDD
A0(RS)
CSB
/WR(RW)
/RD(E)
DB[0]
DB[1]
DB[2]
DB[3]
DB[4]
DB[5]
DB[6]
DB[7]
VSS
VSS
VSS
VSS
PS0
PS1
PS2
CLS
TEST[0]
TEST[1]
TEST[2]
TEST[3]
TEST[4]
TEST[5]
VDD
VDD
VDD
VDD2
VDD2
VDD2
VOUT
VOUT
VOUT
CPA3P
CAP3P
CAP1P
CAP1P
CAP1N
CAP1N
CAP1N
CAP2P
CAP2P
CAP2N
CAP2N
CAP4P
CAP4P
VRS
V0
V1
X
2543.915
2424.915
2350.675
2276.575
2157.575
2084.575
1965.575
1892.575
1773.575
1700.575
1581.575
1508.575
1389.575
1316.575
1197.575
1124.575
1051.575
978.575
905.575
830.945
711.945
638.945
519.945
447.945
298.945
223.945
48.945
-26.055
-201.055
-276.94
-349.94
-422.94
-495.94
-568.94
-641.94
-714.94
-787.94
-860.94
-933.94
-1006.94
-1079.94
-1152.94
-1225.94
-1298.94
-1371.94
-1444.94
-1517.94
-1590.94
-1663.94
-1736.71
-1809.94
-1892.1
-1965.26
-2053.56
(2-line & 1-line with double height)
Y
379
379
379
379
379
379
379
379
379
379
379
379
379
379
379
379
379
379
379
379
379
379
379
379
379
379
379
379
379
379
379
379
379
379
379
379
379
379
379
379
379
379
379
379
379
379
379
379
379
379
379
379
379
379
PAD No.
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
5/61
PIN Name
V2
V3
V4
COM[8]
COM[7]
COM[6]
COM[5]
COM[4]
COM[3]
COM[2]
COM[1]
COMI1
SEG[1]
SEG[2]
SEG[3]
SEG[4]
SEG[5]
SEG[6]
SEG[7]
SEG[8]
SEG[9]
SEG[10]
SEG[11]
SEG[12]
SEG[13]
SEG[14]
SEG[15]
SEG[16]
SEG[17]
SEG[18]
SEG[19]
SEG[20]
SEG[21]
SEG[22]
SEG[23]
SEG[24]
SEG[25]
SEG[26]
SEG[27]
SEG[28]
SEG[29]
SEG[30]
SEG[31]
SEG[32]
SEG[33]
SEG[34]
SEG[35]
SEG[36]
SEG[37]
SEG[38]
SEG[39]
SEG[40]
SEG[41]
SEG[42]
X
-2126.56
-2199.56
-2272.56
-2611.93
-2566.93
-2521.93
-2476.93
-2431.93
-2386.93
-2341.93
-2296.93
-2251.93
-2206.93
-2161.93
-2116.93
-2071.93
-2026.93
-1981.93
-1936.93
-1891.93
-1846.93
-1801.93
-1756.93
-1711.93
-1666.93
-1621.93
-1576.93
-1531.93
-1486.93
-1441.93
-1396.93
-1351.93
-1306.93
-1261.93
-1216.93
-1171.93
-1126.93
-1081.93
-1036.93
-991.93
-946.93
-901.93
-856.93
-811.93
-766.93
-721.93
-676.93
-631.93
-586.93
-541.93
-496.93
-451.93
-406.93
-361.93
Unit: um
Y
379
379
379
-369
-369
-369
-369
-369
-369
-369
-369
-369
-369
-369
-369
-369
-369
-369
-369
-369
-369
-369
-369
-369
-369
-369
-369
-369
-369
-369
-369
-369
-369
-369
-369
-369
-369
-369
-369
-369
-369
-369
-369
-369
-369
-369
-369
-369
-369
-369
-369
-369
-369
-369
2007/01/25
ST7038
PAD No.
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
Ver 1.1
PIN Name
SEG[43]
SEG[44]
SEG[45]
SEG[46]
SEG[47]
SEG[48]
SEG[49]
SEG[50]
SEG[51]
SEG[52]
SEG[53]
SEG[54]
SEG[55]
SEG[56]
SEG[57]
SEG[58]
SEG[59]
SEG[60]
SEG[61]
SEG[62]
SEG[63]
SEG[64]
SEG[65]
SEG[66]
SEG[67]
SEG[68]
SEG[69]
SEG[70]
SEG[71]
SEG[72]
SEG[73]
SEG[74]
SEG[75]
SEG[76]
SEG[77]
SEG[78]
SEG[79]
SEG[80]
SEG[81]
SEG[82]
SEG[83]
SEG[84]
SEG[85]
SEG[86]
SEG[87]
SEG[88]
SEG[89]
SEG[90]
SEG[91]
SEG[92]
SEG[93]
SEG[94]
SEG[95]
SEG[96]
SEG[97]
X
-316.93
-271.93
-226.93
-181.93
-136.93
-91.93
-46.93
-1.93
43.07
88.07
133.07
178.07
223.07
268.07
313.07
358.07
403.07
448.07
493.07
538.07
583.07
628.07
673.07
718.07
763.07
808.07
853.07
898.07
943.07
988.07
1033.07
1078.07
1123.07
1168.07
1213.07
1258.07
1303.07
1348.07
1393.07
1438.07
1483.07
1528.07
1573.07
1618.07
1663.07
1708.07
1753.07
1798.07
1843.07
1888.07
1933.07
1978.07
2023.07
2068.07
2113.07
Y
-369
-369
-369
-369
-369
-369
-369
-369
-369
-369
-369
-369
-369
-369
-369
-369
-369
-369
-369
-369
-369
-369
-369
-369
-369
-369
-369
-369
-369
-369
-369
-369
-369
-369
-369
-369
-369
-369
-369
-369
-369
-369
-369
-369
-369
-369
-369
-369
-369
-369
-369
-369
-369
-369
-369
PAD No.
164
165
166
167
168
169
170
171
172
173
174
175
6/61
PIN Name
SEG[98]
SEG[99]
SEG[100]
COM[9]
COM[10]
COM[11]
COM[12]
COM[13]
COM[14]
COM[15]
COM[16]
COMI2
X
2158.07
2203.07
2248.07
2293.07
2338.07
2383.07
2428.07
2473.07
2518.07
2563.07
2608.07
2653.07
Y
-369
-369
-369
-369
-369
-369
-369
-369
-369
-369
-369
-369
2007/01/25
ST7038
PAD CENTER COORDINATES
PAD No.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
Ver 1.1
PIN Name
XRESET
OSC
VDD
A0(RS)
CSB
/WR(RW)
/RD(E)
DB[0]
DB[1]
DB[2]
DB[3]
DB[4]
DB[5]
DB[6]
DB[7]
VSS
VSS
VSS
VSS
PS0
PS1
PS2
CLS
TEST[0]
TEST[1]
TEST[2]
TEST[3]
TEST[4]
TEST[5]
VDD
VDD
VDD
VDD2
VDD2
VDD2
VOUT
VOUT
VOUT
CAP3P
CAP3P
CAP1P
CAP1P
CAP1N
CAP1N
CAP1N
CAP2P
CAP2P
CAP2N
CAP2N
CAP4P
CAP4P
VRS
V0
V1
X
2543.915
2424.915
2350.675
2276.575
2157.575
2084.575
1965.575
1892.575
1773.575
1700.575
1581.575
1508.575
1389.575
1316.575
1197.575
1124.575
1051.575
978.575
905.575
830.945
711.945
638.945
519.945
447.945
298.945
223.945
48.945
-26.055
-201.055
-276.94
-349.94
-422.94
-495.94
-568.94
-641.94
-714.94
-787.94
-860.94
-933.94
-1006.94
-1079.94
-1152.94
-1225.94
-1298.94
-1371.94
-1444.94
-1517.94
-1590.94
-1663.94
-1736.71
-1809.94
-1892.1
-1965.26
-2053.56
(1-line, SHLC=“H”)
Y
379
379
379
379
379
379
379
379
379
379
379
379
379
379
379
379
379
379
379
379
379
379
379
379
379
379
379
379
379
379
379
379
379
379
379
379
379
379
379
379
379
379
379
379
379
379
379
379
379
379
379
379
379
379
PAD No.
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
7/61
Unit: um
PIN Name
V2
V3
V4
COM[8]
COM[7]
COM[6]
COM[5]
COM[4]
COM[3]
COM[2]
COM[1]
COMI1
SEG[1]
SEG[2]
SEG[3]
SEG[4]
SEG[5]
SEG[6]
SEG[7]
SEG[8]
SEG[9]
SEG[10]
SEG[11]
SEG[12]
SEG[13]
SEG[14]
SEG[15]
SEG[16]
SEG[17]
SEG[18]
SEG[19]
SEG[20]
SEG[21]
SEG[22]
SEG[23]
SEG[24]
SEG[25]
SEG[26]
SEG[27]
SEG[28]
SEG[29]
SEG[30]
SEG[31]
SEG[32]
SEG[33]
SEG[34]
SEG[35]
SEG[36]
SEG[37]
SEG[38]
SEG[39]
SEG[40]
SEG[41]
SEG[42]
X
-2126.56
-2199.56
-2272.56
-2611.93
-2566.93
-2521.93
-2476.93
-2431.93
-2386.93
-2341.93
-2296.93
-2251.93
-2206.93
-2161.93
-2116.93
-2071.93
-2026.93
-1981.93
-1936.93
-1891.93
-1846.93
-1801.93
-1756.93
-1711.93
-1666.93
-1621.93
-1576.93
-1531.93
-1486.93
-1441.93
-1396.93
-1351.93
-1306.93
-1261.93
-1216.93
-1171.93
-1126.93
-1081.93
-1036.93
-991.93
-946.93
-901.93
-856.93
-811.93
-766.93
-721.93
-676.93
-631.93
-586.93
-541.93
-496.93
-451.93
-406.93
-361.93
Y
379
379
379
-369
-369
-369
-369
-369
-369
-369
-369
-369
-369
-369
-369
-369
-369
-369
-369
-369
-369
-369
-369
-369
-369
-369
-369
-369
-369
-369
-369
-369
-369
-369
-369
-369
-369
-369
-369
-369
-369
-369
-369
-369
-369
-369
-369
-369
-369
-369
-369
-369
-369
-369
2007/01/25
ST7038
PAD No.
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
Ver 1.1
PIN Name
SEG[43]
SEG[44]
SEG[45]
SEG[46]
SEG[47]
SEG[48]
SEG[49]
SEG[50]
SEG[51]
SEG[52]
SEG[53]
SEG[54]
SEG[55]
SEG[56]
SEG[57]
SEG[58]
SEG[59]
SEG[60]
SEG[61]
SEG[62]
SEG[63]
SEG[64]
SEG[65]
SEG[66]
SEG[67]
SEG[68]
SEG[69]
SEG[70]
SEG[71]
SEG[72]
SEG[73]
SEG[74]
SEG[75]
SEG[76]
SEG[77]
SEG[78]
SEG[79]
SEG[80]
SEG[81]
SEG[82]
SEG[83]
SEG[84]
SEG[85]
SEG[86]
SEG[87]
SEG[88]
SEG[89]
SEG[90]
SEG[91]
SEG[92]
SEG[93]
SEG[94]
SEG[95]
SEG[96]
SEG[97]
X
-316.93
-271.93
-226.93
-181.93
-136.93
-91.93
-46.93
-1.93
43.07
88.07
133.07
178.07
223.07
268.07
313.07
358.07
403.07
448.07
493.07
538.07
583.07
628.07
673.07
718.07
763.07
808.07
853.07
898.07
943.07
988.07
1033.07
1078.07
1123.07
1168.07
1213.07
1258.07
1303.07
1348.07
1393.07
1438.07
1483.07
1528.07
1573.07
1618.07
1663.07
1708.07
1753.07
1798.07
1843.07
1888.07
1933.07
1978.07
2023.07
2068.07
2113.07
Y
-369
-369
-369
-369
-369
-369
-369
-369
-369
-369
-369
-369
-369
-369
-369
-369
-369
-369
-369
-369
-369
-369
-369
-369
-369
-369
-369
-369
-369
-369
-369
-369
-369
-369
-369
-369
-369
-369
-369
-369
-369
-369
-369
-369
-369
-369
-369
-369
-369
-369
-369
-369
-369
-369
-369
PAD No.
164
165
166
167
168
169
170
171
172
173
174
175
8/61
PIN Name
SEG[98]
SEG[99]
SEG[100]
NC
NC
NC
NC
NC
NC
NC
NC
COMI2
X
2158.07
2203.07
2248.07
2293.07
2338.07
2383.07
2428.07
2473.07
2518.07
2563.07
2608.07
2653.07
Y
-369
-369
-369
-369
-369
-369
-369
-369
-369
-369
-369
-369
2007/01/25
ST7038
PAD CENTER COORDINATES
PAD No.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
Ver 1.1
PIN Name
XRESET
OSC
VDD
A0(RS)
CSB
/WR(RW)
/RD(E)
DB[0]
DB[1]
DB[2]
DB[3]
DB[4]
DB[5]
DB[6]
DB[7]
VSS
VSS
VSS
VSS
PS0
PS1
PS2
CLS
TEST[0]
TEST[1]
TEST[2]
TEST[3]
TEST[4]
TEST[5]
VDD
VDD
VDD
VDD2
VDD2
VDD2
VOUT
VOUT
VOUT
CAP3P
CAP3P
CAP1P
CAP1P
CAP1N
CAP1N
CAP1N
CAP2P
CAP2P
CAP2N
CAP2N
CAP4P
CAP4P
VRS
V0
V1
X
2543.915
2424.915
2350.675
2276.575
2157.575
2084.575
1965.575
1892.575
1773.575
1700.575
1581.575
1508.575
1389.575
1316.575
1197.575
1124.575
1051.575
978.575
905.575
830.945
711.945
638.945
519.945
447.945
298.945
223.945
48.945
-26.055
-201.055
-276.94
-349.94
-422.94
-495.94
-568.94
-641.94
-714.94
-787.94
-860.94
-933.94
-1006.94
-1079.94
-1152.94
-1225.94
-1298.94
-1371.94
-1444.94
-1517.94
-1590.94
-1663.94
-1736.71
-1809.94
-1892.1
-1965.26
-2053.56
(1-line, SHLC=“L”)
Y
379
379
379
379
379
379
379
379
379
379
379
379
379
379
379
379
379
379
379
379
379
379
379
379
379
379
379
379
379
379
379
379
379
379
379
379
379
379
379
379
379
379
379
379
379
379
379
379
379
379
379
379
379
379
PAD No.
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
9/61
Unit: um
PIN Name
V2
V3
V4
NC
NC
NC
NC
NC
NC
NC
NC
COMI1
SEG[1]
SEG[2]
SEG[3]
SEG[4]
SEG[5]
SEG[6]
SEG[7]
SEG[8]
SEG[9]
SEG[10]
SEG[11]
SEG[12]
SEG[13]
SEG[14]
SEG[15]
SEG[16]
SEG[17]
SEG[18]
SEG[19]
SEG[20]
SEG[21]
SEG[22]
SEG[23]
SEG[24]
SEG[25]
SEG[26]
SEG[27]
SEG[28]
SEG[29]
SEG[30]
SEG[31]
SEG[32]
SEG[33]
SEG[34]
SEG[35]
SEG[36]
SEG[37]
SEG[38]
SEG[39]
SEG[40]
SEG[41]
SEG[42]
X
-2126.56
-2199.56
-2272.56
-2611.93
-2566.93
-2521.93
-2476.93
-2431.93
-2386.93
-2341.93
-2296.93
-2251.93
-2206.93
-2161.93
-2116.93
-2071.93
-2026.93
-1981.93
-1936.93
-1891.93
-1846.93
-1801.93
-1756.93
-1711.93
-1666.93
-1621.93
-1576.93
-1531.93
-1486.93
-1441.93
-1396.93
-1351.93
-1306.93
-1261.93
-1216.93
-1171.93
-1126.93
-1081.93
-1036.93
-991.93
-946.93
-901.93
-856.93
-811.93
-766.93
-721.93
-676.93
-631.93
-586.93
-541.93
-496.93
-451.93
-406.93
-361.93
Y
379
379
379
-369
-369
-369
-369
-369
-369
-369
-369
-369
-369
-369
-369
-369
-369
-369
-369
-369
-369
-369
-369
-369
-369
-369
-369
-369
-369
-369
-369
-369
-369
-369
-369
-369
-369
-369
-369
-369
-369
-369
-369
-369
-369
-369
-369
-369
-369
-369
-369
-369
-369
-369
2007/01/25
ST7038
PAD No.
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
Ver 1.1
PIN Name
SEG[43]
SEG[44]
SEG[45]
SEG[46]
SEG[47]
SEG[48]
SEG[49]
SEG[50]
SEG[51]
SEG[52]
SEG[53]
SEG[54]
SEG[55]
SEG[56]
SEG[57]
SEG[58]
SEG[59]
SEG[60]
SEG[61]
SEG[62]
SEG[63]
SEG[64]
SEG[65]
SEG[66]
SEG[67]
SEG[68]
SEG[69]
SEG[70]
SEG[71]
SEG[72]
SEG[73]
SEG[74]
SEG[75]
SEG[76]
SEG[77]
SEG[78]
SEG[79]
SEG[80]
SEG[81]
SEG[82]
SEG[83]
SEG[84]
SEG[85]
SEG[86]
SEG[87]
SEG[88]
SEG[89]
SEG[90]
SEG[91]
SEG[92]
SEG[93]
SEG[94]
SEG[95]
SEG[96]
SEG[97]
X
-316.93
-271.93
-226.93
-181.93
-136.93
-91.93
-46.93
-1.93
43.07
88.07
133.07
178.07
223.07
268.07
313.07
358.07
403.07
448.07
493.07
538.07
583.07
628.07
673.07
718.07
763.07
808.07
853.07
898.07
943.07
988.07
1033.07
1078.07
1123.07
1168.07
1213.07
1258.07
1303.07
1348.07
1393.07
1438.07
1483.07
1528.07
1573.07
1618.07
1663.07
1708.07
1753.07
1798.07
1843.07
1888.07
1933.07
1978.07
2023.07
2068.07
2113.07
Y
-369
-369
-369
-369
-369
-369
-369
-369
-369
-369
-369
-369
-369
-369
-369
-369
-369
-369
-369
-369
-369
-369
-369
-369
-369
-369
-369
-369
-369
-369
-369
-369
-369
-369
-369
-369
-369
-369
-369
-369
-369
-369
-369
-369
-369
-369
-369
-369
-369
-369
-369
-369
-369
-369
-369
PAD No.
164
165
166
167
168
169
170
171
172
173
174
175
10/61
PIN Name
SEG[98]
SEG[99]
SEG[100]
COM[8]
COM[7]
COM[6]
COM[5]
COM[4]
COM[3]
COM[2]
COM[1]
COMI2
X
2158.07
2203.07
2248.07
2293.07
2338.07
2383.07
2428.07
2473.07
2518.07
2563.07
2608.07
2653.07
Y
-369
-369
-369
-369
-369
-369
-369
-369
-369
-369
-369
-369
2007/01/25
ST7038
BLOCK DIAGRAM
OSC
XRESET
Reset
circuit
CLS
Instruction
register(IR)
Instruction
decoder
RS
RW
E
CSB
24-bit
shift
register
Common
signal
driver
100-bit
shift
register
100-bit
latch
circuit
Segment
signal
driver
Data
register
(DR)
Input/
output
buffer
COM1 to
COM16
(or 24)
COMI
Address
counter
(AC)
DB4 to
DB7
Busy
flag
ICON RAM
80 bits
SEG1 to
SEG100
(or 80)
V0~V4
LCD drive
voltage
follower
Character
generator RAM
(CGRAM)
64 bytes
VSS
Display data
RAM
(DDRAM)
80x8 bits
MPU
interface
PS0
PS1
PS2
DB0 to
DB3
Timing
generator
CPG
Character
generator ROM
(CGROM)
10240 bits
Cursor
and
blink
controller
Voltage
booster
circuit
VOUT
CAP1P
CAP1N
CAP2P
CAP2N
CAP3P
CAP4P
Parallel/serial converter
and
attribute circuit
VDD
Ver 1.1
11/61
2007/01/25
ST7038
PIN DESCRIPTION
Name
I/O
Interfaced
with
XRESET
I
MPU
A0(RS)
I
MPU
/WR(R/W)
I
MPU
/RD(E)
I
MPU
CSB
I
MPU
DB7~DB0
I/O
MPU
PS2~PS0
Ver 1.1
I
MPU
Function
External reset pin.
Low active.
Register select.
0: Instruction register (for writing)
Busy flag & address counter (for reading)
1: Data register (for write and read)
This Pin must connect to “VDD” when it is not used
8080-series interface (/WR):
Write enable signal input pin (low active).
6800-series interface (R/W):
Select read or write
R/W=0: Write
R/W=1: Read
This Pin must connect to “VDD” when serial mode is selected.
8080-series interface (/RD):
Read enable signal input pin (low active).
6800-series interface (E):
Data strobe signal input. It starts data read/write (high active).
This Pin must connect to “VDD” when serial mode is selected.
Chip select in parallel/serial interface (low active). In serial interface, the
falling edge of CSB will reset the internal shift register and counter.
2
This Pin must connect to “VDD” when I C mode is selected.
For parallel 8-bit parallel interface:
DB7~DB0 are 8-bit bi-directional data bus and should be connected to 8-bit
data bus of the microprocessor.
When the chip select is not active (CSB=H), DB7~DB0 are high impedance.
For parallel 4-bit parallel interface:
DB7~DB4 are used for data transfer between MPU and ST7038;
DB3~DB0 are not used and must be left OPEN or connected to VDD.
For serial interface (3-line and 4-line):
DB7: serial data input (SI);
DB6: serial clock input (SCL).
DB5~DB0 are not used and must be left OPEN or connected to VDD.
2
For I C interface:
DB7~DB6: slave addresses (SA1~SA0) and must be fixed to “H” or “L”;
DB5~DB3: serial data output (SDA-out);
DB2~DB1: serial data input (SDA-in);
DB0: serial clock input (SCL).
DB1~DB5 must be connected together (SDA).
The ITO resistance on SDA/SCL will form a voltage divider with the pull-up
resistor on system. To keep the signal quality better, customers should keep
the ITO resistance as low as possible.
Parallel / Serial access mode selection
PS2
PS1
PS0
Access mode
0
0
0
8080-series parallel MPU interface
0
0
1
6800-series parallel MPU interface
0
1
0
4-line serial MPU interface
0
1
1
3-line serial MPU interface
2
1
0
0
I C serial MPU interface
12/61
2007/01/25
ST7038
Name
Interfaced
with
I/O
COM1~COM16
(COM1~COM24)
O
LCD
COMI1, COMI2
O
LCD
SEG1~SEG100
(SEG1~SEG80)
O
LCD
CAP1P, CAP2P,
CAP3P, CAP4P,
CAP1N, CAP2N
Power
Power
VOUT
Power
Power
V0~V4
Power
Power
VDD
VDD2
VSS
Power
Power
Power
Power
Power
Power
VRS
Power
Power
CLS
I
Option
OSC
I
Oscillation
Function
Common driver outputs.
Signals that are not used will output the non-selection waveform. For
example, COM9 to COM16 output the non-selection waveform in 1-line
display mode.
Common driver outputs for ICON.
Segment driver outputs.
The output map is different from display modes (3-line, 2-line and 1-line)
please refer to Table 9 for detailed output map.
For voltage booster circuit (VDD-VSS).
External capacitor about 0.1uF~4.7uF.
Built-in Voltage Booster output.
If using external booster circuit, this pin is used as the power input.
Power supply for LCD drive
V0: built-in Voltage Regulator output.
If using external regulator circuit, this pin is used as the power input.
Internal regulator programmable range: V0 - VSS = 7V (Max);
External power endurance: V0 - VSS = 12V (Max).
V1~V4: built-in voltage follower outputs.
If using external follower circuit, connect the external power to these pins.
Please always keep the voltage relation between these pins to be:
VOUT > V0 > V1 > V2 > V3 > V4 > VSS
Power for digital circuits. Connect to 1.8V~3.3V power source.
Power for analog circuit. Connect to 1.8V~3.3V power source.
Ground.
Reserved to monitor the internal Voltage Regulator reference level.
Must be left open.
Select to use internal/external oscillation system.
0: External clock will be input through OSC pin;
1: Using internal clock and the OSC pin must be fixed to VDD.
External clock input pin.
If using external clock, connect this pin to the clock source.
If using internal clock, connect this pin to VDD.
Reserved for testing only. Must be left open.
TEST0~TEST5
Test Only
Notes:
1.
Please connect all unused input pins to VDD.
2.
The microprocessor interface pins (CSB, /WR, /RD, A0 and D7~D0) should not be left floating in any operation mode.
Recommended ITO Resistance Limitation
ITO Resistance
(VDD2 ≥ 2.4V)
No Limitation
Floating
<100Ω
<1KΩ
*3
<500Ω
*4
<10KΩ
PIN Name
*1
ITO Resistance
(VDD2 < 2.4V)
No Limitation
Floating
<80Ω
<800Ω
*3
<200Ω
*4
<8KΩ
PS2~PS0, CLS, OSC
TEST0~TEST5, VRS
VDD, VDD2, VSS, VOUT
*2
A0, /WR(R/W), /RD(E), CSB, DB0~DB7 ,
V0~V4, CAP1P, CAP1N, CAP2P, CAP2N, CAP3P, CAP4P
XRESET
Notes:
1.
If using internal clock, OSC is connect to VDD and there will be “No Limitation” on its ITO resistance.
If using external clock, the ITO resistance of OSC should be kept lower than 500Ω to control the clock signal quality.
2
2.
If using I C interface mode, the resistance of SDA signal should be lower than 300Ω.
3.
To get a better power system efficiency, the recommended ITO resistance value should be lower than 300Ω.
Ver 1.1
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ST7038
FUNCTION DESCRIPTION
MICROPROCESSOR INTERFACE
Chip Select Input
The CSB pin is used for chip selection. ST7038 can interface with an MPU when CSB is "L". When CSB is set to “H”, the
control signal inputs, A0, /RD(E) and /WR(R/W), are disabled and DB0 to DB7 are set to be high impedance. When using
3-line or 4-line serial interface, the internal shift register and counter are reset right after the falling edge of CSB.
Parallel / Serial Interface
ST7038 has five interface modes to interface with an MPU, which are three serial interfaces and two parallel interfaces.
These interface modes are selected by PS2~PS0 pins as shown below.
Table 1
Parallel / Serial
PS2
L
L
L
L
H
Parallel
Serial
PS1
L
L
H
H
L
Parallel / Serial Interface Modes
PS0
L
H
L
H
L
CSB
CSB
CSB
CSB
CSB
--
Interface Mode
8000-series parallel MPU interface mode
6880-series parallel MPU interface mode
4-line SPI (Serial Peripheral Interface) mode
3-line SPI (Serial Peripheral Interface) mode
2
I C interface mode
Parallel Interface (PS[2:0] = "0, 0, X")
The 8-bit bi-directional data bus is used in parallel interface and the type of MPU is selected by PS0 as shown in Table 2. The
access type is determined by signals on A0, /RD(E) and /WR(R/W) as shown in Table 3.
Table 2
PS0
L
H
CSB
CSB
CSB
Microprocessor Selection in Parallel Interface
A0
A0
A0
/RD(E)
/RD
E
Table 3
/WR(R/W)
/WR
R/W
DB0 to DB7
DB0 to DB7
DB0 to DB7
MPU Type
8080-series MPU
6800-series MPU
Parallel Access
Common
6800-series MPU
8080-series MPU
Description
A0
E
R/W
/RD
/WR
H
H
H
L
H
Read display data
H
H
L
H
L
Write display data
L
H
H
L
H
Read status
L
H
L
H
L
Write register (instruction)
Note: By fixing the /RD(E) pin to “H” in 6800-series interface, the CSB pin can be used as the “Enable” signal. In this way, the
data is latched at the rising edge of CSB and the access type is determined by the signals A0 and /WR(R/W).
2
Serial Interface (3-Line / 4-Line / I C)
The serial interface mode can be selected by PS2~PS0 as listed below:
Serial mode
PS2
PS1
PS0
4-Line SPI mode
L
H
L
3-Line SPI mode
L
H
H
2
I C SPI mode
H
L
L
Note: Please connect the pins which are not used to “H”.
CSB
CSB
CSB
Not Used
A0
A0
Not used
Not Used
3-Line/4-Line SPI (PS[2:0] = "0, 1, X")
When CSB=”L”, ST7038 is active and the SI and SCL inputs are enabled. When CSB=”H”, ST7038 is inactive and the
internal 8-bit shift register and 3-bit counter are reset. The data/command indication is controlled via the software A0 bit (for
3-Line SPI) or the A0 Pin (for 4-Line SPI). For 4-Line SPI, A0=”H” indicates signal on data bus is display data while A0=”L”
indicates signal on data bus is instruction. For 3-Line SPI, the first bit is A0 which indicates the following bits belong to display
data or instruction. Serial data will be latched on the rising edge of serial clock. The shift register will collect the serial bits and
reformat them to be an 8-bit parallel data at the 8th (4-Line SPI) or 9th (3-Line SPI) serial clock. The DDRAM column address
pointer will be increased by one automatically after the 8-bit data is transferred into the DDRAM. The read of data or status
(BF and AC) is not allowed in serial interface (neither 3-Line SPI nor 4-Line SPI).
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ST7038
Figure 1
The 4-Line SPI Mode access timing
Figure 2
The 3-Line SPI Mode access timing
2
I C Interface (PS[2:0] = "1, 0, 0")
2
The I C Interface uses two-signal to communicate between different ICs or modules. The two signals are SDA (Serial Data)
and SCL (Serial Clock). Both lines must be connected to a pull-up resistor to provide the “H” voltage level. Data transfer may
be initiated only when the bus is not busy.
2
ST7038i support I C interface with only write function. Status read or data read is impossible (except reading the
Acknowledge signal). The related signals are listed below:
Ø
SCL: serial clock input
Ø
SDA_IN: serial data input
Ø
SDA_OUT: acknowledge response output
Ø
SA1~SA0: select the slave address and the available slave addresses are: “0111100” to “0111111”.
l
l
l
BIT TRANSFER
One data bit is transferred during each clock pulse. The data on the SDA line must remain stable during the HIGH
period of the clock pulse because changes in the data line at this time will be interpreted as a control signal. Bit transfer
is illustrated in Figure 3.
START AND STOP CONDITIONS
Both SDA and SCL lines remain HIGH when the bus is not busy. A HIGH-to-LOW transition on SDA while SCL is HIGH
is defined as the START condition (S). A LOW-to-HIGH transition of SDA while SCL is HIGH is defined as the STOP
condition (P). The START and STOP conditions are illustrated in Figure 4.
SYSTEM CONFIGURATION
2
The system configuration of I C interface is illustrated in Figure 5. The related glossaries are listed below:
Ø
Transmitter: the device sends the data to the bus
Ø
Master: the device, which initiates a transfer, generates clock signals and terminates a transfer
Ø
Slave: the device addressed by a master
Ø
Multi-Master: more than one master can attempt to control the bus at the same time without corrupting the
message
Ø
Arbitration: a procedure to ensure that, if more than one master tries to control the bus simultaneously, only one
is allowed to do so and the message is not corrupted
Ø
Synchronization: a procedure to synchronize the clock signals of two or more devices.
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ST7038
l
ACKNOWLEDGEMENT
Acknowledge signal (ACK) is not identical with the Busy Flag (BF) signal in parallel interface. Since internal
status cannot be read out, a certain delay is needed before writing the next instructions/data.
Each byte of 8-bit is followed by an acknowledge bit. To check the acknowledge bit, the transmitter must release SDA
to HIGH first and then the master generates an extra acknowledge related clock pulse for the acknowledge bit. A slave
receiver which is addressed must generate an acknowledge bit after the reception of each byte. A master receiver
must also generate an acknowledge bit after the reception of each byte that has been clocked out of the slave
transmitter. The device that acknowledges must pull-down the SDA line during the LOW period of the acknowledge
clock, so that the SDA is stable LOW during the HIGH period of the acknowledge clock (setup time and hold times
2
must be taken into consideration). Acknowledgement on the I C Interface is illustrated in Figure 6.
Figure 3
Figure 4
Definition of START and STOP conditions
Figure 5
Figure 6
Ver 1.1
Bit Transfer
System Configuration
2
Acknowledgement on the I C Interface
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ST7038
l
2
I C Interface protocol
2
ST7038 receives command/data issued by MPU with correct slave address. Before any data is transmitted on the I C
Interface, the device, which should respond, is addressed first. Four kinds of 7-bit slave address (0111100 to 0111111)
2
are reserved for ST7038. The R/W bit is assigned to 0 for write only. The I C Interface protocol is illustrated in Figure 7.
2
The sequence is initiated with a START condition (S) from the I C Interface master, which is followed by the slave
2
address. All slaves with the corresponding address acknowledge in parallel, all the others will ignore the I C Interface
transfer. After acknowledgement, one or more command words follow which define the status of the addressed slaves.
A command word consists of a control byte, which defines Co and A0, plus a data byte. The last control byte is tagged
with a cleared most significant bit (i.e. the continuation bit Co). After a control byte with a cleared Co bit, only data bytes
will follow. The state of the A0 bit defines whether the data byte is interpreted as a command or as RAM data. All
addressed slaves on the bus also acknowledge the control and data bytes. After the last control byte, depending on the
A0 bit setting; either a series of display data bytes or command data bytes may follow. If the A0 bit is set to logic 1,
these display bytes are stored in the display RAM at the address specified by the data pointer. The data pointer is
automatically updated and the data is directed to the intended ST7038i device. If the A0 bit of the last control byte is set
to logic 0, these command bytes will be decoded and the setting of the device will be changed according to the
received commands. Only the addressed slave makes the acknowledgement after each byte. At the end of the
2
transmission the I C INTERFACE-bus master issues a STOP condition (P).
Figure 7
Co
l
2
I C Interface Protocol
0
Last control byte to be sent. Only a stream of data bytes is allowed to follow.
This stream may only be terminated by a STOP condition.
1
Another control byte will follow the data byte unless a STOP condition is received.
Data Register and Instruction Register
During write operation, two 8-bit registers are used. One is data register (DR), the other is instruction register (IR).
The data register (DR) is used as temporary data storage place for being written into internal RAM blocks (DDRAM,
CGRAM and ICON RAM). The RAM block is selected by RAM address setting instruction. Each internal operation,
writing into RAM, is done automatically. That means: after MPU writes data into DR, the data in DR is transferred into
DDRAM/CGRAM/ICON RAM automatically.
The instruction register (IR) is used only to store instruction code transferred from MPU. MPU cannot read instruction
data back via this register (IR).
Use the A0 bit in control byte to select the correct register (DR or IR):
Table 4
A0
L
H
Ver 1.1
R/W
L
L
Operations according to A0 and R/W bits.
Operation
Instruction Write operation (MPU writes Instruction code into IR)
Data Write operation (MPU writes data into DR)
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ST7038
Busy Flag (BF)
When BF is "High” (Busy), it indicates that the internal operation is being processed. So during this time the next instruction
cannot be accepted. BF can be read in parallel interface mode. By issuing A0=”Low” and R/W=”High” (Read Status
operation), BF (Busy Flag) can be checked on DB7. Before executing the next instruction, be sure that BF is not “High”.
Address Counter (AC)
Address Counter (AC) stores DDRAM/CGRAM/ICON RAM address which is transferred from IR. After writing into (reading
from) DDRAM/CGRAM/ICON RAM, AC is automatically increased (decreased) by 1. By issuing A0="Low" and R/W="High"
(Read Status Operation), AC can be read on DB6 ~ DB0.
Figure 8
DDRAM Address
Display Data RAM (DDRAM)
Display Data RAM (DDRAM) stores display data represented in 8-bit character codes. Each character code has a unique
font stored in the Character Generator ROM (CGROM). The Display Data RAM (DDRAM) capacity is 80 x 8 bits, or 80
characters. The unused area in Display Data RAM (DDRAM) can be used as general data RAM. Please refer to the following
sections for the relationships between DDRAM address and display position on the LCD module under different display
operation. Please note that: In following demonstration, the DDRAM address in the address counter (AC) is hexadecimal
format while the character position is decimal format.
1-LINE DISPLAY (N2=0, N1=0)
In this mode, each line can use 80 RAM-cells to store the display data. The relation between DDRAM address and display
position is illustrated in Figure 9. For example, 20 characters are displayed (with 100 segments); the default relation between
DDRAM Address and display position is illustrated on the top of Figure 10. When the display shift operation is performed, the
relation is changed, just as shown in Figure 10.
Figure 9
1-Line Display Mode
Figure 10 1-Line Display Mode with 20-Character Display
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ST7038
2-LINE DISPLAY (N2=0, N1=1)
In this mode, each line can use 40 RAM-cells to store the display data. The relation between DDRAM address and display
position is illustrated in Figure 11 (NOTE: The end address of the first line and the start address of the second line are not
consecutive). For example, 20 characters by 2 lines are displayed (with 100 segments); the default relation between DDRAM
Address and display position is illustrated on the top of Figure 12. When display shift operation is performed, the relation is
changed, just as shown in Figure 12.
Figure 11 2-Line Display Mode
Figure 12 2-Line Display Mode with 20-Character Display
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ST7038
3-LINE DISPLAY (N2=1, N1=0)
In this mode, each line can use 16 RAM-cells to store the display data. The relation between DDRAM address and display
position is illustrated in Figure 13. For example, 16 characters by 3 lines are displayed (with 80 segments); the default
relation between DDRAM Address and display position is illustrated on the top of Figure 14. When display shift operation is
performed, the relation is changed, just as shown in Figure 14.
Figure 13 3-Line Display Mode
Figure 14 3-Line Display Mode with 20-Character Display
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ST7038
Character Generator ROM (CGROM)
The Character Generator ROM stores 5x8-dot character patterns for 8-bit character codes. It stores 256 5x8-dot character
patterns which can be selected by 8-bit character code (Table 5). The first 16 patterns are multiplexed with the Character
Generator RAM (CGRAM). By using instruction to set OPR2 & OPR1, customer can use the patterns stored in CGRAM to
replace these 16 default patterns. The detailed setting is illustrated in Table 7. User-defined character patterns are also
supported by changing the content in mask-programmed ROM. Table 5 illustrated the relation between Character Codes and
Character Patterns.
ST7038-0B
Table 5
Ver 1.1
ROM Table (ROM Code ID: 0B)
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ST7038
Character Generator RAM (CGRAM)
The Character Generator RAM is reserved for customers to rewrite character patterns by program. Total 8 character patterns
(each one is 5x8-dot) can be stored in CGRAM. Each byte of CGRAM has 5 bits and a character pattern (5x8-bit) uses 8
bytes to store its pattern. Refer to Table 6 for the relationship among DDRAM data, CGRAM addresses and CGRAM data.
Areas that are not used for display can be used as general data RAM (* only 5-bit per byte).
To display the CGRAM Data (customized Character Pattern), write the Character Code (light green part in Table 6) into
DDRAM (be sure the OPR2 & OPR1 settings are correct… refer to Table 7).
Generate CGRAM Pattern
Display CGRAM Pattern
CGRAM Address
(Instruction)
Character Code
(DDRAM Data)
b7
0
0
Table 6
b6
0
0
b5
0
0
b4
0
0
b3
-
-
*4
*4
b2
0
0
b1
0
0
b0
0
1
b5
0
0
b4
0
0
b3
0
1
Character Pattern
(CGRAM Data)
b2
b1
b0
b4
b3
b2
b1
b0
0
0
0
b7
1
1
1
1
1
0
0
1
0
0
1
0
0
0
1
0
0
0
1
0
0
0
1
1
0
0
1
0
0
1
0
0
0
0
1
0
0
1
0
1
0
0
1
0
0
1
1
0
0
0
1
0
0
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
0
0
0
1
1
0
0
0
1
0
1
0
1
0
0
0
1
0
1
1
1
1
1
1
0
1
0
0
1
0
1
0
0
1
0
1
1
0
0
1
0
1
1
0
1
0
0
0
1
1
1
1
0
0
0
0
0
-
-
b6
-
-
b5
-
-
Relationship among CGRAM Address, Character Code (DDRAM Data) & Character Pattern (CGRAM Data)
Notes:
1.
Character code bits 2 to 0 are identical with CGRAM address bits 5 to 3 (the red block and red arrow).
These 3 bits indicate there are maximum 8 character patterns can be generated by CGRAM.
2.
CGRAM address bits 2 to 0 point to the character pattern line position. The 8th line is the cursor position and its display
is formed by a logical OR with the cursor. Try to keep the 8th line data at 0. Otherwise, those pixels with 1 in the 8th line
will be turned ON no matter the cursor is ON or OFF.
3.
Character pattern row positions correspond to CGRAM data bits 4 to 0 (bit 4 is on the left side).
4.
As shown in Table 6, character patterns in CGRAM are selected when character code bits 7 to 4 are all 0 (assume
OPR2 & OPR1 setting are correct). However, since character code bit 3 is not used, the “R” pattern in Table 6 can be
selected by either character code 01H or 09H.
5.
In CGRAM data, “1” corresponds to display selection, “0” to non-selection while “-” indicates no effect.
6.
Different CGRAM size can be selected by instruction (OPR2 & OPR1). Please refer to Table 7 and instruction
description.
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ST7038
Replaced By CGRAM Pattern
Replaced By CGRAM Pattern
Replaced By CGRAM Pattern
Replaced By CGRAM Pattern
2007/01/25
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Ver 1.1
Use OPR2 & OPR1 to configure the mapping between CGRAM and CGROM
Table 7
ST7038
ICON RAM
There are 80 bits ICON RAM embedded in ST7038. Each bit is mapped to an ICON pixel. Write “1”/”0” into the ICON RAM to
control the ICON ON/OFF. Refer to Table 8 for the relationship between ICON RAM address and ICON mapping.
ICON RAM Mapping when SHLS=1:
ICON Address
00H
01H
02H
03H
04H
05H
06H
07H
08H
09H
0AH
0BH
0CH
0DH
0EH
0FH
b7
-
b6
-
b5
-
ICON RAM bits
b4
b3
ICON1
ICON2
ICON6
ICON7
ICON11
ICON12
ICON16
ICON17
ICON21
ICON22
ICON26
ICON27
ICON31
ICON32
ICON36
ICON37
ICON41
ICON42
ICON46
ICON47
ICON51
ICON52
ICON56
ICON57
ICON61
ICON62
ICON66
ICON67
ICON71
ICON72
ICON76
ICON77
b2
ICON3
ICON8
ICON13
ICON18
ICON23
ICON28
ICON33
ICON38
ICON43
ICON48
ICON53
ICON58
ICON63
ICON68
ICON73
ICON78
b1
ICON4
ICON9
ICON14
ICON19
ICON24
ICON29
ICON34
ICON39
ICON44
ICON49
ICON54
ICON59
ICON64
ICON69
ICON74
ICON79
b0
ICON5
ICON10
ICON15
ICON20
ICON25
ICON30
ICON35
ICON40
ICON45
ICON50
ICON55
ICON60
ICON65
ICON70
ICON75
ICON80
b6
-
b5
-
ICON RAM bits
b4
b3
ICON80
ICON79
ICON75
ICON74
ICON70
ICON69
ICON65
ICON64
ICON60
ICON59
ICON55
ICON54
ICON50
ICON49
ICON45
ICON44
ICON40
ICON39
ICON35
ICON34
ICON30
ICON29
ICON25
ICON24
ICON20
ICON19
ICON15
ICON14
ICON10
ICON9
ICON5
ICON4
b2
ICON78
ICON73
ICON68
ICON63
ICON58
ICON53
ICON48
ICON43
ICON38
ICON33
ICON28
ICON23
ICON18
ICON13
ICON8
ICON3
b1
ICON77
ICON72
ICON67
ICON62
ICON57
ICON52
ICON47
ICON42
ICON37
ICON32
ICON27
ICON22
ICON17
ICON12
ICON7
ICON2
b0
ICON76
ICON71
ICON66
ICON61
ICON56
ICON51
ICON46
ICON41
ICON36
ICON31
ICON26
ICON21
ICON16
ICON11
ICON6
ICON1
ICON RAM Mapping when SHLS=0:
ICON Address
00H
01H
02H
03H
04H
05H
06H
07H
08H
09H
0AH
0BH
0CH
0DH
0EH
0FH
b7
-
Table 8
ICON RAM Address and ICON Mapping
Timing Generation Circuit
The timing generation circuit generates timing signals for the operation of internal circuits such as: DDRAM, CGROM and
CGRAM. RAM read timing for display and RAM access timing for MPU are generated separately so that the interfering with
each other can be avoided. Therefore, when writing data to DDRAM, for example, there will be no undesirable interference,
such as flickering, in the whole display area.
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ST7038
LCD Driver Circuit
ST7038 LCD Driver Circuit has 3 kinds of output mode: 8+1 common outputs, 16+1 common outputs and 24+1 common
outputs. Besides, ST7038 also support horizontal and vertical mirror feature. Please refer to for the relationship of Pin
Number and Pin Function.
Table 9
DH
SHLC
COM
PAD
PAD
PAD
PAD
PAD
PAD
PAD
PAD
PAD
PAD
Rows
66
65~58
67~71
72~76
77~156
157~162
163~166
167~174
175
No.
COMI2
Output (Pin Function)
Display setting
Line
COM
1
1
0
NC
COMI1
1
1
16+1
2
0
0
1
24+1
1
0
0
SEG
SEG
SEG
SEG
[8:1]
[1:5]
[6:10]
[11:90]
[91:96]
[97:100]
COM
[1:8]
[9:16]
COM
COM
COM
0
3
COM
COM
SEG
[16:9]
1
2
NC
[1:8]
8+1
0
1
Pin Number vs. Pin Function in different display mode
NC
[8:1]
COM[4:1]
COM
COM
[5:12]
+ COMI1
[13:16]
[17:24]
COM
COM[21:24]
COM
COM
[20:13]
+ COMI1
COM
COM[4:1]
NC
SEG
[1:80]
NC
[12:9]
[8:1]
COM
COM
[5:12]
+ COMI1
[13:16]
[17:24]
COM
COM[21:24]
COM
COM
[20:13]
+ COMI1
[12:9]
[8:1]
Note:
1.
SHLC=1: COM scan direction is normal;
SHLC=0: COM scan direction is reversed.
* Pin definition of COM is changed when SHLC=0.
2.
ICON COM (COMI1/COMI2) scan direction will never be changed (always the last).
3.
SHLS=1: SEG scan direction is normal (SEG1~SEG100 or SEG1~SEG80);
SHLS=0: SEG scan direction is reversed (SEG100~SEG1 or SEG80~SEG1).
* Pin definition of SEG is NOT changed when SHLS=0
Cursor and Blink Control Circuit
ST7038 can generate the cursor and blink effects with built-in cursor/blink control circuit. The cursor or blink effect will appear
at the current DDRAM display position which is kept in the AC (Address Counter).
Ver 1.1
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ST7038
INSTRUCTIONS
Instruction Code
Description
DB0
DB1
DB2
DB3
DB4
DB5
DB6
DB7
R/W
A0
Instruction
Execution Time
OSC=
OSC=
OSC=
260.4K 284.1K 531.1K
Hz
Hz
Hz
Write "20H" to clear DDRAM and set
1.8
1,6
AC to "00H".
ms
ms
93 us
85 us
70 us
93 us
85 us
70 us
93 us
85 us
70 us
93 us
85 us
70 us
93 us
85 us
70 us
0
0
0
93 us
85 us
70 us
93 us
85 us
70 us
93 us
85 us
70 us
93 us
85 us
70us
Default Instruction Table (IS[1:0]: Don’t Care)
Clear Display
0
0
0
0
0
0
0
0
0
1
1ms
Set AC to "00H". It will return cursor to
Return Home
0
0
0
0
0
0
0
0
1
X
the original position if shifted.
The contents in DDRAM are not
changed.
Set cursor move direction and display
Set Entry Mode
0
0
0
0
0
0
0
1
I/D
S
shift direction.
The effects are performed after each
data access (write or read).
D=1: Entire display on;
Display Control
0
0
0
0
0
0
1
D
C
B
C=1: Cursor on;
B=1: Cursor position on.
X
IS0
X
AC0
AC1
1
DL
AC2
0
1
AC3
0
0
AC4
0
AC5
Address
0
AC6
Set DDRAM
0
IS1
Function Set
DL: Interface data is 8/4 bits;
IS[1:0]: select instruction table.
Set DDRAM address into AC (address
counter).
Before next access, Check BF will
know if the internal operation is
AC0
AC1
AC2
AC3
BF
AC4
1
AC5
0
AC6
Read Status
finished or not.
The contents of AC (address counter)
can also be read.
Write Data
1
0
D7
D6
D5
D4
D3
D2
D1
D0
Read Data
1
1
D7
D6
D5
D4
D3
D2
D1
D0
1
S/C
R/L
X
X
Write data into internal RAM
(DDRAM/CGRAM/ICONRAM)
Read data from internal RAM
(DDRAM/CGRAM/ICONRAM)
Instruction table 0: IS[1:0]=(0,0)
Cursor or Display
Shift
0
1
AC0
0
AC1
0
0
AC2
0
AC3
Ver 1.1
0
AC4
Address
0
AC5
Set CGRAM
0
26/61
S/C and R/L: Immediately move cursor
or shift display by 1.
Set CGRAM address into AC
(address counter)
2007/01/25
ST7038
Instruction table 1: IS[1:0]=(0,1)
1
0
0
0
1
0
1
OPF2~1:
Select
built-in
voltage
93 us
85 us
70us
93 us
85 us
70 us
93us
85us
70us
93 us
85 us
70 us
93 us
85 us
70 us
93 us
85 us
70 us
93 us
85 us
70 us
93 us
85 us
70 us
follower circuit.
Set ICON address into AC (address
VC4
0
BS2~1: Bias select;
AC0
0
VC5
1
AC1
0
VC6
0
AC2
0
OPF1
0
OPF2
0
PD
V0 Control 1
0
BS1
Address
0
AC3
Set ICON RAM
0
BS2
Follower Control
PD: Power down;
counter).
VC6~4: Set V0 (High-nibble).
Ion: ICON display on/off;
0
1
1
0
Fon
0
Ron
0
Bon
Control
Ion
ICON/Power
Bon: Set booster circuit on/off;
Ron: Set regulator circuit on/off;
Fon: Set follower circuit on/off.
1
1
1
VC0
0
VC1
0
VC2
0
VC3
V0 Control 2
Set V0 (Low-nibble).
Instruction table 2: IS[1:0]=(1,0)
UD: Double Height Position (DHu or
Set Display Mode
0
0
0
0
0
1
UD DH
N2
N1
DHd);
DH: Double Height;
N2, N1: Display line number.
OPR2~1:
0
1
0
0
direction
0
0
1
0
1
0
FR0
0
FR1
Ver 1.1
CGRAM mapping select
SHLS: Set SEG scan direction
SHLC: Set COM scan direction
FR2
Set Frame Rate
SHLC
0
SHLS
0
OPR1
COM/SEG
OPR2
Select CGRAM &
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FRC2~0: Select Frame Rate
2007/01/25
ST7038
INSTRUCTION DESCRIPTION
IS[1:0]: Don’t Care
Clear Display
Clear all the display data by writing "20H" (space code) to all DDRAM address. Then set DDRAM address "00H" into AC
(address counter). This (AC=00H) will return cursor to the original position, namely, bring the cursor to the left edge on first
line of the display. Besides, this instruction also reset the entry mode to be “increment” (I/D = "1").
Return Home
By setting DDRAM address "00H" into AC (address counter), this instruction returns the cursor back to its “Home” position
(original position or the left edge on the first line). This instruction not only returns cursor to its original position but also
returns the display to its original setting, if it is shifted. Contents in DDRAM are not changed.
Set Entry Mode
Set the moving direction of cursor and display. After each data access, the cursor and display will be moved or shifted
according to I/D-bit and S-bit.
l
I/D: Increment / decrement of DDRAM address (cursor/blink) after each byte data access.
I/D = "1", cursor/blink moves to right and DDRAM address is increased by 1.
I/D = "0", cursor/blink moves to left and DDRAM address is decreased by 1.
* CGRAM operation is the same as DDRAM. CGRAM address is automatically adjusted according I/D bit after each
byte access.
l
S: Shift of entire display.
When writes to DDRAM and the S bit is "H", the “Screen” (entire display) shifts instead of the cursor moves. The shift
direction is controlled by the I/D-bit after each byte wrote:
I/D = "1", display shift left;
I/D = "0", display shift right.
When reads from DDRAM (CGRAM: read/write) or the S bit is "L", the shift of entire display is not performed.
* CGRAM operation is not affected by this feature.
Refer to Figure 10, Figure 12, Figure 14 and the following table for detailed information.
Ver 1.1
S
I/D
Description
H
H
Shift the display to the left
H
L
Shift the display to the right
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Display Control
Set Display and Cursor mode.
l
D: Display ON/OFF control bit.
D = "1", the display is turned on.
D = "0", the display is turned off, but display data is remained in DDRAM.
l
C: Cursor ON/OFF control bit.
C = "1", cursor is turned on.
C = "0", cursor is disappeared from current display, but I/D register remains its data.
l
B: Cursor Blink ON/OFF control bit.
B = "1", cursor blink is on. The display on the cursor position will alternate between all-black and the character.
B = "0", blink is off.
Function Set
l
DL: Interface data length control bit. It selects parallel 8-bit or 4-bit interface mode.
When DL = "1", use parallel 8-bit bus to communicate with MPU.
When DL = "0", use parallel 4-bit bus to communicate with MPU.
When using parallel 4-bit bus mode, each instruction needs to be transfer twice, including this instruction.
l
IS[1:0]: Selects instruction table.
When IS[1:0]=(0,0): Normal instruction is selected(refer instruction table 0).
When IS[1:0]=(0,1): Extension instruction is selected(refer instruction table 1 ).
When IS[1:0]=(1,0): Extension instruction is selected(refer instruction table 2 ).
When IS[1:0]=(1,1): Do not use !!
Set DDRAM Address
This instruction sets DDRAM address into AC. This instruction makes DDRAM data available for MPU access.
l
N2=0, N1=0: 1-Line display mode, the valid DDRAM address is from "00H" to "4FH".
l
N2=0, N1=1: 2-Line display mode, the valid DDRAM address will be:
st
1 Line: "00H" to "27H";
2
l
nd
Line: “40H" to "67H".
N2=1, N1=don’t care: 3-Line display mode, the valid DDRAM address will be:
st
1 Line: “00H” to “0FH”;
2
nd
Line: “10H” to “1FH”;
rd
3 Line: “20H” to “2FH”.
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ST7038
Read Status
BF: Busy Flag
When BF is “H”, it indicates that the internal operation is processing. So the next instruction(s) cannot be accepted until
2
BF=”L”. Be sure to check BF bit before issuing next instruction. In serial interface mode (including I C mode), please use
delay to avoid the next instruction conflict with the internal operation.
AC: Address Counter
In parallel interface modes the Address Counter (AC) can be read by MPU on DB6~DB0. The AC stores DDRAM/CGRAM
address which is transferred from IR. After each byte access (read/write) with DDRAM/CGRAM, AC is adjusted by 1
automatically (increase or decrease is controlled by the setting of Entry Mode).
Write Data to CGRAM, DDRAM or ICON RAM
This operation writes binary 8-bit data to CGRAM, DDRAM or ICON RAM. The selection of RAM (DDRAM, CGRAM or ICON
RAM) is controlled by the previous “Set xxxxx Address” instruction (Set DDRAM Address, Set CGRAM Address, Set ICON
RAM Address).
RAM set instruction can also determine the AC direction to RAM.
After write operation, the address is adjusted by 1 automatically (increase or decrease is controlled by the setting of Entry
Mode).
Read Data from DDRAM, CGRAM or ICON RAM
This operation reads binary 8-bit data from DDRAM, CGRAM or ICON RAM. The selection of RAM (DDRAM, CGRAM or
ICON RAM) is controlled by the previous “Set xxxxx Address” instruction. Make sure the selected RAM (DDRAM, CGRAM or
ICON RAM) is correct before read data operation.
Instruction Table 0, IS[1:0]=(0,0)
Cursor or Display Shift
This instruction is different from the “Entry Mode Set” instruction. The shift is performed immediately right after receiving this
instruction. The data search or data correction in applications can be easily achieved by using screen and cursor shift.
S/C
Ver 1.1
R/L
Description
AC Value
L
L
Shift cursor left.
AC=AC-1
L
H
Shift cursor right.
AC=AC+1
H
L
H
H
Shift Screen (current display) left.
Cursor follows the screen to shift left.
Shift Screen (current display) right.
Cursor follows the screen to shift right.
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AC=AC
AC=AC
2007/01/25
ST7038
l
S/C: Selects Cursor or Screen to perform the shift function.
S/C=”H”: The Screen (current display) is selected to shift. The direction is controlled by R/L bit;
S/C=”L”: The Cursor is selected to shift. The direction is controlled by R/L bit.
l
R/L: Selects the shift direction.
R/L=”H”: The shift direction is toward Right;
R/L=”L”: The shift direction is toward Left.
Cursor Shift
When display line mode is more than 1-Line, the cursor will move to the first position on the next line if AC reaches the last
valid address. If the line address is at the last line, the cursor will shift to the first position on the first line.
Screen Shift
The screen shift is performed simultaneously on each line in all kinds of display line mode. Each line is shifted individually.
The content kept in AC is not changed when performing Screen Shift operation.
Set CGRAM Address
This instruction sets CGRAM address into AC. This instruction makes CGRAM data available for MPU access.
Instruction Table 1, IS[1:0]=(0,1)
Follower Control
BS[2:1]
Bias level selection
(0,0)
Select 1/4 Bias
(0,1)
Select 1/5 Bias
(1,0)
Select 1/6 Bias
(1,1)
Select 1/7 Bias
OPF[2:1]
Follower circuit selection
(0,0)
Select built-in Follower
(0,1)
Select built-in bias resistor (9.9K)
(1,0)
Select built-in bias resistor (3.3K)
(1,1)
Select external bias circuit (built-in Follower is OFF)
Set ICON RAM Address
This instruction sets ICON RAM address into AC. This instruction makes ICON data available for MPU access. The valid
ICON RAM address is from "00H" to "0FH", when IS[1:0]=(0,1).
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ST7038
V0 Control 1 & 2
V0 Control 1
V0 Control 2
l
PD: Set Power Down Mode ON/OFF.
PD=”H”: Enter Power Down Mode;
PD=”L”: Exit Power Down Mode.
l
VC[6:0]: Set V0 voltage. Please refer to “POWER SUPPLY FOR LCD ” section for more detailed information.
VC6
VC5
VC4
VC3
VC2
VC1
VC0
V0 (V)
0
0
0
0
0
0
0
2.000
0
0
0
0
0
0
1
2.024
0
0
0
0
0
1
0
2.048
0
0
0
0
0
1
1
2.071
:
:
:
:
:
:
:
:
1
1
1
1
1
0
0
4.952
1
1
1
1
1
0
1
4.976
1
1
1
1
1
1
0
5.000
1
1
1
1
1
1
1
5.024
ICON/Power Control
Setting
ION
BON
RON
FON
H
ICON display: ON
Built-in Booster: ON
Built -in Regulator: ON
Built -in Follower: ON
L
ICON display: OFF
Built -in Booster: OFF
Built -in Regulator: OFF
Built -in Follower: OFF
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Instruction Table 2, IS[1:0]=(1,0)
Set Display Mode
UD: Select double height font display position on screen. This bit is only valid when N2=0, N1=1 and DH=1.
l
UD=”H”: Double height font is displayed on COM1~COM16;
UD=”L”: Double height font is displayed on COM9~COM24.
DH=0, N2=1 & UD=X (don`t care): 3-Line normal display mode
DH=1, N2=0, N1=1 & UD=0: COM1~8 is normal, COM9~24 is double height
DH=1, N2=0, N1=1 & UD=1: COM17~24 is normal,COM1~16 is double height
DH: Display double height font (5X16 dot-matrix) control bit.
l
Please refer to the following table for detailed setting and description.
DH
L
UD
X
N2=0, N1=0 (1-Line)
N2=0, N1=1 (2-Line)
N2=1, N1=X (3-Line)
Normal Display
Normal Display
Normal Display
DDRAM: 00H~27H
DDDRAM: 00H~0FH
DDRAM: 00H~4FH
COM1~16: Double Height
H
H
H
L
COM17~24: Normal Display
Double Height (COM1~16)
DDDRAM: 00H~0FH
DDRAM: 00H~27H
COM1~8: Normal Display
Do NOT use
COM9~24: Double Height
DDDRAM: 00H~0FH
Ver 1.1
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For example, the normal height font and the doubled height font are shown as below.
2 line mode normal display (DH=0, N2=0, N1=1)
1 line mode with double height font (DH=1, N2=0, N1=0)
l
N[2,1]: Control the “Display Line Number”.
ST7038 has 17-common and 100-segment LCD driving signals as default. If operated in 1-Line Display mode, the
used common pads are COM1~COM8 and COMI (for ICON). If operated in 3-Line Display mode, some segments will
be used as commons. Please refer to Table 9 or the “Pad Location Coordinates” section for more detailed information.
N2
N1
Display Mode
0
0
1-Line Display mode
0
1
2-Line Display mode
1
X
3-Line Display mode
Table 10
l
N[2,1] vs. Display Line Number
Complete Display Modes:
UD
DH
N2
N1
Display Mode Description
Duty
X
0
0
0
1-Line Display mode
1/(8+1)
X
1
0
0
1-Line Display mode, double height
1/(16+1)
X
0
0
1
2-Line Display mode
1/(16+1)
1
1
0
1
2-Line Display mode, double height (UP)
1/(24+1)
0
1
0
1
2-Line Display mode, double height (DOWN)
1/(24+1)
X
X
1
X
3-Line Display mode
1/(24+1)
Select CGRAM & COM/SEG direction
l
OPR2, OPR1:
Select CGROM size. The CGROM stores 256 characters. The first 16 characters can be replaced by CGRAM data
(customized pattern). By setting OPR2 and OPR1, the CGROM pattern will be changed as shown in Table 7. The used
character numbers are shown below:
Ver 1.1
OPR2
OPR1
CGROM
CGRAM
0
0
240
8
0
1
248
8
1
0
250
6
1
1
256
0
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l
SHLS: (Pin definition is NOT changed when SHLS=0)
SHLS=1: SEG1~100
←Column address 0~99 (Normal)
SHLS=0: SEG100~1
←Column address 99~0 (Invert)
* Pin definition of SEG is NOT changed when SHLS=0
* 3-Line Display Mode uses only 80 segments.
l
SHLC: (Pin definition is changed when SHLC=0)
SHLC=1: COM1~24
←Row address 0~23 (Normal)
SHLC=0: COM1~24
←Row address 23~0 (Invert)
* Pin definition of COM is changed when SHLC=0
* Please refer to Table 9 for the detailed output map.
Set Frame Rate
FR[2:0]: Set Frame Rate according the table below:
Ver 1.1
FR2
FR1
FR0
Frame Rate (Hz)
0
0
0
65.35±15%
0
0
1
68.03±15%
70.92±10%
0
1
0
0
1
1
74.07±15%
1
0
0
77.52±15%
1
0
1
111.1±15%
1
1
0
120.5±15%
1
1
1
131.6±15%
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(Default)
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ST7038
MPU INTERFACE
The ST7038 supports various kinds of MPU interface to communicate with MPU: Parallel 4-bit 6800/8080-series, Parallel
2
8-bit 6800/8080-series, Serial 3/4-Line SPI and I C operation. The following figures are referential circuits connected with
different kinds of MPU.
The microprocessor interface pins (CSB, /WR, /RD, A0 and D7~D0) should not be left floating in any operation mode.
l
Intel 8051 interface: 4-Bit parallel (6800-series)
l
Intel 8051 interface: 4 Bit parallel (8080-series)
l
Intel 8051 interface: 8 Bit parallel (6800-series)
l
Intel 8051 interface: 8 Bit parallel (8080-series)
Ver 1.1
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l
Intel 8051 interface: Serial 4-line SPI
l
Intel 8051 interface: Serial 3-line SPI
l
Intel 8051 interface: Serial I C
Ver 1.1
2
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INITIALIZATION
Initial Flow
POWER ON and external reset
Wait time >40mS
After VDD stable
Contrast set
Function set
RS
0
R/W
0
RS
0
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
0
0
1
DL
X
X
IS1 IS0
R/W
0
Wait time >32.4μS
Wait time >32.4μS
Power/Contrast Set
Function set
RS
0
R/W
0
RS
0
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
0
0
1
DL
X
X
IS1 IS0
R/W
0
Internal OSC frequency
R/W
0
Bias Set/Built-in voltage follower circuit
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
FRC FR2 FR1 FR0
0
1
0
1
RS
0
R/W
0
Wait time >32.4μS
R/W
0
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
OPF2
OPF1
BS2
BS1
0
0
0
1
Wait time >32.4μS
Function set
RS
0
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
0
1
0
1
PD VC6 VC5 VC4
Wait time >32.4μS
Wait time >32.4μS
RS
0
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
0
1
1
1
VC3 VC2 VC1 VC0
ICON/Power Ser
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
0
0
1
DL
X
X
IS1 IS0
RS
0
R/W
0
Wait time >32.4μS
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
Bon
Ron
Fon
0
1
1
0
Ion
Wait time >200mS
(for power stable)
Display ON/OFF control
RS
0
R/W
0
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
0
0
0
0
1
D
C
B
Wait time >32.4μS
Initialization end
Ver 1.1
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Initial Code (8051 MPU, Parallel 8-bit Interface)
;---------------------------------------------------------------------------------
MOV
INITIAL_START:
RET
CALL
HARDWARE_RESET
;---------------------------------------------------------------------------------
CALL
DELAY40mS
MOV
WRINS_NOCHK
CALL
DELAY40uS
MOV
CHK_BUSY:
A,#32H
CALL
WRINS_NOCHK
CALL
DELAY40uS
MOV
CLR
;FUNCTION SET
;8 bit,
A,#32H
CALL
P1,#FFH
;Check Busy Flag
RS
SETB
RW
SETB
E
JB
;FUNCTION SET
CLR
;8 bit,
;For Check Busy Flag
P1.7,$
E
RET
A,#54H
;Internal OSC frequency
adjustment
CALL
WRINS_CHK
CALL
DELAY40uS
MOV
A,#31H
CALL
WRINS_CHK
CALL
DELAY40uS
MOV
A,#7FH
CALL
WRINS_CHK
CALL
DELAY40uS
MOV
A,#53H
CALL
WRINS_CHK
CALL
DELAY40uS
MOV
A,#14H
CALL
WRINS_CHK
CALL
DELAY40uS
MOV
A,#67H
CALL
WRINS_CHK
CALL
DELAY200mS
MOV
A,#0CH
CALL
WRINS_CHK
CALL
DELAY40uS
MOV
A,#01H
CALL
WRINS_CHK
CALL
DELAY2mS
;FUNCTION SET
;8 bit,
;Contrast set
;Power down/Contrast set
; Bias/Follwer set
; ICON/Power(B,R,F) set
;for power stable
;DISPLAY ON
;CLEAR DISPLAY
;--------------------------------------------------------------------------------MAIN_START:
XXXX
XXXX
XXXX
;--------------------------------------------------------------------------------WRINS_CHK:
CALL
CHK_BUSY
WRINS_NOCHK:
CLR
RS
;EX:Port 3.0
CLR
RW
;EX:Port 3.1
SETB
E
MOV
P1,A
CLR
E
Ver 1.1
;EX:Port 3.2
;EX:Port 1=Data Bus
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ST7038
Initial Code (8051 MPU, Serial 4-line SPI Interface)
;-------------------------------------------------------------------
PUSH
INITIAL_START:
ANL
A,#F0H
INITIAL_START:
CLR
RS
CALL
HARDWARE_RESET
CLR
RW
CALL
DELAY40mS
SETB
E
MOV
A,#22H
CALL
WRINS_NOCHK
CALL
DELAY40uS
MOV
A,#22H
CALL
WRINS_NOCHK
CALL
DELAY40uS
A
;FUNCTION SET
MOV
P1,A
;8 bit,
CLR
E
POP
A
SWAP
A
;FUNCTION SET
;EX:Port 3.0
;EX:Port 3.1
;EX:Port 3.2
;EX:Port1=Data Bus
WRINS_ONCE:
;8 bit,
ANL
A,#F0H
CLR
RS
adjustment
CLR
RW
CALL
WRINS_CHK
SETB
E
CALL
DELAY40uS
MOV
P1,A
CLR
E
MOV
P1,#FFH ;For Check Bus Flag
MOV
MOV
A,#54H
A,#21H
CALL
WRINS_CHK
CALL
DELAY40uS
MOV
;Internal OSC frequency
A,#7FH
;FUNCTION SET
;8 bit,
RET
;-------------------------------------------------------------------
;Contrast set
CALL
WRINS_CHK
CHK_BUSY:
CALL
DELAY40uS
PUSH
A
MOV
P1,#FFH
MOV
A,#53H
CALL
WRINS_CHK
CALL
DELAY40uS
MOV
A,#14H
;Power down/Contrast set
$1
; Bias/Follwer set
CLR
RS
SETB
RW
CALL
WRINS_CHK
SETB
E
CALL
DELAY40uS
MOV
A,P1
CLR
E
MOV
P1,#FFH
CLR
RS
SETB
RW
E
MOV
A,#67H
CALL
WRINS_CHK
CALL
DELAY200mS
MOV
A,#0CH
; ICON/Power(B,R,F) set
;for power stable
;DISPLAY ON
CALL
WRINS_CHK
SETB
CALL
DELAY40uS
NOP
MOV
A,#01H
;Check Busy Flag
CLR
;CLEAR DISPLAY
CALL
WRINS_CHK
JB
CALL
DELAY2mS
POP
E
A.7,$1
A
RET
;------------------------------------------------------------------MAIN_START:
XXXX
XXXX
XXXX
.
.
.
.
.
;------------------------------------------------------------------WRINS_CHK:
CALL
CHK_BUSY
WRINS_NOCHK:
Ver 1.1
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2007/01/25
ST7038
Initial Code (8051 MPU, Parallel 4-bit Interface)
;---------------------------------------------------------------------------------
RLC
A
INITIAL_START:
MOV
SI,C
CALL
HARDWARE_RESET
SET
SCL
CALL
DELAY40mS
MOV
NOP
A,#32H
CALL
WRINS_NOCHK
CALL
DELAY40uS
MOV
;FUNCTION SET
;8 bit,
A,#32H
CALL
WRINS_NOCHK
CALL
DELAY40uS
MOV
CLR
SCL
DJNZ
R1,$1
POP
1
CALL
DLY1.5mS
;FUNCTION SET
;8 bit,
RET
A,#54H
;Internal OSC frequency
adjustment
CALL
WRINS_NOCHK
CALL
DELAY40uS
MOV
CALL
A,#31H
WRINS_NOCHK
CALL
A,#7FH
DELAY40uS
MOV
A,#53H
;Power down/Contrast set
WRINS_NOCHK
CALL
DELAY40uS
MOV
A,#14H
CALL
WRINS_NOCHK
CALL
DELAY40uS
MOV
A,#67H
CALL
WRINS_NOCHK
CALL
DELAY200mS
MOV
CALL
;Contrast set
WRINS_NOCHK
CALL
CALL
;8 bit,
DELAY40uS
MOV
CALL
;FUNCTION SET
A,#0CH
; Bias/Follwer set
; ICON/Power(B,R,F) set
;for power stable
;DISPLAY ON
WRINS_NOCHK
CALL
MOV
DELAY40uS
A,#01H
CALL
WRINS_NOCHK
CALL
DELAY2mS
;CLEAR DISPLAY
;--------------------------------------------------------------------------------MAIN_START:
XXXX
XXXX
XXXX
XXXX
.
.
;--------------------------------------------------------------------------------WRINS_NOCHK:
PUSH
1
MOV R1,#8
CLR
RS
$1
Ver 1.1
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2007/01/25
ST7038
LCD & ST7038 CONNECTION
SHLC/SHLS bits can select different scan direction for LCD panel.
1 & 2-Line Display Mode
l
COM normal direction, SEG normal direction
(SHLC=1, SHLS=1)
l
COM normal direction, SEG reverse direction
(SHLC=1, SHLS=0)
l
COM reverse direction, SEG normal direction
(SHLC=0, SHLS=1)
l
COM reverse direction, SEG reverse direction (SHLC=0, SHLS=0)
3-Line Display Mode
l
COM normal direction, SEG normal direction
l
COM normal direction, SEG reverse direction
(SHLC=1, SHLS=1)
3 line x 16 characters, SHLC=1 SHLS=1
(SHLC=1, SHLS=0)
3 line x 16 characters, SHLC=1, SHLS=0
Ver 1.1
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ST7038
l
COM reverse direction, SEG normal direction
(SHLC=0, SHLS=1)
l
COM reverse direction, SEG reverse direction (SHLC=0, SHLS=0)
3 line x 16 characters, SHLC=0, SHLS=1
3 line x 16 characters, SHLC=0, SHLS=0
Ver 1.1
43/61
2007/01/25
ST7038
POWER SUPPLY FOR LCD DRIVER
Built-in Booster circuit:
The voltage booster uses analog power (VDD2) to generate boosted voltage. The boost stage is controlled by hardware
connection. Please refer to the following figure for the detailed booster circuit connection.
Built-in Regulator circuit:
The built-in Regulator circuit is shown below, where the Vref = 1.47V.
VC6
VC5
VC4
VC3
VC2
VC1
VC0
V0 (V)
0
0
0
0
0
0
0
2.000
0
0
0
0
0
0
1
2.024
0
0
0
0
0
1
0
2.048
0
0
0
0
0
1
1
2.071
:
:
:
:
:
:
:
:
1
1
1
1
1
0
0
4.952
1
1
1
1
1
0
1
4.976
1
1
1
1
1
1
0
5.000
1
1
1
1
1
1
1
5.024
Notes:
l
VOUT ≧ V0 ≧ V1 ≧ V2 ≧ V3 ≧ V4 ≧ Vss must be maintained.
l
If the calculation value of V0 is higher than VOUT, the real V0 value will saturate to VOUT.
l
Internal built-in booster can only be used when OPF1=0,OPF2=0.
l
To keep V0 level stable, be sure the voltage level of VOUT is higher than V0 by at least 0.5V
(even displaying the heaviest-loading pattern).
If the panel size is larger than 3”, the recommend VOUT should be higher than V0 by at least 0.8V
(even displaying the heaviest-loading pattern).
Ver 1.1
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ST7038
Built-in Follower circuit:
There are 3 kinds of built-in Follower circuits. By instruction, the follower can be configured to be:
OPF[2:1]
Description
(0,0)
Select built-in Follower
(0,1)
Select built-in bias resistor (9.9K)
(1,0)
Select built-in bias resistor (3.3K)
(1,1)
Select external bias circuit (built-in Follower is OFF)
Note:
l
When using built-in bias resistors (9.9K or 3.3K), the current consumption maybe larger than using built-in Follower.
Furthermore, the loading of built-in Booster is increasing too. That will cause the Booster efficiency drop and V0 maybe
affected.
Referential Power Connection:
When using internal Booster, Regulator and Follower, the referential connection is shown below.
1.8V~3.3V
C1
VSS
VDD/VDD2
VOUT
V0
OPEN CAP4P
CAP2P
ST7038
OPEN CAP2N
V1
V2
V3
CAP1N
V4
CAP1P
VSS
VOP
C1
OPEN CAP3P
2X Booster, Regulator & Follower
Note:
l
If LCD panel size is larger than 2”, a V0 capacitor is recommended.
If LCD panel size is larger than 3”, 4 Follower capacitors (V1~V4) are recommended.
l
When VDD2<2.4V, the Booster efficiency maybe lower and the ITO resistance should be lower to solve this problem.
Ver 1.1
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ST7038
ABSOLUTE LIMITING VALUES
VSS is 0V unless otherwise specified.
Symbol
Value
Unit
Digital Power Supply Voltage
Characteristics
VDD
-0.3 ~ 3.6
V
Analog Power Supply Voltage
VDD2
-0.3 ~ 3.6
V
VIN
-0.3 ~ VDD+0.5
V
VOUT, V0
-0.3 ~12
V
V1, V2, V3 & V4
-0.3 ~ 12
Interface Input Voltage
Apply on : CSB, RESB, A0, /WR, /RD, D7~D0
LCD Driver Voltage (Booster & Regulator)
LCD Driver Voltage (Follower)
Operating Temperature
TOPR
Storage Temperature
TSTO
V
-30 ~ +85
o
C
-65 ~ +150
o
C
VOUT
V0 ~ V4
VDD
VDD
VSS
VSS
VSS
System (MPU) Side
ST7038 Chip Side
Notes:
1.
Stresses over the Limiting Values may cause permanent damage to the device.
2.
Parameters are valid over operating temperature range unless otherwise specified. All voltages are relative to VSS
3.
Ensure that the voltage levels of V1, V2, V3 and V4 always follow the rule below:
unless otherwise noted.
VOUT ≧ V0 ≧ V1 ≧ V2 ≧ V3 ≧ V4 ≧ VSS
Ver 1.1
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2007/01/25
ST7038
DC CHARACTERISTICS
VSS is 0V unless otherwise specified.
Characteristics
Symbol
Test Condition
Min.
Typ.
Max.
Unit
Operating Voltage
VDD, VDD2
-
1.65
-
3.3
V
LCD Voltage
V0
V0-Vss
3.0
-
12.0
V
-
160
230
uA
-
-
10
uA
Power Supply Current
IDD
Sleep Mode
IDD
Input High Voltage
VDD=3.0V *
1
(use internal power circuit)
VDD=3.0V
(use internal power circuit)
VIH1
-
0.8 VDD
-
VDD
V
VIL1
-
- 0.3
-
0.2 VDD
V
VIH2
-
0.8 VDD
-
VDD
V
VIL2
-
-
-
0.2 VDD
V
VOH1
IOH = -1.5mA
1.4
-
-
V
VOL1
IOL = 2.0mA
-
-
0.66
V
Common Resistance
RCOM
V0 = 4V, Id = 0.05mA
-
2
20
K
(Except OSC1)
Input Low Voltage
(Except OSC1)
Input High Voltage
(OSC1)
Input Low Voltage
(OSC1)
Output High Voltage
(DB0 - DB7)
Output Low Voltage
(DB0 - DB7)
Segment Resistance
RSEG
V0 = 4V, Id = 0.05mA
-
2
30
K
Input Leakage Current
ILEAK
VDD = 0V to VDD
-1
-
1
A
Pull Up MOS Current
IPUP
VDD = 3V
150
-
-
uA
Internal OSC
fOSC
VDD = 3V, 1/25duty
Frame frequency
FR
FRC=0, Ta=25 C
o
-
370.5
407.6
kHz
-
70.92
78.01
Hz
Notes: When the XRESET Pin is “L”, there is a temporary current over (5mA).
Ver 1.1
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2007/01/25
ST7038
AC CHARACTERISTICS
6800 Interface
o
Ta = -30 ~ 85 C
Item
Address hold time
Address setup time
System cycle time
Signal
RS
E
Data setup time
Data hold time
Access time
D0 to D7
Output disable time
Enable Rise/Fall time
Enable H pulse time
Enable L pulse time
Symbol
VDD=1.8V
VDD=3.3V
Max.
Min.
Max.
Min.
Max.
tAH6
20
-
15
-
15
-
tAW6
20
-
15
-
15
-
tCYC6
240
-
150
-
120
-
tDS6
150
-
80
-
60
-
tDH6
20
-
15
-
15
-
tACC6
-
320
-
260
-
240
tOH6
200
-
130
-
100
-
tr,tf
E
VDD=2.5V
Min.
Units
ns
ns
ns
ns
20
-
20
-
20
ns
tEWH
210
-
120
-
90
-
ns
tEWL
30
-
30
-
30
-
ns
Note: All timing is specified using 20% and 80% of VDD as the reference.
Ver 1.1
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2007/01/25
ST7038
8080 Interface
o
Ta = -30 ~ 85 C
Item
Signal
Symbol
VDD=1.8V
VDD=2.5V
VDD=3.3V
Min.
Max.
Min.
Max.
Min.
Max.
tAH8
80
-
30
-
30
-
tAW8
0
-
0
-
0
-
tCYC8
240
-
190
-
150
-
Enable L pulse width (WRITE)
tCCLW
180
-
140
-
110
-
Enable H pulse width (WRITE)
tCCHW
20
-
20
-
20
-
tCCLR
180
-
140
-
110
-
tCCHR
20
-
20
-
20
-
Address hold time
Address setup time
System cycle time
Enable L pulse width (READ)
RS
/WR
D0 to D7
Enable H pulse width (READ)
WRITE Data setup time
WRITE Data hold time
READ access time, CL= 100 pF
READ Output disable time,
CL = 100 pF
Units
ns
ns
ns
ns
tDS8
120
-
80
-
70
-
ns
tDH8
80
-
50
-
50
-
ns
Read
tACC8
-
240
-
220
-
180
ns
Read
tOH8
120
-
-
100
-
80
ns
/WR
Note: All timing is specified using 20% and 80% of VDD as the reference.
Ver 1.1
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2007/01/25
ST7038
Serial 4-Line Interface
o
Ta = -30 ~ 85 C
Item
Signal
Serial Clock Period
SCL “H” pulse width
SCL
SCL “L” pulse width
Address setup time
Address hold time
Data setup time
Data hold time
CS-SCL time
RS
SI
CSB
Symbol
VDD=1.8V
VDD=2.5V
VDD=3.3V
Min.
Max.
Min.
Max.
Min.
Max.
tSCYC
180
-
110
-
80
-
tSHW
70
-
40
-
40
-
tSLW
80
-
50
-
40
-
tSAS
10
-
10
-
10
-
tSAH
60
-
40
-
30
-
tSDS
20
-
20
-
20
-
tSDH
10
-
10
-
10
-
tCSS
20
-
20
-
20
-
tCSH
210
-
120
-
90
-
Units
ns
ns
ns
ns
Note: All timing is specified using 20% and 80% of VDD as the reference.
Ver 1.1
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ST7038
Serial 3-Line Interface
o
Ta = -30 ~ 85 C
VDD=1.8V
Item
Signal
VDD=3.3V
Units
Min.
Serial Clock Period
VDD=2.5V
Symbol
Max.
Min.
Max.
Min.
Max.
tSCYC
200
-
100
-
80
-
tSHW
70
-
40
-
30
-
SCL “L” pulse width
tSLW
100
-
50
-
40
-
Data setup time
tSDS
20
-
20
-
20
-
tSDH
10
-
10
-
10
-
tCSS
70
-
40
-
20
-
tCSH
200
-
100
-
80
-
SCL “H” pulse width
Data hold time
CS-SCL time
SCL
SI
CSB
ns
ns
ns
Note: All timing is specified using 20% and 80% of VDD as the reference.
Ver 1.1
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ST7038
Serial I2C Interface
o
Ta = -30 ~ 85 C
Item
SCL clock frequency
SCL clock low period
SCL clock high period
Data set-up time
Data hold time
SCL,SDA rise time
SCL,SDA fall time
Capacitive load represent by
each bus line
Setup time for a repeated
START condition
Start condition hold time
Setup time for STOP condition
Bus free time between a Stop
and START condition
Symb Conditio
Signal
ol
n
SCL
SDA
fSCLK
tLOW
tHIGH
tSU;DAT
—
—
VDD=1.8V
VDD=2.5V
VDD=3.3V
Rating
Rating
Rating
Units
Min.
Max.
Min.
Max.
Min.
Max.
DC
1.3
0.6
300
0
—
—
400
—
—
—
400
—
—
—
KHz
0.9
300
300
DC
1.3
0.6
100
0
—
—
400
—
—
—
0.9
300
300
DC
1.3
0.6
200
0
—
—
0.9
300
300
us
us
ns
SCL,
SDA
tHD:DAT
tr
tf
—
Cb
—
—
400
—
400
—
400
pf
tSU;STA
—
0.7
—
0.6
—
0.6
—
us
—
tHD;STA
tSU;STO
—
—
0.6
0.6
—
—
0.6
0.6
—
—
0.6
0.6
—
—
us
us
SCL
tBUF
—
1.3
—
1.3
—
1.3
—
us
SDA
—
ns
Note: All timing is specified using 20% and 80% of VDD as the reference.
Ver 1.1
52/61
2007/01/25
ST7038
Hardware Reset (XRESET)
Ver 1.1
53/61
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ST7038
LCD FRAME RATE
1.
1-Line Display Mode:
Assume the oscillation frequency is 284KHz (1 clock cycle time = 3.52us), 1/4 bias,
1/9 duty, 1 frame = 14.08ms = 71Hz (SHLC=1, SHLS=1).
1
COM1
V0
V1
V2 / V3
V4
VSS
COM2
V0
V1
V2 / V3
V4
VSS
COMI
V0
V1
V2 / V3
V4
VSS
SEGx
V0
V1
V2 / V3
V4
VSS
SEGx
V0
V1
V2 / V3
V4
VSS
2
3
4
7
8
1
2
3
4
7
8
1
2
3
4
7
8
1 Frame
Ver 1.1
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2007/01/25
ST7038
2.
2-Line or 1-Line Double Height Display Mode:
Assume the oscillation frequency is 249.7KHz (1 clock cycle time = 4us), 1/5 bias,
1/17 duty, 1 frame = 14.42ms = 69.36Hz (SHLC=1, SHLS=1).
COMI
V0
V1
V2
V3
V4
VSS
SEGx
V0
V1
V2
V3
V4
VSS
SEGx
V0
V1
V2
V3
V4
VSS
4
15
16
1
2
3
4
15
16
1
2
3
4
15
16
ICON
COM2
V0
V1
V2
V3
V4
VSS
3
ICON
COM1
V0
V1
V2
V3
V4
VSS
2
ICON
1
1 Frame
Ver 1.1
55/61
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ST7038
3.
3-Line or 2-Line Double Height Display Mode:
Assume the oscillation frequency is 370.5KHz (1 clock cycle time = 2.70us), 1/6 bias,
1/25 duty, 1 frame = 14.04ms = 71.25Hz (SHLC=1, SHLS=1).
4
23
24
1
2
3
4
23
24
1
2
3
4
23
24
ICON
3
ICON
2
ICON
1
V0
V1
V2
COM1
V3
V4
VSS
V0
V1
V2
COM2
V3
V4
VSS
COMI
V0
V1
V2
V3
V4
VSS
SEGx
V0
V1
V2
V3
V4
VSS
SEGx
V0
V1
V2
V3
V4
VSS
1 Frame
Ver 1.1
56/61
2007/01/25
ST7038
I/O PAD CONFIGURATION
VDD
PMOS
NMOS
Input PAD (No Pull up):
RS, R/W, XRESET, CSB,
CLS
VDD
VDD
VDD
Enable
PMOS
PMOS
NMOS
PMOS
Data
NMOS
I/O PAD:
DB0-DB7
Ver 1.1
57/61
2007/01/25
ST7038
APPLICATION CIRCUIT
l
6800 series 8-bit Interface:
VSS
VDD
RS
CSB
RW
E
DB0
DB1
DB2
DB3
DB4
DB5
DB6
DB7
RST
Ver 1.1
58/61
2007/01/25
ST7038
l
8080 series 8-bit Interface:
VSS
VDD
RS
CSB
/WR
/RD
DB0
DB1
DB2
DB3
DB4
DB5
DB6
DB7
RST
Ver 1.1
59/61
2007/01/25
ST7038
l
2
I C Interface:
Ver 1.1
60/61
2007/01/25
ST7038
Reversion History
Version
Date
1.0
2006/08/03
1.1
Ver 1.1
2007/01/25
Description
Release Version
1.
Modify minimum operation VDD range to 1.65V.
2.
Remove reversion history before Ver 1.0.
3.
Redraw Timing Figures.
61/61
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