SITRONIX ST7032

ST
Sitronix
ST7032
Dot Matrix LCD Controller/Driver
n Features
l
l
l
l
l
l
l
l
l
l
5 x 8 dot matrix possible
Low power operation support:
-- 2.7 to 5.5V
Range of LCD driver power
-- 3.0 to 7.0V
4-bit, 8-bit, serial MPU or 400kbits/s fast
2
I C-bus interface are available
80 x 8-bit display RAM (80 characters max.)
10,240-bit character generator ROM for a
total of 256 character fonts(max)
64 x 8-bit character generator RAM(max)
16-common x 80-segment and 1-common x
80-segment ICON liquid crystal display
driver
16 x 5 –bit ICON RAM(max)
l
l
l
l
l
l
l
Wide range of instruction functions:
Display clear, cursor home, display on/off,
cursor on/off, display character blink, cursor
shift, display shift, double height font
Automatic reset circuit that initializes the
controller/driver after power on and external
reset pin
Internal oscillator(Frequency=540KHz) and
external clock
Built-in voltage booster and follower circuit
(low power consumption )
Com/Seg direction selectable
Multi-selectable for CGRAM/CGROM size
Instruction compatible to ST7066U and
KS0066U and HD44780
Available in COG type
n Description
The ST7032 dot-matrix liquid crystal display controller can
display alphanumeric, Japanese kana characters, and
symbols. It can be configured to drive a dot-matrix liquid
crystal display under the control of a 4 / 8-bit with
6800-series or 8080-series, 3/4-line serial interface
microprocessor. Since all the functions such as display
RAM, character generator ROM/RAM and liquid crystal
driver, required for driving a dot-matrix liquid crystal display
are internally provided on one chip, a minimal system can
be used with this controller/driver.
The ST7032 character generator ROM size is 256 5x8dot
bits which can be used to generate 256 different character
fonts (5x8dot).
The ST7032 is suitable for low voltage supply (2.7V to
5.5V) and is perfectly suitable for any portable product
which is driven by the battery and requires low power
consumption.
The ST7032 LCD driver consists of 17 common signal
drivers and 80 segment signal drivers. The maximum
display RAM size can be either 80 characters in 1-line
display or 40 characters in 2-line display. A single ST7032
can display up to one 16-character line or two 16-character
lines.
The ST7032 dot-matrix LCD driver does not need extra
cascaded drivers.
n Product Number
ST7032 supports various function for customer. Please specify correct product number for application:
For example, “ST7032–0D” the first part is illustrated below and the second part is the identification code of the built-in
character generation ROM. Please refer to the appendix for the character generation ROM code information.
ST7032
6800-4bit / 8bit, 4-Line interface
(without IIC interface)
ST7032i
IIC interface
Sitronix Technology Corp. reserves the right to change the contents in this document without prior notice.
V1.4
1/61
2008/08/18
ST7032
Version
V1.4
ST7032 Serial Specification Revision History
Date
Description
1.0
2003/3/24
1.1
2003/8/27
1.2
2005/10/17
1.2a
2006/05/23
1.3
2007/11/09
1.4
2008/08/18
1. Change “Version 0.1y-Preliminary” to “Version 1.0”
2. Modify Bias resistor value
3. Modify OSC frequency table
4. Adding Serial interface flow chart & example code
5. Adding “E” connection state for serial interface
1. Include ST7032i
1. To modify Operating Temperature Range Ta=-30°C to 85°C
2. To modify Storage Temperature Range Ta=-65°C to 150°C
3. To modify the vlcd voltage Range 3.0v~7.0v
4. To modify the limiting values -0.3v~+6.0v
5. To add Chip Thickness: 480 um
1. Modify description mistake (Page 1)
1. Add appendix section for Character Generation ROM.
2. Move ROM table to appendix.
Update I/O PAD Circuit
2/61
2008/08/18
ST7032
n Pad Dimensions
54
1
152
55
Center on
(2100,185)
(0,0)
Center on
(-2470,-445)
Center on
(2470, -445)
68
139
69
138
35μm
35μm
30μm
30μm
30μm
30μm
30μm
30μm
30μm
40μm
30μm
30μm
35μm
30μm
Ø Chip Size: 5130.0 x 1080.0μm
Ø Chip Thickness: 480μm
Ø Bump Pitch : 62μm(min)
Ø Bump Height : 17μm(Typ)
Ø Bump Size :
l Pad No.1~54 : 54 x 97μm
l Pad No.55~152 : 40 x 97μm
V1.4
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ST7032
n Pad Location Coordinates
Pad No.
Function
X
Y
Pad No.
Function
X
Y
1
XRESET
2165.5
420.5
41
EXT
-874.5
420.5
2
OSC1
2089.5
420.5
42
VSS
-950.5
420.5
3
OSC2
2013.5
420.5
43
CLS
-1026.5
420.5
4
RS
1937.5
420.5
44
CAP1N
-1102.5
420.5
5
CSB
1861.5
420.5
45
CAP1N
-1178.5
420.5
6
RW
1785.5
420.5
46
VOUT
-1254.5
420.5
7
E
1709.5
420.5
47
VOUT
-1330.5
420.5
8
DB0
1633.5
420.5
48
V0
-1406.5
420.5
9
DB1
1557.5
420.5
49
V0
-1482.5
420.5
10
DB2
1481.5
420.5
50
V1
-1558.5
420.5
11
DB3
1405.5
420.5
51
V2
-1634.5
420.5
12
DB4
1329.5
420.5
52
V3
-1710.5
420.5
13
DB5
1253.5
420.5
53
V4
-1786.5
420.5
14
DB6
1177.5
420.5
54
NC
-1862.5
420.5
15
DB7
1101.5
420.5
55
COM[8]
-2445.5
423
16
VSS
1025.5
420.5
56
COM[7]
-2445.5
361
17
VSS
949.5
420.5
57
COM[6]
-2445.5
299
18
VSS
873.5
420.5
58
COM[5]
-2445.5
237
19
OPF1
797.5
420.5
59
COM[4]
-2445.5
175
20
OPF2
721.5
420.5
60
COM[3]
-2445.5
113
21
OPR1
645.5
420.5
61
COM[2]
-2445.5
51
22
OPR2
569.5
420.5
62
COM[1]
-2445.5
-11
23
SHLC
493.5
420.5
63
COMI1
-2445.5
-73
24
SHLS
417.5
420.5
64
SEG[1]
-2445.5
-135
25
VDD
341.5
420.5
65
SEG[2]
-2445.5
-197
26
VDD
265.5
420.5
66
SEG[3]
-2445.5
-259
27
VDD
189.5
420.5
67
SEG[4]
-2445.5
-321
28
VIN
113.5
420.5
68
SEG[5]
-2445.5
-383
29
VIN
37.5
420.5
69
SEG[6]
-2130.5
-420.5
30
TEST1
-38.5
420.5
70
SEG[7]
-2068.5
-420.5
31
TEST2
-114.5
420.5
71
SEG[8]
-2006.5
-420.5
32
VSS
-190.5
420.5
72
SEG[9]
-1944.5
-420.5
33
NC
-266.5
420.5
73
SEG[10]
-1882.5
-420.5
34
VOUT
-342.5
420.5
74
SEG[11]
-1820.5
-420.5
35
VOUT
-418.5
420.5
75
SEG[12]
-1758.5
-420.5
36
PSB
-494.5
420.5
76
SEG[13]
-1696.5
-420.5
37
VSS
-570.5
420.5
77
SEG[14]
-1634.5
-420.5
38
PSI2B
-646.5
420.5
78
SEG[15]
-1572.5
-420.5
39
CAP1P
-722.5
420.5
79
SEG[16]
-1510.5
-420.5
40
CAP1P
-798.5
420.5
80
SEG[17]
-1448.5
-420.5
V1.4
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ST7032
Pad No.
Function
X
Y
Pad No.
Function
X
Y
81
SEG[18]
-1386.5
-420.5
121
SEG[58]
1093.5
-420.5
82
SEG[19]
-1324.5
-420.5
122
SEG[59]
1155.5
-420.5
83
SEG[20]
-1262.5
-420.5
123
SEG[60]
1217.5
-420.5
84
SEG[21]
-1200.5
-420.5
124
SEG[61]
1279.5
-420.5
85
SEG[22]
-1138.5
-420.5
125
SEG[62]
1341.5
-420.5
86
SEG[23]
-1076.5
-420.5
126
SEG[63]
1403.5
-420.5
87
SEG[24]
-1014.5
-420.5
127
SEG[64]
1465.5
-420.5
88
SEG[25]
-952.5
-420.5
128
SEG[65]
1527.5
-420.5
89
SEG[26]
-890.5
-420.5
129
SEG[66]
1589.5
-420.5
90
SEG[27]
-828.5
-420.5
130
SEG[67]
1651.5
-420.5
91
SEG[28]
-766.5
-420.5
131
SEG[68]
1713.5
-420.5
92
SEG[29]
-704.5
-420.5
132
SEG[69]
1775.5
-420.5
93
SEG[30]
-642.5
-420.5
133
SEG[70]
1837.5
-420.5
94
SEG[31]
-580.5
-420.5
134
SEG[71]
1899.5
-420.5
95
SEG[32]
-518.5
-420.5
135
SEG[72]
1961.5
-420.5
96
SEG[33]
-456.5
-420.5
136
SEG[73]
2023.5
-420.5
97
SEG[34]
-394.5
-420.5
137
SEG[74]
2085.5
-420.5
98
SEG[35]
-332.5
-420.5
138
SEG[75]
2147.5
-420.5
99
SEG[36]
-270.5
-420.5
139
SEG[76]
2445.5
-383
100
SEG[37]
-208.5
-420.5
140
SEG[77]
2445.5
-321
101
SEG[38]
-146.5
-420.5
141
SEG[78]
2445.5
-259
102
SEG[39]
-84.5
-420.5
142
SEG[79]
2445.5
-197
103
SEG[40]
-22.5
-420.5
143
SEG[80]
2445.5
-135
104
SEG[41]
39.5
-420.5
144
COM[9]
2445.5
-73
105
SEG[42]
101.5
-420.5
145
COM[10]
2445.5
-11
106
SEG[43]
163.5
-420.5
146
COM[11]
2445.5
51
107
SEG[44]
225.5
-420.5
147
COM[12]
2445.5
113
108
SEG[45]
287.5
-420.5
148
COM[13]
2445.5
175
109
SEG[46]
349.5
-420.5
149
COM[14]
2445.5
237
110
SEG[47]
411.5
-420.5
150
COM[15]
2445.5
299
111
SEG[48]
473.5
-420.5
151
COM[16]
2445.5
361
112
SEG[49]
535.5
-420.5
152
COMI2
2445.5
423
113
SEG[50]
597.5
-420.5
114
SEG[51]
659.5
-420.5
115
SEG[52]
721.5
-420.5
116
SEG[53]
783.5
-420.5
117
SEG[54]
845.5
-420.5
118
SEG[55]
907.5
-420.5
119
SEG[56]
969.5
-420.5
120
SEG[57]
1031.5
-420.5
V1.4
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ST7032
n Block Diagram
OSC1 OSC2
XRESET
Reset
circuit
CLS
Instruction
register(IR)
Instruction
decoder
RS
RW
E
CSB
Address
counter
(AC)
EXT
16-bit
shift
register
Common
signal
driver
80-bit
shift
register
80-bit
latch
circuit
Segment
signal
driver
Data
register
(DR)
DB4 to
DB7
SHLC
SHLS
Display data
RAM
(DDRAM)
80x8 bits
MPU
interface
PSB
PSI2B
DB0 to
DB3
Timing
generator
CPG
Input/
output
buffer
Busy
flag
ICON RAM
80 bits
COMI
SEG1 to
SEG80
V0~V4
LCD drive
voltage
follower
Character
generator RAM
(CGRAM)
64 bytes
COM1 to
COM16
Character
generator ROM
(CGROM)
10.240 bits
Cursor
and
blink
controller
Voltage
booster
circuit
VOUT
VIN
CAP1P
CAP1N
OPR1,2
OPF1,2
VSS
Parallel/serial converter
and
attribute circuit
VDD
V1.4
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ST7032
n Pin Function
Name
Number
I/O Interfaced with
XRESET
1
I
MPU
RS
1
I
MPU
R/W
1
I
MPU
E
1
I
MPU
CSB
1
I
MPU
DB4 to DB7
4
I/O
MPU
DB0 to DB3
4
I/O
MPU
Ext
1
I
ITO option
PSB
1
I
MPU
PSI2B
OPR1,
OPR2
V1.4
1
2
I
I
ITO option
ITO option
Function
External reset pin. Only if the power on reset used, the
XRESET pin must be fixed to VDD.
Low active.
Select registers.
0: Instruction register (for write)
Busy flag & address counter (for read)
1: Data register (for write and read)
Select read or write (In parallel mode).
0: Write
1: Read
Starts data read/write. (“E” must connect to “VDD” when
serial interface is selected.)
Chip select in parallel mode and serial interface (Low
active).When the CSB in falling edge state (in serial
interface), the shift register and the clock counter are reset.
Four high order bi-directional data bus pins. Used for data
transfer and receive between the MPU and the ST7032.
DB7 can be used as a busy flag. In serial interface mode
DB7 is SI (input data), DB6 is SCL (serial clock).
2
In I C interface DB7 (SDA) is input data and DB6 (SCL) is
clock input.
2
2
SDA and SCL must connect to I C bus (I C bus is to connect
2
a resister between SDA/SCL and the power of I C bus ).
Four low order bi-directional data bus pins. Used for data
transfer and receive between the MPU and the ST7032.
These pins are not used during 4-bit operation.
Extension instruction select:
0:enable extension instruction(add contrast/ICON/double
height font/ extension instruction)
1:disable extension instruction(compatible to ST7066U, but
without 5x11dot font)
Interface selection
0:serial mode
(“E” must connect to “VDD” when serial mode is selected.)
1:parallel mode(4/8 bit)
2
In I C interface PSB must connect to VDD
PSB
PSI2B
Interface
0
0
No use
0
1
SI4
2
1
0
SI2 (I C )
1
1
Parallel 68
Character generator select:
OPR1
OPR2
CGROM
0
0
240
0
1
250
1
0
248
1
1
256
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CGRAM
8
6
8
0
2008/08/18
ST7032
Name
Number
SHLC
1
I/O Interfaced with
Function
Common signals direction select:
I
ITO option
0:Com1~16←Row address 15~0(Invert)
1:Com1~16←Row address 0~15(Normal)
Segment signals direction select:
SHLS
1
I
ITO option
0:Seg1~80←Column address 79~0(Invert)
1:Seg1~80←Column address 0~79(Normal)
COM1 to
COM16
COMI
SEG1 to
SEG80
Common signals that are not used are changed to
16
O
LCD
non-selection waveform. COM9 to COM16
are non-selection waveforms at 1/8 or 1/9 duty factor
2
O
LCD
ICON common signals
80
O
LCD
Segment signals
The built-in voltage follower circuit selection
OPF1 OPF2
OPF1
OPF2
2
I
ITO option
CAP1P
1
-
Power supply
CAP1N
1
-
Power supply
VIN
1
-
Power supply
VOUT
1
-
Power supply
0
0
Bias select
Built-in voltage follower(only use at EXT=0)
0
1
Built-in bias resistor(3.3KΩ) ±30%
1
0
Built-in bias resistor(9.6KΩ) ±30%
1
1
External bias resistor select
For voltage booster circuit(VDD-VSS)
External capacitor about 0.1u~4.7uf
Input the voltage to booster
DC/DC voltage converter. Connect a capacitor between this
terminal and VIN when the built-in booster is used.
Power supply for LCD drive
V0 to V4
5
-
Power supply
V0-Vss = 7V (Max)
Built-in/external Voltage follower circuit
VDD
VSS
2
-
Power supply
I
ITO option
VDD : 2.7V to 5.5V, VSS: 0V
Internal/External oscillation select
CLS
0:external clock
1:internal oscillation
OSC1
OSC2
TEST1,2
V1.4
2
I/O
Oscillation
2
I/O
Test pin
When the pin input is an external clock, it must be input to
OSC1.
TEST1,2 must connect to VDD.
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ST7032
n EXT option pin difference table
ST7066U normal mode (EXT=1)
Booster
Always OFF
Extension mode (EXT=0)
ON/OFF control by instruction
Can’t use the follower circuit
Bias (V0~V4)
Only use external resistor or internal resistor(1/5 Follower or internal/external resistor selectable
bias)
1. Control by instruction with follower
Contrast adjust
Control by external VR
2. Control by external VR with internal/external
resistor
ICON RAM
Can’t be use
RAM size has 80 bit width (S1~S80).
Instruction
Control normal instruction similar to ST7066U.
Double height font
Only 5x8 font
consumption.
Can set 5x8 or 5x16 font
OSC frequency adjust Only adjust by external clock.
V1.4
Control extension instruction for low power
Can set OSC frequency by instruction set.
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ST7032
n Function Description
l System Interface
2
This chip has all four kinds of interface type with MPU: 4-bit bus, 8-bit bus, serial and fast I C interface. 4-bit bus
or 8-bit bus is selected by DL bit in the instruction register.
During read or write operation, two 8-bit registers are used. One is data register (DR); the other is instruction
register (IR).
The data register (DR) is used as temporary data storage place for being written into or read from
DDRAM/CGRAM/ICON RAM, target RAM is selected by RAM address setting instruction. Each internal
operation, reading from or writing into RAM, is done automatically. So to speak, after MPU reads DR data, the
data in the next DDRAM/CGRAM/ICON RAM address is transferred into DR automatically. Also after MPU writes
data to DR, the data in DR is transferred into DDRAM/CGRAM/ICON RAM automatically.
The Instruction register (IR) is used only to store instruction code transferred from MPU. MPU cannot use it to
read instruction data.
Using RS input pin to select command or data in 4-bit/8-bit bus mode.
RS R/W
L
L
L
H
H
H
L
H
Operation
Instruction Write operation (MPU writes Instruction code
into IR)
Read Busy Flag(DB7) and address counter (DB0 ~ DB6)
Data Write operation (MPU writes data into DR)
Data Read operation (MPU reads data from DR)
Table 1. Various kinds of operations according to RS and R/W bits.
2
I C interface
It just only could write Data or Instruction to ST7032 by the IIC Interface.
It could not read Data or Instruction from ST7032 (except Acknowledge signal).
SCL: serial clock input
SDA: serial data input
Slaver address could only set to 0111110, no other slaver address could be set
2
2
The I C interface send RAM data and executes the commands sent via the I C Interface. It could send data bit to the RAM.
2
The I C Interface is two-line communication between different ICs or modules. The two lines are a Serial Data line (SDA)
and a Serial Clock line (SCL). Both lines must be connected to a positive supply via a pull-up resistor. Data transfer may be
initiated only when the bus is not busy.
BIT TRANSFER
One data bit is transferred during each clock pulse. The data on the SDA line must remain stable during the HIGH period of
the clock pulse because changes in the data line at this time will be interpreted as a control signal. Bit transfer is illustrated
in Fig.1.
START AND STOP CONDITIONS
Both data and clock lines remain HIGH when the bus is not busy. A HIGH-to-LOW transition of the data line, while the clock
is HIGH is defined as the START condition (S). A LOW-to-HIGH transition of the data line while the clock is HIGH is defined
as the STOP condition (P). The START and STOP conditions are illustrated in Fig.2.
SYSTEM CONFIGURATION
The system configuration is illustrated in Fig.3.
· Transmitter: the device, which sends the data to the bus
· Master: the device, which initiates a transfer, generates clock signals and terminates a transfer
· Slave: the device addressed by a master
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ST7032
· Multi-Master: more than one master can attempt to control the bus at the same time without corrupting the message
· Arbitration: procedure to ensure that, if more than one master simultaneously tries to control the bus, only one is allowed to
do so and the message is not corrupted
· Synchronization: procedure to synchronize the clock signals of two or more devices.
ACKNOWLEDGE
Acknowledge is not Busy Flag in I2C interface.
Each byte of eight bits is followed by an acknowledge bit. The acknowledge bit is a HIGH signal put on the bus by the
transmitter during which time the master generates an extra acknowledge related clock pulse. A slave receiver which is
addressed must generate an acknowledge after the reception of each byte. A master receiver must also generate an
acknowledge after the reception of each byte that has been clocked out of the slave transmitter. The device that
acknowledges must pull-down the SDA line during the acknowledge clock pulse, so that the SDA line is stable LOW during
the HIGH period of the acknowledge related clock pulse (set-up and hold times must be taken into consideration). A master
receiver must signal an end-of-data to the transmitter by not generating an acknowledge on the last byte that has been
clocked out of the slave. In this event the transmitter must leave the data line HIGH to enable the master to generate a STOP
2
condition. Acknowledgement on the I C Interface is illustrated in Fig.4.
SDA
SCL
data line
stable;
data valid
change
of data
allowed
Figure 1. Bit transfer
SDA
SCL
S
P
START con dition
STOP con dition
Figure 2. Definition of START and STOP conditions
MASTER
TRANSMITTER/
RECEIVER
SLAVE
RECEIVER (1)
0111100
SLAVE
RECEIVER (2)
0111101
SLAVE
RECEIVER (3)
0111110
SLAVE
RECEIVER (4)
0111111
SDA
SCL
Figure 3. System configuration
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ST7032
DATA OUTPUT
BY TRANSMITTER
not acknowledge
DATA OUTPUT
BY RECEIVER
acknowledge
SCL FROM
MASTER
1
2
8
S
9
clock pulse for
acknowledge ment
START
condition
Figure 4. Acknowledgement on the 2-line Interface
2
I C Interface protocol
The ST7032 supports command, data write addressed slaves on the bus.
2
Before any data is transmitted on the I C Interface, the device, which should respond, is addressed first. Only one 7-bit
slave addresses (0111110) is reserved for the ST7032. The R/W is assigned to 0 for Write only.
2
The I C Interface protocol is illustrated in Fig.5.
2
The sequence is initiated with a START condition (S) from the I C Interface master, which is followed by the slave address.
2
All slaves with the corresponding address acknowledge in parallel, all the others will ignore the I C Interface transfer. After
acknowledgement, one or more command words follow which define the status of the addressed slaves.
A command word consists of a control byte, which defines Co and RS, plus a data byte.
The last control byte is tagged with a cleared most significant bit (i.e. the continuation bit Co). After a control byte with a
cleared Co bit, only data bytes will follow. The state of the RS bit defines whether the data byte is interpreted as a command
or as RAM data. All addressed slaves on the bus also acknowledge the control and data bytes. After the last control byte,
depending on the RS bit setting; either a series of display data bytes or command data bytes may follow. If the RS bit is set
to logic 1, these display bytes are stored in the display RAM at the address specified by the data pointer. The data pointer is
automatically updated and the data is directed to the intended ST7032i device. If the RS bit of the last control byte is set to
logic 0, these command bytes will be decoded and the setting of the device will be changed according to the received
2
commands. Only the addressed slave makes the acknowledgement after each byte. At the end of the transmission the I C
INTERFACE-bus master issues a STOP condition (P).
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ST7032
Write mode
acknowledgement
from ST7032i
S 0 1 1 1 1 1 0 0 A 1
slave address
R
S
acknowledgement
from ST7032i
control byte
acknowledgement
from ST7032i
data byte
A
2n>=0bytes
command word
0 1 1 1 1 1 0
1
control byte
acknowledgement
from ST7032i
data byte
A
A P
n>=0bytes
MSB.......................LSB
Co
R
/
W
Co
slave address
0
R
S
1 byte
R/W
Co
Co
A 0
acknowledgement
from ST7032i
R
S
0 0 0 0 0 0
control byte
D D D D D D D D
7 6 5 4 3 2 1 0
data byte
Figure 5. 2-line Interface protocol
Last control byte to be sent. Only a stream of data bytes is allowed to follow.
This stream may only be terminated by a STOP condition.
Another control byte will follow the data byte unless a STOP condition is received.
During write operation, two 8-bit registers are used. One is data register (DR), the other is instruction register
(IR).
The data register (DR) is used as temporary data storage place for being written into DDRAM/CGRAM/ICON
RAM, target RAM is selected by RAM address setting instruction. Each internal operation, writing into RAM, is
done automatically. So to speak, after MPU writes data to DR, the data in DR is transferred into
DDRAM/CGRAM/ICON RAM automatically.
The Instruction register (IR) is used only to store instruction code transferred from MPU. MPU cannot use it to
read instruction data.
2
To select register, use RS input in I C interface.
RS R/W
L
L
H
L
Operation
Instruction Write operation (MPU writes Instruction code
into IR)
Data Write operation (MPU writes data into DR)
Table 2. Various kinds of operations according to RS and R/W bits.
l Busy Flag (BF)
When BF = "High”, it indicates that the internal operation is being processed. So during this time the next
instruction cannot be accepted. BF can be read, when RS = Low and R/W = High (Read Instruction Operation),
through DB7 port. Before executing the next instruction, be sure that BF is not High.
l Address Counter (AC)
Address Counter (AC) stores DDRAM/CGRAM/ICON RAM address, transferred from IR.
After writing into (reading from) DDRAM/CGRAM/ICON RAM, AC is automatically increased (decreased) by 1.
When RS = "Low" and R/W = "High", AC can be read through DB0 ~ DB6 ports.
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ST7032
l
Display Data RAM (DDRAM)
Display data RAM (DDRAM) stores display data represented in 8-bit character codes. Its extended capacity is 80
x 8 bits, or 80 characters. The area in display data RAM (DDRAM) that is not used for display can be used as
general data RAM. See Figure 7 for the relationships between DDRAM addresses and positions on the liquid
crystal display.
The DDRAM address (ADD ) is set in the address counter (AC)as hexadecimal.
Ø
1-line display (N = 0) (Figure 8)
When there are fewer than 80 display characters, the display begins at the head position. For example, if
using only the ST7032, 16 characters are displayed. See Figure 8.
When the display shift operation is performed, the DDRAM address shifts. See Figure 9.
High order bits
Low order bits
Example : DDRAM Address 4F
1
AC6 AC5 AC4 AC3 AC2 AC1 AC0
0
0
1
1
1
1
Figure 7. DDRAM Address
Display Position (digit)
1
DDRAM Address 00
2
3
4
5
6
78 79 80
01 02 03 04 05
........
4D 4E 4F
Figure 8. 1-Line Display
Display Position
1
2
3
4
16
DDRAM Address
00 01 02 03
....
0F
For Shift Left
01 02 03 04
....
10
For Shift Right
4F 00 01 02
....
0E
Figure 9. 1-Line by 16-Character Display Example
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ST7032
Ø
2-line display (N = 1) (Figure 10)
Case 1: When the number of display characters is less than 40 2 lines, the two lines are displayed from the
head. Note that the first line end address and the second line start address are not consecutive. See Figure
10.
Display Position
1
DDRAM Address
(hexadecimal)
2
3
4
5
6
38 39 40
00 01 02 03 04 05
........
25 26 27
40 41 42 43 44 45
........
65 66 67
Figure 10. 2-Line Display
Case 2: For a 16-character 2-line display See Figure 11.
When display shift operation is performed, the DDRAM address shifts. See Figure 11.
Display
Position
DDRAM
Address
For Shift
Left
For Shift
Right
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16
00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F
40 41 42 43 44 45 46 47 48 49 4A 4B 4C 4D 4E 4F
01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F 10
41 42 43 44 45 46 47 48 49 4A 4B 4C 4D 4E 4F 50
27 00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E
67 40 41 42 43 44 45 46 47 48 49 4A 4B 4C 4D 4E
Figure 11. 2-Line by 16-Character Display Example
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ST7032
l Character Generator ROM (CGROM)
The character generator ROM generates 5 x 8 dot character patterns from 8-bit character codes. It can generate
240/250/248/256 5 x 8 dot character patterns (select by OPR1/2 ITO pin). User-defined character patterns are
also available by mask-programmed ROM.
l Character Generator RAM (CGRAM)
In the character generator RAM, the user can rewrite character patterns by program. For 5 x 8 dots, eight
character patterns can be written.
Write into DDRAM the character codes at the addresses shown as the left column of code table (refer to
appendix) to show the character patterns stored in CGRAM.
See Table 4 for the relationship between CGRAM addresses and data and display patterns. Areas that are not
used for display can be used as general data RAM.
l ICON RAM
In the ICON RAM, the user can rewrite icon pattern by program.
There are totally 80 dots for icon can be written.
See Table 5 for the relationship between ICON RAM address and data and the display patterns.
l Timing Generation Circuit
The timing generation circuit generates timing signals for the operation of internal circuits such as
DDRAM, CGROM and CGRAM. RAM read timing for display and internal operation timing by MPU
access are generated separately to avoid interfering with each other. Therefore, when writing data to
DDRAM, for example, there will be no undesirable interference, such as flickering, in areas other than
2
the display area.(In I C interface the reading function is invalid.)
l LCD Driver Circuit
LCD Driver circuit has 17 common and 80 segment signals for LCD driving. Data from CGRAM/CGROM/ICON
is transferred to 80 bit segment latch serially, and then it is stored to 80 bit shift latch. When each common is
selected by 17 bit common register, segment data also output through segment driver from 80 bit segment latch.
l Cursor/Blink Control Circuit
It can generate the cursor or blink in the cursor/blink control circuit. The cursor or the blink appears in the digit at
the display data RAM address set in the address counter.
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ST7032
Character Code
(DDRAM Data)
b7 b6 b5 b4 b3 b2
0
0
0
0
0 0 0 0 0
0
0
0
0
0
0
0
0 0 0 0 0
0
0
0
b1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
CGRAM
Address
b0 b5 b4 b3 b2
0
0
0
0
0
0
0
0
0 0 0
0
1
0
1
0
1
0
1
1
0
1
0
1
0
1
0
0 0 1
1
1
1
1
1
1
1
1
b1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
Character Patterns
(CGRAM Data)
b0 b7 b6 b5 b4
0
1
1
0
0
0
1
0
- - 0
0
1
0
0
0
1
0
0
1
1
1
0
1
1
1
- - 0
1
1
1
0
1
1
0
b3
1
0
0
0
0
0
0
0
1
0
0
1
0
0
0
0
b2
1
1
1
1
1
1
1
0
1
0
0
1
1
0
0
0
b1
1
0
0
0
0
0
0
0
1
0
0
1
0
1
0
0
b0
1
0
0
0
0
0
0
0
0
1
1
0
0
0
1
0
Table 4. Relationship between CGRAM Addresses, Character Codes (DDRAM) and Character
patterns (CGRAM Data)
Notes:
1.
Character code bits 0 to 2 correspond to CGRAM address bits 3 to 5 (3 bits: 8 types).
2.
CGRAM address bits 0 to 2 designate the character pattern line position. The 8th line is the cursor position
and its display is formed by a logical OR with the cursor. Maintain the 8th line data, corresponding to the
cursor display position, at 0 as the cursor display. If the 8th line data is 1, 1 bit will light up the 8th line
regardless of the cursor presence.
3.
Character pattern row positions correspond to CGRAM data bits 0 to 4 (bit 4 being at the left).
4.
As shown Table 4, CGRAM character patterns are selected when character code bits 4 to 7 are all 0.
However, since character code bit 3 has no effect, the R display example above can be selected by either
character code 00H or 08H.
5.
“1” for CGRAM data corresponds to display selection and “0” to non-selection,“-“ Indicates no effect.
6.
Different OPR1/2 ITO option can select different CGRAM size.
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ST7032
When SHLS=1, ICON RAM map refer below table
ICON RAM bits
ICON address
D7
D6
D5
D4
D3
D2
D1
D0
00H
-
-
-
S1
S2
S3
S4
S5
01H
-
-
-
S6
S7
S8
S9
S10
02H
-
-
-
S11
S12
S13
S14
S15
03H
-
-
-
S16
S17
S18
S19
S20
04H
-
-
-
S21
S22
S23
S24
S25
05H
-
-
-
S26
S27
S28
S29
S30
06H
-
-
-
S31
S32
S33
S34
S35
07H
-
-
-
S36
S37
S38
S39
S40
08H
-
-
-
S41
S42
S43
S44
S45
09H
-
-
-
S46
S47
S48
S49
S50
0AH
-
-
-
S51
S52
S53
S54
S55
0BH
-
-
-
S56
S57
S58
S59
S60
0CH
-
-
-
S61
S62
S63
S64
S65
0DH
-
-
-
S66
S67
S68
S69
S70
0EH
-
-
-
S71
S72
S73
S74
S75
0FH
-
-
-
S76
S77
S78
S79
S80
When SHLS=0, ICON RAM map refer below table
ICON RAM bits
ICON address
D7
D6
D5
D4
D3
D2
D1
D0
00H
-
-
-
S80
S79
S78
S77
S76
01H
-
-
-
S75
S74
S73
S72
S71
02H
-
-
-
S70
S69
S68
S67
S66
03H
-
-
-
S65
S64
S63
S62
S61
04H
-
-
-
S60
S59
S58
S57
S56
05H
-
-
-
S55
S54
S53
S52
S51
06H
-
-
-
S50
S49
S48
S47
S46
07H
-
-
-
S45
S44
S43
S42
S41
08H
-
-
-
S40
S39
S38
S37
S36
09H
-
-
-
S35
S34
S33
S32
S31
0AH
-
-
-
S30
S29
S28
S27
S26
0BH
-
-
-
S25
S24
S23
S22
S21
0CH
-
-
-
S20
S19
S18
S17
S16
0DH
-
-
-
S15
S14
S13
S12
S11
0EH
-
-
-
S10
S9
S8
S7
S6
0FH
-
-
-
S5
S4
S3
S2
S1
Table 5. ICON RAM map
When ICON RAM data is filled the corresponding position displayed is described as the following table.
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ST7032
n Instructions
There are four categories of instructions that:
l Designate ST7032 functions, such as display format, data length, etc.
l Set internal RAM addresses
l Perform data transfer with internal RAM
l Others
Ø
instruction table at “Normal mode”
(When “EXT” option pin connect to VDD, the instruction set follow below table)
Instruction Code
Instruction
Description
RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
Clear Display
0
0
0
0
0
0
0
0
0
Return Home
0
0
0
0
0
0
0
0
1
Entry Mode
Set
0
0
0
0
0
0
0
1
I/D
Display
ON/OFF
0
0
0
0
0
0
1
D
C
Cursor or
Display Shift
0
0
0
0
0
1
Function Set
0
0
0
0
1
DL
Set CGRAM
0
0
0
1
Set DDRAM
address
0
0
1
Read Busy
flag and
address
Write data
to RAM
Read data
from RAM
0
1
1
0
1
1
S/C R/L
x
Instruction
Execution Time
OSC= OSC= OSC=
380KHz 540kHz 700KHz
Write "20H" to DDRAM. and set
1.08
0.76
0.59
ms
ms
ms
DDRAM address to "00H" from AC
Set DDRAM address to "00H" from
AC and return cursor to its original
1.08
0.76
0.59
x
ms
ms
ms
position if shifted. The contents of
DDRAM are not changed.
Sets cursor move direction and
specifies display shift. These
26.3 us 18.5 us 14.3 us
S
operations are performed during
data write and read.
D=1:entire display on
26.3 us 18.5 us 14.3 us
B C=1:cursor on
B=1:cursor position on
S/C and R/L:
Set cursor moving and display shift
26.3 us 18.5 us 14.3 us
x
control bit, and the direction, without
changing DDRAM data.
1
DL: interface data is 8/4 bits
N: number of line is 2/1
26.3 us 18.5 us 14.3 us
AC5 AC4 AC3 AC2 AC1 AC0
Set CGRAM address in address
counter
26.3 us 18.5 us 14.3 us
AC6 AC5 AC4 AC3 AC2 AC1 AC0
Set DDRAM address in address
counter
26.3 us 18.5 us 14.3 us
N
x
x
x
Whether during internal operation or
not can be known by reading BF.
0
0
0
BF AC6 AC5 AC4 AC3 AC2 AC1 AC0
The contents of address counter
can also be read.
Write data into internal RAM
26.3 us 18.5 us 14.3 us
D7 D6 D5 D4 D3 D2 D1 D0
(DDRAM/CGRAM)
Read data from internal RAM
26.3 us 18.5 us 14.3 us
D7 D6 D5 D4 D3 D2 D1 D0
(DDRAM/CGRAM)
Note:
Be sure the ST7032 is not in the busy state (BF = 0) before sending an instruction from the MPU to the ST7032.
If an instruction is sent without checking the busy flag, the time between the first instruction and next instruction
will take much longer than the instruction time itself. Refer to Instruction Table for the list of each instruction
execution time.
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Ø
instruction table at “Extension mode”
(when “EXT” option pin connect to VSS, the instruction set follow below table)
Instruction Code
Instruction
Description
RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
Clear
Display
0
0
0
0
0
0
0
0
0
Return
Home
0
0
0
0
0
0
0
0
1
Entry Mode
Set
0
0
0
0
0
0
0
1
I/D
Display
ON/OFF
0
0
0
0
0
0
1
D
C
Function Set
0
0
0
0
1
DL
N
DH
*0
Set DDRAM
address
0
0
1
Instruction
Execution Time
OSC= OSC= OSC=
380KHz 540kHz 700KHz
Write "20H" to DDRAM. and set
1.08
0.76
0.59
ms
ms
ms
DDRAM address to "00H" from AC
Set DDRAM address to "00H" from
AC and return cursor to its original
1.08
0.76
0.59
x
ms
ms
ms
position if shifted. The contents of
DDRAM are not changed.
Sets cursor move direction and
specifies display shift. These
26.3 us 18.5 us 14.3 us
S
operations are performed during
data write and read.
D=1:entire display on
26.3 us 18.5 us 14.3 us
B C=1:cursor on
B=1:cursor position on
DL: interface data is 8/4 bits
N: number of line is 2/1
26.3 us 18.5 us 14.3 us
IS
DH: double height font
IS: instruction table select
1
AC6 AC5 AC4 AC3 AC2 AC1 AC0
Set DDRAM address in address
counter
26.3 us 18.5 us 14.3 us
Whether during internal operation or
not can be known by reading BF.
0
0
0
0
1
BF AC6 AC5 AC4 AC3 AC2 AC1 AC0
The contents of address counter
can also be read.
Write data
Write data into internal RAM
26.3 us 18.5 us 14.3 us
1
0
D7 D6 D5 D4 D3 D2 D1 D0
to RAM
(DDRAM/CGRAM/ICONRAM)
Read data
Read data from internal RAM
26.3 us 18.5 us 14.3 us
1
1
D7 D6 D5 D4 D3 D2 D1 D0
from RAM
(DDRAM/CGRAM/ICONRAM)
Note * : this bit is for test command , and must always set to “0”
Read Busy
flag and
address
Instruction table 0(IS=0)
Cursor or
Display Shift
0
0
0
0
Set CGRAM
0
0
0
1
S/C and R/L:
Set cursor moving and display shift
26.3 us 18.5 us 14.3 us
0
1 S/C R/L x
x
control bit, and the direction, without
changing DDRAM data.
Set CGRAM address in address
26.3 us 18.5 us 14.3 us
AC5 AC4 AC3 AC2 AC1 AC0
counter
Instruction table 1(IS=1)
Internal OSC
frequency
0
0
0
0
0
1
BS
Set ICON
address
0
0
0
1
0
0
AC3 AC2 AC1 AC0
Power/ICON
control/Contr
ast set
0
0
0
1
0
1
Ion Bon C5
Follower
control
0
0
0
1
1
0
Fon
Rab Rab Rab
2
1
0
Contrast set
0
0
0
1
1
1
C3
C2
V1.4
F2
F1
C1
F0
C4
C0
BS=1:1/4 bias
BS=0:1/5 bias
F2~0: adjust internal OSC
frequency for FR frequency.
Set ICON address in address
counter.
Ion: ICON display on/off
Bon: set booster circuit on/off
C5,C4: Contrast set for internal
follower mode.
Fon: set follower circuit on/off
Rab2~0:
select follower amplified ratio.
Contrast set for internal follower
mode.
20/61
26.3 us 18.5 us 14.3 us
26.3 us 18.5 us 14.3 us
26.3 us 18.5 us 14.3 us
26.3 us 18.5 us 14.3 us
26.3 us 18.5 us 14.3 us
2008/08/18
ST7032
n Instruction Description
l
Clear Display
RS R/W
0
0
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
0
0
0
0
0
0
0
1
Clear all the display data by writing "20H" (space code) to all DDRAM address, and set DDRAM address to
"00H" into AC (address counter). Return cursor to the original status, namely, bring the cursor to the left edge
on first line of the display. Make entry mode increment (I/D = "1").
l
Return Home
RS R/W
0
0
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
0
0
0
0
0
0
1
X
Return Home is cursor return home instruction. Set DDRAM address to "00H" into the address counter.
Return cursor to its original site and return display to its original status, if shifted. Contents of DDRAM do not
change.
l
Entry Mode Set
RS R/W
0
0
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
0
0
0
0
0
1
I/D
S
Set the moving direction of cursor and display.
Ø
I/D : Increment / decrement of DDRAM address (cursor or blink)
When I/D = "High", cursor/blink moves to right and DDRAM address is increased by 1.
When I/D = "Low", cursor/blink moves to left and DDRAM address is decreased by 1.
* CGRAM operates the same as DDRAM, when read from or write to CGRAM.
Ø
S: Shift of entire display
When DDRAM read (CGRAM read/write) operation or S = "Low", shift of entire display is not performed. If
S = "High" and DDRAM write operation, shift of entire display is performed according to I/D value (I/D = "1":
shift left, I/D = "0" : shift right).
V1.4
S
I/D
Description
H
H
Shift the display to the left
H
L
Shift the display to the right
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ST7032
l
Display ON/OFF
RS R/W
0
0
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
0
0
0
0
1
D
C
B
Control display/cursor/blink ON/OFF 1 bit register.
Ø
D : Display ON/OFF control bit
When D = "High", entire display is turned on.
When D = "Low", display is turned off, but display data is remained in DDRAM.
Ø
C : Cursor ON/OFF control bit
When C = "High", cursor is turned on.
When C = "Low", cursor is disappeared in current display, but I/D register remains its data.
Ø
B : Cursor Blink ON/OFF control bit
When B = "High", cursor blink is on, that performs alternate between all the high data and display
character at the cursor position.
When B = "Low", blink is off.
Alternating
display
Every
64 frames
Cursor
l
Cursor or Display Shift
RS R/W
0
Ø
0
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
0
0
0
1
S/C R/L
X
X
S/C: Screen/Cursor select bit
When S/C=”High”, Screen is controlled by R/L bit.
When S/C=”Low”, Cursor is controlled by R/L bit.
Ø
R/L: Right/Left
When R/L=”High”, set direction to right.
When R/L=”Low”, set direction to left.
Without writing or reading of display data, shift right/left cursor position or display. This instruction is used to
correct or search display data. During 2-line mode display, cursor moves to the 2nd line after 40th digit of 1st
line. Note that display shift is performed simultaneously in all the line. When displayed data is shifted
repeatedly, each line shifted individually. When display shift is performed, the contents of address counter are
not changed.
V1.4
S/C
R/L
Description
L
L
Shift cursor to the left
AC=AC-1
L
H
Shift cursor to the right
AC=AC+1
H
L
Shift display to the left. Cursor follows the display shift
AC=AC
H
H
Shift display to the right. Cursor follows the display shift AC=AC
22/61
AC Value
2008/08/18
ST7032
l
Function Set
RS R/W
0
Ø
0
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
0
0
1
DL
N
DH
0
IS
DL : Interface data length control bit
When DL = "High", it means 8-bit bus mode with MPU.
When DL = "Low", it means 4-bit bus mode with MPU. So to speak, DL is a signal to select 8-bit or 4-bit
bus mode.
When in 4-bit bus mode, it needs to transfer 4-bit data by two times.
Ø
N : Display line number control bit
When N = "High", 2-line display mode is set.
When N = "Low", it means 1-line display mode.
Ø
DH : Double height font type control bit
When DH = " High " and N= “Low”, display font is selected to double height mode(5x16 dot),RAM address
can only use 00H~27H.
When DH= “High” and N= “High”, it is forbidden.
When DH = " Low ", display font is normal (5x8 dot).
N
DH
L
L
H
H
L
H
L
H
EXT option pin connect to high EXT option pin connect to low
Display Lines Character Font Display Lines Character Font
1
1
2
2
5x8
5x8
5x8
5x8
1
1
2
5x8
5x16
5x8
Forbidden
2 line mode normal display (DH=0/N=1)
1 line mode with double height font (DH=1/N=0)
Ø
IS : normal/extension instruction select
When IS=” High”, extension instruction be selected (refer extension instruction table)
When IS=” Low”, normal instruction be selected (refer normal instruction table)
V1.4
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ST7032
l
Set CGRAM Address
RS R/W
0
0
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
0
1
AC5 AC4 AC3 AC2 AC1 AC0
Set CGRAM address to AC.
This instruction makes CGRAM data available from MPU.
l
Set DDRAM Address
RS R/W
0
0
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
1
AC6 AC5 AC4 AC3 AC2 AC1 AC0
Set DDRAM address to AC.
This instruction makes DDRAM data available from MPU.
When 1-line display mode (N = 0), DDRAM address is from "00H" to "4FH".
In 2-line display mode (N = 1), DDRAM address in the 1st line is from "00H" to "27H", and
DDRAM address in the 2nd line is from "40H" to "67H".
l
Read Busy Flag and Address
RS R/W
0
1
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
BF AC6 AC5 AC4 AC3 AC2 AC1 AC0
When BF = “High”, indicates that the internal operation is being processed. So during this time the next
instruction cannot be accepted.
The address Counter (AC) stores DDRAM/CGRAM addresses, transferred from IR.
After writing into (reading from) DDRAM/CGRAM, AC is automatically increased (decreased) by 1.
V1.4
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ST7032
l
Write Data to CGRAM,DDRAM or ICON RAM
RS R/W
1
0
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
D7
D6
D5
D4
D3
D2
D1
D0
Write binary 8-bit data to CGRAM, DDRAM or ICON RAM
The selection of RAM from DDRAM, CGRAM or ICON RAM, is set by the previous address set instruction
: DDRAM address set, CGRAM address set, ICON RAM address set. RAM set instruction can also determine
the AC direction to RAM.
After write operation, the address is automatically increased/decreased by 1, according to the entry mode.
l
Read Data from CGRAM,DDRAM or ICON RAM
RS R/W
1
1
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
D7
D6
D5
D4
D3
D2
D1
D0
Read binary 8-bit data from DDRAM/CGRAM/ICON RAM
The selection of RAM is set by the previous address set instruction. If address set instruction of RAM is not
performed before this instruction, the data that read first is invalid, because the direction of AC is not
determined. If you read RAM data several times without RAM address set instruction before read operation,
you can get correct RAM data from the second, but the first data would be incorrect, because there is no time
margin to transfer RAM data.
※Read data must be “set address” before this instruction.
V1.4
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ST7032
l
Bias selection/Internal OSC frequency adjust
RS R/W
0
Ø
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
0
0
0
0
1
BS
F2
F1
F0
BS: bias selection
When BS=”High”, the bias will be 1/4
When BS=”Low”, the bias will be 1/5
BS will be invalid when external bias resistors are used (OPF1=1, OPF2=1)
Ø
F2,F1,F0 : Internal OSC frequency adjust
When CLS connect to high, that instruction can adjust OSC and Frame frequency.
Frame frequency ( Hz )
(2 line mode)
VDD = 3.0 V
VDD = 5.0 V
F2
F1
F0
0
0
0
0
0
1
0
1
0
122
131
144
120
133
149
0
1
1
161
167
1
1
1
1
0
0
1
1
0
1
0
1
183
221
274
347
192
227
277
347
l
400
350
300
Frame(Hz)
Internal frequency adjust
250
200
150
100
50
0
0
1
2
3
4
5
Instruction Step
6
Set ICON RAM address
RS R/W
0
0
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
0
1
0
0
AC3 AC2 AC1 AC0
Set ICON RAM address to AC.
This instruction makes ICON data available from MPU.
When IS=1 at Extension mode,
The ICON RAM address is from "00H" to "0FH".
l
Power/ICON control/Contrast set(high byte)
RS R/W
0
Ø
0
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
0
1
0
1
ION BON C5
C4
Ion: set ICON display on/off
When Ion = "High", ICON display on.
When Ion = "Low", ICON display off.
Ø
Bon: switch booster circuit
Bon can only be set when internal follower is used (OPF1=0, OPF2=0).
When Bon = "High", booster circuit is turn on.
When Bon = "Low", booster circuit is turn off.
Ø
V1.4
C5,C4 : Contrast set(high byte)
C5,C4,C3,C2,C1,C0 can only be set when internal follower is used (OPF1=0,OPF2=0).They can more
precisely adjust the input reference voltage of V0 generator. The details please refer to the supply voltage
for LCD driver.
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7
ST7032
l
Follower control
RS R/W
0
Ø
0
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
Rab Rab Rab
0
1
1
0 FON
2
1
0
Fon: switch follower circuit
Fon can only be set when internal follower is used (OPF1=0,OPF2=0).
When Fon = "High", internal follower circuit is turn on.
When Fon = "Low", internal follower circuit is turn off.
Ø
Rab2,Rab1,Rab0 : V0 generator amplified ratio
Rab2,Rab1,Rab0 can only be set when internal follower is used (OPF1=0,OPF2=0).They can adjust the
amplified ratio of V0 generator. The details please refer to the supply voltage for LCD driver.
l
Contrast set(low byte)
RS R/W
0
Ø
0
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
0
1
1
1
C3
C2
C1
C0
C3,C2,C1,C0:Contrast set(low byte)
C5,C4,C3,C2,C1,C0 can only be set when internal follower is used (OPF1=0,OPF2=0).They can more
precisely adjust the input reference voltage of V0 generator. The details please refer to the supply voltage
for LCD driver.
V1.4
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ST7032
n Reset Function
Initializing by Internal Reset Circuit
An internal reset circuit automatically initializes the ST7032 when the power is turned on. The following
instructions are executed during the initialization. The busy flag (BF) is kept in the busy state (BF = 1) until the
initialization ends. The busy state lasts for 40 ms after VDD rises to stable.
1.
Display clear
2.
Function set:
DL = 1; 8-bit interface data
N = 0; 1-line display
DH=0; normal 5x8 font
IS=0; use instruction table 0
3.
Display on/off control:
D = 0; Display off
C = 0; Cursor off
B = 0; Blinking off
4.
Entry mode set:
I/D = 1; Increment by 1
S = 0; No shift
5.
Internal OSC frequency
(F2,F1,F0)=(1,0,0)
6.
ICON control
Ion=0; ICON off
7.
Power control
BS=0; 1/5bias
Bon=0; booster off
Fon=0; follower off
(C5,C4,C3,C2,C1,C0)=(1,0,0,0,0,0)
(Rab2,Rab1,Rab0)=(0,1,0)
Note:
If the electrical characteristics conditions listed under the table Power Supply Conditions Using
Internal Reset Circuit are not met, the internal reset circuit will not operate normally and will fail to initialize the
ST7032.
When internal Reset Circuit not operate, ST7032 can be reset by XRESET pin from MPU control signal.
V1.4
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ST7032
n Initializing by Instruction
l
8-bit Interface (fosc=380KHz)
POWER ON and external reset
Wait time >40mS
After VDD stable
Function set
RS
0
R/W
0
DB7
0
DB6 DB5 DB4
0
1
1
DB3 DB2 DB1
N
DH
X
DB0
IS
BF cannot be
checked before
this instruction.
DB0
IS
BF cannot be
checked before
this instruction.
Wait time >26.3μ S
Function set
RS
0
R/W
0
DB7
0
DB6 DB5 DB4
0
1
1
DB3 DB2 DB1
N
DH
X
Wait time >26.3μ S
Internal OSC frequency
RS
0
R/W
0
DB7
0
DB6 DB5 DB4
0
0
1
DB3 DB2 DB1
BS
F2
F1
DB0
F0
Wait time >26.3μ S
Contrast Set
RS
0
R/W
0
DB7
0
DB6 DB5 DB4
1
1
1
DB3 DB2 DB1
C3
C2
C1
DB0
C0
Wait time >26.3μ S
Power/ICON/Contrast control
RS
0
R/W
0
DB7
0
DB6 DB5 DB4
1
0
1
DB3 DB2 DB1
Bon
C5
Ion
DB0
C4
Wait time >26.3μ S
Follower control
RS
0
R/W
0
DB7
0
DB6 DB5 DB4
1
1
0
DB3 DB2 DB1
Fon Rab2 Rab1
DB0
Rab0
Wait time >200mS
(for power stable)
Display ON/OFF control
RS
0
R/W
0
DB7
0
DB6 DB5 DB4
0
0
0
DB3 DB2 DB1
1
D
C
DB0
B
Wait time >26.3μ S
Initialization end
V1.4
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ST7032
Ø
Initial Program Code Example For 8051 MPU(8 Bit Interface):
;--------------------------------------------------------------------------------INITIAL_START:
CALL HARDWARE_RESET
CALL DELAY40mS
MOV A,#38H
;FUNCTION SET
CALL WRINS_NOCHK ;8 bit,N=1,5*7dot
CALL DELAY30uS
MOV A,#39H
;FUNCTION SET
CALL WRINS_NOCHK ;8 bit,N=1,5*7dot,IS=1
CALL DELAY30uS
MOV A,#14H
;Internal OSC frequency adjustment
CALL WRINS_CHK
CALL DELAY30uS
MOV A,#78H
; Contrast control
CALL WRINS_CHK
CALL DELAY30uS
MOV A,#5EH
;Power/ICON/Contrast control
CALL WRINS_CHK
CALL DELAY30uS
MOV A,#6AH
;Follower control
CALL WRINS_CHK
CALL DELAY200mS
;for power stable
MOV A,#0CH
;DISPLAY ON
CALL WRINS_CHK
CALL DELAY30uS
MOV A,#01H
;CLEAR DISPLAY
CALL WRINS_CHK
CALL DELAY2mS
MOV A,#06H
;ENTRY MODE SET
CALL WRINS_CHK
;CURSOR MOVES TO RIGHT
CALL DELAY30uS
;--------------------------------------------------------------------------------MAIN_START:
XXXX
XXXX
XXXX
XXXX
;--------------------------------------------------------------------------------WRINS_CHK:
CALL CHK_BUSY
WRINS_NOCHK:
CLR
RS
;EX:Port 3.0
CLR
RW
;EX:Port 3.1
SETB E
;EX:Port 3.2
MOV P1,A
;EX:Port 1=Data Bus
CLR
E
MOV P1,#FFH
;For Check Busy Flag
RET
;--------------------------------------------------------------------------------CHK_BUSY:
;Check Busy Flag
CLR
RS
SETB RW
SETB E
JB
P1.7,$
CLR
E
RET
V1.4
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l
V1.4
4-bit Interface (fosc=380KHz)
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ST7032
Ø
Initial Program Code Example For 8051 MPU(4 Bit Interface):
;------------------------------------------------------------------.
INITIAL_START:
.
CALL HARDWARE_RESET
.
CALL DELAY40mS
.
MOV A,#38H
;FUNCTION SET
;------------------------------------------------------------------CALL WRINS_ONCE ;8 bit, 5*7 dot
WRINS_CHK:
CALL DELAY2mS
CALL CHK_BUSY
WRINS_NOCHK:
MOV A,#38H
;FUNCTION SET
PUSH A
CALL WRINS_ONCE
;8 bit, 5*7 dot
ANL A,#F0H
CALL DELAY30uS
CLR RS
;EX:Port 3.0
CLR RW
;EX:Port 3.1
MOV A,#38H
;FUNCTION SET
SETB E
;EX:Port 3.2
CALL WRINS_ONCE
;8 bit, 5*7 dot
MOV P1,A
;EX:Port1=Data Bus
CALL DELAY30uS
CLR E
POP A
CALL CHK_BUSY
SWAP A
MOV A,#28H
;FUNCTION SET
WRINS_ONCE:
CALL WRINS_ONCE
; 4 bit, 5*7 dot
ANL A,#F0H
CALL DELAY30uS
CLR RS
CLR RW
MOV A,#29H
;FUNCTION SET
SETB E
CALL WRINS_CHK
; 4 bit N = 1, 5*7 dot
MOV P1,A
CALL DELAY30uS
; IS = 1
CLR E
MOV P1,#FFH
;For Check Bus Flag
MOV A,#14H
;Internal OSC
RET
CALL WRINS_CHK
;------------------------------------------------------------------CALL DELAY30uS
CHK_BUSY:
;Check Busy Flag
PUSH A
MOV
A,#78H
;Contrast set
MOV P1,#FFH
CALL WRINS_CHK
$1
CALL DELAY30uS
CLR RS
SETB RW
MOV A,#5EH
;Power/ICON/Contrast
SETB E
CALL WRINS_CHK
MOV A,P1
CALL DELAY30uS
CLR E
MOV P1,#FFH
MOV A,#6AH
;Follower control
CLR RS
CALL WRINS_CHK
SETB RW
CALL DELAY200mS
;For power stable
SETB E
NOP
MOV A,#0CH
;DISPLAY ON
CLR E
CALL WRINS_CHK
JB
A.7,$1
CALL DELAY30uS
POP A
RET
MOV A,#01H
;CLEAR DISPLAY
CALL WRINS_CHK
CALL DELAY2mS
MOV A,#06H
;ENTRY MODE SET
CALL WRINS_CHK
CALL DELAY30uS
;------------------------------------------------------------------MAIN_START:
XXXX
XXXX
XXXX
.
V1.4
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l
Serial interface & IIC interface ( fosc = 380KHz )
POWER ON and external reset
Wait time >40mS
After VDD stable
Function set
RS
0
R/W
0
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
0
0
1
1
N
DH
0
IS
Wait time >26.3μ S
Function set
RS
0
R/W
0
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
0
0
1
1
N
DH
0
IS
Wait time >26.3μ S
Internal OSC frequency
RS
0
R/W
0
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
0
0
0
1
BS
F2
F1
F0
Power/ICON/Contrast control
RS
0
R/W
0
Wait time >26.3μ S
Wait time >26.3μS
Contrast set
RS
0
R/W
0
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
Bon
C5
C4
0
1
0
1
Ion
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
0
1
1
1
C3
C2
C1
C0
Follower control
RS
0
R/W
0
Wait time >26.3μ S
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
0
1
1
0
Fon Rab2 Rab1 Rab0
Wait time >200mS
(for power stable)
Display ON/OFF control
RS
0
R/W
0
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
0
0
0
0
1
D
C
B
Wait time >26.3μS
Initialization end
V1.4
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ST7032
Ø
Initial Program Code Example For 8051 MPU(Serial Interface):
;--------------------------------------------------------------------------------INITIAL_START:
CALL HARDWARE_RESET
CALL DELAY40mS
MOV A,#38H
;FUNCTION SET
CALL WRINS_NOCHK ;8 bit,N=1,5*7dot
CALL DELAY30uS
MOV A,#39H
;FUNCTION SET
CALL WRINS_NOCHK ;8 bit,N=1,5*7dot,IS=1
CALL DELAY30uS
MOV A,#14H
;Internal OSC frequency adjustment
CALL WRINS_NOCHK
CALL DELAY30uS
MOV A,#78H
;Contrast set
CALL WRINS_NOCHK
CALL DELAY30uS
MOV A,#5EH
;Power/ICON/Contrast control
CALL WRINS_NOCHK
CALL DELAY30uS
MOV A,#6AH
;Follower control
CALL WRINS_NOCHK
CALL DELAY200mS
;for power stable
MOV A,#0CH
;DISPLAY ON
CALL WRINS_NOCHK
CALL DELAY30uS
MOV A,#01H
;CLEAR DISPLAY
CALL WRINS_NOCHK
CALL DELAY2mS
MOV A,#06H
;ENTRY MODE SET
CALL WRINS_NOCHK ;CURSOR MOVES TO RIGHT
CALL DELAY30uS
;--------------------------------------------------------------------------------MAIN_START:
XXXX
XXXX
XXXX
XXXX
.
.
.
;--------------------------------------------------------------------------------WRINS_NOCHK:
PUSH 1
MOV
R1,#8
CLR
RS
$1
RLC
A
MOV SI,C
SET
SCL
NOP
CLR
SCL
DJNZ R1,$1
POP 1
CALL
RET
V1.4
DLY1.5mS
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ST7032
n Interfacing to the MPU
The ST7032 can send data in two 4-bit operations/one 8-bit operation, serial 1 bit operation or fast I2C operation,
thus allowing interfacing with 4-bit, 8-bit or I2C MPU.
l
For 4-bit interface data, only four bus lines (DB4 to DB7) are used for transfer. Bus lines DB0 to DB3
are disabled. The data transfer between the ST7032 and the MPU is completed after the 4-bit data has been
transferred twice. As for the order of data transfer, the four high order bits (for 8-bit operation, DB4 to DB7)
are transferred before the four low order bits (for 8-bit operation, DB0 to DB3). The busy flag must be
checked (one instruction) after the 4-bit data has been transferred twice. Two more 4-bit operations then
transfer the busy flag and address counter data.
Ø
Example of busy flag check timing sequence
CSB
RS
R/W
E
Internal
operation
DB7
Functioning
IR7
IR3
Instruction write
Ø
AC3
Busy flag check
Not
Busy
AC3
Busy flag check
IR3
Instruction write
Intel 8051 interface(4 Bit)
COM1 to COM16
P1.0 to P1.3
4
16
DB4 to DB7
P3.0
P3.1
P3.2
P3.3
RS
R/W
E
SEG1 to SEG80
CSB
Intel 8051 Serial
V1.4
IR7
80
ST7032
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l
For 8-bit interface data, all eight bus lines (DB0 to DB7) are used.
Ø
Example of busy flag check timing sequence
CSB
RS
R/W
E
Internal
operation
Functioning
DB7
Data
Instruction
write
Ø
Not
Busy
Busy
Busy
Busy flag
check
Busy flag
check
Busy flag
check
Instruction
write
Intel 8051 interface(8 Bit)
COM1 to COM16
P1.0 to P1.7
8
16
DB0 to DB7
P3.0
P3.1
P3.2
P3.3
RS
R/W
E
SEG1 to SEG80
CSB
Intel 8051 Serial
V1.4
Data
80
ST7032
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l
For serial interface data, only two bus lines (DB6 to DB7) are used.
Ø
Example of timing sequence
CSB
SI
D7
D6
D5
D4
D3
D2
D1
D0
D7
D6
D5
D4
D3
D2
SCL
1
2
3
4
5
6
7
8
9
10
11
12
13
14
RS
Note:The falling edge must cause on CSB before the serial clock ( SCL ) active.
Ø
Intel 8051 interface(Serial)
COM1 to COM16
P1.6 to P1.7
2
SI , SCL
P3.0
P3.3
RS
CSB
SEG1 to SEG80
Intel 8051 Serial
V1.4
16
80
ST7032
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l
For I2C interface data, only two bus lines (DB6 to DB7) are used.
Ø
Example of timing sequence
SDA
D7
D6
D5
D4
D3
D2
D1
D0
ACK
.......
1
2
3
4
5
6
7
8
9
Intel 8051 interface( I2C )
COM1 to COM16
P1.6 to P1.7
2
Intel 8051 Serial
16
SDA , SCL
SEG1 to SEG80
V1.4
ACK
......
SCL
Ø
D0
80
ST7032
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ST7032
n Supply Voltage for LCD Drive
l
When external bias resistors are used
(OPF1=1,OPF2=1)
VCC (2.7~ 5.5V)
VCC (2.7~ 5.5V)
Vext
OPF1 OPF2 VDD
OPF1 OPF2 VDD
VOUT
V0
VIN
CAP1P
CAP1N
VR
VR
VOUT
V0
VIN
R
V1
V2
V3
R
CAP1P
V1
CAP1N
V2
VLCD
V3
R
R
V4
R
R
VSS
VSS
l
R
R
VLCD
V4
1/4 bias
Vext
1/5 bias
GND
GND
When built-in bias resistors(9.6KΩ) are used
(OPF1=1,OPF2=0)
VCC(2.7~5.5V)
OPF1
VOUT
Vext
VDD
VR
V0
VIN
CAP1P
V1
CAP1N
V2
VLCD
V3
V4
OPF2
VSS
GND
V1.4
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ST7032
l
When built-in bias resistors(3.3KΩ) are used
(OPF1=0,OPF2=1)
VCC (2.7~ 5.5V)
OPF2
Vext
VDD
VOUT
VR
V0
VIN
CAP1P
V1
CAP1N
V2
VLCD
V3
V4
OPF1
VSS
GND
l
When built-in voltage followers with external Vout are used
(OPF1=0,OPF2=0 and instruction setting Bon=0,Fon=1)
VCC (2.7~ 5.5V)
Vext ≧ V0
Don't need to connect stable capacitor when
use internal follower circuit
VOUT
VDD
VIN
V0
CAP1P
V1
CAP1N
V2
VLCD
V3
V4
OPF1 OPF2 VSS
GND
V1.4
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ST7032
l
When built-in booster and voltage followers are used(OPF1=0,OPF2=0)
VCC (2.7~ 3.5V)
Don't need to connect stable capacitor when
use internal follower circuit
VIN
VDD
VOUT
V0
CAP1P
V1
CAP1N
V2
VOUT≦2xVDD
VDD=2.7~3.5V
VSS=0V
VLCD
V3
2 x step-up voltage relationships
V4
OPF1 OPF2 VSS
GND
Note:
Ensure V0 level stable, that must let |Vout-V0| over 0.5V(if panel size over 4.5”,the |Vout-V0| propose over 0.8V).
|Vout-V0|>0.5V(minimum)
Vout
V0
VCC
VDD
GND
VSS
(System side)
V1.4
(ST7032Side)
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ST7032
Ø
V0 voltage follower value calculation
VDD
Vout(≧VDD)
V0=(1+
Vref
Rb
) Vref
Ra *
V0
α+36
)
100
While Vref=VDD * (
Rb
Ra
VSS
C5
C4
C3
C2
C1
C0
α
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
1
0
0
1
2
.
.
1
1
1
1
1
1
1
1
1
.
.
1
1
1
0
1
1
1
0
1
61
62
63
Rab2 Rab1 Rab0
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
1+Rb/Ra
1
1.25
1.5
1.8
2
2.5
3
3.75
8
7
6
5
4
3
2
1
0
1
3
5
7
9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 51 53 55 57 59 61 63
V0 level (Condition:Booster on, Follower on, VIN=3.5V, VDD=3.0V,Display off)
The recommended curve: follower = 04H
Notes:
1.
Vout ≧V0 ≧V1 ≧V2 ≧V3 ≧V4 ≧Vss must be maintained.
2.
If the calculation value of V0 is higher than Vout, the real V0 value will saturate to Vout.
3.
internal built-in booster can only be used when OPF1=0,OPF2=0.
V1.4
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ST7032
8
7
6
5
4
3
2
1
0
0 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 54 56 58 60 62
V0 level (Condition:Booster on, Follower on, VIN = 3.5 V, VDD=5.0V, Display off)
The recommanded curve: follower = 01H
Notes:
1.
Vout ≧V0 ≧V1 ≧V2 ≧V3 ≧V4 ≧Vss must be maintained.
2.
If the calculation value of V0 is higher than Vout, the real V0 value will saturate to Vout.
3.
internal built-in booster can only be used when OPF1=0,OPF2=0.
V1.4
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ST7032
n AC Characteristics
l
68 Interface
RS
R/W
tAW6
tAH6
CSB
tCYC6
tEWH
tEWL
E
tr
tf
tDS6
tDH6
D0 to D7
(Write)
tACC6
tOH6
D0 to D7
(Read)
Item
Signal
Symbol
Address hold time
RS
tAH6
Address setup time
RS
tAW6
System cycle time
RS
tCYC6
D0 to D7
tDS6
Data setup time
Condition
VDD=2.7 to 4.5V
Rating
Min.
Max.
20
-
20
-
20
-
20
-
400
-
280
-
100
-
80
-
40
-
20
-
-
500
-
400
300
-
150
-
—
—
( Ta = 25°C )
VDD=4.5 to 5.5V
Rating
Units
Min.
Max.
ns
—
Data hold time
D0 to D7
tDH6
Access time
D0 to D7
tACC6
ns
ns
CL = 100 pF
ns
D0 to D7
tOH6
Enable Rise/Fall time
E
tr,tf
—
-
20
-
20
ns
Enable H pulse time
E
tEWH
—
200
-
120
-
ns
Enable L pulse time
E
tEWL
—
150
-
130
-
ns
Output disable time
Note: All timing is specified using 20% and 80% of VDD as the reference.
V1.4
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ST7032
l
Serial Interface
tCSS
tCSH
CSB
tSAS
tSAH
RS
tSCYC
tSLW
tSHW
SCL
tf
tr
tSDS
tSDH
SI
( Ta = 25°C )
Item
Signal
SCL
SCL “L” pulse width
SCL Rise/Fall time
Address setup time
Address hold time
Data setup time
Data hold time
CS-SCL time
Condition
tSCYC
Serial Clock Period
SCL “H” pulse width
Symbol
tSHW
—
tSLW
SCL
RS
SI
CS
tr,tf
tSAS
tSAH
tSDS
tSDH
tCSS
tCSH
—
—
—
—
VDD=2.7 to 4.5V
Rating
VDD=4.5 to 5.5V
Rating
Min.
Max.
Min.
Max.
200
-
100
-
20
-
20
-
160
-
120
-
-
20
-
20
10
-
10
-
250
-
150
-
10
-
10
-
10
-
20
-
20
-
20
-
350
-
200
-
Units
ns
ns
ns
ns
ns
*1 All timing is specified using 20% and 80% of VDD as the standard.
V1.4
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ST7032
l
I2C interface
SDA
tBUF
tHIGH
tLOW
tSU;DAT
SCL
tDH;STA
tr
SDA
tf
tHD;DAT
tSU;STA
Item
Signal Symbol Condition
SCL clock frequency
SCL clock low period
fSCLK
SCL
SCL clock high period
Data set-up time
Data hold time
SCL,SDA rise time
SCL,SDA fall time
Capacitive load represent by each bus
line
Setup time for a repeated START
condition
Start condition hold time
V1.4
—
tHIGH
SI
SCL,
SDA
SI
Setup time for STOP condition
Bus free time between a Stop and
START condition
tLOW
SCL
tSU;DAT
tHD:DAT
tr
tf
—
—
tSU;STO
VDD=2.7 to 4.5V
Rating
( Ta = 25°C )
VDD=4.5 to 5.5V
Rating
Units
Min.
Max.
Min.
Max.
DC
DC
0.6
400
—
—
180
KHz
0.6
400
—
—
—
100
—
ns
0
0.9
0
0.9
us
20+0.1Cb
300
20+0.1Cb
300
20+0.1Cb
300
20+0.1Cb
300
1.3
1.3
us
ns
Cb
—
—
400
—
400
pf
tSU;STA
—
0.6
—
0.6
—
us
tHD;STA
—
0.6
—
0.6
—
us
tSU;STO
—
0.6
—
0.6
—
us
tBUF
—
1.3
—
1.3
—
us
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ST7032
l
Internal Power Supply Reset
2.7V/4.5V
0.2V
0.2V
trcc
0.2V
tOFF
0.1mS≦trcc≦10mS
tOFF≧1mS
Notes:
w tOFF compensates for the power oscillation period caused by momentary power supply oscillations.
w Specified at 4.5V for 5V operation,and at 2.7V for 3V operation.
w If 2.7V/4.5V is not reached during 3V/5V operation, internal reset circuit will not operate normally.
l
Hardware reset(XRESET)
tr≦100nS
2.7V/4.5V
0.2V
tL>100uS
V1.4
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ST7032
n Absolute Maximum Ratings
Characteristics
Symbol
Value
Power Supply Voltage
VDD
-0.3 to +6.0
LCD Driver Voltage
VLCD
7.0- Vss to -0.3+Vss
Input Voltage
VIN
-0.3 to VDD+0.3
Operating Temperature
TA
-30 C to + 85 C
Storage Temperature
TSTO
-65 C to + 150 C
o
o
o
o
n DC Characteristics
( TA = 25℃ , VDD = 2.7 V – 4.5 V )
Symbol Characteristics
Min. Typ. Max.
Unit
VDD
Operating Voltage
-
2.7
-
4.5
V
VLCD
LCD Voltage
V0-Vss
2.7
-
7.0
V
-
160
230
uA
ICC
V1.4
Test Condition
VDD=3.0V
Power Supply Current
(Use internal
booster/follower circuit)
VIH1
Input High Voltage
(Except OSC1)
-
1.9
-
VDD
V
VIL1
Input Low Voltage
(Except OSC1)
-
- 0.3
-
0.8
V
VIH2
Input High Voltage
(OSC1)
-
0.7
VDD
-
VDD
V
VIL2
Input Low Voltage
(OSC1)
-
-
-
0.2
VDD
V
VOH1
Output High Voltage
(DB0 - DB7)
IOH = -1.0mA
0.75
VDD
-
-
V
VOL1
Output Low Voltage
(DB0 - DB7)
IOL = 1.0mA
-
-
0.8
V
VOH2
Output High Voltage
(Except DB0 - DB7)
IOH = -0.04mA
0.8
VDD
-
VDD
V
VOL2
Output Low Voltage
(Except DB0 - DB7)
IOL = 0.04mA
-
-
0.2
VDD
V
RCOM
Common Resistance
VLCD = 4V, Id = 0.05mA
-
2
20
KΩ
RSEG
Segment Resistance
VLCD = 4V, Id = 0.05mA
-
2
30
KΩ
ILEAK
Input Leakage
Current
VIN = 0V to VDD
-1
-
1
µA
IPUP
Pull Up MOS Current
VDD = 3V
20
30
40
µA
fOSC
Oscillation frequency
VDD = 3V,1/17duty
350
540
1100
KHz
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ST7032
n DC Characteristics
( TA = 25℃, VDD = 4.5 V - 5.5 V )
Symbol Characteristics
Min. Typ. Max.
Unit
VDD
Operating Voltage
-
4.5
-
5.5
V
VLCD
LCD Voltage
V0-Vss
2.7
-
7.0
V
-
240
340
uA
ICC
V1.4
Test Condition
VDD=5.0V
Power Supply Current
(Use internal
booster/follower circuit)
VIH1
Input High Voltage
(Except OSC1)
-
2.7
-
VDD
V
VIL1
Input Low Voltage
(Except OSC1)
-
-0.3
-
0.8
V
VIH2
Input High Voltage
(OSC1)
-
0.7
VDD
-
VDD
V
VIL2
Input Low Voltage
(OSC1)
-
-
-
1.0
V
VOH1
Output High Voltage
(DB0 - DB7)
IOH = -1.0mA
3.8
-
VDD
V
VOL1
Output Low Voltage
(DB0 - DB7)
IOL = 1.0mA
-
-
0.8
V
VOH2
Output High Voltage
(Except DB0 - DB7)
IOH = -0.04mA
0.8
VDD
-
VDD
V
VOL2
Output Low Voltage
(Except DB0 - DB7)
IOL = 0.04mA
-
-
0.2
VDD
V
RCOM
Common Resistance
VLCD = 4V, Id = 0.05mA
-
2
20
KΩ
RSEG
Segment Resistance
VLCD = 4V, Id = 0.05mA
-
2
30
KΩ
ILEAK
Input Leakage
Current
VIN = 0V to VDD
-1
-
1
µA
IPUP
Pull Up MOS Current
VDD = 5V
65
95
125
µA
fOSC
Oscillation frequency
VDD = 5V,1/17duty
350
540
1100
KHz
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ST7032
n LCD Frame Frequency
l
1/16 Duty(ST7066U normal mode); Assume the oscillation frequency is 540KHZ, 1 clock cycle time
= 1.85us, 1/16 duty; 1/5 bias,1 frame =1.85us x 200 x 16 = 5.92ms=168.9Hz(SHLC and SHLS connect
to High)
n
200 clocks
1
2
3
4
16
1
2
3
4
16
1
2
3
4
16
V0
V1
V2
COM1
V3
V4
Vss
V0
V1
V2
COM2
V3
V4
Vss
V0
V1
V2
COM16
V3
V4
Vss
V0
V1
V2
SEGx off
V3
V4
Vss
V0
V1
V2
SEGx on
V3
V4
Vss
1 frame
V1.4
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l
1/17 Duty(Extension mode); Assume the oscillation frequency is 540KHZ, 1 clock cycle time =
1.85us, 1/17 duty; 1/5 bias,1 frame =1.85us x 200 x 17 = 6.29ms=159Hz(SHLC and SHLS connect to
High)
200 clocks
1
2
3
4
17
1
2
3
4
17
1
2
3
4
17
V0
V1
V2
COM1
V3
V4
Vss
V0
V1
V2
COM2
V3
V4
Vss
V0
V1
V2
COM17
V3
V4
Vss
V0
V1
V2
SEGx off
V3
V4
Vss
V0
V1
V2
SEGx on
V3
V4
Vss
1 frame
V1.4
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l
1/8 Duty(ST7066U normal mode); Assume the oscillation frequency is 540KHZ, 1 clock cycle time =
1.85us, 1/8 duty; 1/4 bias,1 frame = 1.85us x 400 x 8 = 5.92ms=168.9Hz(SHLC and SHLS connect to
400 clocks
1
2
3
4
8
1
2
3
4
8
1
2
3
4
8
V0
V1
COM1
V2
V3
V4
Vss
V0
V1
COM2
V2
V3
V4
Vss
V0
V1
COM8
V2
V3
V4
Vss
V0
V1
SEGx off
V2
V3
V4
Vss
V0
V1
SEGx on
V2
V3
V4
Vss
1 frame
High)
V1.4
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l
1/9 Duty(Extension mode); Assume the oscillation frequency is 540KHZ, 1 clock cycle time =
1.85us, 1/9 duty; 1/4 bias,1 frame = 1.85us x 400 x 9 = 6.66ms=150Hz(SHLC and SHLS connect to
400 clocks
1
2
3
4
9
1
2
3
4
9
1
2
3
4
9
V0
V1
COM1
V2
V3
V4
Vss
V0
V1
COM2
V2
V3
V4
Vss
V0
V1
COM9
V2
V3
V4
Vss
V0
V1
SEGx off
V2
V3
V4
Vss
V0
V1
SEGx on
V2
V3
V4
Vss
1 frame
High)
V1.4
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ST7032
n I/O Pad Configuration
PSB
PSB=1 => Pull-Up
PSB=0 => Floating
V1.4
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ST7032
n LCD and ST7032 Connection
SHLC/SHLS ITO option pin can select at different direction for LCD panel
l
Com normal direction/Seg normal direction
l
Com normal direction/Seg reverse direction
l
Com reverse direction/Seg normal direction
l
Com reverse direction/Seg reverse direction
V1.4
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ST7032
n Application Circuit(ST7066U normal mode)
Ø
Ø
Ø
Ø
Use internal resistor(9.6K ohm) and contrast adjust with external VR.
Booster always off.
Has 240 character of CGROM and 8 characters of CGRAM
Internal oscillator.
Dot Matrix LCD Panel
VDD
Vext
VOUT
VIN
Com 1-16
Seg 1-80
CLS
SHLC
SHLS
CAP1N
CAP1P
V0
V1
V2
V3
RS,R/W,E,CSB,DB0-DB7,XRESET
V4
ST7032
EXT
OPF1
OPF2
OPR1
OPR2
To MPU
V1.4
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ST7032
n Application Circuit(Extension mode)
Ø
Ø
Ø
Ø
Use internal follower circuit.
Booster has 2 times pump.
Has 240 character of CGROM and 8 characters of CGRAM
Internal oscillator
D ot M atrix LC D P anel
V ext
VDD
VOUT
V IN
C om 1-17
S eg 1-80
C A P 1N
C A P 1P
V0
V1
V2
V3
R S ,R /W ,E ,C S B ,D B 0-D B 7,X R E S ET
V4
S T7032
C LS
SH LC
SH LS
EX T
O PF1
O PF2
O PR 1
O PR 2
To M P U
l
V1.4
When the heavy load is applied, the dotted line part could be added.
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ST7032
n Application Circuit(for glass layout)
l
V1.4
ST7032 over Glass,6800 serial 8bit interface, with booster and follower circuit on
58/61
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ST7032
l
V1.4
ST7032 over Glass,6800 serial 4bit interface, with booster and follower circuit on
59/61
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ST7032
l
V1.4
ST7032 under Glass, serial interface, with booster and follower circuit on
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l
V1.4
ST7032i under Glass, IIC interface, with booster and follower circuit on
61/61
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Appendix – Product Number
Product Number
OPR1
OPR2
Support Character
ST7032-0D
1
1
English/Japan/European
Table A1.
Correspondence between Character Codes and Character Patterns
A1
Table A2.
Select display pattern in CGRAM or CGROM (use OPR1, OPR2)
Replaced By CGRAM Pattern
Replaced By CGRAM Pattern
Replaced By CGRAM Pattern
Replaced By CGRAM Pattern
OPR2,OPR1=(0,0) OPR2,OPR1=(0,1) OPR2,OPR1=(1,0) OPR2,OPR1=(1,1)
A2