ST7036

ST
Sitronix
ST7036
Dot Matrix LCD Controller/Driver
Features
5 x 8 dot matrix possible
Low power operation support:
-- 2.7 to 5.5V
Range of LCD driver power
-- 3.0 to 7.0V
2
4-bit, 8-bit, serial or I C-bus MPU interface
enabled
80 x 8-bit display RAM (80 characters max.)
10,240-bit character generator ROM for a
total of 256 character fonts(max)
64 x 8-bit character generator RAM(max)
Support two display mode:
16-com x 100-seg and 80 ICON
24-com x 80-seg and 80 ICON
16 x 5 –bit ICON RAM(max)
Description
The ST7036 dot-matrix liquid crystal display controller can
display alphanumeric, Japanese kana characters, and
symbols. It can be configured to drive a dot-matrix liquid
crystal display under the control of a 4 / 8-bit with
2
6800-series, serial or fast I C interface microprocessor.
Since all the functions such as display RAM, character
generator ROM/RAM and liquid crystal driver, required for
driving a dot-matrix liquid crystal display are internally
provided on one chip, a minimal system can be used with
this controller/driver.
Wide range of instruction functions:
Display clear, cursor home, display on/off,
cursor on/off, display character blink, cursor
shift, display shift, double height font
Automatic reset circuit that initializes the
controller/driver after power on and external
reset pin
Internal oscillator(Frequency=540kHz) and
external clock
Built-in voltage booster and follower circuit
(low power consumption )
COM/SEG direction selectable
Multi-selectable for CGRAM/CGROM size
Instruction compatible to ST7066U and
KS0066U and HD44780
Available in COG type
The ST7036 is suitable for low voltage supply (2.7V to
5.5V) and is perfectly suitable for any portable product
which is driven by the battery and requires low power
consumption.
The display resolution of ST7036 dot-matrix LCD driver
can be either 1-line x 20 characters, 2-line x 20 characters
or 3-line x 16 characters with 80 bit ICON.
The ST7036 dot-matrix LCD driver does not need extra
cascaded drivers.
The ST7036 character generator ROM size is 256 5x8dot
bits which can be used to generate 256 different character
fonts (5x8dot).
product Name
Character generator
ROM Size
ST7036-0A
-
256
-
1
-
ST7036
6800-4bit / 8bit,4-Line interface
(without IIC interface)
ST7036i
IIC interface
V1.7a
OPR1 OPR2 Support Character
1/70
1
-
English / Japan/Europe
-
2007/10/17
ST7036
Version
st
0.1a
2003/04/28 1 Edition
0.1b
PAD Dimension:
2003/06/03 IC L mark location modified
Chip Size X/Y modified
0.2a
2003/09/01 1. Include ST7036i
1.0
2003/10/24
1.1
V1.7a
ST7036 Serial Specification Revision History
Date
Description
1.
2.
1.
2003/12/24
2.
Add application circuit for 3 line display.
4 bit interface program example modified.
Remove the instruction of frequency adjust.
Add the detail of CGRAM/CGROM arrangement.
1.2
2004/5/13 Remove ‘Preliminary’.
1.3
2004/5/26
1.4
2004/10/20 1. To modify icon RAM mapping. ( P.24 )
1.5
2005/06/13 Modify operating temperature range Ta=-35°C to 85°C
1.6
1.
2.
2005/10/17 3.
4.
5.
1.7
2006/7/10 1. To modify Chip Thickness: 480 um
1.7a
2007/10/17 1. Adding description of 4-line interface in cover
1. Correct the I/O pad configuration.
2
2. Add comments for I C application.
To modify Operating Temperature Range Ta=-30°C to 85°C
To modify Storage Temperature Range Ta=-65°C to 150°C
To modify the vlcd voltage Range 3.0v~7.0v
To modify the limiting values -0.3v~+6.0v
To add Chip Thickness: 635 um
2/70
2007/10/17
ST7036
Pad Dimensions
Chip Size: 5190.0 X 910.0 µm
Chip Thickness: 480 µm
Bump Pitch : 55 µm ( min )
Bump Height : 17 µm ( typ. )
Bump Size :
Pad No.1~52 : 56 x 72 µm
Pad No.53~170 : 35 x 101 µm
V1.7a
3/70
2007/10/17
ST7036
Pad Location Coordinates(N3=0 1 line/2 line)
Pad No. Function
V1.7a
X
Y
Pad No. Function
X
Y
1
XRESET
1859
393
41
CLS
-1181
393
2
OSC
1783
393
42
CAP1N
-1257
393
3
VDD
1707
393
43
CAP1N
-1333
393
4
RS
1631
393
44
VOUT
-1409
393
5
CSB
1555
393
45
VOUT
-1485
393
6
RW
1479
393
46
V0
-1561
393
7
E
1403
393
47
V0
-1637
393
8
DB0
1327
393
48
V1
-1713
393
9
DB1
1251
393
49
V2
-1789
393
10
DB2
1175
393
50
V3
-1865
393
11
DB3
1099
393
51
V4
-1941
393
12
DB4
1023
393
52
NC
-2017
393
13
DB5
947
393
53
COM[8]
-2125
378
14
DB6
871
393
54
COM[7]
-2180
378
15
DB7
795
393
55
COM[6]
-2235
378
16
VSS
719
393
56
COM[5]
-2290
378
17
VSS
643
393
57
COM[4]
-2518
365
18
VSS
567
393
58
COM[3]
-2518
310
19
OPF1
491
393
59
COM[2]
-2518
255
20
OPF2
415
393
60
COM[1]
-2518
200
21
OPR1
339
393
61
COMI1
-2518
145
22
OPR2
263
393
62
SEG[1]
-2518
90
23
SHLC
187
393
63
SEG[2]
-2518
35
24
SHLS
111
393
64
SEG[3]
-2518
-20
25
N3
35
393
65
SEG[4]
-2518
-75
26
TEST1
-41
393
66
SEG[5]
-2518
-130
27
VDD
-117
393
67
SEG[6]
-2518
-185
28
VDD
-193
393
68
SEG[7]
-2518
-240
29
VDD
-269
393
69
SEG[8]
-2518
-295
30
VIN
-345
393
70
SEG[9]
-2518
-350
31
VIN
-421
393
71
SEG[10]
-2253
-378
32
VOUT
-497
393
72
SEG[11]
-2198
-378
33
VOUT
-573
393
73
SEG[12]
-2143
-378
34
PSB
-649
393
74
SEG[13]
-2088
-378
35
VSS
-725
393
75
SEG[14]
-2033
-378
36
PSI2B
-801
393
76
SEG[15]
-1978
-378
37
CAP1P
-877
393
77
SEG[16]
-1923
-378
38
CAP1P
-953
393
78
SEG[17]
-1868
-378
39
EXT
-1029
393
79
SEG[18]
-1813
-378
40
VSS
-1105
393
80
SEG[19]
-1758
-378
4/70
2007/10/17
ST7036
Pad No. Function
X
Y
Pad No. Function
X
Y
81
SEG[20]
-1703
-378
121
SEG[60]
497
-378
82
SEG[21]
-1648
-378
122
SEG[61]
552
-378
83
SEG[22]
-1593
-378
123
SEG[62]
607
-378
84
SEG[23]
-1538
-378
124
SEG[63]
662
-378
85
SEG[24]
-1483
-378
125
SEG[64]
717
-378
86
SEG[25]
-1428
-378
126
SEG[65]
772
-378
87
SEG[26]
-1373
-378
127
SEG[66]
827
-378
88
SEG[27]
-1318
-378
128
SEG[67]
882
-378
89
SEG[28]
-1263
-378
129
SEG[68]
937
-378
90
SEG[29]
-1208
-378
130
SEG[69]
992
-378
91
SEG[30]
-1153
-378
131
SEG[70]
1047
-378
92
SEG[31]
-1098
-378
132
SEG[71]
1102
-378
93
SEG[32]
-1043
-378
133
SEG[72]
1157
-378
94
SEG[33]
-988
-378
134
SEG[73]
1212
-378
95
SEG[34]
-933
-378
135
SEG[74]
1267
-378
96
SEG[35]
-878
-378
136
SEG[75]
1322
-378
97
SEG[36]
-823
-378
137
SEG[76]
1377
-378
98
SEG[37]
-768
-378
138
SEG[77]
1432
-378
99
SEG[38]
-713
-378
139
SEG[78]
1487
-378
100
SEG[39]
-658
-378
140
SEG[79]
1542
-378
101
SEG[40]
-603
-378
141
SEG[80]
1597
-378
102
SEG[41]
-548
-378
142
SEG[81]
1652
-378
103
SEG[42]
-493
-378
143
SEG[82]
1707
-378
104
SEG[43]
-438
-378
144
SEG[83]
1762
-378
105
SEG[44]
-383
-378
145
SEG[84]
1817
-378
106
SEG[45]
-328
-378
146
SEG[85]
1872
-378
107
SEG[46]
-273
-378
147
SEG[86]
1927
-378
108
SEG[47]
-218
-378
148
SEG[87]
1982
-378
109
SEG[48]
-163
-378
149
SEG[88]
2037
-378
110
SEG[49]
-108
-378
150
SEG[89]
2092
-378
111
SEG[50]
-53
-378
151
SEG[90]
2147
-378
112
SEG[51]
2
-378
152
SEG[91]
2202
-378
113
SEG[52]
57
-378
153
SEG[92]
2518
-350
114
SEG[53]
112
-378
154
SEG[93]
2518
-295
115
SEG[54]
167
-378
155
SEG[94]
2518
-240
116
SEG[55]
222
-378
156
SEG[95]
2518
-185
117
SEG[56]
277
-378
157
SEG[96]
2518
-130
118
SEG[57]
332
-378
158
SEG[97]
2518
-75
119
SEG[58]
387
-378
159
SEG[98]
2518
-20
120
SEG[59]
442
-378
160
SEG[99]
2518
35
V1.7a
5/70
2007/10/17
ST7036
Pad No. Function
X
Y
161
SEG[100]
2518
90
162
COM[9]
2518
145
163
COM[10]
2518
200
164
COM[11]
2518
255
165
COM[12]
2518
310
166
COM[13]
2518
365
167
COM[14]
2290
378
168
COM[15]
2235
378
169
COM[16]
2180
378
170
COMI2
2125
378
V1.7a
Pad No. Function
6/70
X
Y
2007/10/17
ST7036
Pad Location Coordinates(N3=1 3 line)
Pad No. Function
V1.7a
X
Y
Pad No. Function
X
Y
1
XRESET
1859
393
41
CLS
-1181
393
2
OSC
1783
393
42
CAP1N
-1257
393
3
VDD
1707
393
43
CAP1N
-1333
393
4
RS
1631
393
44
VOUT
-1409
393
5
CSB
1555
393
45
VOUT
-1485
393
6
RW
1479
393
46
V0
-1561
393
7
E
1403
393
47
V0
-1637
393
8
DB0
1327
393
48
V1
-1713
393
9
DB1
1251
393
49
V2
-1789
393
10
DB2
1175
393
50
V3
-1865
393
11
DB3
1099
393
51
V4
-1941
393
12
DB4
1023
393
52
NC
-2017
393
13
DB5
947
393
53
COM[12]
-2125
378
14
DB6
871
393
54
COM[11]
-2180
378
15
DB7
795
393
55
COM[10]
-2235
378
16
VSS
719
393
56
COM[9]
-2290
378
17
VSS
643
393
57
COM[8]
-2518
365
18
VSS
567
393
58
COM[7]
-2518
310
19
OPF1
491
393
59
COM[6]
-2518
255
20
OPF2
415
393
60
COM[5]
-2518
200
21
OPR1
339
393
61
NC
-2518
145
22
OPR2
263
393
62
COM[4]
-2518
90
23
SHLC
187
393
63
COM[3]
-2518
35
24
SHLS
111
393
64
COM[2]
-2518
-20
25
N3
35
393
65
COM[1]
-2518
-75
26
TEST1
-41
393
66
COMI1
-2518
-130
27
VDD
-117
393
67
NC
-2518
-185
28
VDD
-193
393
68
NC
-2518
-240
29
VDD
-269
393
69
NC
-2518
-295
30
VIN
-345
393
70
NC
-2518
-350
31
VIN
-421
393
71
NC
-2253
-378
32
VOUT
-497
393
72
SEG[1]
-2198
-378
33
VOUT
-573
393
73
SEG[2]
-2143
-378
34
PSB
-649
393
74
SEG[3]
-2088
-378
35
VSS
-725
393
75
SEG[4]
-2033
-378
36
PSI2B
-801
393
76
SEG[5]
-1978
-378
37
CAP1P
-877
393
77
SEG[6]
-1923
-378
38
CAP1P
-953
393
78
SEG[7]
-1868
-378
39
EXT
-1029
393
79
SEG[8]
-1813
-378
40
VSS
-1105
393
80
SEG[9]
-1758
-378
7/70
2007/10/17
ST7036
Pad No. Function
X
Y
Pad No. Function
X
Y
81
SEG[10]
-1703
-378
121
SEG[50]
497
-378
82
SEG[11]
-1648
-378
122
SEG[51]
552
-378
83
SEG[12]
-1593
-378
123
SEG[52]
607
-378
84
SEG[13]
-1538
-378
124
SEG[53]
662
-378
85
SEG[14]
-1483
-378
125
SEG[54]
717
-378
86
SEG[15]
-1428
-378
126
SEG[55]
772
-378
87
SEG[16]
-1373
-378
127
SEG[56]
827
-378
88
SEG[17]
-1318
-378
128
SEG[57]
882
-378
89
SEG[18]
-1263
-378
129
SEG[58]
937
-378
90
SEG[19]
-1208
-378
130
SEG[59]
992
-378
91
SEG[20]
-1153
-378
131
SEG[60]
1047
-378
92
SEG[21]
-1098
-378
132
SEG[61]
1102
-378
93
SEG[22]
-1043
-378
133
SEG[62]
1157
-378
94
SEG[23]
-988
-378
134
SEG[63]
1212
-378
95
SEG[24]
-933
-378
135
SEG[64]
1267
-378
96
SEG[25]
-878
-378
136
SEG[65]
1322
-378
97
SEG[26]
-823
-378
137
SEG[66]
1377
-378
98
SEG[27]
-768
-378
138
SEG[67]
1432
-378
99
SEG[28]
-713
-378
139
SEG[68]
1487
-378
100
SEG[29]
-658
-378
140
SEG[69]
1542
-378
101
SEG[30]
-603
-378
141
SEG[70]
1597
-378
102
SEG[31]
-548
-378
142
SEG[71]
1652
-378
103
SEG[32]
-493
-378
143
SEG[72]
1707
-378
104
SEG[33]
-438
-378
144
SEG[73]
1762
-378
105
SEG[34]
-383
-378
145
SEG[74]
1817
-378
106
SEG[35]
-328
-378
146
SEG[75]
1872
-378
107
SEG[36]
-273
-378
147
SEG[76]
1927
-378
108
SEG[37]
-218
-378
148
SEG[77]
1982
-378
109
SEG[38]
-163
-378
149
SEG[78]
2037
-378
110
SEG[39]
-108
-378
150
SEG[79]
2092
-378
111
SEG[40]
-53
-378
151
SEG[80]
2147
-378
112
SEG[41]
2
-378
152
NC
2202
-378
113
SEG[42]
57
-378
153
NC
2518
-350
114
SEG[43]
112
-378
154
NC
2518
-295
115
SEG[44]
167
-378
155
NC
2518
-240
116
SEG[45]
222
-378
156
NC
2518
-185
117
SEG[46]
277
-378
157
NC
2518
-130
118
SEG[47]
332
-378
158
COM[13]
2518
-75
119
SEG[48]
387
-378
159
COM[14]
2518
-20
120
SEG[49]
442
-378
160
COM[15]
2518
35
V1.7a
8/70
2007/10/17
ST7036
Pad No. Function
X
Y
161
COM[16]
2518
90
162
COM[17]
2518
145
163
COM[18]
2518
200
164
COM[19]
2518
255
165
COM[20]
2518
310
166
COM[21]
2518
365
167
COM[22]
2290
378
168
COM[23]
2235
378
169
COM[24]
2180
378
170
COMI2
2125
378
V1.7a
Pad No. Function
9/70
X
Y
2007/10/17
ST7036
Block Diagram
OSC
XRESET
Reset
circuit
CLS
Timing
generator
CPG
Instruction
register(IR)
Instruction
decoder
RS
RW
E
CSB
Display data
RAM
(DDRAM)
80x8 bits
COMI
Address
counter
(AC)
100-bit
shift
register
PSI2B
EXT
N3
100-bit
latch
circuit
SEG1 to
SEG100
Segment
signal
driver
Data
register
(DR)
DB4 to
DB7
SHLC
SHLS
COM1 to
COM16
(OR 24)
Common
signal
driver
MPU
interface
PSB
DB0 to
DB3
24-bit
shift
register
Input/
output
buffer
V0~V4
LCD drive
voltage
follower
Busy
flag
Character
generator RAM
(CGRAM)
64 bytes
ICON RAM
80 bits
Character
generator ROM
(CGROM)
10.240 bits
Cursor
and
blink
controller
Voltage
booster
circuit
VOUT
VIN
CAP1P
CAP1N
OPR1,2
OPF1,2
VSS
Parallel/serial converter
and
attribute circuit
VDD
V1.7a
10/70
2007/10/17
ST7036
Pin Function
Name
XRESET
Number
1
I/O Interfaced with
I
MPU
Function
External reset pin. Only if the power on reset be used, the
XRESET pin could be fixed to VDD.
Low active.
Select registers.
RS
1
I
MPU
0: Instruction register (for write)
Busy flag & address counter (for read)
1: Data register (for write and read)
Select read or write(In parallel mode).
R/W
1
I
MPU
0: Write
1: Read
E
1
I
MPU
CSB
1
I
MPU
Starts data read/write. (“E” must connect to “VDD” when
serial mode is selected.)
Chip select in parallel mode and serial interface(Low
active). When the CSB in falling edge state ( in serial
interface ), the shift register and the counter are reset.
DB0~DB3 are four low order bi-directional data bus pins.
DB0~DB3 are used for data transfer and receive between
the MPU and the ST7036.
These pins are not used during 4-bit operation and must
connect to VDD.
DB4~DB7 are four high order bi-directional data bus pins.
DB4~DB7 are used for data transfer and receive between
DB0 to DB7
8
I/O
MPU
the MPU and the ST7036. DB7 can be used as a busy flag.
In serial interface mode DB7 is SI(input data),DB6 is
SCL(serial clock).
2
In I C interface DB7 is slave address A1, DB6 is slave
address A0, DB5 DB4 DB3 are SDA –out, DB2 DB1 are
SDA-in and D0 is SCL.
2
2
SDA and SCL must connect to I C bus ( I C bus means that
connecting a resister between SDA/SCL and the power of
2
I C bus ).
Extension instruction select:
0:enable extension instruction(add contrast/ICON/double
Ext
1
I
ITO option
height font/ extension instruction)
1:disable extension instruction(compatible to ST7066U, but
without 5x11dot font)
Interface selection
0:serial mode
PSB
1
I
ITO option
(“E” must connect to “VDD” when serial mode is selected.)
1:parallel mode(4/8 bit)
2
In I C interface PSB must connect to VDD
PSI2B
V1.7a
1
I
ITO option
PSB
PSI2B
0
0
No use
0
1
4-line SPI
1
0
IC
1
1
Parallel 68
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ST7036
Name
Number I/O Interfaced with
Function
Character generator select:
OPR1,OPR2
2
I
OPR1
OPR2
CGROM
CGRAM
0
0
240
8
0
1
250
6
1
0
248
8
1
1
256
0
ITO option
Common signals direction select:
SHLC
1
I
ITO option
0:Com1~24←Row address 23~0(Invert)
1:Com1~24←Row address 0~23(Normal)
Segment signals direction select:
SHLS
1
I
ITO option
0:Seg1~100←Column address 99~0(Invert)
1:Seg1~100←Column address 0~99(Normal)
COM1 to
COM16
COMI2
COMI1
Seg1~Seg10
Seg91~Seg100
Common signals that are not used are changed
16
O
LCD
to non-selection waveform. COM9 to COM16
are non-selection waveforms at 1/8 or 1/9 duty factor
1
O
LCD
21
O
LCD
ICON common signals
Select “N3” pin for common or segment waveform output
(follow up table 2 defined)
1 line/2 line or 3 line select :
N3
1
I
ITO option
0:1 line/2 line SEG0~SEG100:normal
1:3 line COMI1,SEG1~SEG5,SEG97~SEG100 re-defined
SEG11 to
SEG90
80
O
LCD
Segment signals
The built-in voltage follower circuit selection
OPF1 OPF2
OPF1,OPF2
CAP1P
2
2
I
-
ITO option
Bias select
0
0
Built-in voltage follower(only use at EXT=0)
0
1
Built-in bias resistor(3.3KΩ)
1
0
Built-in bias resistor(9.6KΩ)
1
1
External bias resistor select
Power supply
For voltage booster circuit(VDD-VSS)
CAP1N
2
-
Power supply
External capacitor about 0.1u~4.7uf
VIN
2
-
Power supply
Input the voltage to booster
VOUT
4
-
Power supply
DC/DC voltage converter. Connect a capacitor between this
terminal and VIN when the built-in booster is used.
Power supply for LCD drive
V0 to V4
6
-
Power supply
V0-Vss = 7V (Max)
Built-in/external Voltage follower circuit
VDD,VSS
4,5
-
Power supply
CLS
1
I
ITO option
VDD : 2.7V to 5.5V, VSS: 0V
Internal/External oscillation select
0:external clock
1:internal oscillation
When the pin input is an external clock, it must be input to
OSC
1
I
Oscillation
TEST1
1
I/O
Test pin
OSC.
When the on-chip oscillator is used, it must be connected
to VDD.
V1.7a
TEST1 must connect to VDD.
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ST7036
EXT option pin difference table
Normal mode (EXT=1)
Mode
Difference
Booster
( Instruction compatible to ST7066U )
Always OFF
Extension mode (EXT=0)
ON/OFF controlled by instruction
Can’t use the follower circuit
Bias (V0~V4)
Only use external resistor or internal resistor(1/5 Follower or internal/external resistor selectable
bias)
1. Controlled by instruction with follower
Contrast adjust
Control by external VR
2. Controlled by external VR with
internal/external resistor
ICON RAM
Can’t be use
Instruction
Control normal instruction similar to ST7066U.
Double height font
Only 5x8 font
V1.7a
RAM size has 80 bit width(S1~S80).
Control extension instruction for low power
consumption.
Can set 5x8 or 5x16 font
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ST7036
Function Description
System Interface
2
This chip has all four kinds of interface type with MPU: 4-bit bus, 8-bit bus, serial and fast I C interface. 4-bit bus
or 8-bit bus is selected by DL bit in the instruction register.
During read or write operation, two 8-bit registers are used. One is data register (DR), the other is instruction
register(IR).
The data register(DR) is used as temporary data storage place for being written into or read from
DDRAM/CGRAM/ICON RAM, target RAM is selected by RAM address setting instruction. Each internal
operation, reading from or writing into RAM, is done automatically. So to speak, after MPU reads DR data, the
data in the next DDRAM/CGRAM/ICON RAM address is transferred into DR automatically. Also after MPU writes
data to DR, the data in DR is transferred into DDRAM/CGRAM/ICON RAM automatically.
The Instruction register(IR) is used only to store instruction code transferred from MPU. MPU cannot use it to
read instruction data.
To select register, use RS input pin in 4-bit/8-bit bus mode.
RS R/W
L
L
H
H
L
H
L
H
Operation
Instruction Write operation (MPU writes Instruction code into IR)
Read Busy Flag(DB7) and address counter (DB0 ~ DB6)
Data Write operation (MPU writes data into DR)
Data Read operation (MPU reads data from DR)
Table 1. Various kinds of operations according to RS and R/W bits.
2
I C interface
It just only could write Data or Instruction to ST7036 by the IIC Interface.
It could not read Data or Instruction from ST7036 (except Acknowledge signal).
SCL: serial clock input
SDA_IN: serial data input
SDA_OUT: acknowledge response output
Slaver address could set from “0111100” to “0111111”.
2
2
The I C interface send RAM data and executes the commands sent via the I C Interface. It could send data in to the RAM.
2
The I C Interface is two-line communication between different ICs or modules. The two lines are a Serial Data line (SDA)
and a Serial Clock line (SCL). Both lines must be connected to a positive supply via a pull-up resistor. Data transfer may be
initiated only when the bus is not busy.
BIT TRANSFER
One data bit is transferred during each clock pulse. The data on the SDA line must remain stable during the HIGH period of
the clock pulse because changes in the data line at this time will be interpreted as a control signal. Bit transfer is illustrated
in Fig.1.
START AND STOP CONDITIONS
Both data and clock lines remain HIGH when the bus is not busy. A HIGH-to-LOW transition of the data line, while the clock
is HIGH is defined as the START condition (S). A LOW-to-HIGH transition of the data line while the clock is HIGH is defined
as the STOP condition (P). The START and STOP conditions are illustrated in Fig.2.
SYSTEM CONFIGURATION
The system configuration is illustrated in Fig.3.
· Transmitter: the device, which sends the data to the bus
· Master: the device, which initiates a transfer, generates clock signals and terminates a transfer
· Slave: the device addressed by a master
· Multi-Master: more than one master can attempt to control the bus at the same time without corrupting the message
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· Arbitration: procedure to ensure that, if more than one master simultaneously tries to control the bus, only one is allowed to
do so and the message is not corrupted
· Synchronization: procedure to synchronize the clock signals of two or more devices.
ACKNOWLEDGE
Acknowledge signal (ACK) is not BF signal in parallel interface.
Each byte of eight bits is followed by an acknowledge bit. The acknowledge bit is a HIGH signal put on the bus by the
transmitter during which time the master generates an extra acknowledge related clock pulse. A slave receiver which is
addressed must generate an acknowledge after the reception of each byte. A master receiver must also generate an
acknowledge after the reception of each byte that has been clocked out of the slave transmitter. The device that
acknowledges must pull-down the SDA line during the acknowledge clock pulse, so that the SDA line is stable LOW during
the HIGH period of the acknowledge related clock pulse (set-up and hold times must be taken into consideration). A master
receiver must signal an end-of-data to the transmitter by not generating an acknowledge on the last byte that has been
clocked out of the slave. In this event the transmitter must leave the data line HIGH to enable the master to generate a STOP
2
condition. Acknowledgement on the I C Interface is illustrated in Fig.4.
SDA
SCL
data line
stable;
data valid
change
of data
allowed
Fig .1 Bit transfer
SDA
SCL
S
P
START condition
STOP condition
Fig .2 Definition of START and STOP conditions
MASTER
TRANSMITTER/
RECEIVER
SLAVE
RECEIVER (1)
0111100
SLAVE
RECEIVER (2)
0111101
SLAVE
RECEIVER (3)
0111110
SLAVE
RECEIVER (4)
0111111
SDA
SCL
Fig .3 System configuration
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ST7036
DATA OUTPUT
BY TRANSMITTER
not acknowledge
DATA OUTPUT
BY RECEIVER
SCL FROM
MASTER
acknowledge
2
1
8
S
9
clock pulse for
acknowledgement
START
condition
Fig .4 Acknowledgement on the IIC Interface
2
I C Interface protocol
The ST7036 supports command, data write addressed slaves on the bus.
2
Before any data is transmitted on the I C Interface, the device, which should respond, is addressed first. Four 7-bit slave
addresses (0111100 to 0111111) are reserved for the ST7036. The R/W is assigned to 0 for Write only.
2
The I C Interface protocol is illustrated in Fig.5.
2
The sequence is initiated with a START condition (S) from the I C Interface master, which is followed by the slave address.
2
All slaves with the corresponding address acknowledge in parallel, all the others will ignore the I C Interface transfer. After
acknowledgement, one or more command words follow which define the status of the addressed slaves.
A command word consists of a control byte, which defines Co and RS, plus a data byte.
The last control byte is tagged with a cleared most significant bit (i.e. the continuation bit Co). After a control byte with a
cleared Co bit, only data bytes will follow. The state of the RS bit defines whether the data byte is interpreted as a command
or as RAM data. All addressed slaves on the bus also acknowledge the control and data bytes. After the last control byte,
depending on the RS bit setting; either a series of display data bytes or command data bytes may follow. If the RS bit is set
to logic 1, these display bytes are stored in the display RAM at the address specified by the data pointer. The data pointer is
automatically updated and the data is directed to the intended ST7036i device. If the RS bit of the last control byte is set to
logic 0, these command bytes will be decoded and the setting of the device will be changed according to the received
2
commands. Only the addressed slave makes the acknowledgement after each byte. At the end of the transmission the I C
INTERFACE-bus master issues a STOP condition (P).
Write mode
acknowledgement
from ST7036i
S 0 1 1 1 1 1 0 0 A 1
slave address
R
S
acknowledgement
from ST7036i
control byte
acknowledgement
from ST7036i
data byte
A
A 0
Co
0 1 1 1 1 1 0
slave address
0
1
control byte
1 byte
R/W
2n>=0 bytes
command word
Co
R
S
acknowledgement
from ST7036i
A
acknowledgement
from ST7036i
data byte
A P
n>=0 bytes
MSB.......................LSB
Co
R
/
W
C R
0 0 0 0 0 0
o S
control byte
D D D D D D D D
7 6 5 4 3 2 1 0
data byte
Fig .5 IIC Interface protocol
Last control byte to be sent. Only a stream of data bytes is allowed to follow.
This stream may only be terminated by a STOP condition.
Another control byte will follow the data byte unless a STOP condition is received.
During write operation, two 8-bit registers are used. One is data register (DR), the other is instruction
register(IR).
The data register(DR) is used as temporary data storage place for being written into DDRAM/CGRAM/ICON
RAM, target RAM is selected by RAM address setting instruction. Each internal operation, writing into RAM, is
done automatically. So to speak, after MPU writes data to DR, the data in DR is transferred into
DDRAM/CGRAM/ICON RAM automatically.
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The Instruction register(IR) is used only to store instruction code transferred from MPU. MPU cannot use it to
read instruction data.
To select register, use RS bit input in IIC interface.
RS R/W
L
H
L
L
Operation
Instruction Write operation (MPU writes Instruction code into IR)
Data Write operation (MPU writes data into DR)
Table 2. Various kinds of operations according to RS and R/W bits.
Busy Flag (BF)
When BF = "High”, it indicates that the internal operation is being processed. So during this time the next
instruction cannot be accepted. BF can be read, when RS = Low and R/W = High (Read Instruction Operation),
through DB7 port. Before executing the next instruction, be sure that BF is not High.
Address Counter (AC)
Address Counter(AC) stores DDRAM/CGRAM/ICON RAM address, transferred from IR.
After writing into (reading from) DDRAM/CGRAM/ICON RAM, AC is automatically increased (decreased) by 1.
When RS = "Low" and R/W = "High", AC can be read through DB0 ~ DB6 ports.
Display Data RAM (DDRAM)
Display data RAM (DDRAM) stores display data represented in 8-bit character codes. Its extended capacity is 80
x 8 bits, or 80 characters. The area in display data RAM (DDRAM) that is not used for display can be used as
general data RAM. See Figure 6 for the relationships between DDRAM addresses and positions on the liquid
crystal display.
The DDRAM address (ADD ) is set in the address counter (AC) as hexadecimal.
1-line display (N3=0,N = 0) (Figure 7)
When there are fewer than 80 display characters, the display begins at the head position. For
example, if using only the ST7036, 20 characters are displayed. See Figure 7.
When the display shift operation is performed, the DDRAM address shifts. See Figure 8.
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2-line display (N3=0,N = 1) (Figure 9)
Case 1: When the number of display characters is less than 40 x 2 lines, the two lines are displayed from the
head. Note that the first line end address and the second line start address are not consecutive. For example,
when just the ST7036 is used, 20 characters x 2 lines are displayed. See Figure 9.
When display shift operation is performed, the DDRAM address shifts. See Figure 10.
Display Position
1
DDRAM
Address
(hexadecimal)
2
3
4
5
6
38 39 40
00 01 02 03 04 05
........
25 26 27
40 41 42 43 44 45
........
65 66 67
Fig. 9 2-Line Display
Display
Position
1
2
3
4
5
6
7
8
17 18 19 20
DDRAM
Address
00 01 02 03 04 05 06 07
……………
10 11 12 13
40 41 42 43 44 45 46 47
……………
50 51 52 53
For Shift
Left
01 02 03 04 05 06 07 08
……………
11 12 13 14
41 42 43 44 45 46 47 48
……………
51 52 53 54
For Shift
Right
27 00 01 02 03 04 05 06
……………
0F 10 11 12
67 40 41 42 43 44 45 46
……………
4F 50 51 52
Fig. 10 2-Line by 20-Character Display Example
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3-line display (N3=1,N =1) (Figure 11)
Case 1: When the number of display characters is less than 16 x 3 lines, the tree lines are displayed from the
head. For example, when just the ST7036 is used, 16 characters x 3 lines are displayed. See Figure 11.
When display shift operation is performed, the DDRAM address shifts. See Figure 12.
Display Position
1
DDRAM
Address
(hexadecimal)
2
3
4
5
6
14 15 16
00 01 02 03 04 05
........
0D 0E 0F
10 11 12 13 14 15
........
1D 1E 1F
20 21 22 23 24 25
........
2D 2E 2F
Fig. 11 3-Line Display
Display Position
1
DDRAM
Address
(hexadecimal)
4
5
6
14 15 16
........
0D 0E 0F
10 11 12 13 14 15
........
1D 1E 1F
20 21 22 23 24 25
........
2D 2E 2F
2
3
4
5
6
14 15 16
01 02 03 04 05 06
........
0E 0F 00
11 12 13 14 15 16
........
1E 1F 10
21 22 23 24 25 26
........
2E 2F 20
1
For Shift Right
3
00 01 02 03 04 05
1
For Shift Left
2
2
3
4
5
6
14 15 16
0F 00 01 02 03 04
........
0C 0D 0E
1F 10 11 12 13 14
........
1C 1D 1E
2F 20 21 22 23 24
........
2C 2D 2E
Fig. 12 3-Line Display
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Character Generator ROM (CGROM)
The character generator ROM generates 5 x 8 dot character patterns from 8-bit character codes. It can generate
240/250/248/256 5 x 8 dot character patterns(select by OPR1/2 ITO pin). User-defined character patterns are
also available by mask-programmed ROM.
Character Generator RAM (CGRAM)
In the character generator RAM, the user can rewrite character patterns by program. For 5 x 8 dots, eight
character patterns can be written.
Write into DDRAM the character codes at the addresses shown as the left column of Table 5 to show the
character patterns stored in CGRAM.
See Table 5 for the relationship between CGRAM addresses and data and display patterns. Areas that are not
used for display can be used as general data RAM.
ICON RAM
In the ICON RAM, the user can rewrite icon pattern by program.
There are totally 80 dots for icon can be written.
See Table 6 for the relationship between ICON RAM address and data and the display patterns.
Timing Generation Circuit
The timing generation circuit generates timing signals for the operation of internal circuits such as
DDRAM, CGROM and CGRAM. RAM read timing for display and internal operation timing by MPU
access are generated separately to avoid interfering with each other. Therefore, when writing data to
DDRAM, for example, there will be no undesirable interference, such as flickering, in areas other than
the display area.
LCD Driver Circuit(N3=0)
LCD Driver circuit has 17 common and 100 segment signals for LCD driving. Data from CGRAM/CGROM/ICON
is transferred to 100 bit segment latch serially, and then it is stored to 100 bit shift latch. When each common is
selected by 17 bit common register, segment data also output through segment driver from 100 bit segment
latch. In case of 1-line display mode, COM1 ~ COM8(with COMI) have 1/9 duty, and in 2-line mode, COM1 ~
COM16(with COMI) have 1/17 duty ratio.
LCD Driver Circuit(N3=1)
LCD Driver circuit has 25 common and 80 segment signals for LCD driving. Data from CGRAM/CGROM/ICON
is transferred to 80 bit segment latch serially, and then it is stored to 80 bit shift latch. When each common is
selected by 25 bit common register, segment data also output through segment driver from 80 bit segment latch.
In case of 3-line display mode, COM1 ~ COM24(with COMI) have 1/25 duty.
COM/SEG Output pins
N3
COMI1
VSS
COMI1
VDD
NC
COM
[1:8]
COM
[1:8]
COM
[5:12]
SEG
[1:5]
SEG
[1:5]
COM[4:1]
+ COMI1
SEG
[6:10]
SEG
[6:10]
NC
SEG
[11:90]
SEG
[11:90]
SEG
[1:80]
SEG
[91:96]
SEG
[91:96]
NC
SEG
[97:100]
SEG
[97:100]
COM
[13:16]
COM
[9:16]
COM
[9:16]
COM
[17:24]
COMI2
COMI2
COMI2
Table 3. COM/SEG output define
Cursor/Blink Control Circuit
It can generate the cursor or blink in the cursor/blink control circuit. The cursor or the blink appears in the digit at
the display data RAM address set in the address counter.
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Table 4 Correspondence between Character Codes and Character Patterns
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CGRAM/CGROM arrangement with (OPR1, OPR2)=
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Character Code
(DDRAM Data)
b7 b6 b5 b4 b3 b2
0
0
0
0
0 0 0 0 0
0
0
0
0
0
0
0
0 0 0 0 0
0
0
0
b1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
CGRAM
Address
b0 b5 b4 b3 b2
0
0
0
0
0
0
0
0
0 0 0
0
1
0
1
0
1
0
1
1
0
1
0
1
0
1
0
0 0 1
1
1
1
1
1
1
1
1
b1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
Character Patterns
(CGRAM Data)
b0 b7 b6 b5 b4
0
1
1
0
0
0
1
0
- - 0
0
1
0
0
0
1
0
0
1
1
1
0
1
1
1
- - 0
1
1
1
0
1
1
0
b3
1
0
0
0
0
0
0
0
1
0
0
1
0
0
0
0
b2
1
1
1
1
1
1
1
0
1
0
0
1
1
0
0
0
b1
1
0
0
0
0
0
0
0
1
0
0
1
0
1
0
0
b0
1
0
0
0
0
0
0
0
0
1
1
0
0
0
1
0
Table 5 Relationship between CGRAM Addresses, Character Codes (DDRAM) and Character
patterns (CGRAM Data)
Notes:
1.
Character code bits 0 to 2 correspond to CGRAM address bits 3 to 5 (3 bits: 8 types).
2.
CGRAM address bits 0 to 2 designate the character pattern line position. The 8th line is the cursor position
and its display is formed by a logical OR with the cursor. Maintain the 8th line data, corresponding to the
cursor display position, at 0 as the cursor display. If the 8th line data is 1, 1 bits will light up the 8th line
regardless of the cursor presence.
3.
Character pattern row positions correspond to CGRAM data bits 0 to 4 (bit 4 being at the left).
4.
As shown Table 5, CGRAM character patterns are selected when character code bits 4 to 7 are all 0.
However, since character code bit 3 has no effect, the T display example above can be selected by either
character code 00H or 08H.
5.
“1” for CGRAM data corresponds to display selection and “0” to non-selection,“-“ Indicates no effect.
6.
Different OPR1/2 ITO option can select different CGRAM size.
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When ICON RAM data is filled the corresponding position displayed is described as the following table.
When SHLS=1, ICON RAM map refer below table
ICON
D7~D5
Address
00H
01H
02H
03H
04H
05H
06H
07H
08H
09H
0AH
0BH
0CH
0DH
0EH
0FH
-
D4
ICON RAM bits
D2
D3
D1
D0
N3 = 0
N3 = 1
N3 = 0
N3 = 1
N3 = 0
N3 = 1
N3 = 0
N3 = 1
N3 = 0
N3 = 1
S1/S81
S6/S86
S11/S91
S16/S96
S21
S26
S31
S36
S41
S46
S51
S56
S61
S66
S71
S76
S1
S6
S11
S16
S21
S26
S31
S36
S41
S46
S51
S56
S61
S66
S71
S76
S2/S82
S7/S87
S12/S92
S17/S97
S22
S27
S32
S37
S42
S47
S52
S57
S62
S67
S72
S77
S2
S7
S12
S17
S22
S27
S32
S37
S42
S47
S52
S57
S62
S67
S72
S77
S3/S83
S8/S88
S13/S93
S18/S98
S23
S28
S33
S38
S43
S48
S53
S58
S63
S68
S73
S78
S3
S8
S13
S18
S23
S28
S33
S38
S43
S48
S53
S58
S63
S68
S73
S78
S4/S84
S9/S89
S14/S94
S19/S99
S24
S29
S34
S39
S44
S49
S54
S59
S64
S69
S74
S79
S4
S9
S14
S19
S24
S29
S34
S39
S44
S49
S54
S59
S64
S69
S74
S79
S5/S85
S10/S90
S15/S95
S20/S100
S25
S30
S35
S40
S45
S50
S55
S60
S65
S70
S75
S80
S5
S10
S15
S20
S25
S30
S35
S40
S45
S50
S55
S60
S65
S70
S75
S80
When SHLS=0, ICON RAM map refer below table
ICON
D7~D5
Address
00H
01H
02H
03H
04H
05H
06H
07H
08H
09H
0AH
0BH
0CH
0DH
0EH
0FH
-
D4
ICON RAM bits
D2
D3
D1
D0
N3 = 0
N3 = 1
N3 = 0
N3 = 1
N3 = 0
N3 = 1
N3 = 0
N3 = 1
N3 = 0
N3 = 1
S100/S20
S95/S15
S90/S10
S85/S5
S80
S75
S70
S65
S60
S55
S50
S45
S40
S35
S30
S25
S80
S75
S70
S65
S60
S55
S50
S45
S40
S35
S30
S25
S20
S15
S10
S5
S99/S19
S94/S14
S89/S9
S84/S4
S79
S74
S69
S64
S59
S54
S49
S44
S39
S34
S29
S24
S79
S74
S69
S64
S59
S54
S49
S44
S39
S34
S29
S24
S19
S14
S9
S4
S98/S18
S93/S13
S88/S8
S83/S3
S78
S73
S68
S63
S58
S53
S48
S43
S38
S33
S28
S23
S78
S73
S68
S63
S58
S53
S48
S43
S38
S33
S28
S23
S18
S13
S8
S3
S97/S17
S92S12
S87/S7
S82/S2
S77
S72
S67
S62
S57
S52
S47
S42
S37
S32
S27
S22
S77
S72
S67
S62
S57
S52
S47
S42
S37
S32
S27
S22
S17
S12
S7
S2
S96/S16
S91/S11
S86/S6
S81/S1
S76
S71
S66
S61
S56
S51
S46
S41
S36
S31
S26
S21
S76
S71
S66
S61
S56
S51
S46
S41
S36
S31
S26
S21
S16
S11
S6
S1
Table 6 ICON RAM map
V1.7a
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ST7036
Instructions
There are four categories of instructions that:
Designate ST7036 functions, such as display format, data length, etc.
Set internal RAM addresses
Perform data transfer with internal RAM
Others
instruction table at “Normal mode”
(when “EXT” option pin connect to VDD, the instruction set follow below table)
Instruction
Execution Time
Instruction Code
Instruction
Description
RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
Clear
Display
Return
Home
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Write "20H" to DDRAM. and set
DDRAM address to "00H" from AC
0
1
1
Set DDRAM address to "00H" from
AC and return cursor to its original
X
position if shifted. The contents of
DDRAM are not changed.
OSC= OSC= OSC=
380kHz 540kHz 700kHz
1.08
ms
0.76
ms
0.59
ms
1.08
ms
0.76
ms
0.59
ms
Entry Mode
Set
0
0
0
0
0
0
0
1
I/D
Sets cursor move direction and
specifies display shift. These
S
operations are performed during
data write and read.
Display
ON/OFF
0
0
0
0
0
0
1
D
C
B
X
S/C and R/L:
Set cursor moving and display shift
26.3 µs 18.5 µs 14.3 µs
X
control bit, and the direction, without
changing DDRAM data.
X
X
Cursor or
Display Shift
0
0
0
0
0
1
Function Set
0
0
0
0
1
DL
Set CGRAM
0
0
0
1
Set DDRAM
Address
0
0
1
Read Busy
Flag and
Address
Write Data
to RAM
Read Data
from RAM
S/C R/L
D=1:entire display on
C=1:cursor on
B=1:cursor position on
26.3 µs 18.5 µs 14.3 µs
26.3 µs 18.5 µs 14.3 µs
DL: interface data is 8/4 bits
N: number of line is 2/1
26.3 µs 18.5 µs 14.3 µs
AC5 AC4 AC3 AC2 AC1 AC0
Set CGRAM address in address
counter
26.3 µs 18.5 µs 14.3 µs
AC6 AC5 AC4 AC3 AC2 AC1 AC0
Set DDRAM address in address
counter
26.3 µs 18.5 µs 14.3 µs
N
X
0
1
Whether during internal operation or
not can be known by reading BF.
BF AC6 AC5 AC4 AC3 AC2 AC1 AC0
The contents of address counter
can also be read.
1
0
D7
D6
D5
D4
D3
D2
D1
D0
Write data into internal RAM
(DDRAM/CGRAM)
26.3 µs 18.5 µs 14.3 µs
1
1
D7
D6
D5
D4
D3
D2
D1
D0
Read data from internal RAM
(DDRAM/CGRAM)
26.3 µs 18.5 µs 14.3 µs
0
0
0
Note:
Be sure the ST7036 is not in the busy state (BF = 0) before sending an instruction from the MPU to the ST7036.
If an instruction is sent without checking the busy flag, the time between the first instruction and next instruction
will take much longer than the instruction time itself. Refer to Instruction Table for the list of each instruction
execution time.
V1.7a
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ST7036
instruction table at “Extension mode”
(when “EXT” option pin connect to VSS, the instruction set follow below table)
Instruction
Execution Time
Instruction Code
Instruction
Description
RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
Clear
Display
Return
Home
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
Write "20H" to DDRAM. and set
DDRAM address to "00H" from AC
1.08
ms
0.76
ms
0.59
ms
x
Set DDRAM address to "00H" from
AC and return cursor to its original
position if shifted. The contents of
DDRAM are not changed.
1.08
ms
0.76
ms
0.59
ms
Entry Mode
Set
0
0
0
0
0
0
0
1
I/D
Sets cursor move direction and
specifies display shift. These
S
operations are performed during
data write and read.
Display
ON/OFF
0
0
0
0
0
0
1
D
C
B
Function Set
0
0
0
Set DDRAM
Address
0
0
1
Read Busy
Flag and
Address
Write Data
to RAM
Read Data
from RAM
V1.7a
0
1
DL
N
OSC= OSC= OSC=
380kHz 540kHz 700kHz
D=1:entire display on
C=1:cursor on
B=1:cursor position on
DL: interface data is 8/4 bits
N: number of line is 2/1
DH IS2 IS1
DH: double height font
IS[2:1]: instruction table select
AC6 AC5 AC4 AC3 AC2 AC1 AC0
Set DDRAM address in address
counter
26.3 µs 18.5 µs 14.3 µs
26.3 µs 18.5 µs 14.3 µs
26.3 µs 18.5 µs 14.3 µs
26.3 µs 18.5 µs 14.3 µs
0
1
Whether during internal operation or
not can be known by reading BF.
BF AC6 AC5 AC4 AC3 AC2 AC1 AC0
The contents of address counter
can also be read.
1
0
D7
D6
D5
D4
D3
D2
D1
D0
Write data into internal RAM
(DDRAM/CGRAM/ICONRAM)
26.3 µs 18.5 µs 14.3 µs
1
1
D7
D6
D5
D4
D3
D2
D1
D0
Read data from internal RAM
(DDRAM/CGRAM/ICONRAM)
26.3 µs 18.5 µs 14.3 µs
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0
0
0
2007/10/17
ST7036
Instruction table 0(IS[2:1]=[0,0])
Cursor or
Display Shift
0
0
0
0
Set CGRAM
0
0
0
1
0
1
S/C R/L
X
S/C and R/L:
Set cursor moving and display shift
26.3 µs 18.5 µs 14.3 µs
X
control bit, and the direction, without
changing DDRAM data.
AC5 AC4 AC3 AC2 AC1 AC0
Set CGRAM address in address
counter
26.3 µs 18.5 µs 14.3 µs
Instruction table 1(IS[2:1]=[0,1])
Bias Set
0
0
0
0
0
1
Set ICON
Address
0
0
0
1
0
0
BS
1
0
BS=1:1/4 bias
BS=0:1/5 bias
26.3 µs 18.5 µs 14.3 µs
FX FX: fixed on high in 3-line
application and fixed on low in other
applications.
AC3 AC2 AC1 AC0
Power/ICON
Control/
Contrast Set
0
0
0
1
0
1
Ion Bon C5
Follower
Control
0
0
0
1
1
0
Fon
Contrast Set
0
0
0
1
1
1
C3
Set ICON address in address
counter.
Ion: ICON display on/off
Bon: set booster circuit on/off
C4
C5,C4: Contrast set for internal
follower mode.
Rab Rab Rab
2
1
0
C2
C1
C0
26.3 µs 18.5 µs 14.3 µs
26.3 µs 18.5 µs 14.3 µs
Fon: set follower circuit on/off
Rab2~0:
select follower amplified ratio.
26.3 µs 18.5 µs 14.3 µs
Contrast set for internal follower
mode.
26.3 µs 18.5 µs 14.3 µs
Instruction table 2(IS[2:1]=[1,0])
Double
Height
Position
Select
0
0
0
0
0
1
UD
X
x
x
UD: Double height position select
26.3 µs 18.5 µs 14.3 µs
Reserved
0
0
0
1
X
X
X
X
X
X
Do not use (reserved for test)
26.3 µs 18.5 µs 14.3 µs
Instruction table 3(IS[2:1]=[1,1]):Do not use (reserved for test)
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ST7036
Instruction Description
Clear Display
RS R/W
0
0
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
0
0
0
0
0
0
0
1
Clear all the display data by writing "20H" (space code) to all DDRAM address, and set DDRAM address to
"00H" into AC (address counter). Return cursor to the original status, namely, bring the cursor to the left edge
on first line of the display. Make entry mode increment (I/D = "1").
Return Home
RS R/W
0
0
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
0
0
0
0
0
0
1
X
Return Home is cursor return home instruction. Set DDRAM address to "00H" into the address counter.
Return cursor to its original site and return display to its original status, if shifted. Contents of DDRAM does
not change.
Entry Mode Set
RS R/W
0
0
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
0
0
0
0
0
1
I/D
S
Set the moving direction of cursor and display.
I/D : Increment / decrement of DDRAM address (cursor or blink)
When I/D = "High", cursor/blink moves to right and DDRAM address is increased by 1.
When I/D = "Low", cursor/blink moves to left and DDRAM address is decreased by 1.
* CGRAM operates the same as DDRAM, when read from or write to CGRAM.
S: Shift of entire display
When DDRAM read (CGRAM read/write) operation or S = "Low", shift of entire display is not performed. If
S = "High" and DDRAM write operation, shift of entire display is performed according to I/D value (I/D =
"1" : shift left, I/D = "0" : shift right).
V1.7a
S
I/D
Description
H
H
Shift the display to the left
H
L
Shift the display to the right
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ST7036
Display ON/OFF
RS R/W
0
0
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
0
0
0
0
1
D
C
B
Control display/cursor/blink ON/OFF 1 bit register.
D : Display ON/OFF control bit
When D = "High", entire display is turned on.
When D = "Low", display is turned off, but display data is remained in DDRAM.
C : Cursor ON/OFF control bit
When C = "High", cursor is turned on.
When C = "Low", cursor is disappeared in current display, but I/D register remains its data.
B : Cursor Blink ON/OFF control bit
When B = "High", cursor blink is on, that performs alternate between all the high data and display
character at the cursor position.
When B = "Low", blink is off.
Alternating
display
Every
64 frames
Cursor
Cursor or Display Shift
RS R/W
0
0
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
0
0
0
1
S/C R/L
X
X
S/C: Screen/Cursor select bit
When S/C=”High”, Screen is controlled by R/L bit.
When S/C=”Low”, Cursor is controlled by R/L bit.
R/L: Right/Left
When R/L=”High”, set direction to right.
When R/L=”Low”, set direction to left.
Without writing or reading of display data, shift right/left cursor position or display. This instruction is used to
correct or search display data. During 2-line mode display, cursor moves to the 2nd line after 40th digit of 1st
line. Note that display shift is performed simultaneously in all the line. When displayed data is shifted
repeatedly, each line shifted individually. When display shift is performed, the contents of address counter are
not changed.
V1.7a
S/C
R/L
Description
L
L
Shift cursor to the left
AC=AC-1
L
H
Shift cursor to the right
AC=AC+1
H
L
Shift display to the left. Cursor follows the display shift
AC=AC
H
H
Shift display to the right. Cursor follows the display shift AC=AC
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AC Value
2007/10/17
ST7036
Function Set
RS R/W
0
0
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
0
0
1
DL
N
DH IS2 IS1
DL : Interface data length control bit
When DL = "High", it means 8-bit bus mode with MPU.
When DL = "Low", it means 4-bit bus mode with MPU. So to speak, DL is a signal to select
8-bit or 4-bit bus mode.
When 4-bit bus mode, it needs to transfer 4-bit data by two times.
N : Display line number control bit
When N = "High", 2-line display mode is set.
When N = "Low", it means 1-line display mode.
When “N3” option pin connect to VDD, N must set “N=1”.
DH : Double height font type control bit
When DH = " High " and N= “Low”, display font is selected to double height mode(5x16 dot),RAM address
can only use 00H~27H.
When DH= “High” and N= “High”, it is forbidden.
When DH = " Low ", display font is normal (5x8 dot).
N
L
L
H
H
EXT option pin connect to
high
DH
Character
Display Lines
Font
L
H
L
H
1
1
2
2
5x8
5x8
5x8
5x8
EXT option pin connect to
low
Character
Display Lines
Font
1
1
2
5x8
5x16
5x8
Forbidden
2 line mode normal display (DH=0/N=1)
1 line mode with double height font (DH=1/N=0)
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ST7036
IS[2:1]: instruction table select
When IS[2:1]=(0,0): normal instruction be selected(refer instruction table 0)
When IS[2:1]=(0,1):extension instruction be selected(refer instruction table 1 )
When IS[2:1]=(1,0):extension instruction be selected(refer instruction table 2 )
When IS[2:1]=(1,1):Do not use (reserved for test)
Double height position set: IS[2:1]=(1,0)
RS R/W
0
0
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
0
0
0
1
UD
X
X
X
UD: Select double height font display position of screen.(N3=VDD)
When UD = "High", double height font is show on Com1~Com16.
RS R/W
0
0
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
0
1
0
0
AC3 AC2 AC1 AC0
When UD = "Low", double height font is show on Com9~Com24.
V1.7a
DH
UD
2 LINES(N3=VSS)
H
H
Com1~Com16 Double Height
H
L
L
X
3 LINES(N3=VDD)
Com1~Com16 Double Height
Com17~Com24 Normal Display
Com1~Com8 Normal Display
Com1~Com16 Double Height
Com9~Com24 Double Height
Normal Display
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Normal Display
2007/10/17
ST7036
3 Line mode normal display (DH = 0 / N = 1 / UD = don`t care )
COM1 ..8 is normal , COM9 .. 24 is a double height font (DH = 1 / N = 1 / UD = 0 )
COM17 ..24 is normal , COM1 .. 16 is a double height font (DH = 1 / N = 1 / UD = 1 )
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ST7036
Set CGRAM Address
RS R/W
0
0
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
0
1
AC5 AC4 AC3 AC2 AC1 AC0
Set CGRAM address to AC.
This instruction makes CGRAM data available from MPU.
Set DDRAM Address
RS R/W
0
0
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
1
AC6 AC5 AC4 AC3 AC2 AC1 AC0
Set DDRAM address to AC.
This instruction makes DDRAM data available from MPU.
When 1-line display mode (N = 0), DDRAM address is from "00H" to "4FH".
In 2-line display mode (N = 1), DDRAM address in the 1st line is from "00H" to "27H", and
DDRAM address in the 2nd line is from "40H" to "67H".
In 3-line display mode (N3=1, N=1), DDRAM address in the 1st line is from “00H” to “OFH”, DDRAM in the
2nd line is from “10H” to “1FH”, and DDRAM in the 3rd line is from “20H” to “2FH”.
Read Busy Flag and Address
RS R/W
0
1
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
BF AC6 AC5 AC4 AC3 AC2 AC1 AC0
When BF = “High”, indicates that the internal operation is being processed. So during this time the next
instruction cannot be accepted.
The address Counter (AC) stores DDRAM/CGRAM addresses, transferred from IR.
After writing into (reading from) DDRAM/CGRAM, AC is automatically increased (decreased) by 1.
Write Data to CGRAM,DDRAM or ICON RAM
RS R/W
1
0
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
D7
D6
D5
D4
D3
D2
D1
D0
Write binary 8-bit data to CGRAM,DDRAM or ICON RAM
The selection of RAM from DDRAM, CGRAM or ICON RAM, is set by the previous address set instruction
: DDRAM address set, CGRAM address set, ICON RAM address set. RAM set instruction can also determine
the AC
direction to RAM.
After write operation, the address is automatically increased/decreased by 1, according to
the entry mode.
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ST7036
Read Data from CGRAM,DDRAM or ICON RAM
RS R/W
1
1
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
D7
D6
D5
D4
D3
D2
D1
D0
Read binary 8-bit data from DDRAM/CGRAM./ICON RAM
The selection of RAM is set by the previous address set instruction. If address set instruction of RAM is not
performed before this instruction, the data that read first is invalid, because the direction of AC is not
determined. If you read RAM data several times without RAM address set instruction before read operation,
you can get correct RAM data from the second, but the first data would be incorrect, because there is no time
margin to transfer RAM data.
Bias Set
BS: bias selection
When BS=”High”, the bias will be 1/4
When BS=”Low”, the bias will be 1/5
BS will be invalid when external bias resistors are used(OPF1=1,OPF2=1)
FX: must be fixed on high in 3-line application and fixed on low in other applications.
Set ICON RAM address
Set ICON RAM address to AC.
This instruction makes ICON data available from MPU.
When IS=1 at Extension mode,
The ICON RAM address is from "00H" to "0FH".
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ST7036
Power/ICON control/Contrast set(high byte)
RS R/W
0
0
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
0
1
0
1
ION BON C5
C4
Ion: set ICON display on/off
When Ion = "High", ICON display on.
When Ion = "Low", ICON display off.
Bon: switch booster circuit
Bon can only be set when internal follower is used (OPF1=0,OPF2=0).
When Bon = "High", booster circuit is turn on.
When Bon = "Low", booster circuit is turn off.
C5,C4 : Contrast set(high byte)
C5,C4,C3,C2,C1,C0 can only be set when internal follower is used (OPF1=0,OPF2=0).They can more
precisely adjust the input reference voltage of V0 generator. The details please refer to the supply voltage
for LCD driver.
Follower control
RS R/W
0
0
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
Rab Rab Rab
0
1
1
0 FON
2
1
0
Fon: switch follower circuit
Fon can only be set when internal follower is used (OPF1=0,OPF2=0).
When Fon = "High", internal follower circuit is turn on.
When Fon = "Low", internal follower circuit is turn off.
Note that Fon must be set to “Low” if (OPF1, OPF2) is not (0,0).
Rab2,Rab1,Rab0 : V0 generator amplified ratio
Rab2,Rab1,Rab0 can only be set when internal follower is used (OPF1=0,OPF2=0).They can adjust the
amplified ratio of V0 generator. The details please refer to the supply voltage for LCD driver.
Contrast set(low byte)
RS R/W
0
0
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
0
1
1
1
C3
C2
C1
C0
C3,C2,C1,C0:Contrast set(low byte)
C5,C4,C3,C2,C1,C0 can only be set when internal follower is used (OPF1=0,OPF2=0).They can more
precisely adjust the input reference voltage of V0 generator. The details please refer to the supply voltage
for LCD driver.
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ST7036
Reset Function
Initializing by Internal Reset Circuit
An internal reset circuit automatically initializes the ST7036 when the power is turned on. The
following instructions are executed during the initialization. The busy flag (BF) is kept in the busy state (BF = 1)
until the initialization ends. The busy state lasts for 40 ms after VDD rises to stable.
1.
Display clear
2.
Function set:
DL = 1; 8-bit interface data
N = 0; 1-line display
DH=0; normal 5x8 font
IS[2:1]=(0,0); use instruction table 0
3.
Display on/off control:
D = 0; Display off
C = 0; Cursor off
B = 0; Blinking off
4.
Entry mode set:
I/D = 1; Increment by 1
S = 0; No shift
5.
3 line: FX=1
1/2 line: FX=0
6.
ICON control
Ion=0; ICON off
7.
Power control
BS=0; 1/5bias
Bon=0; booster off
Fon=0; follower off
(C5,C4,C3,C2,C1,C0)=(1,0,0,0,0,0)
(Rab2,Rab1,Rab0)=(0,1,0)
8.
Double Height Position Select
UD=0, double height font is show on Com9~Com24.
Note:
If the electrical characteristics conditions listed under the table Power Supply Conditions Using
Internal Reset Circuit are not met, the internal reset circuit will not operate normally and will fail
to initialize the ST7036.
When internal Reset Circuit not operate,ST7036 can be reset by XRESET pin from MPU control signal.
V1.7a
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ST7036
Initializing by Instruction
8-bit Interface (fosc=380kHz)
P O W E R O N o r e x te r n a l r e s e t
W a it tim e > 4 0 m S
A fte r V D D s ta b le
F u n c tio n s e t
RS
0
R /W
0
DB7
0
DB6
0
DB5
1
DB4
1
DB3
N
DB2
DH
DB1
IS 2
DB0
IS 1
B F cannot be
c h e c k e d b e fo r e
th is in s tr u c tio n .
DB2
DH
DB1
IS 2
DB0
IS 1
B F cannot be
c h e c k e d b e fo r e
th is in s tr u c tio n .
DB2
1
DB1
0
DB0
FX
DB2
DB1
DB0
C2
C1
C0
W a it tim e > 2 6 .3 μ S
F u n c tio n s e t
RS
0
R /W
0
DB7
0
DB6
0
DB5
1
DB4
1
DB3
N
W a it tim e > 2 6 .3 μ S
B ia s S e t
RS
0
R /W
0
DB7
0
DB6
0
DB5
0
DB4
1
DB3
BS
W a it tim e > 2 6 .3 μ S
C o n tr a s t s e t
RS
0
R /W
0
DB7
0
DB6
1
DB5
1
DB4
1
DB3
C3
W a it tim e > 2 6 .3 μ S
P o w e r /IC O N /C o n tr a s t c o n t ro l
RS
0
R /W
0
DB7
0
DB6
1
DB5
0
DB4
1
DB3
Io n
DB2
DB1
DB0
Bon
C5
C4
DB2
DB1
DB0
R ab2
R ab1
R ab0
DB1
C
DB0
B
W a it tim e > 2 6 .3 μ S
F o llo w e r c o n tr o l
RS
0
R /W
0
DB7
0
DB6
1
DB5
1
DB4
0
DB3
Fon
W a it tim e > 2 6 .3 μ S
D is p la y O N /O F F c o n tr o l
RS
0
R /W
0
DB7
0
DB6
0
DB5
0
DB4
0
DB3
1
DB2
D
W a it tim e > 2 6 .3 μ S
In itia liz a tio n e n d
V1.7a
37/70
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ST7036
Initial Program Code Example For 8051 MPU(8 Bit Interface):
;--------------------------------------------------------------------------------INITIAL_START:
CALL DELAY40mS
MOV A,#38H
;FUNCTION SET
CALL WRINS_NOCHK ;8 bit, N=1,5*7dot
CALL DELAY30uS
MOV A,#38H
;FUNCTION SET
CALL WRINS_NOCHK ;8 bit, N=1,5*7dot
CALL DELAY30uS
MOV A,#14H
;set bias
CALL WRINS_CHK
CALL DELAY30uS
MOV A,#78H
;Contrast set adjustment
CALL WRINS_CHK
CALL DELAY30uS
MOV A,#5EH
;Power/ICON/Contrast control
CALL WRINS_CHK
CALL DELAY30uS
MOV A,#6AH
;Follower control
CALL WRINS_CHK
CALL DELAY30uS
MOV A,#0CH
;DISPLAY ON
CALL WRINS_CHK
CALL DELAY30uS
MOV A,#01H
;CLEAR DISPLAY
CALL WRINS_CHK
CALL DELAY2mS
MOV A,#06H
;ENTRY MODE SET
CALL WRINS_CHK
;CURSOR MOVES TO RIGHT
CALL DELAY30uS
;--------------------------------------------------------------------------------MAIN_START:
XXXX
XXXX
XXXX
XXXX
;--------------------------------------------------------------------------------WRINS_CHK:
CALL CHK_BUSY
WRINS_NOCHK:
CLR
RS
;EX: Port 3.0
CLR
RW
;EX: Port 3.1
SETB E
;EX:Port 3.2
MOV P1,A
;EX:Port 1=Data Bus
CLR
E
MOV P1,#FFH
;For Check Busy Flag
RET
;--------------------------------------------------------------------------------CHK_BUSY:
;Check Busy Flag
CLR
RS
SETB RW
SETB E
JB
P1.7,$
CLR
E
RET
V1.7a
38/70
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ST7036
V1.7a
4-bit Interface (fosc=380kHz)
39/70
2007/10/17
ST7036
Initial Program Code Example For 8051 MPU(4 Bit Interface):
;------------------------------------------------------------------INITIAL_START:
CALL DELAY40mS
MOV
A,#30H
; FUNCTION SET
CALL
WRINS_ONCE ; 8 bit, DL = 1
CALL
DELAY2mS
MOV
CALL
CALL
A,#30H
; FUNCTION SET
WRINS_ONCE ; 8 bit, DL = 1
DELAY30uS
MOV
CALL
CALL
A,#30H
; FUNCTION SET
WRINS_ONCE ; 8 bit, DL = 1
DELAY30uS
CALL
MOV
CALL
CALL
CHK_BUSY
A,#20H
; FUNCTION SET
WRINS_ONCE ; 4 bit, DL = 0
DELAY30uS
MOV
CALL
CALL
A,#29H
WRINS_CHK
DELAY30uS
; FUNCTION SET
; 4 bit, DL = 0, N = 1,
; IS2 = 0, IS1 = 1
MOV
CALL
CALL
A,#14H
WRINS_CHK
DELAY30uS
;bias
MOV
CALL
CALL
A,#78H
WRINS_CHK
DELAY30uS
;Contrast set
MOV
CALL
CALL
A,#5EH
WRINS_CHK
DELAY30uS
;Power/ICON/Contrast
MOV
CALL
CALL
A,#6AH
WRINS_CHK
DELAY30uS
;Follower control
MOV
CALL
CALL
A,#0CH
WRINS_CHK
DELAY30uS
;DISPLAY ON
MOV
CALL
CALL
A,#01H
WRINS_CHK
DELAY2mS
;CLEAR DISPLAY
XXXX
;------------------------------------------------------------------WRINS_CHK:
CALL CHK_BUSY
WRINS_NOCHK:
PUSH A
ANL A,#F0H
CLR RS
;EX: Port 3.0
CLR RW
;EX: Port 3.1
SETB E
;EX: Port 3.2
MOV P1,A
;EX:Port1=Data Bus
CLR E
POP A
SWAP A
WRINS_ONCE:
ANL A,#F0H
CLR RS
CLR RW
SETB E
MOV P1,A
CLR E
MOV P1,#FFH
;For Check Bus Flag
RET
;------------------------------------------------------------------CHK_BUSY:
;Check Busy Flag
PUSH A
MOV P1,#FFH
$1
CLR RS
SETB RW
SETB E
MOV A,P1
CLR E
MOV P1,#FFH
CLR RS
SETB RW
SETB E
NOP
CLR E
JB
A.7,$1
POP A
RET
MOV A,#06H
;ENTRY MODE SET
CALL WRINS_CHK
CALL DELAY30uS
;------------------------------------------------------------------MAIN_START:
XXXX
XXXX
XXXX
V1.7a
40/70
2007/10/17
ST7036
V1.7a
Serial interface & IIC interface ( fosc = 380kHz )
41/70
2007/10/17
ST7036
Initial Program Code Example For 8051 MPU ( Serial Interface ) :
;--------------------------------------------------------------------------------INITIAL_START:
CALL HARDWARE_RESET
CALL DELAY40mS
MOV A,#38H
;FUNCTION SET
CALL WRINS_NOCHK ;8 bit, N=1,5*7dot
CALL DELAY30uS
MOV A,#39H
;FUNCTION SET
CALL WRINS_NOCHK ;8 bit, N=1,5*7dot,IS=1
CALL DELAY30uS
MOV A,#14H
;bias
CALL WRINS_NOCHK
CALL DELAY30uS
MOV A,#78H
;Contrast set
CALL WRINS_NOCHK
CALL DELAY30uS
MOV A,#5EH
;Power/ICON/Contrast control
CALL WRINS_NOCHK
CALL DELAY30uS
MOV A,#6AH
;Follower control
CALL WRINS_NOCHK
CALL DELAY200mS
;for power stable
MOV A,#0CH
;DISPLAY ON
CALL WRINS_NOCHK
CALL DELAY30uS
MOV A,#01H
;CLEAR DISPLAY
CALL WRINS_NOCHK
CALL DELAY2mS
MOV A,#06H
;ENTRY MODE SET
CALL WRINS_NOCHK ;CURSOR MOVES TO RIGHT
CALL DELAY30uS
;--------------------------------------------------------------------------------MAIN_START:
XXXX
XXXX
XXXX
XXXX
.
.
.
;--------------------------------------------------------------------------------WRINS_NOCHK:
PUSH 1
MOV
R1,#8
CLR
RS
$1
RLC
A
MOV SI,C
SETB SCL
NOP
CLR
SCL
DJNZ R1,$1
POP 1
CALL
RET
V1.7a
DLY1.5mS
42/70
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ST7036
Interfacing to the MPU
The ST7036 can send data in two 4-bit operations/one 8-bit operation, serial 1 bit operation or fast I2C operation,
thus allowing interfacing with 4-bit, 8-bit or I2C MPU.
For 4-bit interface data, only four bus lines (DB4 to DB7) are used for transfer. Bus lines DB0 to DB3
are disabled. The data transfer between the ST7036 and the MPU is completed after the 4-bit data has been
transferred twice. As for the order of data transfer, the four high order bits (for 8-bit operation, DB4 to DB7)
are transferred before the four low order bits (for 8-bit operation, DB0 to DB3). The busy flag must be
checked (one instruction) after the 4-bit data has been transferred twice. Two more 4-bit operations then
transfer the busy flag and address counter data.
Example of busy flag check timing sequence
CSB
RS
R/W
E
Internal
operation
DB7
Functioning
IR7
IR3
Instruction write
Busy flag check
AC3
Busy flag check
IR7
IR3
Instruction write
Intel 8051 interface(4 Bit)
P1.0 to P1.3
COM1 to
COM16/24
DB4 to DB7
4
P3.0
P3.1
P3.2
P3.3
RS
R/W
E
CSB
Intel 8051 Serial
V1.7a
Not
Busy
AC3
SEG1 to
SEG100/80
16/24
100/80
ST7036
43/70
2007/10/17
ST7036
For 8-bit interface data, all eight bus lines (DB0 to DB7) are used.
Example of busy flag check timing sequence
CSB
RS
R/W
E
Internal
operation
Functioning
DB7
Data
Instruction
write
Busy
Busy
Busy flag
check
Busy flag
check
Busy flag
check
Data
Instruction
write
Intel 8051 interface(8 Bit)
P1.0 to P1.7
COM1 to
COM16/24
DB0 to DB7
8
P3.0
P3.1
P3.2
P3.3
RS
R/W
E
CSB
Intel 8051 Serial
V1.7a
Not
Busy
16/24
SEG1 to 100/80
SEG100/80
ST7036
44/70
2007/10/17
ST7036
For serial interface data, only two bus lines (DB6 to DB7) are used.
Example of timing sequence
CSB
SI
D7
D6
D5
D4
D3
D2
D1
D0
D7
D6
D5
D4
D3
D2
SCL
1
2
3
4
5
6
7
8
9
10
11
12
13
14
RS
Intel 8051 interface ( Serial 4-line )
P1.6 to P1.7
COM1 to
COM16/24
2
16/24
SI , SCL
P3.0
P3.3
RS
CSB
SEG1 to 100/80
SEG100/80
Intel 8051 Serial
V1.7a
ST7036
45/70
2007/10/17
ST7036
For I2C interface data, all eight bus lines (DB0 to DB7) are used.
Example of timing sequence
SDA
D7
D6
D5
D4
D3
D2
D1
D0
ACK
1
2
3
4
5
6
7
8
9
V1.7a
D0
ACK
......
SCL
.......
Intel 8051 interface ( I2C interface )
46/70
2007/10/17
ST7036
Supply Voltage for LCD Drive
When external bias resistors are used
(OPF1=1,OPF2=1)
VCC (2.7~ 5.5V)
VCC (2.7~ 5.5V)
Vext
OPF1 OPF2 VDD
VOUT
V0
VIN
CAP1P
CAP1N
OPF1 OPF2
VR
VDD
VR
VOUT
V0
VIN
R
V1
V2
V3
R
CAP1P
V1
CAP1N
V2
VLCD
V3
R
V4
V4
R
R
VSS
R
R
VLCD
R
1/4 bias
Vext
VSS
1/5 bias
GND
GND
When built-in bias resistors(9.6KΩ) are used
(OPF1=1,OPF2=0)
VCC(2.7~5.5V)
OPF1
VOUT
Vext
VDD
VR
V0
VIN
CAP1P
V1
CAP1N
V2
VLCD
V3
V4
OPF2
VSS
GND
Note: Do not use built-in booster while built-in bias resistors are used.
V1.7a
47/70
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ST7036
When built-in bias resistors(3.3KΩ) are used
(OPF1=0,OPF2=1)
VCC (2.7~ 5.5V)
OPF2
Vext
VDD
VOUT
VIN
VR
V0
CAP1P
V1
CAP1N
V2
VLCD
V3
V4
OPF1
VSS
GND
Note: Do not use built-in booster while built-in bias resistors are used.
When built-in voltage followers with external Vout are used
(OPF1=0,OPF2=0 and instruction setting Bon=0,Fon=1)
VCC (2.7~ 5.5V)
Vext ≧ V0
Don't need to connect stable capacitor when
use internal follower circuit
VOUT
VDD
VIN
V0
CAP1P
V1
CAP1N
V2
VLCD
V3
V4
OPF1 OPF2 VSS
GND
V1.7a
48/70
2007/10/17
ST7036
When built-in booster and voltage followers are used(OPF1=0,OPF2=0)
VCC (2.7~ 3.5V)
Don't need to connect stable capacitor when
use internal follower circuit
VIN
VOUT
VDD
V0
CAP1P
V1
CAP1N
V2
VOUT≦2xVDD
VDD=2.7~3.5V
VSS=0V
VLCD
V3
2 x step-up voltage relationships
V4
OPF1 OPF2 VSS
GND
Note:
Ensure V0 level stable, that must let |Vout-V0| over 0.5V(if panel size over 4.5”,the |Vout-V0| propose over 0.8V).
|Vout-V0|>0.5V(minimum)
Vout
V0
VCC
VDD
GND
VSS
(System side)
V1.7a
(ST7036Side)
49/70
2007/10/17
ST7036
V0 voltage follower value calculation
Vout(≧VDD)
VDD
Rb
) x Vref
Ra
α+36
)
While Vref=VDD x (
100
Vref
V0=(1+
V0
Rb
Ra
VSS
C5
C4
C3
C2
C1
C0
α
Rab2
Rab1
Rab0
1+Rb/Ra
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
1
1
0
0
1
1.25
0
0
0
0
1
0
2
0
1
0
1.5
:
:
0
1
1
1.8
1
0
0
2
:
:
1
1
1
1
0
1
61
1
0
1
2.5
1
1
1
1
1
0
62
1
1
0
3
1
1
1
1
1
1
63
1
1
1
3.75
8
7
6
5
4
3
2
1
0
1
3
5
7
9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 51 53 55 57 59 61 63
V0 level (Condition:Booster on, Follower on, VIN=3.5V, VDD=3.0V,Display off)
The recommended curve: follower = 04H
Notes:
1.
Vout ≧V0 ≧V1 ≧V2 ≧V3 ≧V4 ≧Vss must be maintained.
2.
If the calculation value of V0 is higher than Vout, the real V0 value will saturate to Vout.
3.
internal built-in booster can only be used when OPF1=0,OPF2=0.
V1.7a
50/70
2007/10/17
ST7036
8
7
6
5
4
3
2
1
0
0 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 54 56 58 60 62
V0 level (Condition: VDD=5.0V, external Vout=7.0V)
The recommended curve: followe=01H
Notes:
1.
Vout ≧V0 ≧V1 ≧V2 ≧V3 ≧V4 ≧Vss must be maintained.
2.
If the calculation value of V0 is higher than Vout, the real V0 value will saturate to Vout.
3.
internal built-in booster can only be used when OPF1=0,OPF2=0.
V1.7a
51/70
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ST7036
AC Characteristics
68 Interface
RS
R/W
tAW6
tAH6
CSB
tCYC6
tEWH
tEWL
E
tDS6
tDH6
D0 to D7
(Write)
tACC6
tOH6
D0 to D7
(Read)
Item
Address hold time
Signal
RS
Symbol
Condition
VDD=2.7 to 4.5V
Rating
( Ta =-35°C to 85°C )
VDD=4.5 to 5.5V
Rating
Units
Min.
Max.
Min.
Max.
20
-
20
-
20
-
20
-
400
-
280
-
100
-
80
-
40
-
20
-
-
500
-
400
300
-
150
-
tAH6
—
Address setup time
RS
tAW6
System cycle time
RS
tCYC6
D0 to D7
tDS6
Data setup time
—
ns
—
Data hold time
D0 to D7
tDH6
Access time
D0 to D7
tACC6
ns
ns
CL = 100 pF
ns
Output disable time
D0 to D7
tOH6
Enable H pulse time
E
tEWH
—
200
-
120
-
ns
Enable L pulse time
E
tEWL
—
150
-
130
-
ns
Note: All timing is specified using 20% and 80% of VDD as the reference.
V1.7a
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ST7036
Serial Interface
tCSS
tCSH
CSB
tSAS
tSAH
RS
tSCYC
tSLW
tSHW
SCL
tSDS
tSDH
SI
Item
Signal
Symbol
Condition
VDD=2.7 to 4.5V
Rating
Min.
tSCYC
Serial Clock Period
SCL “H” pulse width
SCL
Address hold time
Data setup time
Data hold time
CS-SCL time
—
tSLW
SCL “L” pulse width
Address setup time
tSHW
RS
SI
CS
tSAS
tSAH
tSDS
tSDH
tCSS
tCSH
—
—
—
Max.
( Ta =-35°C to 85°C )
VDD=4.5 to 5.5V
Rating
Units
Min.
Max.
200
-
100
-
20
-
20
-
160
-
120
-
10
-
10
-
250
-
150
-
10
-
10
-
10
-
20
-
20
-
20
-
350
-
200
-
ns
ns
ns
ns
*1 All timing is specified using 20% and 80% of VDD as the standard.
V1.7a
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ST7036
I2C interface
SDA
tBUF
tHIGH
tLOW
tSU;DAT
SCL
tf
tDH;STA
tr
SDA
tHD;DAT
tSU;STA
Item
Signal Symbol Condition
SCL clock frequency
SCL clock low period
fSCLK
SCL
SCL clock high period
Data set-up time
Data hold time
SCL,SDA rise time
SDA
SCL,
SDA
Setup time for STOP condition
V1.7a
—
tHIGH
SCL,SDA fall time
Capacitive load represent by each bus
line
Setup time for a repeated START
condition
SDA
Start condition hold time
Bus free time between a Stop and
START condition
tLOW
SCL
tSU;DAT
tHD:DAT
tr
—
—
tf
tSU;STO
VDD=2.7 to 4.5V
Rating
( Ta =-35°C to 85°C )
VDD=4.5 to 5.5V
Rating
Units
Min.
Max.
Min.
Max.
DC
300K
—
DC
2.5
1.3
400
—
0.6
—
0.6
—
1800
—
700
—
ns
0
—
0
0.5
µs
20+0.1Cb
300
20+0.1Cb
300
20+0.1Cb
300
20+0.1Cb
300
kHz
µs
ns
Cb
—
—
400
—
400
pf
tSU;STA
—
0.6
—
0.6
—
µs
tHD;STA
—
1.8
—
1.0
—
µs
tSU;STO
—
0.6
—
0.6
—
µs
tBUF
—
1.3
—
1.3
—
µs
54/70
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ST7036
Internal Power Supply Reset
2.7V/4.5V
0.2V
0.2V
trcc
0.2V
tOFF
tOFF≧1mS
0.1mS≦trcc≦10mS
Notes:
tOFF compensates for the power oscillation period caused by momentary power supply
oscillations.
Specified at 4.5V for 5V operation, and at 2.7V for 3V operation.
For if 2.7V/4.5V is not reached during 3V/5V operation, internal reset circuit will not
operate normally.
Hardware reset(XRESET)
tr≦100nS
2.7V/4.5V
0.2V
tL>100uS
V1.7a
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ST7036
Absolute Maximum Ratings
Characteristics
Symbol
Value
Power Supply Voltage
VDD
-0.3 to +6.0
LCD Driver Voltage
VLCD
7.0- Vss to -0.3+Vss
Input Voltage
VIN
-0.3 to VDD+0.3
Operating Temperature
TA
-30 C to + 85 C
Storage Temperature
TSTO
-65 C to + 150 C
o
o
o
o
DC Characteristics
Symbol Characteristics
V1.7a
(VDD = 2.7 V, TA =-35℃ to 85℃)
Test Condition
Min. Typ. Max. Unit
VDD
Operating Voltage
-
2.7
-
4.5
V
VLCD
LCD Voltage
V0-Vss
2.7
-
7.0
V
VIN
Power Supply
-
-
-
3.5
V
IDD
Power Supply Current
VDD=3.0V
(Use internal
booster/follower circuit)
-
160
230
uA
VIH1
Input High Voltage
(Except OSC1)
-
0.7
VDD
-
VDD
V
VIL1
Input Low Voltage
(Except OSC1)
-
- 0.3
-
0.8
V
VIH2
Input High Voltage
(OSC1)
-
0.7
VDD
-
VDD
V
VIL2
Input Low Voltage
(OSC1)
-
-
-
0.2
VDD
V
VOH
Output High Voltage
(DB0 - DB7)
IOH = -1.0mA
0.7
VDD
-
-
V
VOL
Output Low Voltage
(DB0 - DB7)
IOL = 1.0mA
-
-
0.8
V
RCOM
Common Resistance
VLCD = 4V, Id = 0.05mA
-
2
20
KΩ
RSEG
Segment Resistance
VLCD = 4V, Id = 0.05mA
-
2
30
KΩ
ILEAK
Input Leakage
Current
VIN = 0V to VDD
-1
-
1
µA
IPUP
Pull Up MOS Current
VDD = 3V
20
30
40
µA
fOSC
Oscillation frequency
VDD = 3V,1/17duty
350
540
1100
kHz
56/70
2007/10/17
ST7036
DC Characteristics
(VDD = 4.5 V ,TA = -35℃ to 85℃)
Symbol Characteristics
V1.7a
Test Condition
Min. Typ. Max.
Unit
VDD
Operating Voltage
-
4.5
-
5.5
V
VLCD
LCD Voltage
V0-Vss
2.7
-
7.0
V
VIN
Power Supply
-
-
-
3.5
V
IDD
Power Supply Current
VDD=5.0V
(Use internal
booster/follower circuit)
-
240
340
µA
VIH1
Input High Voltage
(Except OSC1)
-
0.7
VDD
-
VDD
V
VIL1
Input Low Voltage
(Except OSC1)
-
-0.3
-
0.8
V
VIH2
Input High Voltage
(OSC1)
-
0.7
VDD
-
VDD
V
VIL2
Input Low Voltage
(OSC1)
-
-
-
1.0
V
VOH
Output High Voltage
(DB0 - DB7)
IOH = -1.0mA
0.8
VDD
-
VDD
V
VOL
Output Low Voltage
(DB0 - DB7)
IOL = 1.0mA
-
-
0.8
V
RCOM
Common Resistance
VLCD = 4V, Id = 0.05mA
-
2
20
KΩ
RSEG
Segment Resistance
VLCD = 4V, Id = 0.05mA
-
2
30
KΩ
ILEAK
Input Leakage
Current
VIN = 0V to VDD
-1
-
1
µA
IPUP
Pull Up MOS Current
VDD = 5V
65
95
125
µA
fOSC
Oscillation frequency
VDD = 5V,1/17duty
350
540
1100
kHz
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ST7036
LCD Frame Frequency
1/16 Duty(ST7066U normal mode); Assume the oscillation frequency is 540KHZ, 1 clock cycle time
= 1.85us, 1/16 duty; 1/5 bias,1 frame =1.85us x 200 x 16 = 5.92ms=168.9Hz(SHLC and SHLS connect
to High)
200 clocks
1
2
3
4
16
1
2
3
4
16
1
2
3
4
16
V0
V1
V2
COM1
V3
V4
Vss
V0
V1
V2
COM2
V3
V4
Vss
V0
V1
V2
COM16
V3
V4
Vss
V0
V1
V2
SEGx off
V3
V4
Vss
V0
V1
V2
SEGx on
V3
V4
Vss
1 frame
V1.7a
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ST7036
1/17 Duty(Extension mode); Assume the oscillation frequency is 540KHZ, 1 clock cycle time =
1.85us, 1/17 duty; 1/5 bias,1 frame =1.85us x 200 x 17 = 6.29ms=159Hz(SHLC and SHLS connect to
High)
200 clocks
1
2
3
4
17
1
2
3
4
17
1
2
3
4
17
V0
V1
V2
COM1
V3
V4
Vss
V0
V1
V2
COM2
V3
V4
Vss
V0
V1
V2
COM17
V3
V4
Vss
V0
V1
V2
SEGx off
V3
V4
Vss
V0
V1
V2
SEGx on
V3
V4
Vss
1 frame
V1.7a
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ST7036
1/8 Duty(ST7066U normal mode); Assume the oscillation frequency is 540KHZ, 1 clock cycle time =
1.85us, 1/8 duty; 1/4 bias,1 frame = 1.85us x 400 x 8 = 5.92ms=168.9Hz(SHLC and SHLS connect to
High)
400 clocks
1
2
3
4
8
1
2
3
4
8
1
2
3
4
8
V0
V1
COM1
V2
V3
V4
Vss
V0
V1
COM2
V2
V3
V4
Vss
V0
V1
COM8
V2
V3
V4
Vss
V0
V1
SEGx off
V2
V3
V4
Vss
V0
V1
SEGx on
V2
V3
V4
Vss
1 frame
V1.7a
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ST7036
1/9 Duty(Extension mode); Assume the oscillation frequency is 540KHZ, 1 clock cycle time =
1.85us, 1/9 duty; 1/4 bias,1 frame = 1.85us x 400 x 9 = 6.66ms=150Hz(SHLC and SHLS connect to
High)
400 clocks
1
2
3
4
9
1
2
3
4
9
1
2
3
4
9
V0
V1
COM1
V2
V3
V4
Vss
V0
V1
COM2
V2
V3
V4
Vss
V0
V1
COM9
V2
V3
V4
Vss
V0
V1
SEGx off
V2
V3
V4
Vss
V0
V1
SEGx on
V2
V3
V4
Vss
1 frame
V1.7a
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ST7036
1/25 Duty( Extension mode and 3-line ); Assume the oscillation frequency is 540KHZ, 1 clock cycle
time = 1.85us, 1/25 duty; 1/4 bias,1 frame = 1.85us x 160 x 25 = 7.40ms=135.1Hz(SHLC and SHLS
connect to High)
160 clocks
1
2
3
4
25
1
2
3
4
25
1
2
3
4
25
V0
V1
COM1
V2
V3
V4
Vss
V0
V1
COM2
V2
V3
V4
Vss
V0
V1
COM25
V2
V3
V4
Vss
V0
V1
SEGx off
V2
V3
V4
Vss
V0
V1
SEGx on
V2
V3
V4
Vss
1 frame
V1.7a
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2007/10/17
ST7036
I/O Pad Configuration
V1.7a
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ST7036
LCD and ST7036 Connection
SHLC/SHLS ITO option pin can select at different direction for LCD panel
Com normal direction/Seg normal direction
3 line x 16 characters, SHLC=1 SHLS=1
Com normal direction/Seg reverse direction
3 line x 16 characters, SHLC=1, SHLS=0
Com reverse direction/Seg normal direction
3 line x 16 characters, SHLC=0, SHLS=1
Com reverse direction/Seg reverse direction
3 line x 16 characters, SHLC=0, SHLS=0
V1.7a
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ST7036
Application Circuit ( Normal mode )
Use internal resistor(9.6K ohm) and contrast adjust with external VR.
Booster always off.
Has 240 character of CGROM.
Internal oscillator.
Dot Matrix LCD Panel
VDD
Vext
VDD
VOUT
VIN
Com 1-24
Seg 1-80
CAP1N
CAP1P
V0
V1
V2
V3
RS,R/W,E,CSB,DB0-DB7,XRESET
V4
ST7036
CLS
SHLC
SHLS
N3
EXT
OPF1
OPF2
OPR1
OPR2
To MPU
V1.7a
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ST7036
Application Circuit(Extension mode)
Use internal follower circuit.
Booster has 2 times pump.
Has 240 character of CGROM.
Internal oscillator.
D ot M atrix LC D P anel
V ext
VDD
VOUT
V IN
C om 1-24
S eg 1-80
C A P 1N
C A P 1P
V0
V1
V2
V3
R S ,R /W ,E ,C S B ,D B 0-D B 7,X R E S ET
V4
S T7036
C LS
S H LC
S H LS
N3
EXT
OPF1
OPF2
OPR1
OPR2
To M P U
V1.7a
When the heavy load is applied, the dotted line part could be added.
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ST7036
Application Circuit ( for glass layout )
V1.7a
ST7036 over Glass,6800 serial 8bit interface, with booster and follower circuit on
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ST7036
V1.7a
ST7036 over Glass,6800 serial 4bit interface, with booster and follower circuit on
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ST7036
V1.7a
ST7036 over Glass, serial interface, with booster and follower circuit on
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2007/10/17
ST7036
2
ST7036 over Glass, I C interface, with booster and follower circuit on
In I2C application, note that the impedence of SDAs and GNDs should be keep in the POWER PIN LEVEL.
V1.7a
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