ST Sitronix ST7070 Dot Matrix LCD Controller/Driver Features 5 x 8 dot matrix possible Low power operation support: -- 2.7 to 5.5V Wide range of LCD driver power -- 3.0 to 7.0V Support high speed serial interface Correspond to high speed MPU bus interface -- 2 MHz (when VCC = 5V) 80 x 9-bit display RAM (80 characters max.) 19840-bit character generator ROM for a total of 496 character fonts(5 x 8 dot) 64 x 8-bit character generator RAM -- 8 character fonts (5 x 8 dot) 16-common x 80-segment liquid crystal display driver Programmable duty cycles -- 1/8 for one line of 5 x 8 dots with cursor -- 1/16 for two lines of 5 x 8 dots & cursor Wide range of instruction functions: Display clear, cursor home, display on/off, cursor on/off, cursor shift, display shift Automatic reset circuit that initializes the controller/driver after power on Internal oscillator with external resistors Low power consumption Bare Chip available (ST7070-XX-B) Description The ST7070 dot-matrix liquid crystal display controller and driver LSI displays alphanumeric, Japanese kana characters, and symbols. It can be configured to drive a dot-matrix liquid crystal display under the control of a 4- or 8-bit microprocessor. With high speed serial interface(3-line SPI , 4-line SPI), the external MCU can control ST7070 directly. Since all the functions such as display RAM, character generator, and liquid crystal driver, required for driving a dot-matrix liquid crystal display are internally provided on one chip, a minimal system can be interfaced with this controller/driver. to easily replace it with an ST7070. The ST7070 character generator ROM is extended to generate 496 5x8 dot character fonts for a total of 496 different character fonts. The low power supply (2.7V to 5.5V) of the ST7070 is suitable for any portable battery-driven product requiring low power dissipation. The ST7070 LCD driver consists of 16 common signal drivers and 80 segment signal drivers which can extend display size by cascading segment driver ST7921. The maximum display size can be either 80 characters in 1-line display or 40 characters in 2-line display. A single ST7070 can display up to one 16-character line or two 16-character lines. The ST7070 has function partial compatibility with the HD44780, KS0066 and SED1278 that allows the user V1.4 Product Name Support Character ST7070-0B Standard code 1/51 2009/04/29 ST7070 ST7070 Serial Specification Revision History Version Date Description 1.0 2004/4/14 Add product name 1.1 2005/1/26 Add serial interface timing characteristic and change serial interface symbols 1.2 2006/5/8 Update Initial Code of serial interface 1.2a 2006/8/31 Update the example figure of Set Display Data Length. 1.3 2008/6/16 1.4 V1.4 Redraw timing figure: 6800 & serial interface. Rename timing item to avoid confuse: 6800: TC=TCYC, TDSW=TDS, TH (Write)=TDH, TDDR=TOD, TH (Read)=TOH Update AC Characteristics: 6800 (2.7V): TCYC (Write), TPW (Write), TDS, TOD 6800 (5V): TPW (Write/Read), TDS, TOD Serial (2.7V): TSCYC, TSHW/TSLW, TSAS, TSDH, TCSS, TCSH Serial (5V): TSCYC, TSHW/TSLW, TSAS, TSDH, TCSH Remove Reversion History before version 1.0. 2009/04/29 Modified RS PIN Description for Serial Interface. Page 7 2/51 2009/04/29 ST7070 Block Diagram OSC1 OSC2 XRESET Reset circuit Timing generator CPG Instruction register(IR) PSB D Instruction decoder RS RW E CL1 CL2 M Display data RAM (DDRAM) 80x9 bits 16-bit shift register Common signal driver 80-bit latch circuit Segment signal driver MPU interface Address counter 80-bit shift register SEG1 to SEG80 Data register (DR) DB4 to DB7 DB0 to DB3 COM1 to COM16 Input/ output buffer LCD drive voltage selector Busy flag Character generator RAM (CGRAM) 64 bytes Character generator ROM (CGROM) 19840 bits Cursor and blink controller GND Parallel/serial converter and attribute circuit Vcc V0 V1.4 V1 3/51 V2 V3 V4 2009/04/29 ST7070 Pad Arrangement Mark Substrate must connect to “Vss”. V1.4 4/51 2009/04/29 ST7070 Pad Configuration Pad No. V1.4 Function X Y Pad No. Function X Y 001 RS -2585 660 033 SEG[52] -472 -790 002 DB[7] -2585 540 034 SEG[53] -367 -790 003 XRESET -2585 430 035 SEG[54] -262 -790 004 DB[6] -2585 320 036 SEG[55] -157 -790 005 DB[5] -2585 210 037 SEG[56] -52 -790 006 DB[4] -2585 105 038 SEG[57] 52 -790 007 DB[3] -2585 0 039 SEG[58] 157 -790 008 DB[2] -2585 -105 040 SEG[59] 262 -790 009 DB[1] -2585 -210 041 SEG[60] 367 -790 010 DB[0] -2585 -320 042 SEG[61] 472 -790 011 PSB -2585 -430 043 SEG[62] 577 -790 012 RW -2585 -540 044 SEG[63] 682 -790 013 E -2585 -660 045 SEG[64] 787 -790 014 COM[9] -2585 -790 046 SEG[65] 892 -790 015 COM[10] -2445 -790 047 SEG[66] 997 -790 016 COM[11] -2315 -790 048 SEG[67] 1102 -790 017 COM[12] -2195 -790 049 SEG[68] 1207 -790 018 COM[13] -2085 -790 050 SEG[69] 1315 -790 019 COM[14] -1975 -790 051 SEG[70] 1425 -790 020 COM[15] -1865 -790 052 SEG[71] 1535 -790 021 COM[16] -1755 -790 053 SEG[72] 1645 -790 022 SEG[41] -1645 -790 054 SEG[73] 1755 -790 023 SEG[42] -1535 -790 055 SEG[74] 1865 -790 024 SEG[43] -1425 -790 056 SEG[75] 1975 -790 025 SEG[44] -1315 -790 057 SEG[76] 2085 -790 026 SEG[45] -1208 -790 058 SEG[77] 2195 -790 027 SEG[46] -1102 -790 059 SEG[78] 2315 -790 028 SEG[47] -997 -790 060 SEG[79] 2445 -790 029 SEG[48] -892 -790 061 SEG[80] 2585 -790 030 SEG[49] -787 -790 062 D 2585 -660 031 SEG[50] -682 -790 063 M 2585 -540 032 SEG[51] -577 -790 064 CL2 2585 -430 5/51 2009/04/29 ST7070 Pad No. V1.4 Function X Y Pad No. Function X Y 065 CL1 2585 -320 098 SEG[17] 52 790 066 OSC2 2585 -210 099 SEG[16] -52 790 067 OSC1 2585 -105 100 SEG[15] -157 790 068 VSS 2585 0 101 SEG[14] -262 790 069 V4 2585 105 102 SEG[13] -367 790 070 V3 2585 210 103 SEG[12] -472 790 071 V2 2585 320 104 SEG[11] -577 790 072 V1 2585 430 105 SEG[10] -682 790 073 V0 2585 540 106 SEG[9] -787 790 074 VDD 2585 660 107 SEG[8] -892 790 075 SEG[40] 2585 790 108 SEG[7] -997 790 076 SEG[39] 2445 790 109 SEG[6] -1102 790 077 SEG[38] 2315 790 110 SEG[5] -1208 790 078 SEG[37] 2195 790 111 SEG[4] -1315 790 079 SEG[36] 2085 790 112 SEG[3] -1425 790 080 SEG[35] 1975 790 113 SEG[2] -1535 790 081 SEG[34] 1865 790 114 SEG[1] -1645 790 082 SEG[33] 1755 790 115 COM[1] -1755 790 083 SEG[32] 1645 790 116 COM[2] -1865 790 084 SEG[31] 1535 790 117 COM[3] -1975 790 085 SEG[30] 1425 790 118 COM[4] -2085 790 086 SEG[29] 1315 790 119 COM[5] -2195 790 087 SEG[28] 1207 790 120 COM[6] -2315 790 088 SEG[27] 1102 790 121 COM[7] -2445 790 089 SEG[26] 997 790 122 COM[8] -2585 790 090 SEG[25] 892 790 091 SEG[24] 787 790 092 SEG[23] 682 790 093 SEG[22] 577 790 094 SEG[21] 472 790 095 SEG[20] 367 790 096 SEG[19] 262 790 097 SEG[18] 157 790 6/51 2009/04/29 ST7070 Pin Function Name Number I/O Interfaced with RS 1 I MPU R/W 1 I MPU E 1 I MPU XRESET PSB 1 1 I I MPU MPU DB4 to DB7 4 I/O MPU DB0 to DB3 4 I/O MPU CL1 1 O Extension driver CL2 1 O Extension driver M 1 O Extension driver D 1 O Extension driver COM1 to COM16 16 O LCD SEG1 to SEG80 80 O LCD V0 to V4 5 - Power supply VCC , GND 2 - Power supply OSC1, OSC2 2 Oscillation resistor clock Function Select registers. 0: Write Instruction or “Read Busy Flag and Address” 1: Data write/read It is not used in 3-Line SPI interface, fix RS at low, not floating. Select read or write. 0: Write 1: Read When serial interface select ,R/W pull low, not floating. Starts data read/write. When serial interface select ,E pull height , not floating. Hardware reset pin, Low active Parallel /Serial selection. PSB: ”1” Parallel , “0” Serial. Four high order bi-directional tristate data bus pins. Used for data transfer and receive between the MPU and the ST7070. DB7 can be used as a busy flag. Serial: DB7:data input pin for serial mode(SI) DB6:serial clock input for serial mode(SCL) DB5:chip select pin for serial mode(/CS) When serial interface select ,D4 pull height , not floating. 4bits mode : These pins are used during 4-bit operation. Four low order bi-directional tristate data bus pins. Used for data transfer and receive between the MPU and the ST7070. These pins are not used during 4-bit operation and serial interface , must pull height , not floating. Clock to latch serial data D sent to the Extension driver Clock to shift serial data D Switch signal for converting the liquid crystal drive waveform to AC Character pattern data corresponding to each segment signal Common signals that are not used are changed to non-selection waveform. COM9 to COM16 are non-selection waveforms at 1/8 duty factor and COM12 to COM16 are non-selection waveforms at 1/11 duty factor. Segment signals Power supply for LCD drive V0 － Vss = 10 V (Max) VCC : 2.7V to 5.5V, GND: 0V When crystal oscillation is performed, a resistor must be connected externally. When the pin input is an external clock, it must be input to OSC1. Note: 1. V0 >= V1 >= V2 >= V3 >= V4 >= Vss must be maintained 2. Two clock options: R=91KΩ(Vcc=5V) R=75KΩ(Vcc=3V) OSC1 OSC2 R V1.4 OSC1 OSC2 Clock input 7/51 2009/04/29 ST7070 Function Description System Interface This chip has all two kinds of interface type with MPU : 4-bit bus and 8-bit bus. 4-bit bus or 8-bit bus is selected by DL bit in the instruction register. During read or write operation, two 8-bit registers are used. One is data register (DR), the other is instruction register(IR). The data register(DR) is used as temporary data storage place for being written into or read from DDRAM/CGRAM, target RAM is selected by RAM address setting instruction. Each internal operation, reading from or writing into RAM, is done automatically. So to speak, after MPU reads DR data, the data in the next DDRAM/CGRAM address is transferred into DR automatically. Also after MPU writes data to DR, the data in DR is transferred into DDRAM/CGRAM automatically. The Instruction register(IR) is used only to store instruction code transferred from MPU. MPU cannot use it to read instruction data. To select register, use RS input pin in 4-bit/8-bit bus mode. RS R/W L L H H L H L H Operation Instruction Write operation (MPU writes Instruction code into IR) Read Busy Flag(DB7) and address counter (DB6 ~ DB0) Data Write operation (MPU writes data into DR) Data Read operation (MPU reads data from DR) Table 1. Various kinds of operations according to RS and R/W bits. Busy Flag (BF) When BF = "High”, it indicates that the internal operation is being processed. So during this time the next instruction cannot be accepted. BF can be read, when RS = Low and R/W = High (Read Instruction Operation), through DB7 port. Before executing the next instruction, be sure that BF is not High. Address Counter (AC) Address Counter(AC) stores DDRAM/CGRAM address, transferred from IR. After writing into (reading from) DDRAM/CGRAM, AC is automatically increased (decreased) by 1. When RS = "Low" and R/W = "High", AC can be read through DB6 ~ DB0 ports. V1.4 8/51 2009/04/29 ST7070 Display Data RAM (DDRAM) Display data RAM (DDRAM) stores display data represented in 9-bit character codes. Its extended capacity is 80 x 9 bits, or 80 characters. The area in display data RAM (DDRAM) that is not used for display can be used as general data RAM. See Figure 1 for the relationships between DDRAM addresses and positions on the liquid crystal display. The DDRAM address (ADD ) is set in the address counter (AC) as hexadecimal. 1-line display (N = 0) (Figure 2) When there are fewer than 80 display characters, the display begins at the head position. For example, if using only the ST7070, 8 characters are displayed. See Figure 3. When the display shift operation is performed, the DDRAM address shifts. See Figure 3. High Order bits Low Order bits Example: DDRAM Address 4F AC AC6 AC5 AC4 AC3 AC2 AC1 AC0 1 0 0 1 1 1 1 Figure 1 DDRAM Address Display Position 1 (Digit) 00 DDRAM Address 2 3 4 5 6 01 02 03 04 05 78 ……………….. 79 80 4D 4E 4F Figure 2 1-Line Display Display Position 1 2 3 4 5 6 7 8 00 01 02 03 04 05 06 07 For Shift Left 01 02 03 04 05 06 07 08 For Shift Right 4F 00 01 02 03 04 05 06 DDRAM Address Figure 3 1-Line by 8-Character Display Example V1.4 9/51 2009/04/29 ST7070 2-line display (N = 1) (Figure 4) Display Position 1 00 DDRAM Address 40 (hexadecimal) 2 3 4 5 6 01 02 03 04 05 41 42 43 44 45 38 39 40 ……………….. 25 26 27 ……………….. 65 66 67 Figure 4 2-Line Display Case 1: When the number of display characters is less than 40 2 lines, the two lines are displayed from the head. Note that the first line end address and the second line start address are not consecutive. For example, when just the ST7070 is used, 16 characters 2 lines are displayed. See Figure 5. When display shift operation is performed, the DDRAM address shifts. See Figure 5. Display 1 Position 00 DDRAM Address 40 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F 41 42 43 44 45 46 47 48 49 4A 4B 4C 4D 4E 4F For Shift Left 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F 10 41 42 43 44 45 46 47 48 49 4A 4B 4C 4D 4E 4F 50 For Shift Right 27 00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 67 40 41 42 43 44 45 46 47 48 49 4A 4B 4C 4D 4E Figure 5 2-Line by 16-Character Display Example Case 2: For a 16-character x 2-line display, See Figure 5. When display shift operation is performed, the DDRAM address shifts. See Figure 5. V1.4 10/51 2009/04/29 ST7070 Character Generator ROM (CGROM) The character generator ROM generates 5 x 8 dot character patterns from 9-bit character codes. It can generate 496 5 x 8 dot character patterns. User-defined character patterns are also available by mask-programmed ROM. Character Generator RAM (CGRAM) In the character generator RAM, the user can rewrite character patterns by program. For 5 x 8 dots, eight character patterns can be written. Write into DDRAM the character codes at the addresses shown as the left column of Table 4 to show the character patterns stored in CGRAM. See Table 5 for the relationship between CGRAM addresses and data and display patterns. Areas that are not used for display can be used as general data RAM. Timing Generation Circuit The timing generation circuit generates timing signals for the operation of internal circuits such as DDRAM, CGROM and CGRAM. RAM read timing for display and internal operation timing by MPU access are generated separately to avoid interfering with each other. Therefore, when writing data to DDRAM, for example, there will be no undesirable interference, such as flickering, in areas other than the display area. LCD Driver Circuit LCD Driver circuit has 16 common and 80 segment signals for LCD driving. Data from CGRAM/CGROM is transferred to 80 bit segment latch serially, and then it is stored to 80 bit shift latch. When each common is selected by 16 bit common register, segment data also output through segment driver from 80 bit segment latch. In case of 1-line display mode, COM1 ~ COM8 have 1/8 duty, and in 2-line mode, COM1 ~ COM16 have 1/16 duty ratio. Cursor Control Circuit It can generate the cursor in the cursor control circuit. The cursor or the blink appears in the digit at the display data RAM address set in the address counter. V1.4 11/51 2009/04/29 ST7070 Table 4 Correspondence between Character Codes and Character Patterns (Page 1) (b8=0) V1.4 12/51 2009/04/29 ST7070 Table 4 Correspondence between Character Codes and Character Patterns (Page 2) (b8=1) V1.4 13/51 2009/04/29 ST7070 Character Code (DDRAM Data) b8 b7 b6 b5 b4 b3 b2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 b1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CGRAM Address b0 b5 b4 b3 b2 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 0 1 0 1 1 0 1 0 1 0 1 0 0 0 1 1 1 1 1 1 1 1 1 b1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 Character Patterns (CGRAM Data) b0 b7 b6 b5 b4 0 1 1 0 0 0 1 0 - - 0 0 1 0 0 0 1 0 0 1 1 1 0 1 1 1 - - 0 1 1 1 0 1 1 0 b3 1 0 0 0 0 0 0 0 1 0 0 1 0 0 0 0 b2 1 1 1 1 1 1 1 0 1 0 0 1 1 0 0 0 b1 1 0 0 0 0 0 0 0 1 0 0 1 0 1 0 0 b0 1 0 0 0 0 0 0 0 0 1 1 0 0 0 1 0 Table 5 Relationship between CGRAM Addresses, Character Codes (DDRAM) and Character patterns (CGRAM Data) Notes: 1. Character code bits 0 to 2 correspond to CGRAM address bits 3 to 5 (3 bits: 8 types). 2. CGRAM address bits 0 to 2 designate the character pattern line position. The 8th line is the cursor position and its display is formed by a logical OR with the cursor. Maintain the 8th line data, corresponding to the cursor display position, at 0 as the cursor display. If the 8th line data is 1, 1 bits will light up the 8th line regardless of the cursor presence. 3. Character pattern row positions correspond to CGRAM data bits 0 to 4 (bit 4 being at the left). 4. As shown Table 5, CGRAM character patterns are selected when character code bits 4 to 7 are all 0. However, since character code bit 3 has no effect, the R display example above can be selected by either character code 00H or 08H. 5. 1 for CGRAM data corresponds to display selection and 0 to non-selection. “-“: Indicates no effect. V1.4 14/51 2009/04/29 ST7070 Instructions There are four categories of instructions that: Designate ST7070 functions, such as display format, data length, etc. Set internal RAM addresses Perform data transfer with internal RAM Others Instruction Table: Instruction Code Instruction RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 Description Description Time (270KHz) EXT = 0 or 1 Clear Display 0 0 0 0 0 0 0 0 0 1 Return Home 0 0 0 0 0 0 0 0 1 x Display ON/OFF 0 0 0 0 0 0 1 D C P Cursor or Display Shift 0 0 0 0 0 1 S/C R/L x Function Set 0 0 0 0 1 DL N EXT x Read Busy flag and address 0 1 BF Write data to RAM 1 0 D7 Read data from RAM 1 1 D7 Write "20H" to DDRAM. and set DDRAM address to "00H" from AC Set DDRAM address to "00H" from AC and return cursor to its original position if shifted. The contents of DDRAM are not changed. D=1:entire display on C=1:cursor on P: font table page selection 1.52 ms 0 us 37 us x Set cursor moving and display shift control bit, and the direction, without changing DDRAM data. 37 us x DL: interface data is 8/4 bits N: number of line is 2/1 37 us Whether during internal operation or not can be AC6 AC5 AC4 AC3 AC2 AC1 AC0 known by reading BF. The contents of address counter can also be read. Write data into internal D6 D5 D4 D3 D2 D1 D0 RAM (DDRAM/CGRAM) Read data from internal D6 D5 D4 D3 D2 D1 D0 RAM (DDRAM/CGRAM) 0 us 37 us 37 us EXT = 0 Sets cursor move direction and specifies display shift. These operations are performed during data write and read. 37 us AC5 AC4 AC3 AC2 AC1 AC0 Set CGRAM address in address counter 37 us AC6 AC5 AC4 AC3 AC2 AC1 AC0 Set DDRAM address in address counter 37 us Entry Mode Set 0 0 0 0 Set CGRAM address 0 0 0 1 Set DDRAM address 0 0 1 V1.4 0 0 0 1 15/51 I/D S 2009/04/29 ST7070 EXT = 1 Bias resistor select 0 0 0 0 0 0 0 1 COM、SEG direction select 0 0 0 1 0 0 C1 C2 Set display data length 0 0 1 L6 L5 L4 L3 L2 Used internal resister only provide 1/5 bias mode . Rb[1:0]=00External Rb1 Rb0 Resister Rb[1:0]=01~11Internal Resistor C1：com1~8com8~1 C2：com9~16com16~9 S1 S2 S1：seg1~40seg40~1 S2：seg41~80seg80~41 L1 L0 To specify the number of data bytes(3SPI mode) 37 us 37 us 37 us Note: Be sure the ST7070 is not in the busy state (BF = 0) before sending an instruction from the MPU to the ST7070. If an instruction is sent without checking the busy flag, the time between the first instruction and next instruction will take much longer than the instruction time itself. Refer to Instruction Table for the list of each instruction execution time. V1.4 16/51 2009/04/29 ST7070 Instruction Description EXT=0 or 1 Clear Display RS Code 0 RW DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 0 0 0 0 0 0 0 1 Clear all the display data by writing "20H" (space code) to all DDRAM address, and set DDRAM address to "00H" into AC (address counter). Return cursor to the original status, namely, bring the cursor to the left edge on first line of the display. Make entry mode increment (I/D = "1"). Return Home RS Code 0 RW DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 0 0 0 0 0 0 1 x Return Home is cursor return home instruction. Set DDRAM address to "00H" into the address counter. Return cursor to its original site and return display to its original status, if shifted. Contents of DDRAM does not change. Display ON/OFF RS Code 0 RW DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 0 0 0 0 1 D C P Control display/cursor/blink ON/OFF 1 bit register. D : Display ON/OFF control bit When D = "High", entire display is turned on. When D = "Low", display is turned off, but display data is remained in DDRAM. C : Cursor ON/OFF control bit When C = "High", cursor is turned on. When C = "Low", cursor is disappeared in current display, but I/D register remains its data. Alternating display Every 32 frames Cursor P : Font table selection bit When P = "Low", it select page 1 of font table.(set DDRAM data bit-8=0) When P = "High", it select page 2 of font table(set DDRAM data bit-8=1) V1.4 17/51 2009/04/29 ST7070 Cursor or Display Shift RS Code 0 RW DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 0 0 0 1 S/C R/L x x Without writing or reading of display data, shift right/left cursor position or display. This instruction is used to correct or search display data. During 2-line mode display, cursor moves to the 2nd line after 40th digit of 1st line. Note that display shift is performed simultaneously in all the line. When displayed data is shifted repeatedly, each line shifted individually. When display shift is performed, the contents of address counter are not changed. S/C R/L Description L L Shift cursor to the left AC=AC-1 L H Shift cursor to the right AC=AC+1 H L Shift display to the left. Cursor follows the display shift AC=AC H H Shift display to the right. Cursor follows the display shift AC=AC Function Set RS Code AC Value 0 RW DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 0 0 1 DL N EXT x x DL : Interface data length control bit When DL = "High", it means 8-bit bus mode with MPU. When DL = "Low", it means 4-bit bus mode with MPU. So to speak, DL is a signal to select 8-bit or 4-bit bus mode. When 4-bit bus mode, it needs to transfer 4-bit data by two times. N : Display line number control bit When N = "Low", it means 1-line display mode. When N = "High", 2-line display mode is set. EXT : Select basic or extended instruction set When EXT=”L” the commands ‘Entry Mode Set’ , ‘Set CGRAM address’ and ‘Set DDRAM address’ can be performed , when EXT=”H” the commands ‘Bias resistor select’ , ‘COM、SEG direction select’ and ‘Set display data length’ can be performed. Other command can be executed in both cases. When EXT=”L” : disable extension instruction When EXT=”H” : enable extension instruction V1.4 18/51 2009/04/29 ST7070 Read Busy Flag and Address Code RS RW DB7 0 1 BF DB6 DB5 DB4 DB3 DB2 DB1 DB0 AC6 AC5 AC4 AC3 AC2 AC1 AC0 When BF = “High”, indicates that the internal operation is being processed.So during this time the next instruction cannot be accepted. The address Counter (AC) stores DDRAM/CGRAM addresses, transferred from IR. After writing into (reading from) DDRAM/CGRAM, AC is automatically increased (decreased) by 1. Write Data to CGRAM or DDRAM RS Code 1 RW DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 D7 D6 D5 D4 D3 D2 D1 D0 Write binary 8-bit data to DDRAM/CGRAM. The selection of RAM from DDRAM, CGRAM, is set by the previous address set instruction : DDRAM address set, CGRAM address set. RAM set instruction can also determine the AC direction to RAM. DDRAM data bit-8 is come from “P”(Display on/off instruction) register setting After write operation, the address is automatically increased/decreased by 1, according to the entry mode. Read Data from CGRAM or DDRAM RS Code 1 RW DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 1 D7 D6 D5 D4 D3 D2 D1 D0 Read binary 8-bit data from DDRAM/CGRAM. The selection of RAM is set by the previous address set instruction. If address set instruction of RAM is not performed before this instruction, the data that read first is invalid, because the direction of AC is not determined. If you read RAM data several times without RAM address set instruction before read operation, you can get correct RAM data from the second, but the first data would be incorrect, because there is no time margin to transfer RAM data. In case of DDRAM read operation, cursor shift instruction plays the same role as DDRAM address set instruction : it also transfer RAM data to output data register. After read operation address counter is automatically increased/decreased by 1 according to the entry mode. After CGRAM read operation, display shift may not be executed correctly. * In case of RAM write operation, after this AC is increased/decreased by 1 like read operation. In this time, AC indicates the next address position, but you can read only the previous data by read instruction. V1.4 19/51 2009/04/29 ST7070 EXT=0 Entry Mode Set RS Code 0 RW DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 0 0 0 0 0 1 I/D S Set the moving direction of cursor and display. I/D : Increment / decrement of DDRAM address (cursor or blink) When I/D = "High", cursor moves to right and DDRAM address is increased by 1. When I/D = "Low", cursor moves to left and DDRAM address is decreased by 1. * CGRAM operates the same as DDRAM, when read from or write to CGRAM. S: Shift of entire display When DDRAM read (CGRAM read/write) operation or S = "Low", shift of entire display is not performed. If S = "High" and DDRAM write operation, shift of entire display is performed according to I/D value (I/D = "1" : shift left, I/D = "0" : shift right). S I/D Description H H Shift the display to the left H L Shift the display to the right Set CGRAM Address Code RS RW 0 0 DB7 0 DB6 1 DB5 DB4 DB3 DB2 DB1 DB0 AC5 AC4 AC3 AC2 AC1 AC0 Set CGRAM address to AC. This instruction makes CGRAM data available from MPU. Set DDRAM Address Code RS RW 0 0 DB7 1 DB6 DB5 DB4 DB3 DB2 DB1 DB0 AC6 AC5 AC4 AC3 AC2 AC1 AC0 Set DDRAM address to AC. This instruction makes DDRAM data available from MPU. When 1-line display mode (N = 0), DDRAM address is from "00H" to "4FH". In 2-line display mode (N = 1), DDRAM address in the 1st line is from "00H" to "27H", and DDRAM address in the 2nd line is from "40H" to "67H". V1.4 20/51 2009/04/29 ST7070 EXT=1 Bias resistor select RS RW 0 0 Code DB7 0 DB6 DB5 0 DB4 0 DB3 0 0 DB2 1 DB1 DB0 Rb1 Rb0 Set internal bias resistor value. Rb1 Rb0 L L External bias resistor select. L H Build-in resistor select (R=2.2K). H L Build-in resistor select (R=6.8K). H H Build-in resistor select (R=9.0K). Description COM、 、SEG direction select Code RS RW 0 0 DB7 0 DB6 1 DB5 0 DB4 0 DB3 DB2 DB1 DB0 C1 C2 S1 S2 The SEG and COM output in ST7070 all have bi-direction control by the register. COM OUTPUT : COM output C1 COM1 COM8 0 COM1 Common Address COM8 1 COM8 Common Address COM1 COM output C2 COM9 COM16 0 COM9 Common Address COM16 1 COM16 Common Address COM9 SEG OUTPUT : SEG output S1 SEG1 SEG40 0 SEG1 Segment Address SEG40 1 SEG40 Segment Address SEG1 SEG output S2 V1.4 SEG41 SEG80 0 SEG41 Segment Address SEG80 1 SEG80 Segment Address SEG41 21/51 2009/04/29 ST7070 Set display data length Code RS RW 0 0 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 L6 L5 L4 L3 L2 L1 L0 1 L6 L5 L4 L3 L2 L1 L0 Data length 0 0 0 0 0 0 0 1 0 0 0 0 0 0 1 2 … … … … … … …. … 1 0 0 1 1 1 0 79 1 0 0 1 1 1 1 80 Only in 3line-SPI interface will use the register to set the number of display data(Max=4F). To write data to DDRAM , send Data Direction Command in 3-pin SPI . Data is latched at the rising edge of SCLK . And the DDRAM column address pointer will be increased by one automatically. V1.4 22/51 2009/04/29 ST7070 Reset Function Initializing by Internal Reset Circuit An internal reset circuit automatically initializes the ST7070 when the power is turned on or hardware reset pin has low. The following instructions are executed during the initialization. The busy flag (BF) is kept in the busy state until the initialization ends (BF = 1). The busy state lasts for 40 ms after VCC rises to 4.5 V. 1. Display clear 2. Function set: DL = 1; 8-bit interface data N = 1; 2-line display EXT=0;disable extension instruction. 3. Display on/off control: D = 0; Display off C = 0; Cursor off P = 0; Page 1 of font table(DDRAM data b8=0) 4. Entry mode set: I/D = 1; Increment by 1 S = 0; No shift 5. Bias resistor select: Rb1=0;Rb2=0 select external bias resistor. 6. COM、SEG direction select: C1=0;C2=0;S1=0;S2=0 not reverse. Note: If the electrical characteristics conditions listed under the table Power Supply Conditions Using Internal Reset Circuit are not met, the internal reset circuit will not operate normally and will fail to initialize the ST7070. For such a case, initialization must be performed by the MPU as explain by the following figure. V1.4 23/51 2009/04/29 ST7070 Initializing by Instruction 8-bit Interface (fosc=270KHz) POWER ON Wait time >40mS After Vcc >4.5V Function set RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 0 0 0 1 1 N X X BF cannot be checked before this instruction. X Wait time >37uS Function set RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 0 0 0 1 1 N X X X BF cannot be checked before this instruction. Wait time >37uS Display ON/OFF control RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 0 0 0 0 0 1 D C P Wait time >37uS Display clear RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 0 0 0 0 0 0 0 0 1 Wait time >1.52mS Entry mode set RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 0 0 0 0 0 0 1 I/D S Initialization end V1.4 24/51 2009/04/29 ST7070 Initial Program Code Example For 8051 MPU(8 Bit Interface): ;--------------------------------------------------------------------------------INITIAL_START: CALL DELAY40mS MOV CALL CALL A,#38H ;FUNCTION SET WRINS_NOCHK ;8 bit,N=1,5*7dot DELAY37uS MOV CALL CALL A,#38H ;FUNCTION SET WRINS_NOCHK ;8 bit,N=1,5*7dot DELAY37uS MOV CALL CALL A,#0FH WRINS_CHK DELAY37uS ;DISPLAY ON MOV CALL CALL A,#01H WRINS_CHK DELAY1.52mS ;CLEAR DISPLAY MOV A,#06H ;ENTRY MODE SET CALL WRINS_CHK ;CURSOR MOVES TO RIGHT CALL DELAY37uS ;--------------------------------------------------------------------------------MAIN_START: XXXX XXXX XXXX XXXX . . . . ;--------------------------------------------------------------------------------WRINS_CHK: CALL CHK_BUSY WRINS_NOCHK: CLR RS ;EX:Port 3.0 CLR RW ;EX:Port 3.1 SETB E ;EX:Port 3.2 MOV P1,A ;EX:Port 1=Data Bus CLR E MOV P1,#FFH ;For Check Busy Flag RET ;--------------------------------------------------------------------------------CHK_BUSY: ;Check Busy Flag CLR RS SETB RW SETB E JB P1.7,$ CLR E RET V1.4 25/51 2009/04/29 ST7070 V1.4 4-bit Interface (fosc=270KHz) 26/51 2009/04/29 ST7070 Initial Program Code Example For 8051 MPU(4 Bit Interface): ;------------------------------------------------------------------INITIAL_START: CALL DELAY40mS MOV CALL CALL A,#38H WRINS_ONCE DELAY2mS ;FUNCTION SET ;8 bit,N=1,5*7dot MOV CALL CALL A,#38H WRINS_ONCE DELAY37uS ;FUNCTION SET ;8 bit,N=1,5*7dot MOV CALL CALL A,#38H WRINS_ONCE DELAY37uS ;FUNCTION SET ;8 bit,N=1,5*7dot MOV CALL CALL A,#28H ;FUNCTION SET WRINS_NOCHK ;4 bit,N=1,5*7dot DELAY37uS MOV CALL CALL A,#28H ;FUNCTION SET WRINS_NOCHK ;4 bit,N=1,5*7dot DELAY37uS MOV CALL CALL A,#0FH WRINS_CHK DELAY37uS ;DISPLAY ON MOV CALL CALL A,#01H WRINS_CHK DELAY1.52mS ;CLEAR DISPLAY MOV A,#06H ;ENTRY MODE SET CALL WRINS_CHK CALL DELAY37uS ;------------------------------------------------------------------MAIN_START: XXXX XXXX XXXX XXXX . . . . . . . . . V1.4 27/51 ;------------------------------------------------------------------WRINS_CHK: CALL CHK_BUSY WRINS_NOCHK: PUSH A ANL A,#F0H CLR RS ;EX:Port 3.0 CLR RW ;EX:Port 3.1 SETB E ;EX:Port 3.2 MOV P1,A ;EX:Port1=Data Bus CLR E POP A SWAP A WRINS_ONCE: ANL A,#F0H CLR RS CLR RW SETB E MOV P1,A CLR E MOV P1,#FFH ;For Check Bus Flag RET ;------------------------------------------------------------------CHK_BUSY: ;Check Busy Flag PUSH A MOV P1,#FFH $1 CLR RS SETB RW SETB E MOV A,P1 CLR E MOV P1,#FFH CLR RS SETB RW SETB E NOP CLR E JB A.7,$1 POP A RET 2009/04/29 ST7070 Serial Interface (fosc=270KHz) POWER ON Wait time >40mS After Vcc >4.5V Function set RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 0 0 0 1 1 N X X BF cannot be checked before this instruction. X Wait time >37uS Display ON/OFF control RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 0 0 0 0 0 1 D C P Wait time >37uS Display clear RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 0 0 0 0 0 0 0 0 1 Wait time >1.52mS Entry mode set RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 0 0 0 0 0 0 1 I/D S Initialization end V1.4 28/51 2009/04/29 ST7070 Interfacing to the MPU The ST7070 can send data in either two 4-bit operations or one 8-bit operation or serial operation, thus allowing interfacing with 4- or 8-bit or serial MPU. For 4-bit interface data, only four bus lines (DB4 to DB7) are used for transfer. Bus lines DB0 to DB3 are disabled. The data transfer between the ST7070 and the MPU is completed after the 4-bit data has been transferred twice. As for the order of data transfer, the four high order bits (for 8-bit operation, DB4 to DB7) are transferred before the four low order bits (for 8-bit operation, DB0 to DB3). The busy flag must be checked (one instruction) after the 4-bit data has been transferred twice. Two more 4-bit operations then transfer the busy flag and address counter data. Example of busy flag check timing sequence RS R/W E Internal operation Functioning DB7 IR7 IR3 Instruction write AC 3 Busy flag check Not AC Busy 3 Busy flag check IR3 Instruction write Intel 8051 interface COM1 to COM16 P1.0 to P1.3 4 P3.0 P3.1 P3.2 16 DB4 to DB7 RS R/W E Intel 8051 Serial V1.4 IR7 SEG1 to SEG80 80 ST7070 29/51 2009/04/29 ST7070 For 8-bit interface data, all eight bus lines (DB0 to DB7) are used. Example of busy flag check timing sequence RS R/W E Internal operation Functioning DB7 Not Busy Data Busy Busy Instruction write Busy flag check Busy flag check Busy flag check Instruction write Intel 8051 interface COM1 to COM16 P1.0 to P1.7 8 16 DB0 to DB7 P3.0 P3.1 P3.2 RS R/W E Intel 8051 Serial V1.4 Data SEG1 to SEG80 80 ST7070 30/51 2009/04/29 ST7070 For serial interface data, bus lines (DB5 to DB7) are used. 4-Pin SPI Example of timing sequence CSB SI D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 SCL 1 2 3 4 5 6 7 8 9 10 11 12 13 14 RS Intel 8051 interface(Serial) COM1 to COM16 P1.5to P1.7 3 SI , SCL , /CS P3.0 RS SEG1 to SEG80 Intel 8051 Serial V1.4 16 80 ST7070 31/51 2009/04/29 ST7070 For serial interface data, bus lines (DB5 to DB7) are used. 3-Pin SPI Example of timing sequence /CB SI DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 DB7 display data length DB6 DB7 DB6 DB5 DB4 DB3 SCL set command number of data Intel 8051 interface(Serial) COM1 to COM16 P1.5to P1.7 3 Intel 8051 Serial 16 SI , SCL , /CS SEG1 to SEG80 V1.4 set data 80 ST7070 32/51 2009/04/29 ST7070 Supply Voltage for LCD Drive There are different voltages that supply to ST7070’s pin (V0 – V4) to obtain LCD drive waveform. We could use the register command (Ra1,Ra0) to set up the Internal or External Bias Resister. The relations of the bias, duty factor and supply voltages are shown as below. External Bias Resistor could set up to 1/4 bias and 1/5 bias, but Internal Bias Resistor only could set up to 1/5 bias. Duty Factor External 1/8 Resistor 1/8,1/16 Bias Supply Voltage 1/4 1/5 Bias Resistor Select Ra1=0,Ra0=0 Ra1=0,Ra0=0 V0 VLCD VLCD V1 3/4VLCD 4/5VLCD V2 1/2VLCD 3/5VLCD V3 1/2VLCD 2/5VLCD V4 1/4VLCD 1/5VLCD +5V +5V VR VR V0 V0 R R V1 V1 R R V2 V2 VLCD V3 R V3 R V4 V4 R R 1/4 bias (1/8 duty cycle) V1.4 VLCD R 1/5 bias (1/16 duty cycle) Vss 33/51 Vss 2009/04/29 ST7070 Duty Factor Internal 1/8 , 1/16 Resistor Bias Supply Voltage 1/5 1/5 1/5 Bias Resistor Select Ra1=0,Ra0=1 Ra1=1,Ra0=0 Ra1=1,Ra0=1 Internal Resistor R=2.2K R=6.8K R=9.0K V0 VLCD VLCD VLCD V1 4/5VLCD 4/5VLCD 4/5VLCD V2 3/5VLCD 3/5VLCD 3/5VLCD V3 2/5VLCD 2/5VLCD 2/5VLCD V4 1/5VLCD 1/5VLCD 1/5VLCD +5V +5V Ra1=0,Ra0=1 Ra1=1,Ra0=0 VR VR V0 V0 R R V1 V1 R R V2 V3 V4 V2 VLCD R V3 R V4 VLCD R R R R VSS VSS 1/5 bias R=2.2K (1/8,1/16 duty cycle) 1/5 bias R=6.8K (1/8,1/16 duty cycle) GND GND +5V Ra1=1,Ra0=1 VR V0 R V1 R V2 V3 V4 R VLCD R R VSS 1/5 bias R=9.0K (1/8,1/16 duty cycle) V1.4 GND 34/51 2009/04/29 ST7070 Timing Characteristics Parallel Interface Write/Read by MPU Writing data from MPU to ST7070 (Serial) CSB tCSS tCSH tSAS tSAH RS tSCYC tSLW SCL tf tr tSDS SI tSDH VIH VIL V1.4 tSHW First bit Last bit 35/51 2009/04/29 ST7070 Interface Timing with External Driver tct VOH2 CL1 VOL2 tCWH tCWH CL2 tCST tCWL tct D tDH tSU M tDM Internal Power Supply Reset 2.7V/4.5V 0.2V 0.2V trcc 0.2V tOFF 0.1mS≦trcc≦80mS tOFF≧1mS Notes: tOFF compensates for the power oscillation period caused by momentary power supply oscillations. Specified at 4.5V for 5V operation,and at 2.7V for 3V operation. For if 4.5V is not reached during 5V operation,teh internal reset circuit will not operate normally. V1.4 36/51 2009/04/29 ST7070 AC Characteristics In 6800 interface (TA = 25°C, VCC = 2.7V ) Symbol Characteristics Test Condition Min. Typ. Max. Unit Internal Clock Operation fOSC OSC Frequency R = 75KΩ 190 270 350 KHz External Clock Operation fEX Tr,Tf External Frequency - 125 270 410 KHz Duty Cycle - 45 50 55 % Rise/Fall Time - - - 0.2 µs 60 - - us Write Mode (Writing data from MPU to ST7070) Pin E (except clear display) TCYC Enable Cycle Time TPW Enable Pulse Width Pin E 30 - - ns Tr,Tf Enable Rise/Fall Time Pin E - - 25 ns TAS Address Setup Time Pins: RS,RW 0 - - ns TAH Address Hold Time Pins: RS,RW 10 - - ns TDS Data Setup Time Pins: DB0 - DB7 30 - - ns TDH Data Hold Time Pins: DB0 - DB7 10 - - ns Read Mode (Reading Data from ST7070 to MPU) TCYC Enable Cycle Time Pin E 1200 - - ns TPW Enable Pulse Width Pin E 480 - - ns Tr,Tf Enable Rise/Fall Time Pin E - - 25 ns TAS Address Setup Time Pins: RS,RW 0 - - ns TAH Address Hold Time Pins: RS,RW 10 - - ns TOD Output Delay Time Pins: DB0 - DB7 - - 420 ns TOH Output Hold Time Pins: DB0 - DB7 10 - - ns Interface Mode with LCD Driver(ST7921) V1.4 TCWH Clock Pulse with High Pins: CL1, CL2 800 - - ns TCWL Clock Pulse with Low Pins: CL1, CL2 800 - - ns TCST Clock Setup Time Pins: CL1, CL2 500 - - ns TSU Data Setup Time Pin: D 300 - - ns TDH Data Hold Time Pin: D 300 - - ns TDM M Delay Time Pin: M 0 - 2000 ns 37/51 2009/04/29 ST7070 AC Characteristics In 6800 interface (TA = 25°C, VCC = 5V) Symbol Characteristics Test Condition Min. Typ. Max. Unit Internal Clock Operation fOSC OSC Frequency R = 91KΩ 190 270 350 KHz External Clock Operation fEX Tr,Tf External Frequency - 125 270 410 KHz Duty Cycle - 45 50 55 % Rise/Fall Time - - - 0.2 µs 40 - - us Write Mode (Writing data from MPU to ST7070) Pin E (except clear display) TCYC Enable Cycle Time TPW Enable Pulse Width Pin E 20 - - ns Tr,Tf Enable Rise/Fall Time Pin E - - 25 ns TAS Address Setup Time Pins: RS,RW,E 0 - - ns TAH Address Hold Time Pins: RS,RW,E 10 - - ns TDS Data Setup Time Pins: DB0 - DB7 20 - - ns TDH Data Hold Time Pins: DB0 - DB7 10 - - ns Read Mode (Reading Data from ST7070 to MPU) TCYC Enable Cycle Time Pin E 1200 - - ns TPW Enable Pulse Width Pin E 430 - - ns Tr,Tf Enable Rise/Fall Time Pin E - - 25 ns TAS Address Setup Time Pins: RS,RW,E 0 - - ns TAH Address Hold Time Pins: RS,RW,E 10 - - ns TOD Output Delay Time Pins: DB0 - DB7 - - 390 ns TOH Output Hold Time Pins: DB0 - DB7 10 - - ns Interface Mode with LCD Driver(ST7921) V1.4 TCWH Clock Pulse with High Pins: CL1, CL2 800 - - ns TCWL Clock Pulse with Low Pins: CL1, CL2 800 - - ns TCST Clock Setup Time Pins: CL1, CL2 500 - - ns TSU Data Setup Time Pin: D 300 - - ns TDH Data Hold Time Pin: D 300 - - ns TDM M Delay Time Pin: M 0 - 2000 ns 38/51 2009/04/29 ST7070 AC Characteristics In Serial interface (TA = 25°C, VCC = 2.7V ) Symbol Characteristics Test Condition Min. Typ. Max. Unit Internal Clock Operation fOSC OSC Frequency R = 75KΩ 190 270 350 KHz External Clock Operation fEX Tr,Tf External Frequency - 125 270 410 KHz Duty Cycle - 45 50 55 % Rise/Fall Time - - - 0.2 µs Write Mode (Writing data from MPU to ST7070) TSCYC SCL Cycle Time SCL 2480 - - ns TSHW,SLW SCL Pulse Width SCL 1190 - - ns Tr,Tf SCL Rise/Fall Time SCL - - 25 ns TSAS Address Setup Time RS 75 - - ns TSAH Address Hold Time RS 10 - - ns TSDS Data Setup Time SI 10 - - ns TSDH Data Hold Time SI 75 - - ns TCSS CS-SCL Time CS 75 ns TCSH CS-SCL Time CS 250 ns Interface Mode with LCD Driver(ST7921) V1.4 TCWH Clock Pulse with High Pins: CL1, CL2 800 - - ns TCWL Clock Pulse with Low Pins: CL1, CL2 800 - - ns TCST Clock Setup Time Pins: CL1, CL2 500 - - ns TSU Data Setup Time Pin: D 300 - - ns TDH Data Hold Time Pin: D 300 - - ns TDM M Delay Time Pin: M 0 - 2000 ns 39/51 2009/04/29 ST7070 AC Characteristics In Serial Interface (TA = 25°C, VCC = 5V) Symbol Characteristics Test Condition Min. Typ. Max. Unit Internal Clock Operation fOSC OSC Frequency R = 91KΩ 190 270 350 KHz External Clock Operation fEX Tr,Tf External Frequency - 125 270 410 KHz Duty Cycle - 45 50 55 % Rise/Fall Time - - - 0.2 µs Write Mode (Writing data from MPU to ST7070) TSCYC SCL Cycle Time SCL 2010 - - ns TSHW,SLW SCL Pulse Width SCL 1010 - - ns Tr,Tf SCL Rise/Fall Time SCL - - 25 ns TSAS Address Setup Time RS 60 - - ns TSAH Address Hold Time RS 10 - - ns TSDS Data Setup Time SI 10 - - ns TSDH Data Hold Time SI 60 - - ns TCSS CS-SCL Time CS 60 ns TCSH CS-SCL Time CS 160 ns Interface Mode with LCD Driver(ST7921) V1.4 TCWH Clock Pulse with High Pins: CL1, CL2 800 - - ns TCWL Clock Pulse with Low Pins: CL1, CL2 800 - - ns TCST Clock Setup Time Pins: CL1, CL2 500 - - ns TSU Data Setup Time Pin: D 300 - - ns TDH Data Hold Time Pin: D 300 - - ns TDM M Delay Time Pin: M 0 - 2000 ns 40/51 2009/04/29 ST7070 Absolute Maximum Ratings Characteristics Symbol Value Power Supply Voltage VCC -0.3 to +5.5 LCD Driver Voltage VLCD Vss+7.0 to Vss-0.3 Input Voltage VIN -0.3 to VCC+0.3 Operating Temperature TA -40°C to + 90°C Storage Temperature TSTO -55°C to + 125°C DC Characteristics ( TA = 25°C, VCC = 2.7 V – 4.5 V ) Test Condition Symbol Characteristics Min. Typ. Max. Unit VCC Operating Voltage - 2.7 - 4.5 V VLCD LCD Voltage V0 - Vss 3.0 - 7.0 V ICC Power Supply Current fOSC = 270KHz VCC=3.0V - 0.1 0.25 mA VIH1 Input High Voltage (Except OSC1) - 0.7Vcc - VCC V VIL1 Input Low Voltage (Except OSC1) - - 0.3 - 0.6 V VIH2 Input High Voltage (OSC1) - 0.7Vcc - VCC V VIL2 Input Low Voltage (OSC1) - - - 0.2Vcc V VOH1 Output High Voltage (DB0 - DB7) IOH = -0.1mA 0.75 Vcc - - V VOL1 Output Low Voltage (DB0 - DB7) IOL = 0.1mA - - 0.2Vcc V VOH2 Output High Voltage (Except DB0 - DB7) IOH = -0.04mA 0.8VCC - VCC V VOL2 Output Low Voltage (Except DB0 - DB7) IOL = 0.04mA - - 0.2VCC V RCOM Common Resistance VLCD = 4V, Id = 0.05mA - 2 20 KΩ RSEG Segment Resistance VLCD = 4V, Id = 0.05mA - 2 30 KΩ ILEAK Input Leakage Current VIN = 0V to VCC -1 - 1 µA IPUP Pull Up MOS Current VCC = 3V 10 60 120 µA NOTE : External bias resistor select , so Idd doesn’t include the follower current. V1.4 41/51 2009/04/29 ST7070 DC Characteristics ( TA = 25°C, VCC = 4.5 V - 5.5 V ) Symbol Characteristics Test Condition Min. Typ. Max. Unit VCC Operating Voltage - 4.5 - 5.5 V VLCD LCD Voltage V0 - Vss 3.0 - 7.0 V ICC Power Supply Current fOSC = 270KHz VCC=5.0V - 0.2 0.5 mA VIH1 Input High Voltage (Except OSC1) - 2.5 - VCC V VIL1 Input Low Voltage (Except OSC1) - -0.3 - 0.6 V VIH2 Input High Voltage (OSC1) - VCC-1 - VCC V VIL2 Input Low Voltage (OSC1) - - - 1.0 V VOH1 Output High Voltage (DB0 - DB7) IOH = -0.1mA 3.9 - VCC V VOL1 Output Low Voltage (DB0 - DB7) IOL = 0.1mA - - 0.4 V VOH2 Output High Voltage (Except DB0 - DB7) IOH = -0.04mA 0.9VCC - VCC V VOL2 Output Low Voltage (Except DB0 - DB7) IOL = 0.04mA - - 0.1VCC V RCOM Common Resistance VLCD = 4V, Id = 0.05mA - 2 20 KΩ RSEG Segment Resistance VLCD = 4V, Id = 0.05mA - 2 30 KΩ ILEAK Input Leakage Current VIN = 0V to VCC -1 - 1 µA IPUP Pull Up MOS Current VCC = 5V 90 200 330 µA NOTE : External bias resistor select , so Idd doesn’t include the follower current. V1.4 42/51 2009/04/29 ST7070 LCD Frame Frequency Assume the oscillation frequency is 270KHZ, 1 clock cycle time = 3.7us, 1/16 duty; 1/5 bias,1 frame = 3.7us x 200 x 16 = 11840us=11.8ms(84.7Hz) 200 clocks 1 2 3 4 16 1 2 3 4 16 1 2 3 4 16 V0 V1 V2 COM1 V3 V4 Vss V0 V1 V2 COM2 V3 V4 Vss V0 V1 V2 COM16 V3 V4 Vss V0 V1 V2 SEGx off V3 V4 Vss V0 V1 V2 SEGx on V3 V4 Vss 1 frame V1.4 43/51 2009/04/29 ST7070 Assume the oscillation frequency is 270KHZ, 1 clock cycle time = 3.7us, 1/8 duty; 1/4 bias,1 frame = 3.7us x 400 x 8 = 11840us=11.8ms (84.7Hz) 400 clocks 1 2 3 4 8 1 2 3 4 8 1 2 3 4 8 V0 V1 COM1 V2 V3 V4 Vss V0 V1 COM2 V2 V3 V4 Vss V0 V1 COM8 V2 V3 V4 Vss V0 V1 SEGx off V2 V3 V4 Vss V0 V1 SEGx on V2 V3 V4 Vss 1 frame V1.4 44/51 2009/04/29 ST7070 I/O Pad Configuration VCC VCC VCC VCC PSB PSB PMOS PMOS PMOS NMOS NMOS NMOS PSB=1==>E(Floating) PSB=0==>E(Pull up) VCC PSB PSB=1==>R/W(With Pull up) PSB=0==>R/W(With Pull down) VCC PMOS PMOS NMOS PSB=1==>RS(With Pull up) PSB=0==>RS(Floating) VCC PMOS Output PAD:CL1,CL2,M,D NMOS V1.4 45/51 2009/04/29 ST7070 VCC VCC VCC Enable PMOS PMOS NMOS VCC PSB VCC PMOS Data NMOS I/O PAD:DB4-DB0 PSB=1==> Pull up PSB=0==>Pull up VCC Enable PMOS PMOS NMOS PMOS Data NMOS I/O PAD:DB7-DB5 PSB=1==> Pull up PSB=0==>Floating V1.4 46/51 2009/04/29 ST7070 LCD and ST7070 Connection ST7070 1. 5x8 dots, 16 characters x 1 line (1/4 bias, 1/8 duty) COM1 . . . . . . . . COM8 SEG1 . . . . . SEG80 LCD Panel: 16 Characters x 1 line 2. 5x8 dots, 16 characters x 2 line (1/5 bias, 1/16 duty) ST7070 COM1 . . . . . . . . COM8 COM9 . . . . . . . . COM16 SEG1 . . . . . . . . . . SEG80 V1.4 LCD Panel: 16 Characters x 2 line 47/51 2009/04/29 ST7070 3. 5x8 dots, 32 characters x 1 line (1/5 bias, 1/16 duty) ST7070 COM1 . . . . . . . . COM8 SEG1 . . . . . . SEG80 LCD Panel: 32 Characters x 1 line COM9 . . . . . . . . COM16 V1.4 48/51 2009/04/29 ST7070 Application Circuit Com 1-16 D V4 V3 V2 V1 V0 M CL1 CL2 GND VCC Seg 1-80 ST7070 RS/RW/E/DB0-DB7 To MPU Vcc(+5V) VR Dot Matrix LCD Panel Seg 1~96 2 (Line) X 40 ( Characters ) 5X8 dots/character Seg 1~24 DL2 SHL1 V3 M CL2 CL1 DR1 DR2 SHL2 Resistor VSS ST7921 DL1 CL1 VSS DR1 CL2 ST7921 SHL2 V0 M V0 V3 VSS SHL1 VCC V2 DL2 Resistor DR2 Resistor DL1 Resistor VCC V2 Resistor VR=10K~30Kohm Note:Resistor=2.2K~10K ohm 2009/04/29 49/51 V1.4 ST7070 THE MPU INTERFACE The ST7070 Series can be connected to 6800 Series MPUs. Moreover, using the serial interface it is possible to operate the ST7070 series chips with fewer signal lines. The display area can be enlarged by using multiple ST7070 Series chips . When this is done , the chip select signal can be used to select the individual Ics to access. (1) 6800 8 bits Series MPUs VDD VCC RS VDD PSB RS VLCD R V0 MPU D0 to D7 R/W E R D0 to D7 R/W ST7070 V1 R V2 R E V3 /RES R /RES V4 GND R GND VSS When use external bias resistor must connect VSS (2) 6800 4 bits Series MPUs VDD VCC D0 to D3 RS VDD PSB VLCD RS R V0 MPU D4 to D7 R/W E D4 to D7 R/W ST7070 R V1 R V2 R E V3 /RES R /RES V4 GND R GND VSS When use external bias resistor must connect VSS V1.4 50/51 2009/04/29 ST7070 (3) Using the Serial Interface—For 4 SPI VDD VDD PSB VCC RS D7(SI) D0 to D5 RS D7(SI) V0 D6(SCL) V1 D5(CS) V2 VLCD R R MPU D6(SCL) GND D5(CS) /RES ST7070 R R/W V3 E V4 /RES R R R GND VSS When use external bias resistor must connect VSS (4) Using the Serial Interface—For 3 SPI VDD VCC D0 to D5 RS D7(SI) VDD PSB D7(SI) V0 D6(SCL) V1 D5(CS) V2 VLCD R R MPU D6(SCL) GND D5(CS) /RES ST7070 R R/W V3 E V4 /RES R R R GND VSS When use external bias resistor must connect VSS V1.4 51/51 2009/04/29