RENESAS M34506E4FP

4506 Group
REJ03B0106-0301
Rev.3.01
2005.02.07
SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER
DESCRIPTION
The 4506 Group is a 4-bit single-chip microcomputer designed with
CMOS technology. Its CPU is that of the 4500 series using a
simple, high-speed instruction set. The computer is equipped with
two 8-bit timers (each timer has a reload register), interrupts, and
10-bit A/D converter.
The various microcomputers in the 4506 Group include variations
of the built-in memory size as shown in the table below.
FEATURES
●Minimum instruction execution time ................................ 0.68 µs
(at 4.4 MHz oscillation frequency, in high-speed mode)
●Supply voltage .......................................................... 2.0 V to 5.5 V
(It depends on the oscillation frequency and operating mode.)
ROM (PROM) size
(✕ 10 bits)
2048 words
4096 words
4096 words
Part number
M34506M2-XXXFP
M34506M4-XXXFP
M34506E4FP (Note)
●Timers
Timer 1 ...................................... 8-bit timer with a reload register
Timer 2 ...................................... 8-bit timer with a reload register
●Interrupt ........................................................................ 4 sources
●Key-on wakeup function pins ................................................... 12
●Input/Output port ...................................................................... 14
●A/D converter .................. 10-bit successive comparison method
●Watchdog timer
●Clock generating circuit (ceramic resonator/RC oscillation)
●LED drive directly enabled (port D)
APPLICATION
Electrical household appliance, consumer electronic products, office automation equipment, etc.
RAM size
(✕ 4 bits)
128 words
256 words
256 words
Package
ROM type
PRSP0020DA-A
PRSP0020DA-A
PRSP0020DA-A
Mask ROM
Mask ROM
One Time PROM
Note: Shipped in blank.
PIN CONFIGURATION
1
20
P00
VSS
2
19
P01
XIN
3
18
P02
XOUT
4
17
P03
CNVSS
5
16
P10
RESET
6
15
P11
P21/AIN1
7
14
P12/CNTR
P20/AIN0
8
13
P13/INT
D3/K
9
12
D0
D2/C
10
11
D1
M34506Mx-XXXFP
M34506E4FP
VDD
Outline PRSP0020DA-A (20P2N-A)
Pin configuration (top view) (4506 Group)
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I/O port
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Port P1
4
Block diagram (4506 Group)
page 2 of 111
A/D converter
(10 bits ✕ 2 ch)
Watchdog timer
(16 bits)
Timer 2 (8 bits)
Register A (4 bits)
Register B (4 bits)
Register E (8 bits)
Register D (3 bits)
Stack register SK (8 levels)
Interrupt stack register SDP (1level)
ALU (4 bits)
4500 Series
CPU core
128, 256 words ✕ 4 bits
RAM
2048, 4096 words ✕ 10 bits
ROM
Memory
XIN -XOUT
Timer 1 (8 bits)
Port D
4
System clock generating circuit
Port P2
2
Timer
Internal peripheral functions
Port P0
4
4506 Group
BLOCK DIAGRAM
4506 Group
PERFORMANCE OVERVIEW
Parameter
Number of basic instructions
Minimum instruction execution time
Memory sizes ROM
M34506M2
M34506M4/E4
RAM
M34506M2
M34506M4/E4
Input/Output D0–D3
I/O
ports
P00–P03 I/O
P10–P13 I/O
P20, P21 I/O
Timers
C
K
CNTR
INT
AIN0, AIN1
Timer 1
Timer 2
I/O
I/O
Timer I/O
Interrupt input
Analog input
A/D converter
Analog input
Sources
Nesting
Subroutine nesting
Device structure
Package
Operating temperature range
Supply voltage
Interrupt
Power
Active mode
dissipation
(typical value)
RAM back-up mode
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Function
110
0.68 µs (at 4.4 MHz oscillation frequency, in high-speed mode)
2048 words ✕ 10 bits
4096 words ✕ 10 bits
128 words ✕ 4 bits
256 words ✕ 4 bits
Four independent I/O ports .
Input is examined by skip decision.
Ports D2 and D3 are equipped with a pull-up function and a key-on wakeup function. Both functions can be switched by software.
Ports D2 and D3 are also used as ports C and K, respectively.
4-bit I/O port; each pin is equipped with a pull-up function and a key-on wakeup function. Both
functions can be switched by software.
4-bit I/O port; each pin is equipped with a pull-up function and a key-on wakeup function. Both
functions can be switched by software.
Ports P12 and P13 are also used as CNTR and INT, respectively.
2-bit I/O port; each pin is equipped with a pull-up function and a key-on wakeup function. Both
functions can be switched by software.
Ports P20 and P21 are also used as AIN0 and AIN1, respectively.
1-bit I/O; Port C is also used as port D2.
1-bit I/O; Port K is also used as port D3.
1-bit I/O; CNTR pin is also used as port P12.
1-bit input; INT pin is also used as port P13.
Two independent I/O ports; AIN0, AIN1 are also used as P20 and P21, respectively.
8-bit programmable timer with a reload register.
8-bit programmable timer with a reload register and has a event counter.
10-bit wide, This is equipped with an 8-bit comparator function.
2 channel (AIN0 pin, AIN1 pin)
4 (one for external, two for timer, one for A/D)
1 level
8 levels
CMOS silicon gate
20-pin plastic molded SOP (PRSP0020DA-A)
–20 °C to 85 °C
2.0 V to 5.5 V (It depends on the oscillation frequency and operating mode. Refer to the recommended operating condition.)
1.7 mA (Ta=25°C, VDD = 5.0 V, 4.0 MHz oscillation frequency, in high-speed mode, output transistors in the cut-off state)
0.5 mA (Ta=25°C, VDD = 3.0 V, 2.0 MHz oscillation frequency, in high-speed mode, output transistors in the cut-off state)
0.1 µA (Ta=25°C, VDD = 5 V, output transistors in the cut-off state)
4506 Group
PIN DESCRIPTION
Pin
VDD
VSS
CNVSS
RESET
Name
Power supply
Ground
CNVSS
Reset input/output
Input/Output
—
—
—
I/O
XIN
System clock input
XOUT
System clock output
D0–D3
I/O port D
I/O
P00–P03
I/O port P0
I/O
P10–P13
I/O port P1
I/O
P20, P21
I/O port P2
I/O
Port C
I/O port C
I/O
Port K
I/O port K
I/O
CNTR
Timer input/output
I/O
INT
Interrupt input
Input
AIN0–AIN1
Analog input
Input
Input
Output
Function
Connected to a plus power supply.
Connected to a 0 V power supply.
Connect CNVSS to VSS and apply “L” (0V) to CNVSS certainly.
An N-channel open-drain I/O pin for a system reset. When the watchdog timer or the
built-in power-on reset causes the system to be reset, the RESET pin outputs “L” level.
I/O pins of the system clock generating circuit. When using a ceramic resonator, connect
it between pins XIN and XOUT. A feedback resistor is built-in between them. When using
the RC oscillation, connect a resistor and a capacitor to XIN, and leave XOUT pin open.
Each pin of port D has an independent 1-bit wide I/O function. Each pin has an output latch. For input use, set the latch of the specified bit to “1.” Input is examined by
skip decision. The output structure is N-channel open-drain. Ports D2 and D3 are
equipped with a pull-up function and a key-on wakeup function. Both functions can
be switched by software.
Ports D2 and D3 are also used as ports C and K, respectively.
Port P0 serves as a 4-bit I/O port, and it can be used as inputs when the output latch
is set to “1.” The output structure is N-channel open-drain. Port P0 has a key-on
wakeup function and a pull-up function. Both functions can be switched by software.
Port P1 serves as a 4-bit I/O port, and it can be used as inputs when the output latch
is set to “1.” The output structure is N-channel open-drain. Port P1 has a key-on
wakeup function and a pull-up function. Both functions can be switched by software.
Ports P12 and P13 are also used as CNTR and INT, respectively.
Port P2 serves as a 2-bit I/O port, and it can be used as inputs when the output latch
is set to “1.” The output structure is N-channel open-drain. Port P2 has a key-on
wakeup function and a pull-up function. Both functions can be switched by software.
Ports P20 and P21 are also used as AIN0 and AIN1, respectively.
1-bit I/O port. Port C can be used as inputs when the output latch is set to “1.” The
output structure is N-channel open-drain. Port C has a key-on wakeup function and
a pull-up function. Both functions can be switched by software. Port C is also used
as port D2.
1-bit I/O port. Port K can be used as inputs when the output latch is set to “1.” The
output structure is N-channel open-drain. Port K has a key-on wakeup function and
a pull-up function. Both functions can be switched by software. Port K is also used
as port D3.
CNTR pin has the function to input the clock for the timer 2 event counter, and to output the timer 1 or timer 2 underflow signal divided by 2. This pin is also used as port
P12.
INT pin accepts external interrupts. It has the key-on wakeup function which can be
switched by software. This pin is also used as port P13.
A/D converter analog input pins. AIN0 and AIN1 are also used as ports P20 and P21,
respectively.
MULTIFUNCTION
Pin
D2
D3
P12
P13
Multifunction
C
K
CNTR
INT
Pin
C
K
CNTR
INT
Multifunction
D2
D3
P12
P13
Pin
P20
P21
Multifunction
AIN0
AIN1
Notes 1: Pins except above have just single function.
2: The input/output of D2, D3, P12 and P13 can be used even when C, K, CNTR (input) and INT are selected.
3: The input of P12 can be used even when CNTR (output) is selected.
4: The input/output of P20, P2 1 can be used even when AIN0, AIN1 are selected.
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Pin
AIN0
AIN1
Multifunction
P20
P21
4506 Group
DEFINITION OF CLOCK AND CYCLE
● Operation source clock
The operation source clock is the source clock to operate this
product. In this product, the following clocks are used.
• External ceramic resonator
• External RC oscillation
• Clock (f(XIN)) by the external clock
• Clock (f(RING)) of the on-chip oscillator which is the internal
oscillator.
● System clock
The system clock is the basic clock for controlling this product.
The system clock is selected by the bits 2 and 3 of the clock control register MR.
Table Selection of system clock
Register MR
System clock
MR3
MR2
(Note 1)
0
0
f(XIN) or f(RING)
0
1
f(XIN)/2 or f(RING)/2
1
0
f(XIN)/4 or f(RING)/4
1
1
f(XIN)/8 or f(RING)/8
● Instruction clock
The instruction clock is a signal derived by dividing the system
clock by 3. The one instruction clock cycle generates the one
machine cycle.
● Machine cycle
The machine cycle is the standard cycle required to execute the
instruction.
Operation mode
High-speed mode
Middle-speed mode
Low-speed mode
Default mode
Notes 1: The on-chip oscillator clock is f(RING), the clock by the
ceramic resonator, RC oscillation or external clock is
f(XIN).
2: The default mode is selected after system is released
from reset and is returned from RAM back-up.
PORT FUNCTION
Port
Port D
Pin
D 0, D 1
D2/C
D3/K
Input
Output
I/O
(4)
Output structure
N-channel open-drain
I/O
unit
1
Control
instructions
SD, RD
SZD, CLD
SCP, RCP
SNZCP
IAK, OKA
OP0A
IAP0
Control
registers
PU2, K2
Port P0 P00–P03
I/O
(4)
N-channel open-drain
4
Port P1 P10, P11
P12/CNTR,
P13/INT
I/O
(4)
N-channel open-drain
4
OP1A
IAP1
PU1, K1
W6, I1
Port P2 P20/AIN0
P21/AIN1
I/O
(2)
N-channel open-drain
2
OP2A
IAP2
PU2, K2
Q1
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PU0, K0
Remark
Built-in programmable pull-up
functions
Key-on wakeup functions
(programmable)
Built-in programmable pull-up
functions
Key-on wakeup functions
(programmable)
Built-in programmable pull-up
functions
Key-on wakeup functions
(programmable)
Built-in programmable pull-up
functions
Key-on wakeup functions
(programmable)
4506 Group
CONNECTIONS OF UNUSED PINS
Pin
XIN
XOUT
D 0, D 1
D2/C
D3/K
P00–P03
P10, P11
P12/CNTR
P13/INT
P20/AIN0
P21/AIN1
Connection
Connect to VSS.
Open.
Open. (Output latch is set to “1.”)
Open. (Output latch is set to “0.”)
Connect to VSS.
Open. (Output latch is set to “1.”)
Open. (Output latch is set to “0.”)
Connect to VSS.
Open. (Output latch is set to “1.”)
Open. (Output latch is set to “0.”)
Connect to VSS.
Open. (Output latch is set to “1.”)
Open. (Output latch is set to “0.”)
Connect to VSS.
Open. (Output latch is set to “1.”)
Open. (Output latch is set to “0.”)
Connect to VSS.
Open. (Output latch is set to “1.”)
Open. (Output latch is set to “0.”)
Connect to VSS.
Usage condition
System operates by the on-chip oscillator. (Note 1)
System operates by the external clock.
(The ceramic resonator is selected with the CMCK instruction.)
System operates by the RC oscillator.
(The RC oscillation is selected with the CRCK instruction.)
System operates by the on-chip oscillator. (Note 1)
The key-on wakeup function is not selected. (Note 4)
The pull-up function and the key-on wakeup function are not selected. (Notes 2, 3)
The pull-up function and the key-on wakeup function are not selected. (Notes 2, 3)
The key-on wakeup function is not selected. (Note 4)
The pull-up function and the key-on wakeup function are not selected. (Notes 2, 3)
The pull-up function and the key-on wakeup function are not selected. (Notes 2, 3)
The key-on wakeup function is not selected. (Note 4)
The pull-up function and the key-on wakeup function are not selected. (Notes 2, 3)
The pull-up function and the key-on wakeup function are not selected. (Notes 2, 3)
The key-on wakeup function is not selected. The input to INT pin is disabled.
(Notes 4, 5)
The pull-up function and the key-on wakeup function are not selected. (Notes 2, 3)
The pull-up function and the key-on wakeup function are not selected. (Notes 2, 3)
The key-on wakeup function is not selected. (Note 4)
The pull-up function and the key-on wakeup function are not selected. (Notes 2, 3)
The pull-up function and the key-on wakeup function are not selected. (Notes 2, 3)
Notes 1: When the ceramic resonator or the RC oscillation is not selected by program, system operates by the on-chip oscillator (internal oscillator).
2: When the pull-up function is left valid, the supply current is increased. Do not select the pull-up function.
3: When the key-on wakeup function is left valid, the system returns from the RAM back-up state immediately after going into the RAM back-up state.
Do not select the key-on wakeup function.
4: When selecting the key-on wakeup function, select also the pull-up function.
5: Clear the bit 3 (I13) of register I1 to “0” to disable to input to INT pin (after reset: I13 = “0”)
(Note when connecting to VSS)
● Connect the unused pins to VSS using the thickest wire at the shortest distance against noise.
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4506 Group
PORT BLOCK DIAGRAMS
Register Y
Skip decision
(SZD instruction)
Decoder
(Note 1)
D0 , D1
CLD
instruction
S
SD instruction
R Q
RD instruction
Pull-up
transistor
Register Y
Decoder
PU22
K22
“L” level
detection circuit
Key-on wakeup
Skip decision
(SZD instruction)
CLD
instruction
Skip decision
(SNZCP
instruction)
S
SD instruction
(Note 1)
D2/C (Note 2)
R Q
RD instruction
SCP instruction
S
RCP instruction
R Q
Pull-up
transistor
Register Y
Decoder
PU23
K23
“L” level
detection circuit
Key-on wakeup
Skip decision
(SZD instruction)
CLD
instruction
IAK instruction
S
SD instruction
Register A
(Note 1)
D3/K (Note 2)
R Q
RD instruction
A0
OKA instruction
D
T Q
Notes 1:
This symbol represents a parasitic diode on the port.
2: Applied potential to ports D2/C and D3/K must be VDD or less.
Port block diagram (1)
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4506 Group
Pull-up transistor
PU0i (Note 2)
Register A IAP0 instruction
Ai
(Note 2)
(Note 1)
P00, P01 (Note 4)
D
Ai
OP0A instruction
T
Q
K0i
Key-on wakeup input
“L” level
detection circuit
Pull-up transistor
PU0j
(Note 3)
Register A IAP0 instruction
Aj
(Note 3)
(Note 1)
P02, P03 (Note 4)
D
Aj
OP0A instruction
T
Q
K0j
Key-on wakeup
“L” level detection
circuit
Notes 1:
This symbol represents a parasitic diode on the port.
2: i represents 0 or 1.
3: j represents 2 or 3.
4: Applied potential to port P0 must be VDD or less.
Port block diagram (2)
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4506 Group
Pull-up transistor
K1i
(Note 2)
PU1i (Note 2)
“L” level
detection circuit
Key-on wakeup input
IAP1 instruction
Register A
Ai
(Note 1)
(Note 2)
P10, P11 (Note 3)
Ai
D
T
OP1A instruction
Q
Pull-up transistor
PU12
K12
“L” level
detection circuit
W 21
W 20
Key-on wakeup input
Clock input for timer 2 event counter
IAP1 instruction
Register A
A2
(Note 1)
P12/CNTR (Note 3)
A2
D
W60
Q
0
Timer 1 or timer 2 underflow
signal divided by 2
1
OP1A instruction
T
K13
“L” level
detection circuit
Key-on wakeup input
Pull-up transistor
PU13
K13
External 0 interrupt
Register A
A3
External interrupt circuit
IAP1 instruction
(Note 1)
P13/INT (Note 3)
A3
OP1A instruction
D
T
Q
Notes 1:
This symbol represents a parasitic diode on the port.
2: i represents 0 or 1.
3: Applied potential to port P1 must be VDD or less.
Port block diagram (3)
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4506 Group
K20
“L” level
detection circuit
Key-on wakeup input
Register A
Pull-up transistor
PU20
IAP2 instruction
(Note 1)
A0
P20/AIN0 (Note 3)
D
A0
T
OP2A instruction
Q
Q1
Decoder
Analog input
K21
Key-on wakeup input
Register A
“L” level
detection circuit
Pull-up transistor
PU21
IAP2 instruction
(Note 1)
A1
P21/AIN1 (Note 3)
D
A1
OP2A instruction
T
Q
Q1
Decoder
Analog input
Notes 1:
This symbol represents a parasitic diode on the port.
2: i represents 0 or 1.
3: Applied potential to port P2 must be VDD or less.
Port block diagram (4)
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4506 Group
I12
Falling
(Note)
One-sided edge
detection circuit
0
I11
0
P13/INT
EXF0
1
I13
External 0
interrupt
1
Both edges
detection circuit
Rising
Wakeup
K13
Timer 1 count start
synchronization
circuit input
Skip
SNZI0 instruction
•
External interrupt circuit structure
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This symbol represents a parasitic diode on the port.
4506 Group
FUNCTION BLOCK OPERATIONS
CPU
<Carry>
(CY)
(1) Arithmetic logic unit (ALU)
(M(DP))
The arithmetic logic unit ALU performs 4-bit arithmetic such as 4bit data addition, comparison, AND operation, OR operation, and
bit manipulation.
ALU
Addition
(A)
<Result>
(2) Register A and carry flag
Register A is a 4-bit register used for arithmetic, transfer, exchange, and I/O operation.
Carry flag CY is a 1-bit flag that is set to “1” when there is a carry
with the AMC instruction (Figure 1).
It is unchanged with both A n instruction and AM instruction. The
value of A0 is stored in carry flag CY with the RAR instruction (Figure 2).
Carry flag CY can be set to “1” with the SC instruction and cleared
to “0” with the RC instruction.
Fig. 1 AMC instruction execution example
<Set>
SC instruction
<Clear>
RC instruction
CY
A 3 A2 A1 A0
<Rotation>
RAR instruction
(3) Registers B and E
Register B is a 4-bit register used for temporary storage of 4-bit
data, and for 8-bit data transfer together with register A.
Register E is an 8-bit register. It can be used for 8-bit data transfer
with register B used as the high-order 4 bits and register A as the
low-order 4 bits (Figure 3).
Register E is undefined after system is released from reset and returned from the RAM back-up. Accordingly, set the initial value.
A0
CY A3 A2 A1
Fig. 2 RAR instruction execution example
TAB instruction
Register B
B3 B2 B1 B0
(4) Register D
Register D is a 3-bit register.
It is used to store a 7-bit ROM address together with register A and
is used as a pointer within the specified page when the TABP p,
BLA p, or BMLA p instruction is executed (Figure 4).
Register D is undefined after system is released from reset and returned from the RAM back-up. Accordingly, set the initial value.
Register A
A3 A2 A1 A0
TEAB instruction
Register E E7 E6 E5 E4 E3 E2 E1 E0
TABE instruction
A3 A2 A1 A0
B3 B2 B1 B0
Register B
TBA instruction
Register A
Fig. 3 Registers A, B and register E
TABP p instruction
ROM
Specifying address
p 6 p5
PCH
p4 p 3 p 2 p 1 p0
PCL
DR2 DR1DR0 A3 A2 A1 A0
8
4
0
Low-order 4bits
Register A (4)
Middle-order 4 bits
Register B (4)
Immediate field
value p
The contents of The contents of
register D
register A
Fig. 4 TABP p instruction execution example
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4506 Group
(5) Stack registers (SKS) and stack pointer (SP)
Stack registers (SKs) are used to temporarily store the contents of
program counter (PC) just before branching until returning to the
original routine when;
• branching to an interrupt service routine (referred to as an interrupt service routine),
• performing a subroutine call, or
• executing the table reference instruction (TABP p).
Stack registers (SKs) are eight identical registers, so that subroutines can be nested up to 8 levels. However, one of stack registers
is used respectively when using an interrupt service routine and
when executing a table reference instruction. Accordingly, be careful not to over the stack when performing these operations
together. The contents of registers SKs are destroyed when 8 levels are exceeded.
The register SK nesting level is pointed automatically by 3-bit
stack pointer (SP). The contents of the stack pointer (SP) can be
transferred to register A with the TASP instruction.
Figure 5 shows the stack registers (SKs) structure.
Figure 6 shows the example of operation at subroutine call.
(6) Interrupt stack register (SDP)
Interrupt stack register (SDP) is a 1-stage register. When an interrupt occurs, this register (SDP) is used to temporarily store the
contents of data pointer, carry flag, skip flag, register A, and register B just before an interrupt until returning to the original routine.
Unlike the stack registers (SKs), this register (SDP) is not used
when executing the subroutine call instruction and the table reference instruction.
Program counter (PC)
Executing BM
instruction
Executing RT
instruction
SK0
(SP) = 0
SK1
(SP) = 1
SK2
(SP) = 2
SK3
(SP) = 3
SK4
(SP) = 4
SK5
(SP) = 5
SK6
(SP) = 6
SK7
(SP) = 7
Stack pointer (SP) points “7” at reset or
returning from RAM back-up mode. It points “0”
by executing the first BM instruction, and the
contents of program counter is stored in SK0.
When the BM instruction is executed after eight
stack registers are used ((SP) = 7), (SP) = 0
and the contents of SK0 is destroyed.
Fig. 5 Stack registers (SKs) structure
(SP) ← 0
(SK0) ← 000116
(PC) ← SUB1
Main program
Subroutine
Address
(7) Skip flag
Skip flag controls skip decision for the conditional skip instructions
and continuous described skip instructions. When an interrupt occurs, the contents of skip flag is stored automatically in the interrupt
stack register (SDP) and the skip condition is retained.
SUB1 :
000016 NOP
NOP
·
·
·
RT
000116 BM SUB1
000216 NOP
(PC) ← (SK0)
(SP) ← 7
Note : Returning to the BM instruction execution
address with the RT instruction, and the BM
instruction becomes the NOP instruction.
Fig. 6 Example of operation at subroutine call
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4506 Group
(8) Program counter (PC)
Program counter (PC) is used to specify a ROM address (page and
address). It determines a sequence in which instructions stored in
ROM are read. It is a binary counter that increments the number of
instruction bytes each time an instruction is executed. However,
the value changes to a specified address when branch instructions,
subroutine call instructions, return instructions, or the table reference instruction (TABP p) is executed.
Program counter consists of PC H (most significant bit to bit 7)
which specifies to a ROM page and PCL (bits 6 to 0) which specifies an address within a page. After it reaches the last address
(address 127) of a page, it specifies address 0 of the next page
(Figure 7).
Make sure that the PCH does not specify after the last page of the
built-in ROM.
Program counter
p6 p5 p4 p3 p2 p1 p0
a6 a5 a4 a3 a2 a1 a0
PCH
Specifying page
PCL
Specifying address
Fig. 7 Program counter (PC) structure
Data pointer (DP)
Z1 Z0 X3 X2 X1 X0 Y3 Y2 Y1 Y0
(9) Data pointer (DP)
Data pointer (DP) is used to specify a RAM address and consists
of registers Z, X, and Y. Register Z specifies a RAM file group, register X specifies a file, and register Y specifies a RAM digit (Figure
8).
Register Y is also used to specify the port D bit position.
When using port D, set the port D bit position to register Y certainly
and execute the SD, RD, or SZD instruction (Figure 9).
• Note
Register Z of data pointer is undefined after system is released
from reset.
Also, registers Z, X and Y are undefined in the RAM back-up. After
system is returned from the RAM back-up, set these registers.
Specifying
RAM digit
Register Y (4)
Register X (4)
Register Z (2)
Specifying RAM file
Specifying RAM file group
Fig. 8 Data pointer (DP) structure
Specifying bit position
Set
D3
0
0
0
D2
1
Register Y (4)
page 14 of 111
D0
1
Port D output latch
Fig. 9 SD instruction execution example
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D1
4506 Group
PROGRAM MEMOY (ROM)
The program memory is a mask ROM. 1 word of ROM is composed
of 10 bits. ROM is separated every 128 words by the unit of page
(addresses 0 to 127). Table 1 shows the ROM size and pages. Figure 10 shows the ROM map of M34506M4.
Table 1 ROM size and pages
Part number
M34506M2
M34506M4
M34506E4
ROM (PROM) size
(✕ 10 bits)
2048 words
4096 words
4096 words
Pages
16 (0 to 15)
32 (0 to 31)
32 (0 to 31)
A part of page 1 (addresses 008016 to 00FF16) is reserved for interrupt addresses (Figure 11). When an interrupt occurs, the
address (interrupt address) corresponding to each interrupt is set
in the program counter, and the instruction at the interrupt address
is executed. When using an interrupt service routine, write the instruction generating the branch to that routine at an interrupt
address.
Page 2 (addresses 010016 to 017F16) is the special page for subroutine calls. Subroutines written in this page can be called from
any page with the 1-word instruction (BM). Subroutines extending
from page 2 to another page can also be called with the BM instruction when it starts on page 2.
ROM pattern (bits 7 to 0) of all addresses can be used as data areas with the TABP p instruction.
9 8 7 6
000016
007F16
008016
00FF16
010016
017F16
018016
5 4 3
2 1 0
Page 0
Interrupt address page
Page 1
Subroutine special page
Page 2
Page 3
0FFF16
Page 31
Fig. 10 ROM map of M34506M4/M34506E4
008016
9 8 7 6 5 4 3 2 1 0
External 0 interrupt address
008216
008416
Timer 1 interrupt address
008616
Timer 2 interrupt address
008816
008A16
008C16
A/D interrupt address
008E16
00FF16
Fig. 11 Page 1 (addresses 008016 to 00FF16) structure
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4506 Group
DATA MEMORY (RAM)
Table 2 RAM size
1 word of RAM is composed of 4 bits, but 1-bit manipulation (with
the SB j, RB j, and SZB j instructions) is enabled for the entire
memory area. A RAM address is specified by a data pointer. The
data pointer consists of registers Z, X, and Y. Set a value to the
data pointer certainly when executing an instruction to access
RAM.
Table 2 shows the RAM size. Figure 12 shows the RAM map.
Part number
M34506M2
M34506M4
M34506E4
RAM size
128 words ✕ 4 bits (512 bits)
256 words ✕ 4 bits (1024 bits)
256 words ✕ 4 bits (1024 bits)
• Note
Register Z of data pointer is undefined after system is released
from reset.
Also, registers Z, X and Y are undefined in the RAM back-up. After
system is returned from the RAM back-up, set these registers.
RAM 256 words ✕ 4 bits (1024 bits)
Register Z
Register Y
Register X
0
1
........ 15
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
Z=0, X=0 to 15
Z=0, X=0 to 7
Fig. 12 RAM map
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2
0
.
.
.
3
6 7
page 16 of 111
256 words (1024 bits) M34506M4/E4
128 words (512 bits) M34506M2
4506 Group
INTERRUPT FUNCTION
The interrupt type is a vectored interrupt branching to an individual
address (interrupt address) according to each interrupt source. An
interrupt occurs when the following 3 conditions are satisfied.
• An interrupt activated condition is satisfied (request flag = “1”)
• Interrupt enable bit is enabled (“1”)
• Interrupt enable flag is enabled (INTE = “1”)
Table 3 shows interrupt sources. (Refer to each interrupt request
flag for details of activated conditions.)
Table 3 Interrupt sources
Priority
Interrupt name
level
1
External 0 interrupt
Activated condition
2
Timer 1 interrupt
Level change of INT
pin
Timer 1 underflow
3
Timer 2 interrupt
Timer 2 underflow
4
A/D interrupt
Completion of
A/D conversion
Interrupt
address
Address 0
in page 1
Address 4
in page 1
Address 6
in page 1
Address C
in page 1
(1) Interrupt enable flag (INTE)
The interrupt enable flag (INTE) controls whether the every interrupt enable/disable. Interrupts are enabled when INTE flag is set to
“1” with the EI instruction and disabled when INTE flag is cleared to
“0” with the DI instruction. When any interrupt occurs, the INTE flag
is automatically cleared to “0,” so that other interrupts are disabled
until the EI instruction is executed.
Table 4 Interrupt request flag, interrupt enable bit and skip instruction
Interrupt name
External 0 interrupt
Timer 1 interrupt
Timer 2 interrupt
(2) Interrupt enable bit
Use an interrupt enable bit of interrupt control registers V1 and V2
to select the corresponding interrupt or skip instruction.
Table 4 shows the interrupt request flag, interrupt enable bit and
skip instruction.
Table 5 shows the interrupt enable bit function.
(3) Interrupt request flag
When the activated condition for each interrupt is satisfied, the corresponding interrupt request flag is set to “1.” Each interrupt
request flag is cleared to “0” when either;
• an interrupt occurs, or
• the next instruction is skipped with a skip instruction.
Each interrupt request flag is set when the activated condition is
satisfied even if the interrupt is disabled by the INTE flag or its interrupt enable bit. Once set, the interrupt request flag retains set
until a clear condition is satisfied.
Accordingly, an interrupt occurs when the interrupt disable state is
released while the interrupt request flag is set.
If more than one interrupt request flag is set when the interrupt disable state is released, the interrupt priority level is as follows
shown in Table 3.
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A/D interrupt
Interrupt
request flag
EXF0
T1F
T2F
ADF
Skip instruction
SNZ0
SNZT1
SNZT2
SNZAD
Interrupt
enable bit
V10
V12
V13
V22
Table 5 Interrupt enable bit function
Interrupt enable bit
1
0
Occurrence of interrupt
Enabled
Disabled
Skip instruction
Invalid
Valid
4506 Group
(4) Internal state during an interrupt
The internal state of the microcomputer during an interrupt is as follows (Figure 14).
• Program counter (PC)
An interrupt address is set in program counter. The address to be
executed when returning to the main routine is automatically
stored in the stack register (SK).
• Interrupt enable flag (INTE)
INTE flag is cleared to “0” so that interrupts are disabled.
• Interrupt request flag
Only the request flag for the current interrupt source is cleared to
“0.”
• Data pointer, carry flag, skip flag, registers A and B
The contents of these registers and flags are stored automatically
in the interrupt stack register (SDP).
(5) Interrupt processing
When an interrupt occurs, a program at an interrupt address is executed after branching a data store sequence to stack register.
Write the branch instruction to an interrupt service routine at an interrupt address.
Use the RTI instruction to return from an interrupt service routine.
Interrupt enabled by executing the EI instruction is performed after
executing 1 instruction (just after the next instruction is executed).
Accordingly, when the EI instruction is executed just before the RTI
instruction, interrupts are enabled after returning the main routine.
(Refer to Figure 13)
Main
routine
• Interrupt enable flag (INTE)
.................................................................. 0 (Interrupt disabled)
• Interrupt request flag (only the flag for the current interrupt
source) ................................................................................... 0
• Data pointer, carry flag, registers A and B, skip flag
........ Stored in the interrupt stack register (SDP) automatically
Fig. 14 Internal state when interrupt occurs
INT pin
(L→H or
H→L input)
Timer 1
underflow
Timer 2
underflow
Activated
condition
EXF0
V10
T1F
V12
T2F
V13
A DF
Request flag
(state retained)
V22
Enable
bit
Fig. 15 Interrupt system diagram
•
•
•
•
EI
R TI
Interrupt is
enabled
: Interrupt enabled state
: Interrupt disabled state
Fig. 13 Program example of interrupt processing
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• Stack register (SK)
The address of main routine to be
....................................................................................................
executed when returning
Completion of
A/D conversion
Interrupt
service routine
Interrupt
occurs
• Program counter (PC)
............................................................... Each interrupt address
page 18 of 111
Address 0
in page 1
Address 4
in page 1
Address 6
in page 1
INTE
Enable
flag
Address C
in page 1
4506 Group
(6) Interrupt control registers
• Interrupt control register V1
Interrupt enable bits of external 0, timer 1 and timer 2 are assigned to register V1. Set the contents of this register through
register A with the TV1A instruction. The TAV1 instruction can be
used to transfer the contents of register V1 to register A.
• Interrupt control register V2
The A/D interrupt enable bit is assigned to register V2. Set the
contents of this register through register A with the TV2A instruction. The TAV2 instruction can be used to transfer the contents of
register V2 to register A.
Table 6 Interrupt control registers
Interrupt control register V1
V13
Timer 2 interrupt enable bit
V12
Timer 1 interrupt enable bit
V11
Not used
V10
External 0 interrupt enable bit
at reset : 00002
0
1
0
1
0
1
0
1
Interrupt control register V2
V23
Not used
V22
A/D interrupt enable bit
V21
Not used
V20
Not used
This bit has no function, but read/write is enabled.
Interrupt disabled (SNZ0 instruction is valid)
Interrupt enabled (SNZ0 instruction is invalid) (Note 2)
at reset : 00002
0
1
0
1
0
1
0
1
(7) Interrupt sequence
Interrupts only occur when the respective INTE flag, interrupt enable bits (V10, V1 2, V13, V22), and interrupt request flag are “1.”
The interrupt actually occurs 2 to 3 machine cycles after the cycle
in which all three conditions are satisfied. The interrupt occurs after
3 machine cycles only when the three interrupt conditions are satisfied on execution of other than one-cycle instructions (Refer to
Figure 16).
page 19 of 111
R/W
Interrupt disabled (SNZT2 instruction is valid)
Interrupt enabled (SNZT2 instruction is invalid) (Note 2)
Interrupt disabled (SNZT1 instruction is valid)
Interrupt enabled (SNZT1 instruction is invalid) (Note 2)
Notes 1: “R” represents read enabled, and “W” represents write enabled.
2: These instructions are equivalent to the NOP instrucion.
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at RAM back-up : 00002
at RAM back-up : 00002
This bit has no function, but read/write is enabled.
Interrupt disabled (SNZAD instruction is valid)
Interrupt enabled (SNZAD instruction is invalid) (Note 2)
This bit has no function, but read/write is enabled.
This bit has no function, but read/write is enabled.
R/W
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Fig. 16 Interrupt sequence
page 20 of 111
T1F, T2F
ADF
EXF0
T2
T3
EI instruction execution cycle
T1
1 machine cycle
T1
T2
T3
T1
T3
T1
T2
T1
T2
The program starts
from the interrupt
address.
Retaining level of system
clock for 4 periods or more
is necessary.
Interrupt disabled state
Flag cleared
T3
2 to 3 machine cycles
(Notes 2, 3)
Interrupt activated
condition is satisfied.
Interrupt enabled state
T2
Notes 1: The 4506 Group operates in the default mode after system is released from reset (system clock = operation source clock divided by 8).
2: The address is stacked to the last cycle.
3: This interval of cycles depends on the executed instruction at the time when each interrupt activated condition is satisfied.
Timer 1,
Timer 2,
and A/D
interrupts
External
interrupt
INT
Interrupt enable
flag (INTE)
System clock
f (XIN) (high-speed mode)
f (XIN) (middle-speed mode)
f (XIN) (low-speed mode)
f (XIN) (default mode)
● When an interrupt request flag is set after its interrupt is enabled (Note 1)
4506 Group
4506 Group
EXTERNAL INTERRUPTS
The 4506 Group has the external 0 interrupt. An external interrupt
request occurs when a valid waveform is input to an interrupt input
pin (edge detection).
The external interrupt can be controlled with the interrupt control
register I1.
Table 7 External interrupt activated conditions
Name
Input pin
External 0 interrupt
INT
Valid waveform
selection bit
I11
I12
Activated condition
When the next waveform is input to INT pin
• Falling waveform (“H”→“L”)
• Rising waveform (“L”→“H”)
• Both rising and falling waveforms
I12
Falling
(Note)
One-sided edge
detection circuit
0
I11
0
P13/INT
EXF0
1
I13
External 0
interrupt
1
Both edges
detection circuit
Rising
Wakeup
K13
Timer 1 count start
synchronization
circuit input
Skip
SNZI0 instruction
•
This symbol represents a parasitic diode on the port.
Fig. 17 External interrupt circuit structure
(1) External 0 interrupt request flag (EXF0)
External 0 interrupt request flag (EXF0) is set to “1” when a valid
waveform is input to INT pin.
The valid waveforms causing the interrupt must be retained at their
level for 4 clock cycles or more of the system clock (Refer to Figure
16).
The state of EXF0 flag can be examined with the skip instruction
(SNZ0). Use the interrupt control register V1 to select the interrupt
or the skip instruction. The EXF0 flag is cleared to “0” when an interrupt occurs or when the next instruction is skipped with the skip
instruction.
• External 0 interrupt activated condition
External 0 interrupt activated condition is satisfied when a valid
waveform is input to INT pin.
The valid waveform can be selected from rising waveform, falling
waveform or both rising and falling waveforms. An example of
how to use the external 0 interrupt is as follows.
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➀ Set the bit 3 of register I1 to “1” for the INT pin to be in the input
enabled state.
➁ Select the valid waveform with the bits 1 and 2 of register I1.
➂ Clear the EXF0 flag to “0” with the SNZ0 instruction.
➃ Set the NOP instruction for the case when a skip is performed
with the SNZ0 instruction.
➄ Set both the external 0 interrupt enable bit (V1 0) and the INTE
flag to “1.”
The external 0 interrupt is now enabled. Now when a valid waveform is input to the INT pin, the EXF0 flag is set to “1” and the
external 0 interrupt occurs.
4506 Group
(2) External interrupt control registers
• Interrupt control register I1
Register I1 controls the valid waveform for the external 0 interrupt. Set the contents of this register through register A with the
TI1A instruction. The TAI1 instruction can be used to transfer the
contents of register I1 to register A.
Table 8 External interrupt control register
Interrupt control register I1
I13
I12
I11
I10
INT pin input control bit (Note 2)
Interrupt valid waveform for INT pin/
return level selection bit (Note 2)
INT pin edge detection circuit control bit
INT pin
timer 1 control enable bit
at reset : 00002
0
1
0
1
0
1
0
1
at RAM back-up : state retained
R/W
INT pin input disabled
INT pin input enabled
Falling waveform (“L” level of INT pin is recognized with the SNZI0
instruction)/“L” level
Rising waveform (“H” level of INT pin is recognized with the SNZI0
instruction)/“H” level
One-sided edge detected
Both edges detected
Disabled
Enabled
Notes 1: “R” represents read enabled, and “W” represents write enabled.
2: When the contents of I12 and I13 are changed, the external interrupt request flag EXF0 may be set. Accordingly, clear EXF0 flag with the SNZ0 instruction when the bit 0 (V10 ) of register V1 to “0”. In this time, set the NOP instruction after the SNZ0 instruction, for the case when a skip is
performed with the SNZ0 instruction.
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4506 Group
(3) Notes on interrupts
➂ Note [3] on bit 2 of register I1
When the interrupt valid waveform of the P13/INT pin is changed
with the bit 2 of register I1 in software, be careful about the following notes.
• Depending on the input state of the P13/INT pin, the external 0 interrupt request flag (EXF0) may be set when the bit 3 of register
I1 is changed. In order to avoid the occurrence of an unexpected
interrupt, clear the bit 0 of register V1 to “0” (refer to Figure 18➀)
and then, change the bit 3 of register I1.
In addition, execute the SNZ0 instruction to clear the EXF0 flag to
“0” after executing at least one instruction (refer to Figure 18➁).
Also, set the NOP instruction for the case when a skip is performed with the SNZ0 instruction (refer to Figure 18➂).
• Depending on the input state of the P13/INT pin, the external 0 interrupt request flag (EXF0) may be set when the bit 2 of register
I1 is changed. In order to avoid the occurrence of an unexpected
interrupt, clear the bit 0 of register V1 to “0” (refer to Figure 20➀)
and then, change the bit 2 of register I1 is changed.
In addition, execute the SNZ0 instruction to clear the EXF0 flag to
“0” after executing at least one instruction (refer to Figure 20➁).
Also, set the NOP instruction for the case when a skip is performed with the SNZ0 instruction (refer to Figure 20➂).
•••
•••
➀ Note [1] on bit 3 of register I1
When the input of the INT pin is controlled with the bit 3 of register I1 in software, be careful about the following notes.
LA
4
TV1A
LA
8
TI1A
NOP
SNZ0
LA
4
TV1A
LA
12
TI1A
NOP
SNZ0
•••
NOP
; (✕✕✕02)
; The SNZ0 instruction is valid ........... ➀
; (✕1✕✕2)
; Interrupt valid waveform is changed
........................................................... ➁
; The SNZ0 instruction is executed
(EXF0 flag cleared)
........................................................... ➂
•••
NOP
; (✕✕✕02)
; The SNZ0 instruction is valid ........... ➀
; (1✕✕✕2)
; Control of INT pin input is changed
........................................................... ➁
; The SNZ0 instruction is executed
(EXF0 flag cleared)
........................................................... ➂
✕ : these bits are not used here.
✕ : these bits are not used here.
Fig. 18 External 0 interrupt program example-1
➁ Note [2] on bit 3 of register I1
When the bit 3 of register I1 is cleared to “0” , the RAM back-up
mode is selected and the input of INT pin is disabled, be careful
about the following notes.
•••
• When the key-on wakeup function of port P13 is not used (register K13 = “0”), clear bits 2 and 3 of register I1 before system
enters to the RAM back-up mode. (refer to Figure 19➀).
; (00✕✕2)
; Input of INT disabled ........................ ➀
; RAM back-up
•••
LA
0
TI1A
DI
EPOF
POF
✕ : these bits are not used here.
Fig. 19 External 0 interrupt program example-2
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Fig. 20 External 0 interrupt program example-3
4506 Group
TIMERS
• Fixed dividing frequency timer
The fixed dividing frequency timer has the fixed frequency dividing ratio (n). An interrupt request flag is set to “1” after every n
count of a count pulse.
The 4506 Group has the following timers.
• Programmable timer
The programmable timer has a reload register and enables the
frequency dividing ratio to be set. It is decremented from a setting value n. When it underflows (count to n + 1), a timer interrupt
request flag is set to “1,” new data is loaded from the reload register, and count continues (auto-reload function).
FF16
n : Counter initial value
Count starts
Reload
Reload
The contents of counter
n
1st underflow
2nd underflow
0016
Time
n+1 count
n+1 count
Timer interrupt “1”
“0”
request flag
An interrupt occurs or
a skip instruction is executed.
Fig. 21 Auto-reload function
The 4506 Group timer consists of the following circuits.
• Prescaler : frequency divider
• Timer 1 : 8-bit programmable timer
• Timer 2 : 8-bit programmable timer
(Timers 1 and 2 have the interrupt function, respectively)
• 16-bit timer
Prescaler and timers 1 and 2 can be controlled with the timer control registers W1, W2 and W6. The 16-bit timer is a free counter
which is not controlled with the control register.
Each function is described below.
Table 9 Function related timers
Circuit
Count source
Structure
Prescaler
Frequency divider
• Instruction clock
Timer 1
8-bit programmable
• Prescaler output (ORCLK)
Frequency
dividing ratio
4, 16
1 to 256
binary down counter
(link to INT input)
Timer 2
8-bit programmable
binary down counter
• Timer 1 underflow
• Prescaler output (ORCLK)
1 to 256
Use of output signal
• Timer 1 and 2 count sources
• Timer 2 count source
• CNTR output
W6
• CNTR output
W2
• Timer 2 interrupt
W6
• System clock
• Instruction clock
16-bit fixed dividing
frequency binary down
counter
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page 24 of 111
65536
W2
• Timer 1 interrupt
• CNTR input
16-bit timer
Control
register
W1
W1
• Watchdog timer
(The 16th bit is counted twice)
4506 Group
Instruction clock
System clock
Prescaler
11
divided by 8
10
divided by 4
XIN
Internal clock
generating circuit
(divided by 3)
01
divided by 2
Clock
generation
circuit
W13
MR3, MR2
Division circuit
00
W12
0
1/4
0
1
1/16
1
ORCLK
I1 2
Falling
I1 1
0
One-sided edge
detection circuit
0
P13/INT
(Note 1)
S Q
1
I1 3
Rising
1
1
Both edges
detection circuit
W10
0
R
I10
W22
Timer 1 underflow signal
(Note 2) W11
0
1
Timer 1 (8)
T1F
Timer 1
interrupt
T2F
Timer 2
interrupt
Reload register R1 (8)
T1AB
(TAB1)
T1AB
(TR1AB)
Register B Register A
(TAB1)
Timer 1 underflow signal
W21,W20
00
W23 (Note 2)
01
0
10
1
11
Timer 2 (8)
Reload register R2 (8)
(T2AB)
(TAB2)
W60
(TAB2)
W61
0
P12/CNTR
Register B Register A
P12 output
0
1/2
1
1/2
1
Timer 2 underflow signal
16-bit timer (WDT)
Instruction clock
1
Data is set automatically from each reload
register when timer 1 or 2 underflows
(auto-reload function)
16
S
Q
WDF1
WRST instruction
(Note 3)
R
Reset signal
(Note 5)
S
DWDT instruction
+
WRST instruction
(Note 4)
R
Q
WEF
D
Reset signal
Fig. 22 Timers structure
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Q
WDF2
T R
Notes 1: Timer 1 count start synchronous circuit is set
by the valid edge of P13/INT pin selected by
bits 1 (I11) and 2 (I12) of register I1.
2: Count source is stopped by clearing to “0.”
3: When the WRST instruction is executed at
WDF1 flag = “1,” WDF1 flag is cleared to “0”
and the next instruction is skipped.
When the WRST instruction is executed at
Watchdog
WDF1 flag = “0,” skip is not executed.
reset signal
4: When the DWDT and WRST instructions are
executed continuously, WEF flag is cleared to
“0” and reset by watchdog timer is not executed.
5: The WEF flag is set to “1” at system reset or
RAM back-up mode.
4506 Group
Table 10 Timer control registers
Timer control register W1
W13
Prescaler control bit
W12
Prescaler dividing ratio selection bit
W11
Timer 1 control bit
W10
Timer 1 count start synchronous circuit
control bit
Timer 2 control bit
W22
Timer 1 count auto-stop circuit selection
bit (Note 2)
at reset : 00002
0
1
0
1
at RAM back-up : state retained
Timer 2 count source selection bits
W20
0
0
1
1
0
1
0
1
Timer control register W6
W63
Not used
W62
Not used
W61
CNTR output selection bit
W60
P12/CNTR function selection bit
R/W
Stop (state retained)
Operating
Count auto-stop circuit not selected
Count auto-stop circuit selected
W21 W20
W21
R/W
Stop (state initialized)
Operating
Instruction clock divided by 4
Instruction clock divided by 16
Stop (state retained)
Operating
Count start synchronous circuit not selected
Count start synchronous circuit selected
0
1
0
1
0
1
0
1
Timer control register W2
W23
at RAM back-up : 00002
at reset : 00002
Count source
Timer 1 underflow signal
Prescaler output (ORCLK)
CNTR input
System clock
at reset : 00002
0
1
0
1
0
1
0
1
at RAM back-up : state retained
R/W
This bit has no function, but read/write is enabled.
This bit has no function, but read/write is enabled.
Timer 1 underflow signal divided by 2 output
Timer 2 underflow signal divided by 2 output
P12(I/O)/CNTR input (Note 3)
P12 (input)/CNTR input/output (Note 3)
Notes 1: “R” represents read enabled, and “W” represents write enabled.
2: This function is valid only when the timer 1 count start synchronization circuit is selected.
3: CNTR input is valid only when CNTR input is selected as the timer 2 count source.
(1) Timer control registers
• Timer control register W1
Register W1 controls the count operation of timer 1, the selection
of count start synchronous circuit, and the frequency dividing ratio and count operation of prescaler. Set the contents of this
register through register A with the TW1A instruction. The TAW1
instruction can be used to transfer the contents of register W1 to
register A.
• Timer control register W2
Register W2 controls the selection of timer 1 count auto-stop circuit, and the count operation and count source of timer 2. Set the
contents of this register through register A with the TW2A instruction. The TAW2 instruction can be used to transfer the contents
of register W2 to register A.
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• Timer control register W6
Register W6 controls the P12/CNTR pin function and the selection of CNTR output. Set the contents of this register through
register A with the TW6A instruction. The TAW6 instruction can
be used to transfer the contents of register W6 to register A..
(2) Prescaler
Prescaler is a frequency divider. Its frequency dividing ratio can be
selected. The count source of prescaler is the instruction clock.
Use the bit 2 of register W1 to select the prescaler dividing ratio
and the bit 3 to start and stop its operation. Prescaler is initialized,
and the output signal (ORCLK) stops when the bit 3 of register W1
is cleared to “0.”
4506 Group
(3) Timer 1 (interrupt function)
(6) Count start synchronization circuit (timer 1)
Timer 1 is an 8-bit binary down counter with the timer 1 reload register (R1). Data can be set simultaneously in timer 1 and the reload
register (R1) with the T1AB instruction. Stop counting and then execute the T1AB instruction to set data to timer 1. Data can be
written to reload register (R1) with the TR1AB instruction.
When writing data to reload register R1 with the TR1AB instruction,
the downcount after the underflow is started from the setting value
of reload register R1.
Timer 1 starts counting after the following process;
➀ set data in timer 1, and
➁ set the bit 1 of register W1 to “1.”
However, INT pin input can be used as the start trigger for timer 1
count operation by setting the bit 0 of register W1 to “1.”
Also, in this time, the auto-stop function by timer 1 underflow can
be performed by setting the bit 2 of register W2 to “1.”
When a value set is n, timer 1 divides the count source signal by n
+ 1 (n = 0 to 255).
Once count is started, when timer 1 underflows (the next count
pulse is input after the contents of timer 1 becomes “0”), the timer
1 interrupt request flag (T1F) is set to “1,” new data is loaded from
reload register R1, and count continues (auto-reload function).
Data can be read from timer 1 with the TAB1 instruction. When
reading the data, stop the counter and then execute the TAB1 instruction.
Timer 1 has the count start synchronous circuit which synchronizes
the input of INT pin, and can start the timer count operation.
Timer 1 count start synchronous circuit function is selected by setting the bit 0 of register W1 to “1.” The control by INT pin input can
be performed by setting the bit 0 of register I1 to “1.”
The count start synchronous circuit is set by level change (“H”→“L”
or “L”→“H”) of INT pin input. This valid waveform is selected by bits
1 (I11) and 2 (I12) of register I1 as follows;
• I11 = “0”: Synchronized with one-sided edge (falling or rising)
• I11 = “1”: Synchronized with both edges (both falling and rising)
When register I11=“0” (synchronized with the one-sided edge), the rising or falling waveform can be selected by the bit 2 of register I1;
• I12 = “0”: Falling waveform
• I12 = “1”: Rising waveform
When timer 1 count start synchronous circuit is used, the count
start synchronous circuit is set, the count source is input to each
timer by inputting valid waveform to INT pin. Once set, the count
start synchronous circuit is cleared by clearing the bit I10 to “0” or
reset.
However, when the count auto-stop circuit is selected (register W22
= “1”), the count start synchronous circuit is cleared (auto-stop) at
the timer 1 underflow.
(7) Count auto-stop circuit (timer 1)
(4) Timer 2 (interrupt function)
Timer 2 is an 8-bit binary down counter with the timer 2 reload register (R2). Data can be set simultaneously in timer 2 and the reload
register (R2) with the T2AB instruction. Stop counting and then execute the T2AB instruction to set data to timer 2.
Timer 2 starts counting after the following process;
➀ set data in timer 2,
➁ select the count source with the bits 0 and 1 of register W2, and
➂ set the bit 3 of register W2 to “1.”
When a value set is n, timer 2 divides the count source signal by n
+ 1 (n = 0 to 255).
Once count is started, when timer 2 underflows (the next count
pulse is input after the contents of timer 2 becomes “0”), the timer
2 interrupt request flag (T2F) is set to “1,” new data is loaded from
reload register R2, and count continues (auto-reload function).
Data can be read from timer 2 with the TAB2 instruction. When
reading the data, stop the counter and then execute the TAB2 instruction.
(5) Timer interrupt request flags (T1F, T2F)
Each timer interrupt request flag is set to “1” when each timer
underflows. The state of these flags can be examined with the skip
instructions (SNZT1, SNZT2).
Use the interrupt control register V1 to select an interrupt or a skip
instruction.
An interrupt request flag is cleared to “0” when an interrupt occurs
or when the next instruction is skipped with a skip instruction.
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Timer 1 has the count auto-stop circuit which is used to stop timer
1 automatically by the timer 1 underflow when the count start synchronous circuit is used.
The count auto-stop cicuit is valid by setting the bit 2 of register W2
to “1”. It is cleared by the timer 1 underflow and the count source to
timer 1 is stopped.
This function is valid only when the timer 1 count start synchronous
circuit is selected.
4506 Group
(8) Timer input/output pin (P12/CNTR pin)
(9) Precautions
CNTR pin is used to input the timer 2 count source and output the
timer 1 and timer 2 underflow signal divided by 2.
The P1 2/CNTR pin function can be selected by bit 0 of register
W6. The CNTR output signal can be selected by bit 1 of register
W6.
When the CNTR input is selected for timer 2 count source, timer 2
counts the falling waveform of CNTR input.
Note the following for the use of timers.
•Prescaler
Stop the prescaler operation to change its frequency dividing ratio.
•Count source
Stop timer 1 or 2 counting to change its count source.
•Reading the count value
Stop timer 1 or 2 counting and then execute the TAB1 or TAB2 instruction to read its data.
•Writing to the timer
Stop timer 1 or 2 counting and then execute the T1AB or T2AB instruction to write its data.
•Writing to reload register R1
When writing data to reload register R1 while timer 1 is operating,
avoid a timing when timer 1 underflows.
CNTR input
(Note)
Timer 2 count
0316
Timer 2 interrupt
request flag
(T2F)
0216
0116
0016
FF16
FE16
Note: This is an example when “FF16” is set to timer 2 reload register R2L.
Fig. 23 Count timing diagram at CNTR input
• Timer 1 and timer 2 count start timing and count time when operation starts
Count starts from the first rising edge of the count source (2) after timer 1 and timer 2 operations start (1).
Time to first underflow (3) is shorter (for up to 1 period of the
count source) than time among next underflow (4) by the timing
to start the timer and count source operations after count starts.
When selecting CNTR input as the count source of timer 2, timer
2 operates synchronizing with the falling edge of CNTR input.
(2)
Count Source
Count Source
(CNTR input)
Timer Value
3
2
1
0
3
2
1
0
3
2
Timer Underflow
Signal
(3)
(4)
(1) Timer
Fig. 24 Timer count start timing and count time when operation starts (T1, T2)
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4506 Group
WATCHDOG TIMER
Watchdog timer provides a method to reset the system when a program run-away occurs. Watchdog timer consists of timer
WDT(16-bit binary counter), watchdog timer enable flag (WEF),
and watchdog timer flags (WDF1, WDF2).
The timer WDT downcounts the instruction clocks as the count
source from “FFFF16” after system is released from reset.
After the count is started, when the timer WDT underflow occurs
(after the count value of timer WDT reaches “FFFF16,” the next
count pulse is input), the WDF1 flag is set to “1.”
If the WRST instruction is never executed until the timer WDT underflow occurs (until timer WDT counts 65534), WDF2 flag is set to
“1,” and the RESET pin outputs “L” level to reset the microcomputer.
Execute the WRST instruction at each period of 65534 machine
cycle or less by software when using watchdog timer to keep the
microcomputer operating normally.
When the WEF flag is set to “1” after system is released from reset,
the watchdog timer function is valid.
When the DWDT instruction and the WRST instruction are executed continuously, the WEF flag is cleared to “0” and the
watchdog timer function is invalid.
The WEF flag is set to "1" at system reset or RAM back-up mode.
The WRST instruction has the skip function. When the WRST instruction is executed while the WDF1 flag is “1”, the WDF1 flag is
cleared to “0” and the next instruction is skipped.
When the WRST instruction is executed while the WDF1 flag is “0”,
the next instruction is not skipped.
The skip function of the WRST instruction can be used even when
the watchdog timer function is invalid.
FFFF 1 6
Value of 16-bit timer (WDT)
000016
➁
WDF1 flag
➁
65534 count
(Note)
➃
WDF2 flag
RESET pin output
➀ Reset
released
➂ WRST instruction
executed
(skip executed)
➄ System reset
➀ After system is released from reset (= after program is started), timer WDT starts count down.
➁ When timer WDT underflow occurs, WDF1 flag is set to “1.”
➂ When the WRST instruction is executed, WDF1 flag is cleared to “0,” the next instruction is skipped.
➃ When timer WDT underflow occurs while WDF1 flag is “1,” WDF2 flag is set to “1” and the
watchdog reset signal is output.
➄ The output transistor of RESET pin is turned “ON” by the watchdog reset signal and system reset is
executed.
Note: The number of count is equal to the number of machine cycle because the count source
of watchdog timer is the instruction clock.
Fig. 25 Watchdog timer function
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; WDF1 flag cleared
•••
WRST
; Watchdog timer function enabled/disabled
; WEF and WDF1 flags cleared
•••
DI
DWDT
WRST
•••
Fig. 26 Program example to start/stop watchdog timer
WRST
; WDF1 flag cleared
NOP
DI
; Interrupt disabled
EPOF
; POF instruction enabled
POF2
↓
Oscillation stop (RAM back-up mode)
•••
When the watchdog timer is used, clear the WDF1 flag at the period of 65534 machine cycles or less with the WRST instruction.
When the watchdog timer is not used, execute the DWDT instruction and the WRST instruction continuously (refer to Figure 26).
The watchdog timer is not stopped with only the DWDT instruction.
The contents of WDF1 flag and timer WDT are initialized at the
RAM back-up mode.
When using the watchdog timer and the RAM back-up mode, initialize the WDF1 flag with the WRST instruction just before the
microcomputer enters the RAM back-up state (refer to Figure 27)
The watchdog timer function is valid after system is returned from
the RAM back-up. When not using the watchdog timer function, execute the DWDT instruction and the WRST instruction continuously
every system is returned from the RAM back-up, and stop the
watchdog timer function.
•••
4506 Group
Fig. 27 Program example to enter the RAM back-up mode
when using the watchdog timer
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4506 Group
A/D CONVERTER
The 4506 Group has a built-in A/D conversion circuit that performs
conversion by 10-bit successive comparison method. Table 11
shows the characteristics of this A/D converter. This A/D converter
can also be used as an 8-bit comparator to compare analog voltages input from the analog input pin with preset values.
Table 11 A/D converter characteristics
Characteristics
Parameter
Successive comparison method
Conversion format
Resolution
Relative accuracy
10 bits
Linearity error: ±2LSB
Differential non-linearity error: ±0.9LSB
Conversion speed
Analog input pin
46.5 µs (High-speed mode at 4.0 MHz
oscillation frequency)
2
Register B (4)
Register A (4)
4
IAP2
(P20, P21)
TAQ1
TQ1A
OP2A
(P20, P21)
4
4
Q13 Q12 Q11 Q10
4
2
8
TALA
TABAD
8
TADAB
Instruction clock
1/6
2
Q13
0
P20/AIN0
P21/AIN1
2-channel multi-plexed analog switch
A/D control circuit
1
ADF
(1)
A/D
interrupt
1
Comparator
Successive comparison
register (AD) (10)
0
Q13
Q13
0
8
10
10
DAC
operation
signal
0
1
Q13
8
DAC
DA converter
8
(Note 1)
VDD
VSS
Comparator register (8)
(Note 2)
Notes 1: This switch is turned ON only when A/D converter is operating and generates the comparison voltage.
2: Writing/reading data to the comparator register is possible only in the comparator mode (Q13=1).
The value of the comparator register is retained even when the mode is switched to the A/D conversion
mode (Q13=0) because it is separated from the successive comparison register (AD). Also, the resolution
in the comparator mode is 8 bits because the comparator register consists of 8 bits.
Fig. 28 A/D conversion circuit structure
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1
1
8
4506 Group
Table 12 A/D control registers
A/D control register Q1
Q13
A/D operation mode selection bit
Q12
Not used
Q11
Analog input pin selection bits
Q10
at reset : 00002
0
1
0
1
Q11 Q10
0
0
0
1
1
0
1
1
at RAM back-up : state retained
R/W
A/D conversion mode
Comparator mode
This bit has no function, but read/write is enabled.
Selected pins
AIN0
AIN1
Not available
Not available
Note: “R” represents read enabled, and “W” represents write enabled.
(1) Operating at A/D conversion mode
(6) Operation description
The A/D conversion mode is set by setting the bit 3 of register Q1 to “0.”
A/D conversion is started with the A/D conversion start instruction
(ADST). The internal operation during A/D conversion is as follows:
(2) Successive comparison register AD
Register AD stores the A/D conversion result of an analog input in
10-bit digital data format. The contents of the high-order 8 bits of
this register can be stored in register B and register A with the
TABAD instruction. The contents of the low-order 2 bits of this register can be stored into the high-order 2 bits of register A with the
TALA instruction. However, do not execute these instructions during A/D conversion.
When the contents of register AD is n, the logic value of the comparison voltage V ref generated from the built-in DA converter can
be obtained with the reference voltage V DD by the following formula:
Logic value of comparison voltage Vref
Vref =
V DD
✕n
1024
n: The value of register AD (n = 0 to 1023)
(3) A/D conversion completion flag (ADF)
A/D conversion completion flag (ADF) is set to “1” when A/D conversion completes. The state of ADF flag can be examined with the
skip instruction (SNZAD). Use the interrupt control register V2 to
select the interrupt or the skip instruction.
The ADF flag is cleared to “0” when the interrupt occurs or when
the next instruction is skipped with the skip instruction.
(4) A/D conversion start instruction (ADST)
A/D conversion starts when the ADST instruction is executed. The
conversion result is automatically stored in the register AD.
(5) A/D control register Q1
Register Q1 is used to select the operation mode and one of analog input pins.
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➀ When the A/D conversion starts, the register AD is cleared to
“00016.”
➁ Next, the topmost bit of the register AD is set to “1,” and the
comparison voltage Vref is compared with the analog input voltage VIN.
➂ When the comparison result is Vref < VIN, the topmost bit of the
register AD remains set to “1.” When the comparison result is
Vref > VIN, it is cleared to “0.”
The 4506 Group repeats this operation to the lowermost bit of the
register AD to convert an analog value to a digital value. A/D conversion stops after 62 machine cycles (46.5 µs when f(X IN) = 4.0
MHz in high-speed mode) from the start, and the conversion result
is stored in the register AD. An A/D interrupt activated condition is
satisfied and the ADF flag is set to “1” as soon as A/D conversion
completes (Figure 29).
4506 Group
Table 13 Change of successive comparison register AD during A/D conversion
At starting conversion
Comparison voltage (Vref) value
Change of successive comparison register AD
VDD
-------------
1
1st comparison
0
0
-----
0
0
0
0
0
0
2
-------------------------
✼1
2nd comparison
1
✼1
3rd comparison
0
-----
-------------
VDD
-------------
✼2
1
-----
-------------
0
0
0
✼1: 1st comparison result
✼3: 3rd comparison result
✼9: 9th comparison result
✼2
✼3
-----
-------------
VDD
±
2
VDD
-------------
✼1
✼8
✼9
4
VDD
A/D conversion result
After 10th comparison
completes
VDD
±
2
✼A
±
VDD
±
4
○
○
2
○
○
±
8
VDD
1024
✼2: 2nd comparison result
✼8: 8th comparison result
✼A: 10th comparison result
(7) A/D conversion timing chart
Figure 29 shows the A/D conversion timing chart.
ADST instruction
62 machine cycles
A/D conversion
completion flag (ADF)
DAC operation signal
Fig. 29 A/D conversion timing chart
(8) How to use A/D conversion
How to use A/D conversion is explained using as example in which
the analog input from P21/AIN1 pin is A/D converted, and the highorder 4 bits of the converted data are stored in address M(Z, X, Y)
= (0, 0, 0), the middle-order 4 bits in address M(Z, X, Y) = (0, 0, 1),
and the low-order 2 bits in address M(Z, X, Y) = (0, 0, 2) of RAM.
The A/D interrupt is not used in this example.
➀ Select the AIN1 pin function and A/D conversion mode with the
register Q1 (refer to Figure 30).
➁ Execute the ADST instruction and start A/D conversion.
➂ Examine the state of ADF flag with the SNZAD instruction to determine the end of A/D conversion.
➃ Transfer the low-order 2 bits of converted data to the high-order
2 bits of register A (TALA instruction).
➄ Transfer the contents of register A to M (Z, X, Y) = (0, 0, 2).
➅ Transfer the high-order 8 bits of converted data to registers A
and B (TABAD instruction).
➆ Transfer the contents of register A to M (Z, X, Y) = (0, 0, 1).
➇ Transfer the contents of register B to register A, and then, store
into M(Z, X, Y) = (0, 0, 0).
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(Bit 3)
0
(Bit 0)
0
0
1
A/D control register Q1
A IN1 pin selected
A/D conversion mode
Fig. 30 Setting registers
4506 Group
(9) Operation at comparator mode
The A/D converter is set to comparator mode by setting bit 3 of the
register Q1 to “1.”
Below, the operation at comparator mode is described.
(10) Comparator register
In comparator mode, the built-in DA comparator is connected to the
8-bit comparator register as a register for setting comparison voltages. The contents of register B is stored in the high-order 4 bits of
the comparator register and the contents of register A is stored in
the low-order 4 bits of the comparator register with the TADAB instruction.
When changing from A/D conversion mode to comparator mode,
the result of A/D conversion (register AD) is undefined.
However, because the comparator register is separated from register AD, the value is retained even when changing from comparator
mode to A/D conversion mode. Note that the comparator register
can be written and read at only comparator mode.
If the value in the comparator register is n, the logic value of comparison voltage Vref generated by the built-in DA converter can be
determined from the following formula:
Logic value of comparison voltage Vref
Vref =
VDD
256
(12) Comparator operation start instruction
(ADST instruction)
In comparator mode, executing ADST starts the comparator operating.
The comparator stops 8 machine cycles after it has started (6 µs at
f(XIN) = 4.0 MHz in high-speed mode). When the analog input voltage is lower than the comparison voltage, the ADF flag is set to “1.”
(13) Notes for the use of A/D conversion 1
Note the following when using the analog input pins also for port
P2 function:
• Selection of analog input pins
Even when P20/AIN0, P21/AIN1 are set to pins for analog input,
they continue to function as port P2 input/output. Accordingly,
when any of them are used as I/O port and others are used as
analog input pins, make sure to set the outputs of pins that are
set for analog input to “1.” Also, the port input function of the pin
functions as an analog input is undefined.
• TALA instruction
When the TALA instruction is executed, the low-order 2 bits of
register AD is transferred to the high-order 2 bits of register A, simultaneously, the low-order 2 bits of register A is “0.”
(14) Notes for the use of A/D conversion 2
✕n
n: The value of register AD (n = 0 to 255)
(11) Comparison result store flag (ADF)
In comparator mode, the ADF flag, which shows completion of A/D
conversion, stores the results of comparing the analog input voltage with the comparison voltage. When the analog input voltage is
lower than the comparison voltage, the ADF flag is set to “1.” The
state of ADF flag can be examined with the skip instruction
(SNZAD). Use the interrupt control register V2 to select the interrupt or the skip instruction.
The ADF flag is cleared to “0” when the interrupt occurs or when
the next instruction is skipped with the skip instruction.
Do not change the operating mode (both A/D conversion mode and
comparator mode) of A/D converter with the bit 3 of register Q1
while the A/D converter is operating.
When the operating mode of A/D converter is changed from the
comparator mode to A/D conversion mode with the bit 3 of register
Q1, note the following;
• Clear the bit 2 of register V2 to “0” to change the operating mode
of the A/D converter from the comparator mode to A/D conversion mode with the bit 3 of register Q1.
• The A/D conversion completion flag (ADF) may be set when the
operating mode of the A/D converter is changed from the comparator mode to the A/D conversion mode. Accordingly, set a
value to the bit 3 of register Q1, and execute the SNZAD instruction to clear the ADF flag.
ADST instruction
8 machine cycles
Comparison result
store flag(ADF)
DAC operation signal
→
Comparator operation completed.
(The value of ADF is determined)
Fig. 31 Comparator operation timing chart
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4506 Group
(15) Definition of A/D converter accuracy
Vn: Analog input voltage when the output data changes from “n” to
“n+1” (n = 0 to 1022)
The A/D conversion accuracy is defined below (refer to Figure 32).
• 1LSB at relative accuracy →
• Relative accuracy
➀ Zero transition voltage (V0T)
This means an analog input voltage when the actual A/D conversion output data changes from “0” to “1.”
➁ Full-scale transition voltage (VFST)
This means an analog input voltage when the actual A/D conversion output data changes from “1023” to ”1022.”
➂ Linearity error
This means a deviation from the line between V0T and VFST of
a converted value between V0T and VFST.
➃ Differential non-linearity error
This means a deviation from the input potential difference required to change a converter value between V0T and VFST by 1
LSB at the relative accuracy.
VFST–V0T
(V)
1022
• 1LSB at absolute accuracy →
VDD
1024
(V)
• Absolute accuracy
This means a deviation from the ideal characteristics between 0
to VDD of actual A/D conversion characteristics.
Output data
Full-scale transition voltage (VFST)
1023
1022
Differential non-linearity error = b–a [LSB]
a
Linearity error = c [LSB]
a
b
a
n+1
n
Actual A/D conversion
characteristics
c
a: 1LSB by relative accuracy
b: Vn+1–Vn
c: Difference between ideal Vn
and actual Vn
Ideal line of A/D conversion
between V0–V1022
1
0
V0
V1
Zero transition voltage (V0T)
Fig. 32 Definition of A/D conversion accuracy
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Vn
Vn+1
V1022
VDD
Analog voltage
4506 Group
RESET FUNCTION
System reset is performed by applying “L” level to RESET pin for
1 machine cycle or more when the following condition is satisfied;
the value of supply voltage is the minimum value or more of the
recommended operating conditions.
Then when “H” level is applied to RESET pin, software starts from
address 0 in page 0.
f(XIN)
RESET
On-chip oscillator (internal oscillator)
Program starts
(address 0 in page 0)
is counted 5359 times.
Fig. 33 Reset release timing
=
Reset input
On-chip oscillator (internal oscillator) is
1 machine cycle or more
counted 5359 times.
0.85VDD
Program starts
(address 0 in page 0)
RESET
0.3VDD
(Note)
Note: Keep the value of supply voltage to the minimum value
or more of the recommended operating conditions.
Fig. 34 RESET pin input waveform and reset operation
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4506 Group
(1) Power-on reset
Reset can be performed automatically at power on (power-on reset) by connecting a diode and a capacitor to RESET pin. Connect
RESET pin and the external circuit at the shortest distance.
VDD
VDD
RESET pin voltage
Pull-up transistor
Internal reset
signal
RESET
pin
Reset
state
Watchdog timer
output
(Note 2)
(Note 1)
Internal reset signal
WEF
Reset released
Power-on
Notes 1:
This symbol represents a parasitic diode.
2: Applied potential to RESET pin must be VDD or less.
Fig. 35 Structure of reset pin and its peripherals, and power-on reset operation
Table 14 Port state at reset
Name
State
Function
D 0, D 1
D0, D1
High-impedance (Note 1)
D2/C, D3/K
D2, D3
High-impedance (Notes 1, 2)
P00, P01, P02, P03
P10, P11, P12/CNTR, P13/INT
P00–P03
P10–P13
High-impedance (Notes 1, 2)
High-impedance (Notes 1, 2)
P20/AIN0, P21/AIN1
P20, P21
High-impedance (Notes 1, 2)
Notes 1: Output latch is set to “1.”
2: Pull-up transistor is turned OFF.
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4506 Group
(2) Internal state at reset
Figure 36 shows internal state at reset (they are the same after system is released from reset). The contents of timers, registers, flags
and RAM except shown in Figure 36 are undefined, so set the initial value to them.
• Program counter (PC) ..........................................................................................................
0 0 0 0 0 0
Address 0 in page 0 is set to program counter.
0
• Interrupt enable flag (INTE) .................................................................................................. 0
(Interrupt disabled)
0
0
0
0
0
0
0
• Power down flag (P) ............................................................................................................. 0
• External 0 interrupt request flag (EXF0) .............................................................................. 0
• Interrupt control register V1 ..................................................................................................
0 0 0 0
• Interrupt control register V2 ..................................................................................................
0 0 0 0
• Interrupt control register I1 ...................................................................................................
0 0 0 0
(Interrupt disabled)
(Interrupt disabled)
• Timer 1 interrupt request flag (T1F) ..................................................................................... 0
• Timer 2 interrupt request flag (T2F) ..................................................................................... 0
• Watchdog timer flags (WDF1, WDF2) .................................................................................. 0
• Watchdog timer enable flag (WEF) ...................................................................................... 1
• Timer control register W1 .....................................................................................................
0 0 0 0
• Timer control register W2 .....................................................................................................
0 0 0 0
(Prescaler and timer 1 stopped)
(Timer 2 stopped)
• Timer control register W6 .....................................................................................................
0 0 0 0
• Clock control register MR .....................................................................................................
1 1 0 0
• Key-on wakeup control register K0 ......................................................................................
0 0 0 0
• Key-on wakeup control register K1 ......................................................................................
0 0 0 0
• Key-on wakeup control register K2 ......................................................................................
0 0 0 0
• Pull-up control register PU0 .................................................................................................
0 0 0 0
• Pull-up control register PU1 .................................................................................................
0 0 0 0
• Pull-up control register PU2 .................................................................................................
0 0 0 0
• A/D conversion completion flag (ADF) ................................................................................. 0
• A/D control register Q1 .........................................................................................................
0 0 0 0
• Carry flag (CY) ...................................................................................................................... 0
• Register A .............................................................................................................................
0 0 0 0
• Register B .............................................................................................................................
0 0 0 0
• Register D .............................................................................................................................
✕ ✕ ✕
• Register E .............................................................................................................................
✕ ✕ ✕ ✕ ✕ ✕ ✕ ✕
• Register X .............................................................................................................................
0 0 0 0
• Register Y .............................................................................................................................
0 0 0 0
• Register Z .............................................................................................................................
✕ ✕
• Stack pointer (SP) ................................................................................................................
1 1 1
• Oscillation clock ..................................................................... On-chip oscillator (operating)
• Ceramic resonator circuit ..................................................................................... Operating
• RC oscillation circuit ...................................................................................................... Stop
“✕” represents undefined.
Fig. 36 Internal state at reset
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4506 Group
RAM BACK-UP MODE
Table 15 Functions and states retained at RAM back-up
The 4506 Group has the RAM back-up mode.
When the POF2 instruction is executed continuously after the
EPOF instruction, system enters the RAM back-up state.
The POF2 instruction is equal to the NOP instruction when the
EPOF instruction is not executed before the POF2 instruction.
As oscillation stops retaining RAM, the function of reset circuit and
states at RAM back-up mode, current dissipation can be reduced
without losing the contents of RAM.
Table 15 shows the function and states retained at RAM back-up.
Figure 36 shows the state transition.
Function
Program counter (PC), registers A, B,
carry flag (CY), stack pointer (SP) (Note 2)
Interrupt control registers V1, V2
✕
(1) Identification of the start condition
Interrupt control register I1
O
Warm start (return from the RAM back-up state) or cold start (return from the normal reset state) can be identified by examining the
state of the power down flag (P) with the SNZP instruction.
Timer 1 function
✕
Timer 2 function
(Note 3)
✕
(2) Warm start condition
Pull-up control registers PU0 to PU2
O
When the external wakeup signal is input after the system enters
the RAM back-up state by executing the EPOF instruction and
POF2 instruction continuously, the CPU starts executing the program from address 0 in page 0. In this case, the P flag is “1.”
Key-on wakeup control registers K0 to K2
O
External 0 interrupt request flag (EXF0)
✕
(3) Cold start condition
The CPU starts executing the program from address 0 in page 0
when;
• reset pulse is input to RESET pin, or
• reset by watchdog timer is performed, or
In this case, the P flag is “0.”
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Contents of RAM
Port level
RAM back-up
✕
O
(Note 5)
Selected oscillation circuit
O
Timer control register W1
✕
O
Timer control registers W2, W6
Clock control register MR
A/D conversion function
A/D control register Q1
Timer 1 interrupt request flag (T1F)
Timer 2 interrupt request flag (T2F)
Watchdog timer flags (WDF1)
Watchdog timer enable flag (WEF)
16-bit timer (WDT)
✕
O
✕
(Note 3)
✕ (Note 4)
✕
✕ (Note 4)
A/D conversion completion flag (ADF)
✕
Interrupt enable flag (INTE)
✕
Notes 1: “O” represents that the function can be retained, and “✕” represents that the function is initialized.
Registers and flags other than the above are undefined at RAM
back-up, and set an initial value after returning.
2: The stack pointer (SP) points the level of the stack register and is
initialized to “7” at RAM back-up.
3: The state of the timer is undefined.
4: Initialize the watchdog timer flag WDF1 with the WRST instruction,
and then execute the POF2 instruction.
5: As for the D2 /C pin, the output latch of port C is set to “1” at the
RAM back-up. However, the output latch of port D2 is retained.
As for the other ports, their output levels are retained at the RAM
back-up.
4506 Group
(4) Return signal
An external wakeup signal is used to return from the RAM back-up
mode because the oscillation is stopped. Table 16 shows the return
condition for each return source.
(5) Control registers
• Key-on wakeup control register K0
Register K0 controls the port P0 key-on wakeup function. Set the
contents of this register through register A with the TK0A instruction. In addition, the TAK0 instruction can be used to transfer the
contents of register K0 to register A.
• Key-on wakeup control register K1
Register K1 controls the port P1 key-on wakeup function. Set the
contents of this register through register A with the TK1A instruction. In addition, the TAK1 instruction can be used to transfer the
contents of register K0 to register A.
• Key-on wakeup control register K2
Register K2 controls the ports P2, D2/C and D3/K key-on wakeup
function. Set the contents of this register through register A with
the TK2A instruction. In addition, the TAK2 instruction can be
used to transfer the contents of register K2 to register A.
External wakeup signal
Table 16 Return source and return condition
Return source
Return condition
Port P0
Return by an external “L” level input.
Port P1 (Note)
Port P2
Ports D2/C, D3/K
Port P13/INT
(Note)
Return by an external “H” level or
“L” level input. The return level
can be selected with the bit 2
(I12) of register I1.
When the return level is input, the
EXF0 flag is not set.
• Pull-up control register PU0
Register PU0 controls the ON/OFF of the port P0 pull-up transistor. Set the contents of this register through register A with the
TPU0A instruction.
• Pull-up control register PU1
Register PU1 controls the ON/OFF of the port P1 pull-up transistor. Set the contents of this register through register A with the
TPU1A instruction.
• Pull-up control register PU2
Register PU2 controls the ON/OFF of the ports P2, D2/C and D3/
K pull-up transistor. Set the contents of this register through register A with the TPU2A instruction.
• Interrupt control register I1
Register I1 controls the valid waveform of the external 0 interrupt, the input control of INT pin and the return input level. Set
the contents of this register through register A with the TI1A instruction. In addition, the TAI1 instruction can be used to transfer
the contents of register I1 to register A.
Remarks
The key-on wakeup function can be selected by one port unit. Set the port
using the key-on wakeup function to “H” level before going into the RAM
back-up state.
Select the return level (“L” level or “H” level) with the bit 2 of register I1 according to the external state before going into the RAM back-up state.
Note: When the bit 3 (K1 3) of register K1 is “0”, the key-on wakeup of the INT pin is valid (“H” or “L” level).
It is “1”, the key-on wakeup of port P13 is valid (“L” level).
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4506 Group
B
Operating
E
POF2 instruction execution
RAM back-up
Operation source clock:
ceramic resonator
Key-on wakeup
On-chip oscillator: stop
RC oscillation circuit: stop
(All functions of
microcomputer stop)
(Stabilizing time b )
CMCK instruction
execution (Note 3)
A
Operating
Reset
(Stabilizing
time a )
POF2 instruction execution
Operation source clock:
on-chip oscillator clock
Ceramic resonator:
operating (Note 2)
RC oscillation circuit: stop
Key-on wakeup
(Stabilizing time a )
CRCK instruction
execution (Note 3)
C
Operating
POF2 instruction execution
Operation source clock:
RC oscillation
On-chip oscillator: stop
Ceramic resonator: stop
Key-on wakeup
(Stabilizing time c )
Operation source clock: stop
Stabilizing time a : Microcomputer starts its operation after counting the on-chip oscillator clock 5359 times by hardware.
Stabilizing time b : Microcomputer starts its operation after counting the f(XIN) 5359 times by hardware.
Stabilizing time c : Microcomputer starts its operation after counting the f(XIN) 165 times by hardware.
Notes 1: Continuous execution of the EPOF instruction and POF2 instruction is required to go into the RAM back-up state.
2: Through the ceramic resonator is operating, the on-chip oscillator clock is selected as the operation source clock.
3: The oscillator clock corresponding to each instruction is selected as the operation source clock,
and the on-chip oscillator is stopped.
Fig. 37 State transition
Power down flag P
EPOF
+ POF2
instruction instruction
S
R
Reset input
● Set source
Q
•••••••
EPOF instruction + POF2 instruction
● Clear source • • • • • • Reset input
Fig. 38 Set source and clear source of the P flag
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Program start
P = “1”
?
No
Cold start
Yes
Warm start
Fig. 39 Start condition identified example using the SNZP instruction
4506 Group
Table 17 Key-on wakeup control register
at reset : 00002
Key-on wakeup control register K0
K03
K02
K01
K00
Port P03 key-on wakeup
0
1
Key-on wakeup not used
control bit
Port P02 key-on wakeup
0
control bit
1
Key-on wakeup not used
Key-on wakeup used
Port P01 key-on wakeup
control bit
0
Key-on wakeup not used
1
Key-on wakeup used
Port P00 key-on wakeup
0
1
Key-on wakeup not used
control bit
Key-on wakeup control register K1
K13
K12
K11
K10
K22
K21
K20
Key-on wakeup used
at RAM back-up : state retained
Port P13/INT key-on wakeup
0
P13 key-on wakeup not used/INT pin key-on wakeup used
control bit
Port P12/CNTR key-on wakeup
1
P13 key-on wakeup used/INT pin key-on wakeup not used
0
Key-on wakeup not used
control bit
1
Key-on wakeup used
Port P11 key-on wakeup
Key-on wakeup not used
control bit
0
1
Port P10 key-on wakeup
0
Key-on wakeup used
Key-on wakeup not used
control bit
1
Key-on wakeup used
at reset : 00002
at RAM back-up : state retained
Port D3/K key-on wakeup
control bit
0
Key-on wakeup not used
1
Key-on wakeup used
Port D2/C key-on wakeup
0
Key-on wakeup not used
control bit
Key-on wakeup used
Port P21/AIN1 key-on wakeup
1
0
control bit
1
Key-on wakeup not used
Key-on wakeup used
Port P20/AIN0 key-on wakeup
control bit
0
Key-on wakeup not used
1
Key-on wakeup used
Note: “R” represents read enabled, and “W” represents write enabled.
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R/W
Key-on wakeup used
at reset : 00002
Key-on wakeup control register K2
K23
at RAM back-up : state retained
R/W
R/W
4506 Group
Table 18 Pull-up control register and interrupt control register
at reset : 00002
Pull-up control register PU0
PU03
PU02
PU01
PU00
Port P03 pull-up transistor
0
Pull-up transistor OFF
control bit
1
Pull-up transistor ON
Port P02 pull-up transistor
0
control bit
1
Pull-up transistor OFF
Pull-up transistor ON
Port P01 pull-up transistor
0
1
Pull-up transistor OFF
control bit
Port P00 pull-up transistor
0
Pull-up transistor OFF
control bit
1
Pull-up transistor ON
Pull-up control register PU1
PU13
PU12
PU11
PU10
at reset : 00002
0
Pull-up transistor OFF
control bit
1
0
Pull-up transistor ON
control bit
Port P11 pull-up transistor
1
Pull-up transistor ON
0
Pull-up transistor OFF
control bit
1
Port P10 pull-up transistor
0
Pull-up transistor ON
Pull-up transistor OFF
control bit
1
Pull-up transistor ON
PU23
PU22
PU21
PU20
Port D3/K pull-up transistor
0
control bit
1
Port D2/C pull-up transistor
0
1
Pull-up transistor OFF
Port P21/AIN1 pull-up transistor
control bit
0
Pull-up transistor OFF
1
Pull-up transistor ON
Port P20/AIN0 pull-up transistor
0
control bit
1
Pull-up transistor OFF
Pull-up transistor ON
control bit
Interrupt control register I1
I13
I12
I11
I10
INT pin input control bit (Note 2)
Interrupt valid waveform for INT pin/
return level selection bit (Note 2)
INT pin edge detection circuit control bit
INT pin
timer 1 control enable bit
0
1
0
1
0
1
W
at RAM back-up : state retained
W
Pull-up transistor OFF
Pull-up transistor ON
Pull-up transistor ON
at reset : 00002
0
1
at RAM back-up : state retained
Pull-up transistor OFF
at reset : 00002
Pull-up control register PU2
W
Pull-up transistor ON
Port P13/INT pull-up transistor
Port P12/CNTR pull-up transistor
at RAM back-up : state retained
at RAM back-up : state retained
R/W
INT pin input disabled
INT pin input enabled
Falling waveform (“L” level of INT pin is recognized with the SNZI0
instruction)/“L” level
Rising waveform (“H” level of INT pin is recognized with the SNZI0
instruction)/“H” level
One-sided edge detected
Both edges detected
Disabled
Enabled
Notes 1: “R” represents read enabled, and “W” represents write enabled.
2: When the contents of I12 and I13 are changed, the external interrupt request flag EXF0 may be set. Accordingly, clear EXF0 flag with the SNZ0 instruction when the bit 0 (V10 ) of register V1 to “0”. In this time, set the NOP instruction after the SNZ0 instruction, for the case when a skip is
performed with the SNZ0 instruction.
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4506 Group
CLOCK CONTROL
The system clock and the instruction clock are generated as the
source clock for operation by these circuits.
Figure 40 shows the structure of the clock control circuit.
The 4506 Group operates by the on-chip oscillator clock (f(RING))
which is the internal oscillator after system is released from reset.
Also, the ceramic resonator or the RC oscillation can be used for
the source oscillation (f(X IN)) of the 4506 Group. The CMCK instruction or CRCK instruction is executed to select the ceramic
resonator or RC oscillator, respectively.
The clock control circuit consists of the following circuits.
• On-chip oscillator (internal oscillator)
• Ceramic resonator
• RC oscillation circuit
• Multi-plexer (clock selection circuit)
• Frequency divider
• Internal clock generating circuit
Division circuit
divided by 8
divided by 4
On-chip oscillator
(internal oscillator)
(Note 1)
divided by 2
Multiplexer
MR3, MR2
11
10
01
00
System clock
Internal clock
generation circuit
(divided by 3)
Instruction clock
Counter
Q S
Q R
Wait time (Note 2)
control circuit
RC oscillation circuit
Q S
CRCK instruction
R
XIN
XOUT
Ceramic resonator
circuit
Q S
R
Q S
R
CMCK
instruction
RESET pin
Key-on wakeup signal
EPOF instruction + POF2 instruction
Notes 1: System operates by the on-chip oscillator clock (f(RING)) until the CMCK or CRCK instruction
is executed after system is released from reset.
2: The wait time control circuit is used to generate the time required to stabilize the f(XIN) oscillation.
After the certain oscillation stabilizing wait time elapses, the program start signal is output.
This circuit operates when system is released from reset or returned from RAM back-up.
Fig. 40 Clock control circuit structure
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Program
start signal
4506 Group
(1) Selection of source oscillation (f(XIN))
The ceramic resonator or RC oscillation can be used for the source
oscillation of the MCU.
After system is released from reset, the MCU starts operation by
the clock output from the on-chip oscillator which is the internal oscillator.
When the ceramic resonator is used, execute the CMCK instruction. When the RC oscillation is used, execute the CRCK
instruction. The oscillation circuit by the CMCK or CRCK instruction
can be selected only at once. The oscillation circuit corresponding
to the first executed one of these two instructions is valid. Other oscillation circuit and the on-chip oscillator stop.
Execute the CMCK or the CRCK instruction in the initial setting routine of program (executing it in address 0 in page 0 is
recommended). Also, when the CMCK or the CRCK instruction is
not executed in program, the MCU operates by the on-chip oscillator.
Reset
On-chip oscillator
operation
CMCK instruction
• Ceramic resonator valid • RC oscillation valid
• On-chip oscillator stop
• On-chip oscillator stop
• Ceramic resonator stop
• RC oscillation stop
Fig. 41 Switch to ceramic resonance/RC oscillation
4506
not use the CMCK instruction
* Do
and CRCK instruction in program.
(2) On-chip oscillator operation
When the MCU operates by the on-chip oscillator as the source oscillation (f(X IN)) without using the ceramic resonator or the RC
oscillator, connect XIN pin to VSS and leave XOUT pin open (Figure
42).
The clock frequency of the on-chip oscillator depends on the supply
voltage and the operation temperature range.
Be careful that variable frequencies when designing application
products.
XIN
XOUT
Fig. 42 Handling of XIN and XOUT when operating on-chip oscillator
4506
(3) Ceramic resonator
When the ceramic resonator is used as the source oscillation
(f(XIN)), connect the ceramic resonator and the external circuit to
pins XIN and XOUT at the shortest distance. Then, execute the
CMCK instruction. A feedback resistor is built in between pins XIN
and XOUT (Figure 43).
XIN
the CMCK instruc* Execute
tion in program.
XOUT
Note: Externally connect a damping
resistor Rd depending on the
oscillation frequency.
Rd
(A feedback resistor is built-in.)
Use the resonator manufacturer’s recommended value
COUT
because constants such as capacitance depend on the
resonator.
CIN
(4) RC oscillation
When the RC oscillation is used as the source oscillation (f(XIN)),
connect the XIN pin to the external circuit of resistor R and the capacitor C at the shortest distance and leave XOUT pin open. Then,
execute the CRCK instruction (Figure 44).
The frequency is affected by a capacitor, a resistor and a microcomputer. So, set the constants within the range of the frequency
limits.
CRCK instruction
Fig. 43 Ceramic resonator external circuit
4506
R
XIN
XOUT
* EinxsetrcuuctteiotnheinCpRroCgKram.
C
Fig. 44 External RC oscillation circuit
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4506 Group
(5) External clock
When the external signal clock is used as the source oscillation
(f(XIN)), connect the XIN pin to the clock source and leave XOUT pin
open. Then, execute the CMCK instruction (Figure 45).
Be careful that the maximum value of the oscillation frequency
when using the external clock differs from the value when using the
ceramic resonator (refer to the recommended operating condition).
Also, note that the RAM back-up mode (POF2 instruction) cannot
be used when using the external clock.
* EinxsetrcuuctteiotnheinCpMroCgKram.
4506
XIN
XOUT
VD D
VSS
External oscillation circuit
(6) Clock control register MR
Register MR controls system clock. Set the contents of this register
through register A with the TMRA instruction. In addition, the TAMR
instruction can be used to transfer the contents of register MR to
register A.
Fig. 45 External clock input circuit
Table 19 Clock control register MR
at reset : 11002
Clock control register MR
MR3
System clock selection bits
MR2
MR1
Not used
MR0
Not used
MR3 MR2
0
0
0
1
1
0
1
1
System clock
f(XIN) (high-speed mode)
f(XIN)/2 (middle-speed mode)
f(XIN)/4 (low-speed mode)
f(XIN)/8 (default mode)
0
1
This bit has no function, but read/write is enabled.
0
1
Note : “R” represents read enabled, and “W” represents write enabled.
ROM ORDERING METHOD
Please submit the information described below when ordering
Mask ROM.
(1) Mask ROM Order Confirmation Form ..................................... 1
(2) Data to be written into mask ROM ............................... EPROM
(three sets containing the identical data)
(3) Mark Specification Form .......................................................... 1
✽For the mask ROM confirmation and the mark specifications,
refer to the “Renesas Technology Corp.” Homepage
(http://www.renesas.com/en/rom).
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at RAM back-up : 11002
page 46 of 111
This bit has no function, but read/write is enabled.
R/W
4506 Group
LIST OF PRECAUTIONS
Timer 1 and timer 2 count start timing and count time when
operation starts
Count starts from the first rising edge of the count source (2) after timer 1 and timer 2 operations start (1).
Time to first underflow (3) is shorter (for up to 1 period of the
count source) than time among next underflow (4) by the timing
to start the timer and count source operations after count starts.
When selecting CNTR input as the count source of timer 2, timer
2 operates synchronizing with the falling edge of CNTR input.
10
➀ Noise and latch-up prevention
Connect a capacitor on the following condition to prevent noise
and latch-up;
• connect a bypass capacitor (approx. 0.1 µF) between pins VDD
and VSS at the shortest distance,
• equalize its wiring in width and length, and
• use relatively thick wire.
In the One Time PROM version, CNVSS pin is also used as VPP
pin. Accordingly, when using this pin, connect this pin to VSS
through a resistor about 5 kΩ (connect this resistor to CNVSS/
VPP pin as close as possible).
(2)
Count Source
➁ Register initial values 1
The initial value of the following registers are undefined after system is released from reset. After system is released from reset,
set initial values.
• Register Z (2 bits)
• Register D (3 bits)
• Register E (8 bits)
➂ Register initial values 2
The initial value of the following registers are undefined at RAM
back-up. After system is returned from RAM back-up, set initial
values.
• Register Z (2 bits)
• Register X (4 bits)
• Register Y (4 bits)
• Register D (3 bits)
• Register E (8 bits)
➃ Stack registers (SKS) and stack pointer (SP)
Stack registers (SKs) are eight identical registers, so that subroutines can be nested up to 8 levels. However, one of stack
registers is used respectively when using an interrupt service
routine and when executing a table reference instruction. Accordingly, be careful not to over the stack when performing these
operations together.
➄ Prescaler
Stop the prescaler operation to change its frequency dividing ratio.
➅Timer count source
Stop timer 1 or 2 counting to change its count source.
➆ Reading the count value
Stop timer 1 or 2 counting and then execute the TAB1 or TAB2
instruction to read its data.
➇ Writing to the timer
Stop timer 1 or 2 counting and then execute the T1AB or T2AB
instruction to write its data.
➈ Writing to reload register R1
When writing data to reload register R1 while timer 1 is operating, avoid a timing when timer 1 underflows.
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Count Source
(CNTR input)
Timer Value
3
2
1
0
3
2
1
0
3
2
Timer Underflow
Signal
(3)
(4)
(1) Timer
Fig. 46 Timer count start timing and count time when operation starts (T1, T2)
11
Watchdog timer
• The watchdog timer function is valid after system is released
from reset. When not using the watchdog timer function, execute
the DWDT instruction and the WRST instruction continuously,
and clear the WEF flag to “0” to stop the watchdog timer function.
• The watchdog timer function is valid after system is returned from
the RAM back-up. When not using the watchdog timer function,
execute the DWDT instruction and the WRST instruction continuously every system is returned from the RAM back-up, and stop
the watchdog timer function.
Multifunction
• The input/output of D2, D3, P12 and P13 can be used even when
C, K, CNTR (input) and INT are selected.
• The input of P12 can be used even when CNTR (output) is selected.
• The input/output of P20 and P21 can be used even when AIN0 and
AIN1 are selected.
12
13
Program counter
Make sure that the PCH does not specify after the last page of
the built-in ROM.
14
POF2 instruction
When the POF2 instruction is executed continuously after the
EPOF instruction, system enters the RAM back-up state.
Note that system cannot enter the RAM back-up state when executing only the POF2 instruction.
Be sure to disable interrupts by executing the DI instruction before executing the EPOF instruction and the POF2 instruction
continuously.
4506 Group
P13/INT pin
Note [1] on bit 3 of register I1
When the input of the INT pin is controlled with the bit 3 of register I1 in software, be careful about the following notes.
Note [3] on bit 2 of register I1
When the interrupt valid waveform of the P13/INT pin is changed
with the bit 2 of register I1 in software, be careful about the following notes.
• Depending on the input state of the P13/INT pin, the external 0 interrupt request flag (EXF0) may be set when the bit 3 of register
I1 is changed. In order to avoid the occurrence of an unexpected
interrupt, clear the bit 0 of register V1 to “0” (refer to Figure 47➀)
and then, change the bit 3 of register I1.
In addition, execute the SNZ0 instruction to clear the EXF0 flag to
“0” after executing at least one instruction (refer to Figure 47➁).
Also, set the NOP instruction for the case when a skip is performed with the SNZ0 instruction (refer to Figure 47➂).
• Depending on the input state of the P13/INT pin, the external 0 interrupt request flag (EXF0) may be set when the bit 2 of register
I1 is changed. In order to avoid the occurrence of an unexpected
interrupt, clear the bit 0 of register V1 to “0” (refer to Figure 49➀)
and then, change the bit 2 of register I1.
In addition, execute the SNZ0 instruction to clear the EXF0 flag to
“0” after executing at least one instruction (refer to Figure 49➁).
Also, set the NOP instruction for the case when a skip is performed with the SNZ0 instruction (refer to Figure 49➂).
•••
•••
15
•••
NOP
; (✕✕✕02)
; The SNZ0 instruction is valid ........... ➀
; (1✕✕✕2)
; Control of INT pin input is changed
........................................................... ➁
; The SNZ0 instruction is executed
(EXF0 flag cleared)
........................................................... ➂
✕ : these bits are not used here.
Fig. 47 External 0 interrupt program example-1
LA
4
TV1A
LA
12
TI1A
NOP
SNZ0
NOP
; (✕✕✕02)
; The SNZ0 instruction is valid ........... ➀
; (✕1✕✕2)
; Interrupt valid waveform is changed
........................................................... ➁
; The SNZ0 instruction is executed
(EXF0 flag cleared)
........................................................... ➂
•••
LA
4
TV1A
LA
8
TI1A
NOP
SNZ0
✕ : these bits are not used here.
Fig. 49 External 0 interrupt program example-3
Note [2] on bit 3 of register I1
When the bit 3 of register I1 is cleared to “0”, the RAM back-up
mode is selected and the input of INT pin is disabled, be careful
about the following notes.
•••
• When the key-on wakeup function of port P13 is not used (register K1 3 = “0”), clear bits 2 and 3 of register I1 before system
enters to the RAM back-up mode. (refer to Figure 48➀).
; (00✕✕2)
; Input of INT disabled ........................ ➀
; RAM back-up
•••
LA
0
TI1A
DI
EPOF
POF2
✕ : these bits are not used here.
Fig. 48 External 0 interrupt program example-2
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4506 Group
Notes for the use of A/D conversion 1
Note the following when using the analog input pins also for port
P2 function:
• Selection of analog input pins
Even when P20/AIN0 and P21/AIN1 are set to pins for analog input, they continue to function as port P2 input/output.
Accordingly, when any of them are used as I/O port and others
are used as analog input pins, make sure to set the outputs of
pins that are set for analog input to “1.” Also, the port input function of the pin functions as an analog input is undefined.
• TALA instruction
When the TALA instruction is executed, the low-order 2 bits of
register AD is transferred to the high-order 2 bits of register A, simultaneously, the low-order 2 bits of register A is “0.”
16
18
Notes for the use of A/D conversion 3
Each analog input pin is equipped with a capacitor which is used
to compare the analog voltage. Accordingly, when the analog
voltage is input from the circuit with high-impedance and, charge/
discharge noise is generated and the sufficient A/D accuracy
may not be obtained. Therefore, reduce the impedance or, connect a capacitor (0.01 µF to 1 µF) to analog input pins (Figure 51).
When the overvoltage applied to the A/D conversion circuit may
occur, connect an external circuit in order to keep the voltage
within the rated range as shown the Figure 52. In addition, test
the application products sufficiently.
Sensor
Notes for the use of A/D conversion 2
Do not change the operating mode (both A/D conversion mode
and comparator mode) of A/D converter with the bit 3 of register
Q1 while the A/D converter is operating.
When the operating mode of A/D converter is changed from the
comparator mode to A/D conversion mode with the bit 3 of register Q1, note the following;
• Clear the bit 2 of register V2 to “0” (refer to Figure 50➀) to
change the operating mode of the A/D converter from the comparator mode to A/D conversion mode with the bit 3 of register
Q1.
• The A/D conversion completion flag (ADF) may be set when the
operating mode of the A/D converter is changed from the comparator mode to the A/D conversion mode. Accordingly, set a
value to the bit 3 of register Q1, and execute the SNZAD instruction to clear the ADF flag.
AIN
17
Fig. 51 Analog input external circuit example-1
About 1kΩ
Sensor
AIN
Fig. 52 Analog input external circuit example-2
•••
LA
8
TV2A
LA
0
TQ1A
Apply the voltage withiin the specifications
to an analog input pin.
; (✕0✕✕2)
; The SNZAD instruction is valid ........ ➀
; (0✕✕✕2)
; Operation mode of A/D converter is
changed from comparator mode to A/D
conversion mode.
•••
SNZAD
NOP
✕ : this bit is not related to change the operation
mode of A/D converter.
Fig. 50 A/D conversion interrupt program example
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4506 Group
19
Clock control
Execute the CMCK or the CRCK instruction in the initial setting
routine of program (executing it in address 0 in page 0 is recommended).
The oscillation circuit by the CMCK or CRCK instruction can be
selected only at once. The oscillation circuit corresponding to the
first executed one of these two instruction is valid. Other oscillation circuits and the on-chip oscillator stop.
20
On-chip oscillator
The clock frequency of the on-chip oscillator depends on the supply voltage and the operation temperature range.
Be careful that variable frequencies when designing application
products.
Also, the oscillation stabilize wait time after system is released
from reset is generated by the on-chip oscillator clock. When
considering the oscillation stabilize wait time after system is released from reset, be careful that the variable frequency of the
on-chip oscillator clock.
21
External clock
When the external signal clock is used as the source oscillation
(f(X IN)), note that the RAM back-up mode (POF2 instructions)
cannot be used.
22
Electric Characteristic Differences Between Mask ROM and One
Time PROM Version MCU
There are differences in electric characteristics, operation margin,
noise immunity, and noise radiation between Mask ROM and One
Time PROM version MCUs due to the difference in the manufacturing processes.
When manufacturing an application system with the One time
PROM version and then switching to use of the Mask ROM version, please perform sufficient evaluations for the commercial
samples of the Mask ROM version.
23
Note on Power Source Voltage
When the power source voltage value of a microcomputer is less
than the value which is indicated as the recommended operating
conditions, the microcomputer does not operate normally and
may perform unstable operation.
In a system where the power source voltage drops slowly when
the power source voltage drops or the power supply is turned off,
reset a microcomputer when the supply voltage is less than the
recommended operating conditions and design a system not to
cause errors to the system by this unstable operation.
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4506 Group
CONTROL REGISTERS
Interrupt control register V1
V13
Timer 2 interrupt enable bit
V12
Timer 1 interrupt enable bit
V11
Not used
V10
External 0 interrupt enable bit
at reset : 00002
0
1
0
1
0
1
0
1
Interrupt control register V2
V23
Not used
V22
A/D interrupt enable bit
V21
Not used
V20
Not used
I12
I11
I10
INT pin input control bit (Note 3)
Interrupt valid waveform for INT pin/
return level selection bit (Note 3)
INT pin edge detection circuit control bit
INT pin
timer 1 control enable bit
MR3
System clock selection bits
MR2
MR1
Not used
MR0
Not used
This bit has no function, but read/write is enabled.
Interrupt disabled (SNZ0 instruction is valid)
Interrupt enabled (SNZ0 instruction is invalid) (Note 2)
0
1
0
1
0
1
0
1
at RAM back-up : 00002
Interrupt disabled (SNZAD instruction is valid)
Interrupt enabled (SNZAD instruction is invalid) (Note 2)
This bit has no function, but read/write is enabled.
This bit has no function, but read/write is enabled.
0
1
at RAM back-up : state retained
R/W
INT pin input disabled
INT pin input enabled
Falling waveform (“L” level of INT pin is recognized with the SNZI0
instruction)/“L” level
Rising waveform (“H” level of INT pin is recognized with the SNZI0
0
1
instruction)/“H” level
0
1
0
1
One-sided edge detected
Both edges detected
Disabled
Enabled
at reset : 11002
MR3 MR2
0
0
0
1
1
0
1
1
0
1
R/W
This bit has no function, but read/write is enabled.
at reset : 00002
Clock control register MR
R/W
Interrupt disabled (SNZT2 instruction is valid)
Interrupt enabled (SNZT2 instruction is invalid) (Note 2)
Interrupt disabled (SNZT1 instruction is valid)
Interrupt enabled (SNZT1 instruction is invalid) (Note 2)
at reset : 00002
Interrupt control register I1
I13
at RAM back-up : 00002
at RAM back-up : 11002
R/W
System clock
f(XIN) (high-speed mode)
f(XIN)/2 (middle-speed mode)
f(XIN)/4 (low-speed mode)
f(XIN)/8 (default mode)
This bit has no function, but read/write is enabled.
0
1
This bit has no function, but read/write is enabled.
Notes 1: “R” represents read enabled, and “W” represents write enabled.
2: These instructions are equivalent to the NOP instruction.
3: When the contents of I12 and I13 are changed, the external interrupt request flag EXF0 may be set. Accordingly, clear EXF0 flag with the SNZ0 instruction when the bit 0 (V1 0) of register V1 to “0”. In this time, set the NOP instruction after the SNZ0 instruction, for the case when a skip is
performed with the SNZ0 instruction.
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4506 Group
Timer control register W1
W13
Prescaler control bit
W12
Prescaler dividing ratio selection bit
W11
Timer 1 control bit
W10
Timer 1 count start synchronous circuit
control bit
Timer 2 control bit
W22
Timer 1 count auto-stop circuit selection
bit (Note 2)
W21
Timer 2 count source selection bits
W20
at reset : 00002
Not used
W62
Not used
W61
CNTR output selection bit
W60
P12/CNTR function selection bit
A/D control register Q1
Q13
A/D operation mode selection bit
Q12
Not used
Q11
Analog input pin selection bits
Q10
page 52 of 111
R/W
Stop (state retained)
Operating
Count auto-stop circuit not selected
Count auto-stop circuit selected
W21 W20
Count source
0
Timer 1 underflow signal
0
0
Prescaler output (ORCLK)
1
1
CNTR input
0
1
System clock
1
at reset : 00002
0
1
0
1
0
1
0
1
at RAM back-up : state retained
R/W
This bit has no function, but read/write is enabled.
This bit has no function, but read/write is enabled.
Timer 1 underflow signal divided by 2 output
Timer 2 underflow signal divided by 2 output
P12(I/O)/CNTR input (Note 3)
P12 (input)/CNTR input/output (Note 3)
at reset : 00002
0
1
0
1
Q11 Q10
0
0
0
1
1
0
1
1
at RAM back-up : state retained
A/D conversion mode
Comparator mode
This bit has no function, but read/write is enabled.
Selected pins
AIN0
AIN1
Not available
Not available
Notes 1: “R” represents read enabled, and “W” represents write enabled.
2: This function is valid only when the timer 1 count start synchronization circuit is selected.
3: CNTR input is valid only when CNTR input is selected as the timer 2 count source.
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at RAM back-up : state retained
0
1
0
1
Timer control register W6
W63
R/W
Stop (state initialized)
Operating
Instruction clock divided by 4
Instruction clock divided by 16
Stop (state retained)
Operating
Count start synchronous circuit not selected
Count start synchronous circuit selected
0
1
0
1
0
1
0
1
Timer control register W2
W23
at RAM back-up : 00002
at reset : 00002
R/W
4506 Group
Key-on wakeup control register K0
K03
K02
K01
K00
Port P03 key-on wakeup
at reset : 00002
control bit
0
1
Port P02 key-on wakeup
0
Key-on wakeup used
Key-on wakeup not used
control bit
Port P01 key-on wakeup
1
Key-on wakeup used
0
Key-on wakeup not used
control bit
1
Key-on wakeup used
Port P00 key-on wakeup
0
1
Key-on wakeup not used
control bit
Key-on wakeup control register K1
K13
K12
K11
K10
K22
K21
K20
Key-on wakeup used
at RAM back-up : state retained
Port P13/INT key-on wakeup
0
P13 key-on wakeup not used/INT pin key-on wakeup used
control bit
Port P12/CNTR key-on wakeup
1
P13 key-on wakeup used/INT pin key-on wakeup not used
0
Key-on wakeup not used
control bit
Key-on wakeup used
Port P11 key-on wakeup
1
0
control bit
1
Port P10 key-on wakeup
0
Key-on wakeup used
Key-on wakeup not used
control bit
1
Key-on wakeup used
at RAM back-up : state retained
Port D3/K key-on wakeup
control bit
0
Key-on wakeup not used
1
Key-on wakeup used
Port D2/C key-on wakeup
Key-on wakeup not used
control bit
0
1
Port P21/AIN1 key-on wakeup
0
control bit
1
Key-on wakeup not used
Key-on wakeup used
Port P20/AIN0 key-on wakeup
0
Key-on wakeup not used
control bit
1
Key-on wakeup used
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R/W
Key-on wakeup not used
at reset : 00002
Note: “R” represents read enabled, and “W” represents write enabled.
R/W
Key-on wakeup not used
at reset : 00002
Key-on wakeup control register K2
K23
at RAM back-up : state retained
Key-on wakeup used
R/W
4506 Group
at reset : 00002
Pull-up control register PU0
PU03
PU02
PU01
PU00
Port P03 pull-up transistor
0
Pull-up transistor OFF
control bit
1
Port P02 pull-up transistor
0
Pull-up transistor ON
Pull-up transistor OFF
control bit
1
0
Pull-up transistor ON
control bit
Port P00 pull-up transistor
1
Pull-up transistor ON
0
Pull-up transistor OFF
control bit
1
Pull-up transistor ON
Port P01 pull-up transistor
Pull-up control register PU1
PU13
PU12
PU11
PU10
Port P13/INT pull-up transistor
at reset : 00002
Pull-up transistor OFF
Port P12/CNTR pull-up transistor
control bit
0
Pull-up transistor OFF
1
Pull-up transistor ON
Port P11 pull-up transistor
0
control bit
1
Pull-up transistor OFF
Pull-up transistor ON
Port P10 pull-up transistor
0
1
control bit
PU23
PU22
PU21
PU20
Port D3/K pull-up transistor
0
control bit
1
0
Port D2/C pull-up transistor
Pull-up transistor OFF
Pull-up transistor ON
Pull-up transistor OFF
Pull-up transistor ON
0
Pull-up transistor OFF
control bit
1
Port P20/AIN0 pull-up transistor
0
Pull-up transistor ON
Pull-up transistor OFF
control bit
1
Pull-up transistor ON
page 54 of 111
at RAM back-up : state retained
W
Pull-up transistor ON
1
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W
Pull-up transistor OFF
control bit
Port P21/AIN1 pull-up transistor
Notes 1: “R” represents read enabled, and “W” represents write enabled.
at RAM back-up : state retained
Pull-up transistor ON
at reset : 00002
Pull-up control register PU2
W
Pull-up transistor OFF
0
1
control bit
at RAM back-up : state retained
4506 Group
INSTRUCTIONS
The 4506 Group has the 110 instructions. Each instruction is described as follows;
(1) Index list of instruction function
(2) Machine instructions (index by alphabet)
(3) Machine instructions (index by function)
(4) Instruction code table
SYMBOL
The symbols shown below are used in the following list of instruction function and the machine instructions.
Symbol
Contents
Contents
Symbol
WDF1
Watchdog timer flag
Register B (4 bits)
Register D (3 bits)
WEF
Watchdog timer enable flag
INTE
Interrupt enable flag
E
Q1
Register E (8 bits)
External 0 interrupt request flag
A/D control register Q1 (4 bits)
EXF0
P
V1
Interrupt control register V1 (4 bits)
ADF
Power down flag
A/D conversion completion flag
V2
Interrupt control register V2 (4 bits)
I1
Interrupt control register I1 (4 bits)
Timer control register W1 (4 bits)
D
Port D (4 bits)
P0
Port P0 (4 bits)
W2
W6
Timer control register W2 (4 bits)
Port P1 (4 bits)
Timer control register W6 (4 bits)
P1
P2
MR
Clock control register MR (4 bits)
C
Port P2 (2 bits)
Port C (1 bit)
K0
Key-on wakeup control register K0 (4 bits)
K
Port K (1 bit)
K1
Key-on wakeup control register K1 (4 bits)
Key-on wakeup control register K2 (4 bits)
x
y
Hexadecimal variable
Pull-up control register PU0 (4 bits)
PU1
Pull-up control register PU1 (4 bits)
z
Hexadecimal variable
Hexadecimal variable
PU2
Pull-up control register PU2 (4 bits)
p
Hexadecimal variable
X
Register X (4 bits)
n
Hexadecimal constant
Y
Register Y (4 bits)
Register Z (2 bits)
i
Hexadecimal constant
j
A 3A 2A 1A 0
Hexadecimal constant
A
Register A (4 bits)
B
DR
W1
K2
PU0
Z
DP
Data pointer (10 bits)
(It consists of registers X, Y, and Z)
Binary notation of hexadecimal variable A
(same for others)
PC
Program counter (14 bits)
PCH
High-order 7 bits of program counter
←
Direction of data movement
PCL
Low-order 7 bits of program counter
Stack register (14 bits ✕ 8)
↔
Data exchange between a register and memory
Decision of state shown before “?”
SK
SP
Stack pointer (3 bits)
?
( )
CY
Carry flag
—
Contents of registers and memories
Negate, Flag unchanged after executing instruction
R1
Timer 1 reload register
M(DP)
RAM address pointed by the data pointer
R2
Timer 2 reload register
a
Label indicating address a6 a5 a4 a3 a2 a1 a0
T1
Timer 1
Timer 2
p, a
Label indicating address a6 a5 a4 a3 a2 a1 a0
Timer 1 interrupt request flag
C
Timer 2 interrupt request flag
+
T2
T1F
T2F
in page p5 p4 p3 p2 p1 p0
Hex. C + Hex. number x (also same for others)
x
Note : Some instructions of the 4506 Group has the skip function to unexecute the next described instruction. The 4506 Group just invalidates the next instruction when a skip is performed. The contents of program counter is not increased by 2. Accordingly, the number of cycles does not change even if skip
is not performed. However, the cycle count becomes “1” if the TABP p, RT, or RTS instruction is skipped.
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4506 Group
INDEX LIST OF INSTRUCTION FUNCTION
Register to register transfer
TAB
Function
(A) ← (B)
Page
GroupMnemonic
ing
75, 88
TBA
(B) ← (A)
81, 88
TAY
(A) ← (Y)
81, 88
TYA
(Y) ← (A)
86, 88
TEAB
(E7–E4) ← (B)
82, 88
XAMI j
RAM to register transfer
GroupMnemonic
ing
(E3–E0) ← (A)
TABE
(B) ← (E7–E4)
Function
(A) ← → (M(DP))
Page
87, 88
(X) ← (X)EXOR(j)
j = 0 to 15
(Y) ← (Y) + 1
TMA j
(M(DP)) ← (A)
83, 88
(X) ← (X)EXOR(j)
j = 0 to 15
LA n
(A) ← n
n = 0 to 15
66, 90
TABP p
(SP) ← (SP) + 1
76, 90
76, 88
(A) ← (E3–E0)
(SK(SP)) ← (PC)
TDA
TAD
(DR2–DR0) ← (A2–A0)
(A2–A0) ← (DR2–DR0)
81, 88
(PCH) ← p (Note)
76, 88
(PCL) ← (DR2–DR0, A3–A0)
(B) ← (ROM(PC))7–4
(A3) ← 0
(A) ← (ROM(PC))3–0
(PC) ← (SK(SP))
TAZ
(A1, A0) ← (Z1, Z0)
(SP) ← (SP) – 1
81, 88
(A3, A2) ← 0
(A) ← (X)
80, 88
TASP
(A2–A0) ← (SP2–SP0)
79, 88
(A3) ← 0
LXY x, y
(X) ← x x = 0 to 15
66, 88
RAM addresses
(Y) ← y y = 0 to 15
LZ z
(Z) ← z z = 0 to 3
66, 88
INY
(Y) ← (Y) + 1
66, 88
DEY
(Y) ← (Y) – 1
63, 88
TAM j
(A) ← (M(DP))
78, 88
RAM to register transfer
(X) ← (X)EXOR(j)
AM
(A) ← (A) + (M(DP))
60, 90
AMC
(A) ← (A) + (M(DP)) + (CY)
60, 90
(CY) ← Carry
Arithmetic operation
TAX
An
(A) ← (A) + n
n = 0 to 15
60, 90
AND
(A) ← (A) AND (M(DP))
61, 90
OR
(A) ← (A) OR (M(DP))
68, 90
SC
(CY) ← 1
71, 90
RC
(CY) ← 0
69, 90
SZC
(CY) = 0 ?
74, 90
CMA
(A) ← (A)
63, 90
RAR
→ CY → A3A2A1A0
68, 90
j = 0 to 15
XAM j
(A) ← → (M(DP))
(X) ← (X)EXOR(j)
86, 88
j = 0 to 15
XAMD j
(A) ← → (M(DP))
(X) ← (X)EXOR(j)
j = 0 to 15
(Y) ← (Y) – 1
Note: p is 0 to 15 for M34506M2,
p is 0 to 31 for M34506M4/E4.
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87, 88
4506 Group
INDEX LIST OF INSTRUCTION FUNCTION (continued)
Branch operation
Page
GroupMnemonic
ing
DI
(INTE) ← 0
64, 94
EI
(INTE) ← 1
64, 94
SNZ0
V10 = 0: (EXF0) = 1 ?
72, 94
SB j
(Mj(DP)) ← 1
j = 0 to 3
70, 90
RB j
(Mj(DP)) ← 0
69, 90
j = 0 to 3
SZB j
(Mj(DP)) = 0 ?
j = 0 to 3
74, 90
SEAM
(A) = (M(DP)) ?
72, 90
SEA n
(A) = n ?
71, 90
Page
After skipping, (EXF0) ← 0
V10 = 1: SNZ0 = NOP
SNZI0
I12 = 1 : (INT) = “H” ?
73, 94
I12 = 0 : (INT) = “L” ?
(A) ← (V1)
79, 94
TV1A
(V1) ← (A)
85, 94
TAV2
(A) ← (V2)
79, 94
TV2A
(V2) ← (A)
85, 94
TAI1
(A) ← (I1)
77, 94
TI1A
(I1) ← (A)
82, 94
(SK(SP)) ← (PC)
TAW1
(A) ← (W1)
80, 94
(PCH) ← 2
(PCL) ← a6–a0
TW1A
(W1) ← (A)
85, 94
TAW2
(A) ← (W2)
80, 94
TW2A
(W2) ← (A)
85, 94
TAW6
(A) ← (W6)
80, 94
TW6A
(W6) ← (A)
86, 94
(B) ← (T17–T14)
75, 94
Ba
(PCL) ← a6–a0
61, 92
BL p, a
(PCH) ← p (Note)
61, 92
(PCL) ← a6–a0
BLA p
Function
TAV1
n = 0 to 15
(PCH) ← p (Note)
61, 92
(PCL) ← (DR2–DR0, A3–A0)
BM a
Subroutine operation
Function
Interrupt operation
Comparison
operation
Bit operation
GroupMnemonic
ing
BML p, a
(SP) ← (SP) + 1
(SP) ← (SP) + 1
62, 92
62, 92
(SK(SP)) ← (PC)
(PCH) ← p (Note)
(PCL) ← a6–a0
BMLA p
(SP) ← (SP) + 1
62, 92
(PCH) ← p (Note)
(PCL) ← (DR2–DR0, A3–A0)
RTI
(PC) ← (SK(SP))
70, 92
(SP) ← (SP) – 1
Timer operation
(SK(SP)) ← (PC)
TAB1
(A) ← (T13–T10)
T1AB
(R17–R14) ← (B)
74, 94
(T17–T14) ← (B)
RT
(PC) ← (SK(SP))
(R13–R10) ← (A)
(T13–T10) ← (A)
70, 92
Return operation
(SP) ← (SP) – 1
RTS
(PC) ← (SK(SP))
70, 92
TAB2
(B) ← (T27–T24)
T2AB
(R27–R24) ← (B)
(T27–T24) ← (B)
(R23–R20) ← (A)
(T23–T20) ← (A)
Note: p is 0 to 15 for M34506M2,
p is 0 to 31 for M34506M4/E4.
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75, 94
(A) ← (T23–T20)
(SP) ← (SP) – 1
75, 94
4506 Group
INDEX LIST OF INSTRUCTION FUNCTION (continued)
Grouping Mnemonic
TR1AB
Function
(R17–R14) ← (B)
Page
GroupMnemonic
ing
84, 94
IAK
SNZT1
V12 = 0: (T1F) = 1 ?
(A0) ← (K)
Page
65, 96
(A3–A1) ← 0
73, 94
OKA
(K) ← (A0)
67, 96
TK0A
(K0) ← (A)
82, 96
TAK0
(A) ← (K0)
77, 96
TK1A
(K1) ← (A)
82, 96
TAK1
(A) ← (K1)
77, 96
TK2A
(K2) ← (A)
83, 96
After skipping, (T1F) ← 0
V12 = 1: SNZT1 = NOP
SNZT2
V13 = 0: (T2F) = 1 ?
73, 94
After skipping, (T2F) ← 0
V13 = 1: SNZT2 = NOP
Input/Output operation
Timer operation
(R13–R10) ← (A)
Function
IAP0
(A) ← (P0)
65, 96
OP0A
(P0) ← (A)
67, 96
IAP1
(A) ← (P1)
65, 96
TAK2
(A) ← (K2)
78, 96
OP1A
(P1) ← (A)
67, 96
TPU0A
(PU0) ← (A)
83, 96
(A1, A0) ← (P21, P20)
65, 96
TPU1A
(PU1) ← (A)
84, 96
TPU2A
(PU2) ← (A)
84, 96
TABAD
In A/D conversion mode (Q13 = 0),
(B) ← (AD9–AD6)
76, 98
IAP2
(A3, A2) ← 0
OP2A
(P21, P20) ← (A1, A0)
68, 96
CLD
(D) ← 1
62, 96
RD
(D(Y)) ← 0
69, 96
In comparator mode (Q13 = 1),
(B) ← (AD7–AD4)
(Y) = 0 to 3
(A) ← (AD3–AD0)
SD
(D(Y)) ← 1
71, 96
(Y) = 0 to 3
TALA
(A3, A2) ← (AD1, AD0)
78, 98
(A1, A0) ← 0
SZD
(D(Y)) = 0 ?
74, 96
(Y) = 0 to 3
SCP
(C) ← 1
71, 96
RCP
(C) ← 0
69, 96
SNZCP
(C) = 1 ?
72, 96
A/D conversion operation
Input/Output operation
(A) ← (AD5–AD2)
TADAB
(AD7–AD4) ← (B)
77, 98
(AD3–AD0) ← (A)
TAQ1
(A) ← (Q1)
79, 98
TQ1A
(Q1) ← (A)
84, 98
ADST
(ADF) ← 0
60, 98
Q13 = 0: A/D conversion starting
Q13 = 1: Comparator operation
starting
SNZAD
V22 = 0: (ADF) = 1 ?
After skipping, (ADF) ← 0
V22 = 1: SNZAD = NOP
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72, 98
4506 Group
INDEX LIST OF INSTRUCTION FUNCTION (continued)
Other operation
GroupMnemonic
ing
Function
Page
NOP
(PC) ← (PC) + 1
67, 98
POF2
RAM back-up
68, 98
EPOF
POF2 instructions valid
64, 98
SNZP
(P) = 1 ?
73, 98
DWDT
Stop of watchdog timer function enabled
64, 98
WRST
(WDF1) = 1 ?
86, 98
CMCK
Ceramic resonance circuit
selected
63, 98
CRCK
RC oscillation circuit selected
63, 98
TAMR
(A) ← (MR)
78, 98
TMRA
(MR) ← (A)
83, 98
After skipping, (WDF1) ← 0
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4506 Group
MACHINE INSTRUCTIONS (INDEX BY ALPHABET)
A n (Add n and accumulator)
Instruction
code
Operation:
D9
0
D0
0
0
1
1
0
n
n
n
n
2
0
6
n
16
(A) ← (A) + n
n = 0 to 15
Number of
words
Number of
cycles
Flag CY
Skip condition
1
1
–
Overflow = 0
Grouping:
Arithmetic operation
Description: Adds the value n in the immediate field to
register A, and stores a result in register A.
The contents of carry flag CY remains unchanged.
Skips the next instruction when there is no
overflow as the result of operation.
Executes the next instruction when there is
overflow as the result of operation.
ADST (A/D conversion STart)
Instruction
code
Operation:
D9
1
D0
0
1
0
0
1
1
1
1
1
2
2
9
F
16
(ADF) ← 0
Q13 = 0: A/D conversion starting
Q13 = 1: Comparator operation starting
(Q13 : bit 3 of A/D control register Q1)
Number of
words
Number of
cycles
Flag CY
Skip condition
1
1
–
–
Grouping:
A/D conversion operation
Description: Clears (0) to A/D conversion completion
flag ADF, and the A/D conversion at the A/D
conversion mode (Q13 = 0) or the comparator operation at the comparator mode (Q13
= 1) is started.
AM (Add accumulator and Memory)
Instruction
code
Operation:
D9
0
D0
0
0
0
0
0
1
0
1
0
2
0
0
A
16
(A) ← (A) + (M(DP))
Number of
words
Number of
cycles
Flag CY
Skip condition
1
1
–
–
Grouping:
Arithmetic operation
Description: Adds the contents of M(DP) to register A.
Stores the result in register A. The contents
of carry flag CY remains unchanged.
AMC (Add accumulator, Memory and Carry)
Instruction
code
Operation:
D9
0
D0
0
0
0
0
0
1
(A) ← (A) + (M(DP)) + (CY)
(CY) ← Carry
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0
1
1
2
0
0
B
16
Number of
words
Number of
cycles
Flag CY
Skip condition
1
1
0/1
–
Grouping:
Arithmetic operation
Description: Adds the contents of M(DP) and carry flag
CY to register A. Stores the result in register A and carry flag CY.
4506 Group
MACHINE INSTRUCTIONS (INDEX BY ALPHABET) (continued)
AND (logical AND between accumulator and memory)
Instruction
code
Operation:
D9
0
D0
0
0
0
0
1
1
0
0
0
2
0
1
8
16
(A) ← (A) AND (M(DP))
Number of
words
Number of
cycles
Flag CY
Skip condition
1
1
–
–
Grouping:
Arithmetic operation
Description: Takes the AND operation between the contents of register A and the contents of
M(DP), and stores the result in register A.
B a (Branch to address a)
Instruction
code
Operation:
D0
D9
0
1
1
a6 a5 a4 a3 a2 a1 a0
2
1
8
+a
a
16
(PCL) ← a6 to a0
Number of
words
Number of
cycles
Flag CY
Skip condition
1
1
–
–
Grouping:
Branch operation
Description: Branch within a page : Branches to address
a in the identical page.
Note:
Specify the branch address within the page
including this instruction.
BL p, a (Branch Long to address a in page p)
Instruction
code
Operation:
D9
D0
0
0
1
1
1
p4 p3 p2 p1 p0
1
0
0
a6 a5 a4 a3 a2 a1 a0 2
2
0
E
+p
p
2
a
a 16
16
(PCH) ← p
(PCL) ← a6 to a0
Number of
words
Number of
cycles
Flag CY
Skip condition
2
2
–
–
Grouping:
Branch operation
Description: Branch out of a page : Branches to address
a in page p.
Note:
p is 0 to 15 for M34506M2, and p is 0 to 31
for M34506M4/E4.
BLA p (Branch Long to address (D) + (A) in page p)
Instruction
code
Operation:
D9
D0
0
0
0
0
0
1
0
1
0
0
p4 0
0
p3 p2 p1 p0 2
(PCH) ← p
(PCL) ← (DR2–DR0, A3–A0)
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0
0
0
2
0
1
0
2
p
p 16
16
Number of
words
Number of
cycles
Flag CY
Skip condition
2
2
–
–
Grouping:
Branch operation
Description: Branch out of a page : Branches to address
(DR2 DR 1 DR 0 A3 A 2 A 1 A 0)2 specified by
registers D and A in page p.
Note:
p is 0 to 15 for M34506M2, and p is 0 to 31
for M34506M4/E4.
4506 Group
MACHINE INSTRUCTIONS (INDEX BY ALPHABET) (continued)
BM a (Branch and Mark to address a in page 2)
Instruction
code
Operation:
D9
0
D0
1
0
a6 a5 a4 a3 a2 a1 a0
2
1
a
a
Number of
words
Number of
cycles
Flag CY
Skip condition
1
1
–
–
16
(SP) ← (SP) + 1
(SK(SP)) ← (PC)
(PCH) ← 2
(PCL) ← a6–a0
Grouping:
Subroutine call operation
Description: Call the subroutine in page 2 : Calls the
subroutine at address a in page 2.
Note:
Subroutine extending from page 2 to another page can also be called with the BM
instruction when it starts on page 2.
Be careful not to over the stack because the
maximum level of subroutine nesting is 8.
BML p, a (Branch and Mark Long to address a in page p)
Instruction
code
Operation:
D9
D0
0
0
1
1
0
p4 p3 p2 p1 p0
1
0
0
a6 a5 a4 a3 a2 a1 a0 2
2
0
C
+p
p
2
a
a 16
Number of
words
Number of
cycles
Flag CY
Skip condition
2
2
–
–
16
(SP) ← (SP) + 1
(SK(SP)) ← (PC)
(PCH) ← p
(PCL) ← a6–a0
Grouping:
Subroutine call operation
Description: Call the subroutine : Calls the subroutine at
address a in page p.
Note:
p is 0 to 15 for M34506M2, and p is 0 to 31
for M34506M4/E4.
Be careful not to over the stack because the
maximum level of subroutine nesting is 8.
BMLA p (Branch and Mark Long to address (D) + (A) in page p)
Instruction
code
Operation:
D9
D0
0
0
0
0
1
1
0
0
0
0
1
0
0
p4 0
0
p3 p2 p1 p0 2
2
0
3
0
2
p
p 16
16
(SP) ← (SP) + 1
(SK(SP)) ← (PC)
(PCH) ← p
(PCL) ← (DR2–DR0, A3–A0)
Number of
words
Number of
cycles
Flag CY
Skip condition
2
2
–
–
Grouping:
Subroutine call operation
Description: Call the subroutine : Calls the subroutine at
address (DR2 DR1 DR0 A3 A2 A1 A0)2 specified by registers D and A in page p.
Note:
p is 0 to 15 for M34506M2, and p is 0 to 31
for M34506M4/E4.
Be careful not to over the stack because the
maximum level of subroutine nesting is 8.
CLD (CLear port D)
Instruction
code
Operation:
D9
0
D0
0
0
0
0
1
(D) ← 1
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0
0
0
1
2
0
1
1
16
Number of
words
Number of
cycles
Flag CY
Skip condition
1
1
–
–
Grouping:
Input/Output operation
Description: Sets (1) to port D.
page 62 of 111
4506 Group
MACHINE INSTRUCTIONS (INDEX BY ALPHABET) (continued)
CMA (CoMplement of Accumulator)
Instruction
code
Operation:
D9
0
D0
0
0
0
0
1
1
1
0
0 2
0
1
C 16
(A) ← (A)
Number of
words
Number of
cycles
Flag CY
Skip condition
1
1
–
–
Grouping:
Arithmetic operation
Description: Stores the one’s complement for register
A’s contents in register A.
CMCK (Clock select: ceraMic resonance ClocK)
Instruction
code
Operation:
D0
D9
1
0
1
0
0
1
1
0
1
0
2
2
9
A
16
Ceramic resonance circuit selected
Number of
words
Number of
cycles
Flag CY
Skip condition
1
1
–
–
Grouping:
Other operation
Description: Selects the ceramic resonance circuit and
stops the on-chip oscillator.
CRCK (Clock select: Rc oscillation ClocK)
Instruction
code
Operation:
D9
1
D0
0
1
0
0
1
1
0
1
1
2
2
9
B
16
RC oscillation circuit selected
Number of
words
Number of
cycles
Flag CY
Skip condition
1
1
–
–
Grouping:
Other operation
Description: Selects the RC oscillation circuit and stops
the on-chip oscillator.
DEY (DEcrement register Y)
Instruction
code
Operation:
D9
0
D0
0
0
0
0
1
(Y) ← (Y) – 1
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0
1
1
1
2
0
1
7
16
Number of
words
Number of
cycles
Flag CY
Skip condition
1
1
–
(Y) = 15
Grouping:
RAM addresses
Description: Subtracts 1 from the contents of register Y.
As a result of subtraction, when the contents of register Y is 15, the next instruction
is skipped. When the contents of register Y
is not 15, the next instruction is executed.
4506 Group
MACHINE INSTRUCTIONS (INDEX BY ALPHABET) (continued)
DI (Disable Interrupt)
Instruction
code
Operation:
D9
0
D0
0
0
0
0
0
0
1
0
0
2
0
0
4
16
(INTE) ← 0
Number of
words
Number of
cycles
Flag CY
Skip condition
1
1
–
–
Grouping:
Interrupt control operation
Description: Clears (0) to interrupt enable flag INTE, and
disables the interrupt.
Note:
Interrupt is disabled by executing the DI instruction after executing 1 machine cycle.
DWDT (Disable WatchDog Timer)
Instruction
code
Operation:
D9
1
D0
0
1
0
0
1
1
1
0
0
2
2
9
C
16
Number of
words
Number of
cycles
Flag CY
Skip condition
1
1
–
–
Grouping:
Other operation
Description: Stops the watchdog timer function by the
WRST instruction after executing the
DWDT instruction.
Stop of watchdog timer function enabled
EI (Enable Interrupt)
Instruction
code
Operation:
D9
0
D0
0
0
0
0
0
0
1
0
1
2
0
0
5
16
(INTE) ← 1
Number of
words
Number of
cycles
Flag CY
Skip condition
1
1
–
–
Grouping:
Interrupt control operation
Description: Sets (1) to interrupt enable flag INTE, and
enables the interrupt.
Note:
Interrupt is enabled by executing the EI instruction after executing 1 machine cycle.
EPOF (Enable POF instruction)
Instruction
code
Operation:
D9
0
D0
0
0
1
0
1
POF2 instruction valid
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1
0
1
1
2
0
5
B
16
Number of
words
Number of
cycles
Flag CY
Skip condition
1
1
–
–
Grouping:
Other operation
Description: Makes the immediate after POF or POF2
instruction valid by executing the EPOF instruction.
4506 Group
MACHINE INSTRUCTIONS (INDEX BY ALPHABET) (continued)
IAK (Input Accumulator from port K)
Instruction
code
Operation:
D9
1
D0
0
0
1
1
0
1
1
1
1
2
2
6
F
16
(A0) ← (K)
(A3–A1) ← 0
Number of
words
Number of
cycles
Flag CY
Skip condition
1
1
–
–
Grouping:
Input/Output operation
Description: Transfers the contents of port K to the bit 0
(A0) of register A.
Note:
After this instruction is executed, “0” is
stored to the high-order 3 bits (A3–A 1 ) of
register A.
IAP0 (Input Accumulator from port P0)
Instruction
code
Operation:
D0
D9
1
0
0
1
1
0
0
0
0
0
2
2
6
0
16
(A) ← (P0)
Number of
words
Number of
cycles
Flag CY
Skip condition
1
1
–
–
Grouping:
Input/Output operation
Description: Transfers the input of port P0 to register A.
IAP1 (Input Accumulator from port P1)
Instruction
code
Operation:
D9
1
D0
0
0
1
1
0
0
0
0
1
2
2
6
1
16
(A) ← (P1)
Number of
words
Number of
cycles
Flag CY
Skip condition
1
1
–
–
Grouping:
Input/Output operation
Description: Transfers the input of port P1 to register A.
IAP2 (Input Accumulator from port P2)
Instruction
code
Operation:
D9
1
D0
0
0
1
1
0
(A1, A0) ← (P21, P20)
(A3, A2) ← 0
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0
0
1
0
2
2
6
2
16
Number of
words
Number of
cycles
Flag CY
Skip condition
1
1
–
–
Grouping:
Input/Output operation
Description: Transfers the input of port P2 to the low-order 2 bits (A1, A0) of register A.
Note:
After this instruction is executed, “0” is
stored to the high-order 2 bits (A3, A2 ) of
register A.
4506 Group
MACHINE INSTRUCTIONS (INDEX BY ALPHABET) (continued)
INY (INcrement register Y)
Instruction
code
Operation:
D9
0
D0
0
0
0
0
1
0
0
1
1
2
0
1
3 16
(Y) ← (Y) + 1
Number of
words
Number of
cycles
Flag CY
Skip condition
1
1
–
(Y) = 0
Grouping:
RAM addresses
Description: Adds 1 to the contents of register Y. As a result of addition, when the contents of
register Y is 0, the next instruction is
skipped. When the contents of register Y is
not 0, the next instruction is executed.
LA n (Load n in Accumulator)
Instruction
code
Operation:
D9
0
D0
0
0
1
1
1
n
n
n
n
2
0
7
n
16
(A) ← n
n = 0 to 15
Number of
words
Number of
cycles
Flag CY
Skip condition
1
1
–
Continuous
description
Grouping:
Arithmetic operation
Description: Loads the value n in the immediate field to
register A.
When the LA instructions are continuously
coded and executed, only the first LA instruction is executed and other LA
instructions coded continuously are
skipped.
LXY x, y (Load register X and Y with x and y)
Instruction
code
Operation:
D9
1
D0
1
x3 x2 x1 x0 y3 y2 y1 y0
2
3
x
y
16
(X) ← x x = 0 to 15
(Y) ← y y = 0 to 15
Number of
words
Number of
cycles
Flag CY
Skip condition
1
1
–
Continuous
description
Grouping:
RAM addresses
Description: Loads the value x in the immediate field to
register X, and the value y in the immediate
field to register Y. When the LXY instructions are continuously coded and executed,
only the first LXY instruction is executed
and other LXY instructions coded continuously are skipped.
LZ z (Load register Z with z)
Instruction
code
Operation:
D9
0
D0
0
0
1
0
0
(Z) ← z z = 0 to 3
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1
0
z1 z0
2
0
4
8
+z 16
Number of
words
Number of
cycles
Flag CY
Skip condition
1
1
–
–
Grouping:
RAM addresses
Description: Loads the value z in the immediate field to
register Z.
4506 Group
MACHINE INSTRUCTIONS (INDEX BY ALPHABET) (continued)
NOP (No OPeration)
Instruction
code
Operation:
D9
0
D0
0
0
0
0
0
0
0
0
0
2
0
0
0
16
(PC) ← (PC) + 1
Number of
words
Number of
cycles
Flag CY
Skip condition
1
1
–
–
Grouping:
Other operation
Description: No operation; Adds 1 to program counter
value, and others remain unchanged.
OKA (Output port K from Accumulator)
Instruction
code
Operation:
D0
D9
1
0
0
0
0
1
1
1
1
1
2
2
1
F
16
(K) ← (A0)
Number of
words
Number of
cycles
Flag CY
Skip condition
1
1
–
–
Grouping:
Input/Output operation
Description: Outputs the contents of bit 0 (A0) of register
A to port K.
OP0A (Output port P0 from Accumulator)
Instruction
code
Operation:
D9
1
D0
0
0
0
1
0
0
0
0
0
2
2
2
0
16
(P0) ← (A)
Number of
words
Number of
cycles
Flag CY
Skip condition
1
1
–
–
Grouping:
Input/Output operation
Description: Outputs the contents of register A to port
P0.
OP1A (Output port P1 from Accumulator)
Instruction
code
Operation:
D9
1
D0
0
0
0
1
0
(P1) ← (A)
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0
0
0
1
2
2
2
1
16
Number of
words
Number of
cycles
Flag CY
Skip condition
1
1
–
–
Grouping:
Input/Output operation
Description: Outputs the contents of register A to port
P1.
4506 Group
MACHINE INSTRUCTIONS (INDEX BY ALPHABET) (continued)
OP2A (Output port P2 from Accumulator)
Instruction
code
Operation:
D9
1
D0
0
0
0
1
0
0
0
1
0
2
2
2
2
16
(P21, P20) ← (A1, A0)
Number of
words
Number of
cycles
Flag CY
Skip condition
1
1
–
–
Grouping:
Input/Output operation
Description: Outputs the contents of the low-order 2 bits
(A1, A0) of register A to port P2.
OR (logical OR between accumulator and memory)
Instruction
code
Operation:
D9
0
D0
0
0
0
0
1
1
0
0
1 2
0
1
9 16
(A) ← (A) OR (M(DP))
Number of
words
Number of
cycles
Flag CY
Skip condition
1
1
–
–
Grouping:
Arithmetic operation
Description: Takes the OR operation between the contents of register A and the contents of
M(DP), and stores the result in register A.
POF2 (Power OFf2)
Instruction
code
Operation:
D9
0
D0
0
0
0
0
0
1
0
0
0
2
0
0
8
16
Number of
words
Number of
cycles
Flag CY
Skip condition
1
1
–
–
Grouping:
Other operation
Description: Puts the system in RAM back-up state by
executing the POF2 instruction after executing the EPOF instruction. Operations of
all functions are stopped.
Note:
If the EPOF instruction is not executed before
executing this instruction, this instruction is
equivalent to the NOP instruction.
RAM back-up
RAR (Rotate Accumulator Right)
Instruction
code
Operation:
D9
0
D0
0
0
0
0
1
→ CY → A3A2A1A0
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1
1
0
1
2
0
1
D
16
Number of
words
Number of
cycles
Flag CY
Skip condition
1
1
0/1
–
Grouping:
Arithmetic operation
Description: Rotates 1 bit of the contents of register A including the contents of carry flag CY to the
right.
4506 Group
MACHINE INSTRUCTIONS (INDEX BY ALPHABET) (continued)
RB j (Reset Bit)
Instruction
code
Operation:
D9
0
D0
0
0
1
0
0
1
1
j
j
2
0
4
C
+j 16
(Mj(DP)) ← 0
j = 0 to 3
Number of
words
Number of
cycles
Flag CY
Skip condition
1
1
–
–
Grouping:
Bit operation
Description: Clears (0) the contents of bit j (bit specified
by the value j in the immediate field) of
M(DP).
RC (Reset Carry flag)
Instruction
code
Operation:
D0
D9
0
0
0
0
0
0
0
1
1
0
2
0
0
6
16
(CY) ← 0
Number of
words
Number of
cycles
Flag CY
Skip condition
1
1
0
–
Grouping:
Arithmetic operation
Description: Clears (0) to carry flag CY.
RCP (Reset Port C)
Instruction
code
Operation:
D9
1
D0
0
1
0
0
0
1
1
0
0
2
2
8
C
16
(C) ← 0
Number of
words
Number of
cycles
Flag CY
Skip condition
1
1
–
–
Grouping:
Input/Output operation
Description: Clears (0) to port C.
RD (Reset port D specified by register Y)
Instruction
code
Operation:
D9
0
D0
0
0
0
0
1
(D(Y)) ← 0
However,
(Y) = 0 to 3
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0
1
0
0
2
0
1
4
16
Number of
words
Number of
cycles
Flag CY
Skip condition
1
1
–
–
Grouping:
Input/Output operation
Description: Clears (0) to a bit of port D specified by register Y.
Note:
Set 0 to 3 to register Y because port D is
four ports (D0–D3).
When values except above are set to register Y, this instruction is equivalent to the
NOP instruction.
4506 Group
MACHINE INSTRUCTIONS (INDEX BY ALPHABET) (continued)
RT (ReTurn from subroutine)
Instruction
code
Operation:
D9
0
D0
0
0
1
0
0
0
1
0
0
2
0
4
4
16
(PC) ← (SK(SP))
(SP) ← (SP) – 1
Number of
words
Number of
cycles
Flag CY
Skip condition
1
2
–
–
Grouping:
Return operation
Description: Returns from subroutine to the routine
called the subroutine.
RTI (ReTurn from Interrupt)
Instruction
code
Operation:
D9
0
D0
0
0
1
0
0
0
1
1
0
2
0
4
6
16
(PC) ← (SK(SP))
(SP) ← (SP) – 1
Number of
words
Number of
cycles
Flag CY
Skip condition
1
1
–
–
Grouping:
Return operation
Description: Returns from interrupt service routine to
main routine.
Returns each value of data pointer (X, Y, Z),
carry flag, skip status, NOP mode status by
the continuous description of the LA/LXY instruction, register A and register B to the
states just before interrupt.
RTS (ReTurn from subroutine and Skip)
Instruction
code
Operation:
D9
0
D0
0
0
1
0
0
0
1
0
1
2
0
4
5
16
(PC) ← (SK(SP))
(SP) ← (SP) – 1
Number of
words
Number of
cycles
Flag CY
Skip condition
1
2
–
Skip at uncondition
Grouping:
Return operation
Description: Returns from subroutine to the routine
called the subroutine, and skips the next instruction at uncondition.
SB j (Set Bit)
Instruction
code
Operation:
D9
0
D0
0
0
1
0
1
(Mj(DP)) ← 0
j = 0 to 3
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1
1
j
j
2
0
5
C
+j 16
Number of
words
Number of
cycles
Flag CY
Skip condition
1
1
–
–
Grouping:
Bit operation
Description: Sets (1) the contents of bit j (bit specified by
the value j in the immediate field) of M(DP).
4506 Group
MACHINE INSTRUCTIONS (INDEX BY ALPHABET) (continued)
SC (Set Carry flag)
Instruction
code
Operation:
D9
0
D0
0
0
0
0
0
0
1
1
1
2
0
0
7
16
(CY) ← 1
Number of
words
Number of
cycles
Flag CY
Skip condition
1
1
1
–
Grouping:
Arithmetic operation
Description: Sets (1) to carry flag CY.
SCP (Set Port C)
Instruction
code
Operation:
D0
D9
1
0
1
0
0
0
1
1
0
1
2
2
8
D
16
(C) ← 1
Number of
words
Number of
cycles
Flag CY
Skip condition
1
1
–
–
Grouping:
Input/Output operation
Description: Sets (1) to port C.
SD (Set port D specified by register Y)
Instruction
code
Operation:
D9
0
D0
0
0
0
0
1
0
1
0
1
2
0
1
5
16
(D(Y)) ← 1
(Y) = 0 to 3
Number of
words
Number of
cycles
Flag CY
Skip condition
1
1
–
–
Grouping:
Input/Output operation
Description: Sets (1) to a bit of port D specified by register Y.
Note:
Set 0 to 3 to register Y because port D is
four ports (D0–D3).
When values except above are set to register Y, this instruction is equivalent to the
NOP instruction.
SEA n (Skip Equal, Accumulator with immediate data n)
Instruction
code
D9
0
0
Operation:
D0
0
0
0
0
0
1
1
1
0
1
(A) = n ?
n = 0 to 15
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0
n
1
n
0
n
1
2
n 2
0
0
2
7
5
16
Number of
words
Number of
cycles
Flag CY
Skip condition
2
2
–
(A) = n
n 16
Grouping:
Comparison operation
Description: Skips the next instruction when the contents of register A is equal to the value n in
the immediate field.
Executes the next instruction when the contents of register A is not equal to the value n
in the immediate field.
4506 Group
MACHINE INSTRUCTIONS (INDEX BY ALPHABET) (continued)
SEAM (Skip Equal, Accumulator with Memory)
Instruction
code
Operation:
D9
0
D0
0
0
0
1
0
0
1
1
0
2
0
2
6
16
(A) = (M(DP)) ?
Number of
words
Number of
cycles
Flag CY
Skip condition
1
1
–
(A) = (M(DP))
Grouping:
Comparison operation
Description: Skips the next instruction when the contents of register A is equal to the contents of
M(DP).
Executes the next instruction when the contents of register A is not equal to the
contents of M(DP).
SNZ0 (Skip if Non Zero condition of external 0 interrupt request flag)
Instruction
code
Operation:
D9
0
D0
0
0
0
1
1
1
0
0
0
2
0
3
8
16
V10 = 0: (EXF0) = 1 ?
After skipping, (EXF0) ← 0
V10 = 1: SNZ0 = NOP
(V10 : bit 0 of the interrupt control register V1)
Number of
words
Number of
cycles
Flag CY
Skip condition
1
1
–
V10 = 0: (EXF0) = 1
Grouping:
Interrupt operation
Description: When V10 = 0 : Skips the next instruction
when external 0 interrupt request flag EXF0
is “1.” After skipping, clears (0) to the EXF0
flag. When the EXF0 flag is “0,” executes
the next instruction.
When V1 0 = 1 : This instruction is equivalent to the NOP instruction.
SNZAD (Skip if Non Zero condition of A/D conversion completion flag)
Instruction
code
Operation:
D9
1
D0
0
1
0
0
0
0
1
1
1
2
2
8
7
16
V22 = 0: (ADF) = 1 ?
After skipping, (ADF) ← 0
V22 = 1: SNZAD = NOP
(V22 : bit 2 of the interrupt control register V2)
Number of
words
Number of
cycles
Flag CY
Skip condition
1
1
–
V22 = 0: (ADF) = 1
Grouping:
A/D conversion operation
Description: When V22 = 0 : Skips the next instruction
when A/D conversion completion flag ADF
is “1.” After skipping, clears (0) to the ADF
flag. When the ADF flag is “0,” executes the
next instruction.
When V22 = 1 : This instruction is equivalent to the NOP instruction.
SNZCP (Skip if Non Zero condition of Port C)
Instruction
code
Operation:
D9
1
D0
0
1
0
0
0
(C) = 1 ?
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1
0
0
1 2
2
8
9 16
Number of
words
Number of
cycles
Flag CY
Skip condition
1
1
–
(C) = 1
Grouping:
Input/Output operation
Description: Skips the next instruction when the contents of port C is “1.”
Executes the next instruction when the contents of port C is “0.”
page 72 of 111
4506 Group
MACHINE INSTRUCTIONS (INDEX BY ALPHABET) (continued)
SNZI0 (Skip if Non Zero condition of external 0 Interrupt input pin)
Instruction
code
Operation:
D9
0
D0
0
0
0
1
1
1
0
1
0 2
0
3
A 16
Number of
words
Number of
cycles
Flag CY
1
1
–
Skip condition
I12 = 0 : (INT) = “L”
I12 = 1 : (INT) = “H”
Grouping:
Interrupt operation
Description: When I1 2 = 0 : Skips the next instruction
when the level of INT pin is “L.” Executes
the next instruction when the level of INT
pin is “H.”
When I1 2 = 1 : Skips the next instruction
when the level of INT pin is “H.” Executes
the next instruction when the level of INT
pin is “L.”
I12 = 0 : (INT) = “L” ?
I12 = 1 : (INT) = “H” ?
(I12 : bit 2 of the interrupt control register I1)
SNZP (Skip if Non Zero condition of Power down flag)
Instruction
code
Operation:
D0
D9
0
0
0
0
0
0
0
0
1
1
2
0
0
3
Number of
words
Number of
cycles
Flag CY
Skip condition
1
1
–
(P) = 1
16
(P) = 1 ?
Grouping:
Other operation
Description: Skips the next instruction when the P flag is
“1”.
After skipping, the P flag remains unchanged.
Executes the next instruction when the P
flag is “0.”
SNZT1 (Skip if Non Zero condition of Timer 1 interrupt request flag)
Instruction
code
Operation:
D9
1
D0
0
1
0
0
0
0
0
0
0
2
2
8
0
Number of
words
Number of
cycles
Flag CY
Skip condition
1
1
–
V12 = 0: (T1F) = 1
16
V12 = 0: (T1F) = 1 ?
After skipping, (T1F) ← 0
V12 = 1: SNZT1 = NOP
(V12 = bit 2 of interrupt control register V1)
Grouping:
Timer operation
Description: When V12 = 0 : Skips the next instruction
when timer 1 interrupt request flag T1F is
“1.” After skipping, clears (0) to the T1F
flag. When the T1F flag is “0,” executes the
next instruction.
When V12 = 1 : This instruction is equivalent to the NOP instruction.
SNZT2 (Skip if Non Zero condition of Timer 2 interrupt request flag)
Instruction
code
Operation:
D9
1
D0
0
1
0
0
0
0
0
0
1
V13 = 0: (T2F) = 1 ?
After skipping, (T2F) ← 0
V13 = 1: SNZT2 = NOP
(V13 = bit 3 of interrupt control register V1)
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2
2
8
1
16
Number of
words
Number of
cycles
Flag CY
Skip condition
1
1
–
V13 = 0: (T2F) = 1
Grouping:
Timer operation
Description: When V13 = 0 : Skips the next instruction
when timer 2 interrupt request flag T2F is
“1.” After skipping, clears (0) to the T2F
flag. When the T2F flag is “0,” executes the
next instruction.
When V13 = 1 : This instruction is equivalent to the NOP instruction.
4506 Group
MACHINE INSTRUCTIONS (INDEX BY ALPHABET) (continued)
SZB j (Skip if Zero, Bit)
Instruction
code
Operation:
D9
0
D0
0
0
0
1
0
0
0
j
j
2
0
2
j
16
(Mj(DP)) = 0 ?
j = 0 to 3
Number of
words
Number of
cycles
Flag CY
Skip condition
1
1
–
(Mj(DP)) = 0
j = 0 to 3
Grouping:
Bit operation
Description: Skips the next instruction when the contents of bit j (bit specified by the value j in
the immediate field) of M(DP) is “0.”
Executes the next instruction when the contents of bit j of M(DP) is “1.”
SZC (Skip if Zero, Carry flag)
Instruction
code
Operation:
D9
0
D0
0
0
0
1
0
1
1
1
1
2
0
2
F
16
(CY) = 0 ?
Number of
words
Number of
cycles
Flag CY
Skip condition
1
1
–
(CY) = 0
Grouping:
Arithmetic operation
Description: Skips the next instruction when the contents of carry flag CY is “0.”
After skipping, the CY flag remains unchanged.
Executes the next instruction when the contents of the CY flag is “1.“
SZD (Skip if Zero, port D specified by register Y)
Instruction
code
Operation:
D9
D0
0
0
0
0
1
0
0
1
0
0
0
0
0
0
1
0
1
0
1
1 2
2
0
2
4 16
0
2
B 16
Number of
words
Number of
cycles
Flag CY
Skip condition
2
2
–
(D(Y)) = 0
(Y) = 0 to 3
Grouping:
Input/Output operation
Description: Skips the next instruction when a bit of port
D specified by register Y is “0.” Executes the
next instruction when the bit is “1.”
Note:
Set 0 to 3 to register Y because port D is
four ports (D0–D3).
When values except above are set to register Y, this instruction is equivalent to the
NOP instruction.
(D(Y)) = 0 ?
(Y) = 0 to 3
T1AB (Transfer data to timer 1 and register R1 from Accumulator and register B)
Instruction
code
Operation:
D9
1
D0
0
0
0
1
1
(T17–T14) ← (B)
(R17–R14) ← (B)
(T13–T10) ← (A)
(R13–R10) ← (A)
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0
0
0
0
2
2
3
0
16
Number of
words
Number of
cycles
Flag CY
Skip condition
1
1
–
–
Grouping:
Timer operation
Description: Transfers the contents of register B to the
high-order 4 bits of timer 1 and timer 1 reload register R1. Transfers the contents of
register A to the low-order 4 bits of timer 1
and timer 1 reload register R1.
4506 Group
MACHINE INSTRUCTIONS (INDEX BY ALPHABET) (continued)
T2AB (Transfer data to timer 2 and register R2 from Accumulator and register B)
Instruction
code
Operation:
D9
1
D0
0
0
0
1
1
0
0
0
1
2
2
3
1 16
(T27–T24) ← (B)
(R27–R24) ← (B)
(T23–T20) ← (A)
(R23–R20) ← (A)
Number of
words
Number of
cycles
Flag CY
Skip condition
1
1
–
–
Grouping:
Timer operation
Description: Transfers the contents of register B to the
high-order 4 bits of timer 2 and timer 2 reload register R2. Transfers the contents of
register A to the low-order 4 bits of timer 2
and timer 2 reload register R2.
TAB (Transfer data to Accumulator from register B)
Instruction
code
Operation:
D0
D9
0
0
0
0
0
1
1
1
1
0
2
0
1
E
Number of
words
Number of
cycles
Flag CY
Skip condition
1
1
–
–
16
(A) ← (B)
Grouping:
Other operation
Description: Transfers the contents of register B to register A.
TAB1 (Transfer data to Accumulator and register B from timer 1)
Instruction
code
Operation:
D9
1
D0
0
0
1
1
1
0
0
0
0
2
2
7
0
Number of
words
Number of
cycles
Flag CY
Skip condition
1
1
–
–
16
(B) ← (T17–T14)
(A) ← (T13–T10)
Grouping:
Timer operation
Description: Transfers the high-order 4 bits (T17–T14) of
timer 1 to register B.
Transfers the low-order 4 bits (T13–T10) of
timer 1 to register A.
TAB2 (Transfer data to Accumulator and register B from timer 2)
Instruction
code
Operation:
D9
1
D0
0
0
1
1
1
(B) ← (T27–T24)
(A) ← (T23–T20)
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0
0
0
1
2
2
7
1
16
Number of
words
Number of
cycles
Flag CY
Skip condition
1
1
–
–
Grouping:
Timer operation
Description: Transfers the high-order 4 bits (T27–T24) of
timer 2 to register B.
Transfers the low-order 4 bits (T23–T20) of
timer 2 to register A.
4506 Group
MACHINE INSTRUCTIONS (INDEX BY ALPHABET) (continued)
TABAD (Transfer data to Accumulator and register B from register AD)
Instruction
code
Operation:
D9
1
D0
0
0
1
1
1
1
0
0
1
2
2
7
9 16
Number of
words
Number of
cycles
Flag CY
Skip condition
1
1
–
–
Grouping:
A/D conversion operation
Description: In the A/D conversion mode (Q13 = 0), transfers the high-order 4 bits (AD9–AD6) of register
AD to register B, and the middle-order 4 bits
(AD5–AD2) of register AD to register A. In the
comparator mode (Q13 = 1), transfers the highorder 4 bits (AD7–AD4) of comparator register
to register B, and the low-order 4 bits (AD3–
AD0) of comparator register to register A.
In A/D conversion mode (Q13 = 0),
(B) ← (AD9–AD6)
(A) ← (AD5–AD2)
In comparator mode (Q13 = 1),
(B) ← (AD7–AD4)
(A) ← (AD3–AD0)
(Q13 : bit 3 of A/D control register Q1)
TABE (Transfer data to Accumulator and register B from register E)
Instruction
code
Operation:
D9
0
D0
0
0
0
1
0
1
0
1
0
2
0
2
A 16
(B) ← (E7–E4)
(A) ← (E3–E0)
Number of
words
Number of
cycles
Flag CY
Skip condition
1
1
–
–
Grouping:
Register to register transfer
Description: Transfers the high-order 4 bits (E 7 –E4) of
register E to register B, and low-order 4 bits
of register E to register A.
TABP p (Transfer data to Accumulator and register B from Program memory in page p)
Instruction
code
Operation:
D9
0
D0
0
1
0
0
p4 p3 p2 p1 p0
2
0
8
+p
p
16
Number of
words
Number of
cycles
Flag CY
Skip condition
1
3
–
–
Grouping:
Arithmetic operation
Description: Transfers bits 7 to 4 to register B and bits 3 to
0 to register A. These bits 7 to 0 are the ROM
pattern in address (DR2 DR1 DR0 A3 A2 A1
A0)2 specified by registers A and D in page p.
Note:
p is 0 to 15 for M34506M2, and p is 0 to 31
for M34506M4/E4.
When this instruction is executed, be careful
not to over the stack because 1 stage of
stack register is used.
(SP) ← (SP) + 1
(SK(SP)) ← (PC)
(PCH) ← p
(PCL) ← (DR2–DR0, A3–A0)
(B) ← (ROM(PC))7–4
(A) ← (ROM(PC))3–0
(PC) ← (SK(SP))
(SP) ← (SP) – 1
TAD (Transfer data to Accumulator from register D)
Instruction
code
Operation:
D9
0
D0
0
0
1
0
1
(A2–A0) ← (DR2–DR0)
(A3) ← 0
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0
0
0
1
2
0
5
1
16
Number of
words
Number of
cycles
Flag CY
Skip condition
1
1
–
–
Grouping:
Register to register transfer
Description: Transfers the contents of register D to the
low-order 3 bits (A2–A0) of register A.
Note:
When this instruction is executed, “0” is
stored to the bit 3 (A3) of register A.
4506 Group
MACHINE INSTRUCTIONS (INDEX BY ALPHABET) (continued)
TADAB (Transfer data to register AD from Accumulator from register B)
Instruction
code
Operation:
D9
1
D0
0
0
0
1
1
1
0
0
1
2
2
3
9
16
Number of
words
Number of
cycles
Flag CY
Skip condition
1
1
–
–
Grouping:
A/D conversion operation
Description: In the A/D conversion mode (Q13 = 0), this instruction is equivalent to the NOP instruction.
In the comparator mode (Q13 = 1), transfers the contents of register B to the
high-order 4 bits (AD7–AD4) of comparator
register, and the contents of register A to
the low-order 4 bits (AD3–AD0) of comparator register.
(Q13 = bit 3 of A/D control register Q1)
(AD7–AD4) ← (B)
(AD3–AD0) ← (A)
TAI1 (Transfer data to Accumulator from register I1)
Instruction
code
Operation:
D0
D9
1
0
0
1
0
1
0
0
1
1
2
2
5
3
16
(A) ← (I1)
Number of
words
Number of
cycles
Flag CY
Skip condition
1
1
–
–
Grouping:
Interrupt operation
Description: Transfers the contents of interrupt control
register I1 to register A.
TAK0 (Transfer data to Accumulator from register K0)
Instruction
code
Operation:
D9
1
D0
0
0
1
0
1
0
1
1
0
2
2
5
6
16
(A) ← (K0)
Number of
words
Number of
cycles
Flag CY
Skip condition
1
1
–
–
Grouping:
Input/Output operation
Description: Transfers the contents of key-on wakeup
control register K0 to register A.
TAK1 (Transfer data to Accumulator from register K1)
Instruction
code
Operation:
D9
1
D0
0
0
1
0
1
1
(A) ← (K1)
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0
0
1
2
2
5
9
16
Number of
words
Number of
cycles
Flag CY
Skip condition
1
1
–
–
Grouping:
Input/Output operation
Description: Transfers the contents of key-on wakeup
control register K1 to register A.
4506 Group
MACHINE INSTRUCTIONS (INDEX BY ALPHABET) (continued)
TAK2 (Transfer data to Accumulator from register K2)
Instruction
code
Operation:
D9
1
D0
0
0
1
0
1
1
0
1
0 2
2
5
A 16
(A) ← (K2)
Number of
words
Number of
cycles
Flag CY
Skip condition
1
1
–
–
Grouping:
Input/Output operation
Description: Transfers the contents of key-on wakeup
control register K2 to register A.
TALA (Transfer data to Accumulator from register LA)
Instruction
code
Operation:
D9
1
D0
0
0
1
0
0
1
0
0
1
2
2
4
9 16
(A3, A2) ← (AD1, AD0)
(A1, A0) ← 0
Number of
words
Number of
cycles
Flag CY
Skip condition
1
1
–
–
Grouping:
A/D conversion operation
Description: Transfers the low-order 2 bits (AD1, AD0) of
register AD to the high-order 2 bits (A3, A2)
of register A.
Note:
After this instruction is executed, “0” is
stored to the low-order 2 bits (A 1 , A 0 ) of
register A.
TAM j (Transfer data to Accumulator from Memory)
Instruction
code
Operation:
D9
1
D0
0
1
1
0
0
j
j
j
j
2
2
C
j
16
(A) ← (M(DP))
(X) ← (X)EXOR(j)
j = 0 to 15
Number of
words
Number of
cycles
Flag CY
Skip condition
1
1
–
–
Grouping:
RAM to register transfer
Description: After transferring the contents of M(DP) to
register A, an exclusive OR operation is
performed between register X and the value
j in the immediate field, and stores the result in register X.
TAMR (Transfer data to Accumulator from register MR)
Instruction
code
Operation:
D9
1
D0
0
0
1
0
1
(A) ← (MR)
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0
0
1
0
2
2
5
2
16
Number of
words
Number of
cycles
Flag CY
Skip condition
1
1
–
–
Grouping:
Other operation
Description: Transfers the contents of clock control register MR to register A.
4506 Group
MACHINE INSTRUCTIONS (INDEX BY ALPHABET) (continued)
TAQ1 (Transfer data to Accumulator from register Q1)
Instruction
code
Operation:
D9
1
D0
0
0
1
0
0
0
1
0
0
2
2
4
4
16
(A) ← (Q1)
Number of
words
Number of
cycles
Flag CY
Skip condition
1
1
–
–
Grouping:
A/D conversion operation
Description: Transfers the contents of A/D control register Q1 to register A.
TASP (Transfer data to Accumulator from Stack Pointer)
Instruction
code
Operation:
D9
0
D0
0
0
1
0
1
0
0
0
0
2
0
5
0
16
(A2–A0) ← (SP2–SP0)
(A3) ← 0
Number of
words
Number of
cycles
Flag CY
Skip condition
1
1
–
–
Grouping:
Register to register transfer
Description: Transfers the contents of stack pointer (SP)
to the low-order 3 bits (A2–A0) of register A.
Note:
After this instruction is executed, “0” is
stored to the bit 3 (A3) of register A.
TAV1 (Transfer data to Accumulator from register V1)
Instruction
code
Operation:
D9
0
D0
0
0
1
0
1
0
1
0
0
2
0
5
4
16
(A) ← (V1)
Number of
words
Number of
cycles
Flag CY
Skip condition
1
1
–
–
Grouping:
Interrupt operation
Description: Transfers the contents of interrupt control
register V1 to register A.
TAV2 (Transfer data to Accumulator from register V2)
Instruction
code
Operation:
D9
0
D0
0
0
1
0
1
0
(A) ← (V2)
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1
0
1
2
0
5
5
16
Number of
words
Number of
cycles
Flag CY
Skip condition
1
1
–
–
Grouping:
Interrupt operation
Description: Transfers the contents of interrupt control
register V2 to register A.
4506 Group
MACHINE INSTRUCTIONS (INDEX BY ALPHABET) (continued)
TAW1 (Transfer data to Accumulator from register W1)
Instruction
code
Operation:
D9
1
D0
0
0
1
0
0
1
0
1
1
2
2
4
B 16
(A) ← (W1)
Number of
words
Number of
cycles
Flag CY
Skip condition
1
1
–
–
Grouping:
Timer operation
Description: Transfers the contents of timer control register W1 to register A.
TAW2 (Transfer data to Accumulator from register W2)
Instruction
code
Operation:
D9
1
D0
0
0
1
0
0
1
1
0
0
2
2
4
C
16
(A) ← (W2)
Number of
words
Number of
cycles
Flag CY
Skip condition
1
1
–
–
Grouping:
Timer operation
Description: Transfers the contents of timer control register W2 to register A.
TAW6 (Transfer data to Accumulator from register W6)
Instruction
code
Operation:
D9
1
D0
0
0
1
0
1
0
0
0
0
2
2
5
0
16
(A) ← (W6)
Number of
words
Number of
cycles
Flag CY
Skip condition
1
1
–
–
Grouping:
Timer operation
Description: Transfers the contents of timer control register W6 to register A.
TAX (Transfer data to Accumulator from register X)
Instruction
code
Operation:
D9
0
D0
0
0
1
0
1
(A) ← (X)
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0
0
1
0
2
0
5
2
16
Number of
words
Number of
cycles
Flag CY
Skip condition
1
1
–
–
Grouping:
Register to register transfer
Description: Transfers the contents of register X to register A.
page 80 of 111
4506 Group
MACHINE INSTRUCTIONS (INDEX BY ALPHABET) (continued)
TAY (Transfer data to Accumulator from register Y)
Instruction
code
Operation:
D9
0
D0
0
0
0
0
1
1
1
1
1 2
0
1
F 16
(A) ← (Y)
Number of
words
Number of
cycles
Flag CY
Skip condition
1
1
–
–
Grouping:
Register to register transfer
Description: Transfers the contents of register Y to register A.
TAZ (Transfer data to Accumulator from register Z)
Instruction
code
Operation:
D9
0
D0
0
0
1
0
1
0
0
1
1 2
0
5
3 16
(A1, A0) ← (Z1, Z0)
(A3, A2) ← 0
Number of
words
Number of
cycles
Flag CY
Skip condition
1
1
–
–
Grouping:
Register to register transfer
Description: Transfers the contents of register Z to the
low-order 2 bits (A1, A0) of register A.
Note:
After this instruction is executed, “0” is
stored to the high-order 2 bits (A3 , A 2) of
register A.
TBA (Transfer data to register B from Accumulator)
Instruction
code
Operation:
D9
0
D0
0
0
0
0
0
1
1
1
0
2
0
0
E
16
(B) ← (A)
Number of
words
Number of
cycles
Flag CY
Skip condition
1
1
–
–
Grouping:
Register to register transfer
Description: Transfers the contents of register A to register B.
TDA (Transfer data to register D from Accumulator)
Instruction
code
Operation:
D9
0
D0
0
0
0
1
0
(DR2–DR0) ← (A2–A0)
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1
0
0
1
2
0
2
9
16
Number of
words
Number of
cycles
Flag CY
Skip condition
1
1
–
–
Grouping:
Register to register transfer
Description: Transfers the contents of the low-order 3
bits (A2–A0) of register A to register D.
4506 Group
MACHINE INSTRUCTIONS (INDEX BY ALPHABET) (continued)
TEAB (Transfer data to register E from Accumulator and register B)
Instruction
code
Operation:
D9
0
D0
0
0
0
0
1
1
0
1
0
2
0
1
A 16
(E7–E4) ← (B)
(E3–E0) ← (A)
Number of
words
Number of
cycles
Flag CY
Skip condition
1
1
–
–
Grouping:
Register to register transfer
Description: Transfers the contents of register B to the
high-order 4 bits (E3–E0) of register E, and
the contents of register A to the low-order 4
bits (E3–E0) of register E.
TI1A (Transfer data to register I1 from Accumulator)
Instruction
code
Operation:
D9
1
D0
0
0
0
0
1
0
1
1
1
2
2
1
7 16
(I1) ← (A)
Number of
words
Number of
cycles
Flag CY
Skip condition
1
1
–
–
Grouping:
Interrupt operation
Description: Transfers the contents of register A to interrupt control register I1.
TK0A (Transfer data to register K0 from Accumulator)
Instruction
code
Operation:
D9
1
D0
0
0
0
0
1
1
0
1
1
2
2
1
B
16
(K0) ← (A)
Number of
words
Number of
cycles
Flag CY
Skip condition
1
1
–
–
Grouping:
Input/Output operation
Description: Transfers the contents of register A to keyon wakeup control register K0.
TK1A (Transfer data to register K1 from Accumulator)
Instruction
code
Operation:
D9
1
D0
0
0
0
0
1
(K1) ← (A)
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0
1
0
0
2
2
1
4
16
Number of
words
Number of
cycles
Flag CY
Skip condition
1
1
–
–
Grouping:
Input/Output operation
Description: Transfers the contents of register A to keyon wakeup control register K1.
4506 Group
MACHINE INSTRUCTIONS (INDEX BY ALPHABET) (continued)
TK2A (Transfer data to register K2 from Accumulator)
Instruction
code
Operation:
D9
1
D0
0
0
0
0
1
0
1
0
1
2
2
1
5
16
(K2) ← (A)
Number of
words
Number of
cycles
Flag CY
Skip condition
1
1
–
–
Grouping:
Input/Output operation
Description: Transfers the contents of register A to keyon wakeup control register K2.
TMA j (Transfer data to Memory from Accumulator)
Instruction
code
Operation:
D9
1
D0
0
1
0
1
1
j
j
j
j
2
2
B
j
16
(M(DP)) ← (A)
(X) ← (X)EXOR(j)
j = 0 to 15
Number of
words
Number of
cycles
Flag CY
Skip condition
1
1
–
–
Grouping:
RAM to register transfer
Description: After transferring the contents of register A
to M(DP), an exclusive OR operation is performed between register X and the value j
in the immediate field, and stores the result
in register X.
TMRA (Transfer data to register MR from Accumulator)
Instruction
code
Operation:
D9
1
D0
0
0
0
0
1
0
1
1
0
2
2
1
6
16
(MR) ← (A)
Number of
words
Number of
cycles
Flag CY
Skip condition
1
1
–
–
Grouping:
Other operation
Description: Transfers the contents of register A to clock
control register MR.
TPU0A (Transfer data to register PU0 from Accumulator)
Instruction
code
Operation:
D9
1
D0
0
0
0
1
0
(PU0) ← (A)
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1
1
0
1
2
2
2
D
16
Number of
words
Number of
cycles
Flag CY
Skip condition
1
1
–
–
Grouping:
Input/Output operation
Description: Transfers the contents of register A to pullup control register PU0.
4506 Group
MACHINE INSTRUCTIONS (INDEX BY ALPHABET) (continued)
TPU1A (Transfer data to register PU1 from Accumulator)
Instruction
code
Operation:
D9
1
D0
0
0
0
1
0
1
1
1
0
2
2
2
E
16
(PU1) ← (A)
Number of
words
Number of
cycles
Flag CY
Skip condition
1
1
–
–
Grouping:
Input/Output operation
Description: Transfers the contents of register A to pullup control register PU1.
TPU2A (Transfer data to register PU2 from Accumulator)
Instruction
code
Operation:
D9
1
D0
0
0
0
1
0
1
1
1
1
2
2
2
F
16
(PU2) ← (A)
Number of
words
Number of
cycles
Flag CY
Skip condition
1
1
–
–
Grouping:
Input/Output operation
Description: Transfers the contents of register A to pullup control register PU2.
TQ1A (Transfer data to register Q1 from Accumulator)
Instruction
code
Operation:
D9
1
D0
0
0
0
0
0
0
1
0
0
2
2
0
4
16
(Q1) ← (A)
Number of
words
Number of
cycles
Flag CY
Skip condition
1
1
–
–
Grouping:
A/D conversion operation
Description: Transfers the contents of register A to A/D
control register Q1.
TR1AB (Transfer data to register R1 from Accumulator and register B)
Instruction
code
Operation:
D9
1
D0
0
0
0
1
1
1
(R17–R14) ← (B)
(R13–R10) ← (A)
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1
1
1
2
2
3
F
16
Number of
words
Number of
cycles
Flag CY
Skip condition
1
1
–
–
Grouping:
Timer operation
Description: Transfers the contents of register B to the
high-order 4 bits (R17–R14) of reload register R1, and the contents of register A to the
low-order 4 bits (R13–R10) of reload register R1.
4506 Group
MACHINE INSTRUCTIONS (INDEX BY ALPHABET) (continued)
TV1A (Transfer data to register V1 from Accumulator)
Instruction
code
Operation:
D9
0
D0
0
0
0
1
1
1
1
1
1 2
0
3
F 16
(V1) ← (A)
Number of
words
Number of
cycles
Flag CY
Skip condition
1
1
–
–
Grouping:
Interrupt operation
Description: Transfers the contents of register A to interrupt control register V1.
TV2A (Transfer data to register V2 from Accumulator)
Instruction
code
Operation:
D9
0
D0
0
0
0
1
1
1
1
1
0 2
0
3
E 16
(V2) ← (A)
Number of
words
Number of
cycles
Flag CY
Skip condition
1
1
–
–
Grouping:
Interrupt operation
Description: Transfers the contents of register A to interrupt control register V2.
TW1A (Transfer data to register W1 from Accumulator)
Instruction
code
Operation:
D9
1
D0
0
0
0
0
0
1
1
1
0
2
2
0
E
16
(W1) ← (A)
Number of
words
Number of
cycles
Flag CY
Skip condition
1
1
–
–
Grouping:
Timer operation
Description: Transfers the contents of register A to timer
control register W1.
TW2A (Transfer data to register W2 from Accumulator)
Instruction
code
Operation:
D9
1
D0
0
0
0
0
0
(W2) ← (A)
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1
1
1
1
2
2
0
F
16
Number of
words
Number of
cycles
Flag CY
Skip condition
1
1
–
–
Grouping:
Timer operation
Description: Transfers the contents of register A to timer
control register W2.
4506 Group
MACHINE INSTRUCTIONS (INDEX BY ALPHABET) (continued)
TW6A (Transfer data to register W6 from Accumulator)
Instruction
code
Operation:
D9
1
D0
0
0
0
0
1
0
0
1
1 2
2
1
3 16
(W6) ← (A)
Number of
words
Number of
cycles
Flag CY
Skip condition
1
1
–
–
Grouping:
Timer operation
Description: Transfers the contents of register A to timer
control register W6.
TYA (Transfer data to register Y from Accumulator)
Instruction
code
Operation:
D9
0
D0
0
0
0
0
0
1
1
0
0
2
0
0
C
16
(Y) ← (A)
Number of
words
Number of
cycles
Flag CY
Skip condition
1
1
–
–
Grouping:
Register to register transfer
Description: Transfers the contents of register A to register Y.
WRST (Watchdog timer ReSeT)
Instruction
code
Operation:
D9
1
D0
0
1
0
1
0
0
0
0
0
2
2
A
0
16
(WDF1) = 1 ?
After skipping, (WDF1) ← 0
Number of
words
Number of
cycles
Flag CY
Skip condition
1
1
–
(WDF1) = 1
Grouping:
Other operation
Description: Skips the next instruction when watchdog
timer flag WDF1 is “1.” After skipping, clears
(0) to the WDF1 flag. When the WDF1 flag
is “0,” executes the next instruction. Also,
stops the watchdog timer function when executing the WRST instruction immediately
after the DWDT instruction.
XAM j (eXchange Accumulator and Memory data)
Instruction
code
Operation:
D9
1
D0
0
1
1
0
1
(A) ←→ (M(DP))
(X) ← (X)EXOR(j)
j = 0 to 15
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j
j
j
j
2
2
D
j
16
Number of
words
Number of
cycles
Flag CY
Skip condition
1
1
–
–
Grouping:
RAM to register transfer
Description: After exchanging the contents of M(DP)
with the contents of register A, an exclusive
OR operation is performed between register X and the value j in the immediate field,
and stores the result in register X.
4506 Group
MACHINE INSTRUCTIONS (INDEX BY ALPHABET) (continued)
XAMD j (eXchange Accumulator and Memory data and Decrement register Y and skip)
Instruction
code
Operation:
D9
1
D0
0
1
1
1
1
j
j
j
j
2
2
F
j
16
Number of
words
Number of
cycles
Flag CY
Skip condition
1
1
–
(Y) = 15
Grouping:
RAM to register transfer
Description: After exchanging the contents of M(DP)
with the contents of register A, an exclusive
OR operation is performed between register X and the value j in the immediate field,
and stores the result in register X.
Subtracts 1 from the contents of register Y.
As a result of subtraction, when the contents of register Y is 15, the next instruction
is skipped. When the contents of register Y
is not 15, the next instruction is executed.
(A) ←→ (M(DP))
(X) ← (X)EXOR(j)
j = 0 to 15
(Y) ← (Y) – 1
XAMI j (eXchange Accumulator and Memory data and Increment register Y and skip)
Instruction
code
D9
1
D0
0
1
1
Operation:
(A) ←→ (M(DP))
(X) ← (X)EXOR(j)
j = 0 to 15
(Y) ← (Y) + 1
Instruction
code
D9
1
0
j
j
j
j
2
j
16
D0
D9
page 87 of 111
Flag CY
Skip condition
1
1
–
(Y) = 0
Number of
words
Number of
cycles
Flag CY
Skip condition
Number of
words
Number of
cycles
Flag CY
Skip condition
16
D0
2
Rev.3.01 2005.02.07
REJ03B0106-0301
E
Number of
cycles
Grouping:
RAM to register transfer
Description: After exchanging the contents of M(DP)
with the contents of register A, an exclusive
OR operation is performed between register X and the value j in the immediate field,
and stores the result in register X.
Adds 1 to the contents of register Y. As a result of addition, when the contents of
register Y is 0, the next instruction is
skipped. when the contents of register Y is
not 0, the next instruction is executed.
2
Instruction
code
2
Number of
words
16
4506 Group
MACHINE INSTRUCTIONS (INDEX BY TYPES)
Number of
words
Number of
cycles
Instruction code
TAB
0
0
0
0
0
1
1
1
1
0
0 1 E
1
1
(A) ← (B)
TBA
0
0
0
0
0
0
1
1
1
0
0 0 E
1
1
(B) ← (A)
TAY
0
0
0
0
0
1
1
1
1
1
0 1 F
1
1
(A) ← (Y)
TYA
0
0
0
0
0
0
1
1
0
0
0 0 C
1
1
(Y) ← (A)
TEAB
0
0
0
0
0
1
1
0
1
0
0 1 A
1
1
(E7–E4) ← (B)
(E3–E0) ← (A)
TABE
0
0
0
0
1
0
1
0
1
0
0 2 A
1
1
(B) ← (E7–E4)
(A) ← (E3–E0)
TDA
0
0
0
0
1
0
1
0
0
1
0 2 9
1
1
(DR2–DR0) ← (A2–A0)
TAD
0
0
0
1
0
1
0
0
0
1
0 5 1
1
1
(A2–A0) ← (DR2–DR0)
(A3) ← 0
TAZ
0
0
0
1
0
1
0
0
1
1
0 5 3
1
1
(A1, A0) ← (Z1, Z0)
(A3, A2) ← 0
TAX
0
0
0
1
0
1
0
0
1
0
0 5 2
1
1
(A) ← (X)
TASP
0
0
0
1
0
1
0
0
0
0
0 5 0
1
1
(A2–A0) ← (SP2–SP0)
(A3) ← 0
LXY x, y
1
1
x3 x2 x1 x0 y3 y2 y1 y0
3 x y
1
1
(X) ← x x = 0 to 15
(Y) ← y y = 0 to 15
LZ z
0
0
0
1
0
0
1
0
z1 z0
0 4 8
+z
1
1
(Z) ← z z = 0 to 3
INY
0
0
0
0
0
1
0
0
1
1
0 1 3
1
1
(Y) ← (Y) + 1
DEY
0
0
0
0
0
1
0
1
1
1
0 1 7
1
1
(Y) ← (Y) – 1
TAM j
1
0
1
1
0
0
j
j
j
j
2 C j
1
1
(A) ← (M(DP))
(X) ← (X)EXOR(j)
j = 0 to 15
XAM j
1
0
1
1
0
1
j
j
j
j
2 D j
1
1
(A) ← → (M(DP))
(X) ← (X)EXOR(j)
j = 0 to 15
XAMD j
1
0
1
1
1
1
j
j
j
j
2 F j
1
1
(A) ← → (M(DP))
(X) ← (X)EXOR(j)
j = 0 to 15
(Y) ← (Y) – 1
XAMI j
1
0
1
1
1
0
j
j
j
j
2 E j
1
1
(A) ← → (M(DP))
(X) ← (X)EXOR(j)
j = 0 to 15
(Y) ← (Y) + 1
TMA j
1
0
1
0
1
1
j
j
j
j
2 B j
1
1
(M(DP)) ← (A)
(X) ← (X)EXOR(j)
j = 0 to 15
Parameter
Mnemonic
RAM to register transfer
RAM addresses
Register to register transfer
Type of
instructions
D9 D8 D7 D6 D 5 D 4 D 3 D 2 D 1 D 0
Rev.3.01 2005.02.07
REJ03B0106-0301
page 88 of 111
Hexadecimal
notation
Function
Skip condition
Carry flag CY
4506 Group
–
–
Transfers the contents of register B to register A.
–
–
Transfers the contents of register A to register B.
–
–
Transfers the contents of register Y to register A.
–
–
Transfers the contents of register A to register Y.
–
–
Transfers the contents of register B to the high-order 4 bits (E3–E0) of register E, and the contents of register A to the low-order 4 bits (E3–E0) of register E.
–
–
Transfers the high-order 4 bits (E7–E4) of register E to register B, and low-order 4 bits of register E to register A.
–
–
Transfers the contents of the low-order 3 bits (A2–A0) of register A to register D.
–
–
Transfers the contents of register D to the low-order 3 bits (A2–A0) of register A.
–
–
Transfers the contents of register Z to the low-order 2 bits (A1, A0) of register A.
–
–
Transfers the contents of register X to register A.
–
–
Transfers the contents of stack pointer (SP) to the low-order 3 bits (A2–A0) of register A.
Continuous
description
–
Loads the value x in the immediate field to register X, and the value y in the immediate field to register Y.
When the LXY instructions are continuously coded and executed, only the first LXY instruction is executed
and other LXY instructions coded continuously are skipped.
–
–
Loads the value z in the immediate field to register Z.
(Y) = 0
–
Adds 1 to the contents of register Y. As a result of addition, when the contents of register Y is 0, the next instruction is skipped. When the contents of register Y is not 0, the next instruction is executed.
(Y) = 15
–
Subtracts 1 from the contents of register Y. As a result of subtraction, when the contents of register Y is 15,
the next instruction is skipped. When the contents of register Y is not 15, the next instruction is executed.
–
–
After transferring the contents of M(DP) to register A, an exclusive OR operation is performed between register X and the value j in the immediate field, and stores the result in register X.
–
–
After exchanging the contents of M(DP) with the contents of register A, an exclusive OR operation is performed between register X and the value j in the immediate field, and stores the result in register X.
(Y) = 15
–
After exchanging the contents of M(DP) with the contents of register A, an exclusive OR operation is performed between register X and the value j in the immediate field, and stores the result in register X.
Subtracts 1 from the contents of register Y. As a result of subtraction, when the contents of register Y is 15,
the next instruction is skipped. When the contents of register Y is not 15, the next instruction is executed.
(Y) = 0
–
After exchanging the contents of M(DP) with the contents of register A, an exclusive OR operation is performed between register X and the value j in the immediate field, and stores the result in register X.
Adds 1 to the contents of register Y. As a result of addition, when the contents of register Y is 0, the next instruction is skipped. when the contents of register Y is not 0, the next instruction is executed.
–
–
After transferring the contents of register A to M(DP), an exclusive OR operation is performed between register X and the value j in the immediate field, and stores the result in register X.
Rev.3.01 2005.02.07
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Datailed description
page 89 of 111
4506 Group
MACHINE INSTRUCTIONS (INDEX BY TYPES) (continued)
Arithmetic operation
Bit operation
Comparison
operation
D9 D8 D7 D6 D 5 D 4 D 3 D 2 D 1 D 0
notation
Number of
cycles
Mnemonic
Type of
instructions
Number of
words
Instruction code
Parameter
0 7 n
1
1
(A) ← n
n = 0 to 15
Hexadecimal
Function
LA n
0
0
0
1
1
1
TABP p
0
0
1
0
0
p4 p3 p2 p1 p0
0 8 p
+p
1
3
(SP) ← (SP) + 1
(SK(SP)) ← (PC)
(PCH) ← p (Note)
(PCL) ← (DR2–DR0, A3–A0)
(B) ← (ROM(PC))7–4
(A) ← (ROM(PC))3–0
(PC) ← (SK(SP))
(SP) ← (SP) – 1
AM
0
0
0
0
0
0
1
0
1
0
0 0 A
1
1
(A) ← (A) + (M(DP))
AMC
0
0
0
0
0
0
1
0
1
1
0 0 B
1
1
(A) ← (A) + (M(DP)) +(CY)
(CY) ← Carry
An
0
0
0
1
1
0
n
n
n
n
0 6 n
1
1
(A) ← (A) + n
n = 0 to 15
AND
0
0
0
0
0
1
1
0
0
0
0 1 8
1
1
(A) ← (A) AND (M(DP))
OR
0
0
0
0
0
1
1
0
0
1
0 1 9
1
1
(A) ← (A) OR (M(DP))
SC
0
0
0
0
0
0
0
1
1
1
0 0 7
1
1
(CY) ← 1
RC
0
0
0
0
0
0
0
1
1
0
0 0 6
1
1
(CY) ← 0
SZC
0
0
0
0
1
0
1
1
1
1
0 2 F
1
1
(CY) = 0 ?
CMA
0
0
0
0
0
1
1
1
0
0
0 1 C
1
1
(A) ← (A)
RAR
0
0
0
0
0
1
1
1
0
1
0 1 D
1
1
→ CY → A3A2A1A0
SB j
0
0
0
1
0
1
1
1
j
j
0 5 C
+j
1
1
(Mj(DP)) ← 1
j = 0 to 3
RB j
0
0
0
1
0
0
1
1
j
j
0 4 C
+j
1
1
(Mj(DP)) ← 0
j = 0 to 3
SZB j
0
0
0
0
1
0
0
0
j
j
0 2 j
1
1
(Mj(DP)) = 0 ?
j = 0 to 3
SEAM
0
0
0
0
1
0
0
1
1
0
0 2 6
1
1
(A) = (M(DP)) ?
SEA n
0
0
0
0
1
0
0
1
0
1
0 2 5
2
2
(A) = n ?
n = 0 to 15
0
0
0
1
1
1
n
n
n
n
0 7 n
n
n
Note : p is 0 to 15 for M34506M2, p is 0 to 31 for M34506M4/E4.
Rev.3.01 2005.02.07
REJ03B0106-0301
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n
n
Skip condition
Carry flag CY
4506 Group
Datailed description
Continuous
description
–
Loads the value n in the immediate field to register A.
When the LA instructions are continuously coded and executed, only the first LA instruction is executed and
other LA instructions coded continuously are skipped.
–
–
Transfers bits 7 to 4 to register B and bits 3 to 0 to register A. These bits 7 to 0 are the ROM pattern in address (DR2 DR1 DR0 A3 A2 A1 A0)2 specified by registers A and D in page p.
When this instruction is executed, be careful not to over the stack because 1 stage of stack register is used.
–
–
Adds the contents of M(DP) to register A. Stores the result in register A. The contents of carry flag CY remains unchanged.
–
0/1 Adds the contents of M(DP) and carry flag CY to register A. Stores the result in register A and carry flag CY.
Overflow = 0
–
Adds the value n in the immediate field to register A, and stores a result in register A.
The contents of carry flag CY remains unchanged.
Skips the next instruction when there is no overflow as the result of operation.
Executes the next instruction when there is overflow as the result of operation.
–
–
Takes the AND operation between the contents of register A and the contents of M(DP), and stores the result in register A.
–
–
Takes the OR operation between the contents of register A and the contents of M(DP), and stores the result
in register A.
–
1
Sets (1) to carry flag CY.
–
0
Clears (0) to carry flag CY.
(CY) = 0
–
Skips the next instruction when the contents of carry flag CY is “0.”
–
–
Stores the one’s complement for register A’s contents in register A.
–
0/1 Rotates 1 bit of the contents of register A including the contents of carry flag CY to the right.
–
–
Sets (1) the contents of bit j (bit specified by the value j in the immediate field) of M(DP).
–
–
Clears (0) the contents of bit j (bit specified by the value j in the immediate field) of M(DP).
(Mj(DP)) = 0
j = 0 to 3
–
Skips the next instruction when the contents of bit j (bit specified by the value j in the immediate field) of
M(DP) is “0.”
Executes the next instruction when the contents of bit j of M(DP) is “1.”
(A) = (M(DP))
–
Skips the next instruction when the contents of register A is equal to the contents of M(DP).
Executes the next instruction when the contents of register A is not equal to the contents of M(DP).
(A) = n
–
Skips the next instruction when the contents of register A is equal to the value n in the immediate field.
Executes the next instruction when the contents of register A is not equal to the value n in the immediate
field.
Rev.3.01 2005.02.07
REJ03B0106-0301
page 91 of 111
4506 Group
MACHINE INSTRUCTIONS (INDEX BY TYPES) (continued)
Number of
words
Number of
cycles
Instruction code
Ba
0
1
1
a6 a5 a4 a3 a2 a1 a0
1 8 a
+a
1
1
(PCL) ← a6–a0
BL p, a
0
0
1
1
p4 p3 p2 p1 p0
0 E p
+p
2
2
(PCH) ← p (Note)
(PCL) ← a6–a0
1
0
0
a6 a5 a4 a3 a2 a1 a0
2 a a
0
0
0
0
0
1
0
0 1 0
2
2
(PCH) ← p (Note)
(PCL) ← (DR2–DR0, A3–A0)
1
0
0
p4 0
0
p3 p2 p1 p0
2 p p
BM a
0
1
0
a6 a5 a4 a3 a2 a1 a0
1 a a
1
1
(SP) ← (SP) + 1
(SK(SP)) ← (PC)
(PCH) ← 2
(PCL) ← a6–a0
BML p, a
0
0
1
1
p4 p3 p2 p1 p0
0 C p
+p
2
2
1
0
0
a6 a5 a4 a3 a2 a1 a0
2 a a
(SP) ← (SP) + 1
(SK(SP)) ← (PC)
(PCH) ← p (Note)
(PCL) ← a6–a0
0
0
0
0
1
1
0
0 3 0
2
2
1
0
0
p4 0
0
p3 p2 p1 p0
2 p p
(SP) ← (SP) + 1
(SK(SP)) ← (PC)
(PCH) ← p (Note)
(PCL) ← (DR2–DR0,A3–A0)
RTI
0
0
0
1
0
0
0
1
1
0
0 4 6
1
1
(PC) ← (SK(SP))
(SP) ← (SP) – 1
RT
0
0
0
1
0
0
0
1
0
0
0 4 4
1
2
(PC) ← (SK(SP))
(SP) ← (SP) – 1
RTS
0
0
0
1
0
0
0
1
0
1
0 4 5
1
2
(PC) ← (SK(SP))
(SP) ← (SP) – 1
Parameter
Mnemonic
Return operation
Subroutine operation
Branch operation
Type of
instructions
D9 D8 D7 D6 D 5 D 4 D 3 D 2 D 1 D 0
BLA p
BMLA p
1
0
0
0
Note : p is 0 to 15 for M34506M2, p is 0 to 31 for M34506M4/E4.
Rev.3.01 2005.02.07
REJ03B0106-0301
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0
0
0
0
Hexadecimal
notation
Function
Skip condition
Carry flag CY
4506 Group
–
–
Branch within a page : Branches to address a in the identical page.
–
–
Branch out of a page : Branches to address a in page p.
–
–
Branch out of a page : Branches to address (DR2 DR1 DR0 A3 A2 A1 A0)2 specified by registers D and A in
page p.
–
–
Call the subroutine in page 2 : Calls the subroutine at address a in page 2.
–
–
Call the subroutine : Calls the subroutine at address a in page p.
–
–
Call the subroutine : Calls the subroutine at address (DR2 DR1 DR0 A3 A2 A1 A0)2 specified by registers D
and A in page p.
–
–
Returns from interrupt service routine to main routine.
Returns each value of data pointer (X, Y, Z), carry flag, skip status, NOP mode status by the continuous description of the LA/LXY instruction, register A and register B to the states just before interrupt.
–
–
Returns from subroutine to the routine called the subroutine.
Skip at uncondition
–
Returns from subroutine to the routine called the subroutine, and skips the next instruction at uncondition.
Rev.3.01 2005.02.07
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Datailed description
page 93 of 111
4506 Group
MACHINE INSTRUCTIONS (INDEX BY TYPES) (continued)
Number of
words
Number of
cycles
Instruction code
DI
0
0
0
0
0
0
0
1
0
0
0 0 4
1
1
(INTE) ← 0
EI
0
0
0
0
0
0
0
1
0
1
0 0 5
1
1
(INTE) ← 1
SNZ0
0
0
0
0
1
1
1
0
0
0
0 3 8
1
1
V10 = 0: (EXF0) = 1 ?
After skipping, (EXF0) ← 0
V10 = 1: SNZ0 = NOP
SNZI0
0
0
0
0
1
1
1
0
1
0
0 3 A
1
1
I12 = 0 : (INT) = “L” ?
Parameter
Mnemonic
Timer operation
Interrupt operation
Type of
instructions
D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
Hexadecimal
notation
Function
I12 = 1 : (INT) = “H” ?
TAV1
0
0
0
1
0
1
0
1
0
0
0 5 4
1
1
(A) ← (V1)
TV1A
0
0
0
0
1
1
1
1
1
1
0 3 F
1
1
(V1) ← (A)
TAV2
0
0
0
1
0
1
0
1
0
1
0 5 5
1
1
(A) ← (V2)
TV2A
0
0
0
0
1
1
1
1
1
0
0 3 E
1
1
(V2) ← (A)
TAI1
1
0
0
1
0
1
0
0
1
1
2 5 3
1
1
(A) ← (I1)
TI1A
1
0
0
0
0
1
0
1
1
1
2 1 7
1
1
(I1) ← (A)
TAW1
1
0
0
1
0
0
1
0
1
1
2 4 B
1
1
(A) ← (W1)
TW1A
1
0
0
0
0
0
1
1
1
0
2 0 E
1
1
(W1) ← (A)
TAW2
1
0
0
1
0
0
1
1
0
0
2 4 C
1
1
(A) ← (W2)
TW2A
1
0
0
0
0
0
1
1
1
1
2 0 F
1
1
(W2) ← (A)
TAW6
1
0
0
1
0
1
0
0
0
0
2 5 0
1
1
(A) ← (W6)
TW6A
1
0
0
0
0
1
0
0
1
1
2 1 3
1
1
(W6) ← (A)
TAB1
1
0
0
1
1
1
0
0
0
0
2 7 0
1
1
(B) ← (T17–T14)
(A) ← (T13–T10)
T1AB
1
0
0
0
1
1
0
0
0
0
2 3 0
1
1
(T17–T14) ← (B)
(R17–R14) ← (B)
(T13–T10) ← (A)
(R13–R10) ← (A)
TAB2
1
0
0
1
1
1
0
0
0
1
2 7 1
1
1
(B) ← (T27–T24)
(A) ← (T23–T20)
T2AB
1
0
0
0
1
1
0
0
0
1
2 3 1
1
1
(T27–T24) ← (B)
(R27–R24) ← (B)
(T23–T20) ← (A)
(R23–R20) ← (A)
TR1AB
1
0
0
0
1
1
1
1
1
1
2 3 F
1
1
(R17–R14) ← (B)
(R13–R10) ← (A)
SNZT1
1
0
1
0
0
0
0
0
0
0
2 8 0
1
1
V12 = 0: (T1F) = 1 ?
After skipping, (T1F) ← 0
V12 = 1: SNZT1 = NOP
SNZT2
1
0
1
0
0
0
0
0
0
1
2 8 1
1
1
V13 = 0: (T2F) = 1 ?
After skipping, (T2F) ← 0
V13 = 1: SNZT2 = NOP
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Skip condition
Carry flag CY
4506 Group
–
–
Clears (0) to interrupt enable flag INTE, and disables the interrupt.
–
–
Sets (1) to interrupt enable flag INTE, and enables the interrupt.
V10 = 0: (EXF0) = 1
–
When V10 = 0 : Skips the next instruction when external 0 interrupt request flag EXF0 is “1.” After skipping,
clears (0) to the EXF0 flag. When the EXF0 flag is “0,” executes the next instruction.
When V10 = 1 : This instruction is equivalent to the NOP instruction. (V10: bit 0 of interrupt control register
V1)
(INT) = “L”
However, I12 = 0
–
When I12 = 0 : Skips the next instruction when the level of INT pin is “L.” Executes the next instruction when
the level of INT pin is “H.”
(INT) = “H”
However, I12 = 1
Datailed description
When I12 = 1 : Skips the next instruction when the level of INT pin is “H.” Executes the next instruction when
the level of INT pin is “L.” (I12: bit 2 of interrupt control register I1)
–
–
Transfers the contents of interrupt control register V1 to register A.
–
–
Transfers the contents of register A to interrupt control register V1.
–
–
Transfers the contents of interrupt control register V2 to register A.
–
–
Transfers the contents of register A to interrupt control register V2.
–
–
Transfers the contents of interrupt control register I1 to register A.
–
–
Transfers the contents of register A to interrupt control register I1.
–
–
Transfers the contents of timer control register W1 to register A.
–
–
Transfers the contents of register A to timer control register W1.
–
–
Transfers the contents of timer control register W2 to register A.
–
–
Transfers the contents of register A to timer control register W2.
–
–
Transfers the contents of timer control register W6 to register A.
–
–
Transfers the contents of register A to timer control register W6.
–
–
Transfers the high-order 4 bits (T17–T14) of timer 1 to register B.
Transfers the low-order 4 bits (T13–T10) of timer 1 to register A.
–
–
Transfers the contents of register B to the high-order 4 bits of timer 1 and timer 1 reload register R1. Transfers the contents of register A to the low-order 4 bits of timer 1 and timer 1 reload register R1.
–
–
Transfers the high-order 4 bits (T27–T24) of timer 2 to register B.
Transfers the low-order 4 bits (T23–T20) of timer 2 to register A.
–
–
Transfers the contents of register B to the high-order 4 bits of timer 2 and timer 2 reload register R2. Transfers the contents of register A to the low-order 4 bits of timer 2 and timer 2 reload register R2.
–
–
Transfers the contents of register B to the high-order 4 bits (R17–R14) of reload register R1, and the contents of register A to the low-order 4 bits (R13–R10) of reload register R1.
V12 = 0: (T1F) = 1
–
When V12 = 0 : Skips the next instruction when timer 1 interrupt request flag T1F is “1.” After skipping,
clears (0) to the T1F flag. When the T1F flag is “0,” executes the next instruction.
When V12 = 1 : This instruction is equivalent to the NOP instruction. (V12: bit 2 of interrupt control register V1)
V13 = 0: (T2F) =1
–
When V13 = 0 : Skips the next instruction when timer 1 interrupt request flag T2F is “1.” After skipping,
clears (0) to the T2F flag. When the T2F flag is “0,” executes the next instruction.
When V13 = 1 : This instruction is equivalent to the NOP instruction. (V13: bit 3 of interrupt control register V1)
Rev.3.01 2005.02.07
REJ03B0106-0301
page 95 of 111
4506 Group
MACHINE INSTRUCTIONS (INDEX BY TYPES) (continued)
Number of
words
Number of
cycles
Instruction code
IAP0
1
0
0
1
1
0
0
0
0
0
2 6 0
1
1
(A) ← (P0)
OP0A
1
0
0
0
1
0
0
0
0
0
2 2 0
1
1
(P0) ← (A)
IAP1
1
0
0
1
1
0
0
0
0
1
2 6 1
1
1
(A) ← (P1)
OP1A
1
0
0
0
1
0
0
0
0
1
2 2 1
1
1
(P1) ← (A)
IAP2
1
0
0
1
1
0
0
0
1
0
2 6 2
1
1
(A1, A0) ← (P21, P20)
(A3, A2) ← 0
OP2A
1
0
0
0
1
0
0
0
1
0
2 2 2
1
1
(P21, P20) ← (A1, A0)
CLD
0
0
0
0
0
1
0
0
0
1
0 1 1
1
1
(D) ← 1
RD
0
0
0
0
0
1
0
1
0
0
0 1 4
1
1
(D(Y)) ← 0
(Y) = 0 to 3
SD
0
0
0
0
0
1
0
1
0
1
0 1 5
1
1
(D(Y)) ← 1
(Y) = 0 to 3
SZD
0
0
0
0
1
0
0
1
0
0
0 2 4
2
2
(D(Y)) = 0 ?
(Y) = 0 to 3
0
0
0
0
1
0
1
0
1
1
0 2 B
SCP
1
0
1
0
0
0
1
1
0
1
2 8 D
1
1
(C) ← 1
RCP
1
0
1
0
0
0
1
1
0
0
2 8 C
1
1
(C) ← 0
SNZCP
1
0
1
0
0
0
1
0
0
1
2 8 9
1
1
(C) = 1?
IAK
1
0
0
1
1
0
1
1
1
1
2 6 F
1
1
(A0) ← (K)
(A3–A1) ← 0
OKA
1
0
0
0
0
1
1
1
1
1
2 1 F
1
1
(K) ← (A0)
TK0A
1
0
0
0
0
1
1
0
1
1
2 1 B
1
1
(K0) ← (A)
TAK0
1
0
0
1
0
1
0
1
1
0
2 5 6
1
1
(A) ← (K0)
TK1A
1
0
0
0
0
1
0
1
0
0
2 1 4
1
1
(K1) ← (A)
TAK1
1
0
0
1
0
1
1
0
0
1
2 5 9
1
1
(A) ← (K1)
TK2A
1
0
0
0
0
1
0
1
0
1
2 1 5
1
1
(K2) ← (A)
TAK2
1
0
0
1
0
1
1
0
1
0
2 5 A
1
1
(A) ← (K2)
TPU0A
1
0
0
0
1
0
1
1
0
1
2 2 D
1
1
(PU0) ← (A)
TPU1A
1
0
0
0
1
0
1
1
1
0
2 2 E
1
1
(PU1) ← (A)
TPU2A
1
0
0
0
1
0
1
1
1
1
2 2 F
1
1
(PU2) ← (A)
Parameter
Mnemonic
Input/Output operation
Type of
instructions
D9 D8 D7 D6 D 5 D 4 D 3 D 2 D 1 D 0
Rev.3.01 2005.02.07
REJ03B0106-0301
page 96 of 111
Hexadecimal
notation
Function
Skip condition
Carry flag CY
4506 Group
–
–
Transfers the input of port P0 to register A.
–
–
Outputs the contents of register A to port P0.
–
–
Transfers the input of port P1 to register A.
–
–
Outputs the contents of register A to port P1.
–
–
Transfers the input of port P2 to the low-order 2 bits (A1, A0) of register A.
–
–
Outputs the contents of the low-order 2 bits (A1, A0) of register A to port P2.
–
–
Sets (1) to port D.
–
–
Clears (0) to a bit of port D specified by register Y.
–
–
Sets (1) to a bit of port D specified by register Y.
(D(Y)) = 0 ?
(Y) = 0 to 3
–
Skips the next instruction when a bit of port D specified by register Y is “0.” Executes the next instruction
when a bit of port D specified by register Y is “1.”
–
–
Sets (1) to port C.
–
–
Clears (0) to port C.
(C) = 1
–
Skips the next instruction when the contents of port C is “1.”
Executes the next instruction when the contents of port C is “0.”
–
–
Transfers the contents of port K to the bit 0 (A0) of register A.
–
–
Outputs the contents of bit 0 (A0) of register A to port K.
–
–
Transfers the contents of register A to key-on wakeup control register K0.
–
–
Transfers the contents of key-on wakeup control register K0 to register A.
–
–
Transfers the contents of register A to key-on wakeup control register K1.
–
–
Transfers the contents of key-on wakeup control register K1 to register A.
–
–
Transfers the contents of register A to key-on wakeup control register K2.
–
–
Transfers the contents of key-on wakeup control register K2 to register A.
–
–
Transfers the contents of register A to pull-up control register PU0.
–
–
Transfers the contents of register A to pull-up control register PU1.
–
–
Transfers the contents of register A to pull-up control register PU2.
Rev.3.01 2005.02.07
REJ03B0106-0301
Datailed description
page 97 of 111
4506 Group
MACHINE INSTRUCTIONS (INDEX BY TYPES) (continued)
Number of
words
Number of
cycles
Instruction code
TABAD
1
0
0
1
1
1
1
0
0
1
2 7 9
1
1
In A/D conversion mode (Q13 = 0),
(B) ← (AD9–AD6)
(A) ← (AD5–AD2)
In comparator mode (Q13 = 1),
(B) ← (AD7–AD4)
(A) ← (AD3–AD0)
TALA
1
0
0
1
0
0
1
0
0
1
2 4 9
1
1
(A3, A2) ← (AD1, AD0)
(A1, A0) ← 0
TADAB
1
0
0
0
1
1
1
0
0
1
2 3 9
1
1
(AD7–AD4) ← (B)
(AD3–AD0) ← (A)
TAQ1
1
0
0
1
0
0
0
1
0
0
2 4 4
1
1
(A) ← (Q1)
TQ1A
1
0
0
0
0
0
0
1
0
0
2 0 4
1
1
(Q1) ← (A)
ADST
1
0
1
0
0
1
1
1
1
1
2 9 F
1
1
(ADF) ← 0
Q13 = 0: A/D conversion starting
Q13 = 1: Comparator operation starting
SNZAD
1
0
1
0
0
0
0
1
1
1
2 8 7
1
1
V22 = 0: (ADF) = 1 ?
After skipping, (ADF) ← 0
V22 = 1: SNZAD = NOP
NOP
0
0
0
0
0
0
0
0
0
0
0 0 0
1
1
(PC) ← (PC) + 1
POF2
0
0
0
0
0
0
1
0
0
0
0 0 8
1
1
RAM back-up
EPOF
0
0
0
1
0
1
1
0
1
1
0 5 B
1
1
POF2 instruction valid
SNZP
0
0
0
0
0
0
0
0
1
1
0 0 3
1
1
(P) = 1 ?
DWDT
1
0
1
0
0
1
1
1
0
0
2 9 C
1
1
Stop of watchdog timer function enabled
WRST
1
0
1
0
1
0
0
0
0
0
2 A 0
1
1
(WDF1) = 1 ?,
after skipping,
(WDF1) ← 0
CMCK
1
0
1
0
0
1
1
0
1
0
2 9 A
1
1
Ceramic resonator selected
CRCK
1
0
1
0
0
1
1
0
1
1
2 9 B
1
1
RC oscillation selected
TAMR
1
0
0
1
0
1
0
0
1
0
2 5 2
1
1
(A) ← (MR)
TMRA
1
0
0
0
0
1
0
1
1
0
2 1 6
1
1
(MR) ← (A)
Parameter
Mnemonic
Other operation
A/D conversion operation
Type of
instructions
D9 D8 D7 D6 D 5 D 4 D 3 D 2 D 1 D 0
Rev.3.01 2005.02.07
REJ03B0106-0301
page 98 of 111
Hexadecimal
notation
Function
Skip condition
Carry flag CY
4506 Group
–
–
In the A/D conversion mode (Q13 = 0), transfers the high-order 4 bits (AD9–AD6) of register AD to register
B, and the middle-order 4 bits (AD5–AD2) of register AD to register A.
In the comparator mode (Q13 = 1), transfers the high-order 4 bits (AD7–AD4) of comparator register to register B, and the low-order 4 bits (AD3–AD0) of comparator register to register A.
(Q13: bit 3 of A/D control register Q1)
–
–
Transfers the low-order 2 bits (AD1, AD0) of register AD to the high-order 2 bits (AD3, AD2) of register A.
–
–
In the A/D conversion mode (Q13 = 0), this instruction is equivalent to the NOP instruction.
In the comparator mode (Q13 = 1), transfers the contents of register B to the high-order 4 bits (AD7–AD4) of
comparator register, and the contents of register A to the low-order 4 bits (AD3–AD0) of comparator register.
(Q13 = bit 3 of A/D control register Q1)
–
–
Transfers the contents of A/D control register Q1 to register A.
–
–
Transfers the contents of register A to A/D control register Q1.
–
–
Clears (0) to A/D conversion completion flag ADF, and the A/D conversion at the A/D conversion mode (Q13
= 0) or the comparator operation at the comparator mode (Q13 = 1) is started.
(Q13 = bit 3 of A/D control register Q1)
V22 = 0: (ADF) = 1
–
When V22 = 0 : Skips the next instruction when A/D conversion completion flag ADF is “1.” After skipping,
clears (0) to the ADF flag. When the ADF flag is “0,” executes the next instruction.
When V22 = 1 : This instruction is equivalent to the NOP instruction. (V22: bit 2 of interrupt control register V2)
–
–
No operation; Adds 1 to program counter value, and others remain unchanged.
–
–
Puts the system in RAM back-up state by executing the POF2 instruction after executing the EPOF instruction.
Operations of all functions are stopped.
–
–
Makes the immediate after POF2 instruction valid by executing the EPOF instruction.
(P) = 1
–
Skips the next instruction when the P flag is “1”.
After skipping, the P flag remains unchanged.
Executes the next instruction when the P flag is “0.”
–
–
Stops the watchdog timer function by the WRST instruction after executing the DWDT instruction.
(WDF1) = 1
–
Skips the next instruction when watchdog timer flag WDF1 is “1.” After skipping, clears (0) to the WDF1 flag.
When the WDF1 flag is “0,” executes the next instruction. Also, stops the watchdog timer function when executing the WRST instruction immediately after the DWDT instruction.
–
–
Selects the ceramic resonance circuit and stops the on-chip oscillator.
–
–
Selects the RC oscillation circuit and stops the on-chip oscillator.
–
–
Transfers the contents of clock control register MR to register A.
–
–
Transfers the contents of register A to clock control register MR.
Rev.3.01 2005.02.07
REJ03B0106-0301
Datailed description
page 99 of 111
4506 Group
INSTRUCTION CODE TABLE
D9–D4 000000 000001 000010 000011 000100 000101 000110 000111 001000 001001 001010 001011 001100 001101 001110 001111
010000 011000
010111 011111
Hex.
D3–D0 notation
00
01
02
03
04
05
06
07
08
09
0A
0B
0C
0D
0E
0F
10–17 18–1F
0000
0
NOP
BLA
SZB
BMLA
0
–
TASP
A
0
LA
0
TABP TABP
0
16*
–
–
BML BML*
BL
BL*
BM
B
0001
1
–
CLD
SZB
1
–
–
TAD
A
1
LA
1
TABP TABP
1
17*
–
–
BML BML*
BL
BL*
BM
B
0010
2
–
–
SZB
2
–
–
TAX
A
2
LA
2
TABP TABP
2
18*
–
–
BML BML*
BL
BL*
BM
B
0011
3
SZB
3
–
–
TAZ
A
3
LA
3
TABP TABP
3
19*
–
–
BML BML*
BL
BL*
BM
B
0100
4
DI
RD
SZD
–
RT
TAV1
A
4
LA
4
TABP TABP
4
20*
–
–
BML BML*
BL
BL*
BM
B
0101
5
EI
SD
SEAn
–
RTS TAV2
A
5
LA
5
TABP TABP
5
21*
–
–
BML BML*
BL
BL*
BM
B
0110
6
RC
–
SEAM
–
RTI
–
A
6
LA
6
TABP TABP
6
22*
–
–
BML BML*
BL
BL*
BM
B
0111
7
SC
DEY
–
–
–
–
A
7
LA
7
TABP TABP
7
23*
–
–
BML BML*
BL
BL*
BM
B
1000
8
POF2 AND
–
SNZ0
LZ
0
–
A
8
LA
8
TABP TABP
8
24*
–
–
BML BML*
BL
BL*
BM
B
1001
9
–
TDA
–
LZ
1
–
A
9
LA
9
TABP TABP
9
25*
–
–
BML BML*
BL
BL*
BM
B
1010
A
AM
TEAB TABE SNZI0
LZ
2
–
A
10
LA
10
TABP TABP
10
26*
–
–
BML BML*
BL
BL*
BM
B
1011
B
AMC
–
–
–
LZ
3
EPOF
A
11
LA
11
TABP TABP
11
27*
–
–
BML BML*
BL
BL*
BM
B
1100
C
TYA
CMA
–
–
RB
0
SB
0
A
12
LA
12
TABP TABP
12
28*
–
–
BML BML*
BL
BL*
BM
B
1101
D
–
RAR
–
–
RB
1
SB
1
A
13
LA
13
TABP TABP
13
29*
–
–
BML BML*
BL
BL*
BM
B
1110
E
TBA
TAB
–
TV2A
RB
2
SB
2
A
14
LA
14
TABP TABP
14
30*
–
–
BML BML*
BL
BL*
BM
B
1111
F
–
TAY
SZC TV1A
RB
3
SB
3
A
15
LA
15
TABP TABP
15
31*
–
–
BML BML*
BL
BL*
BM
B
SNZP INY
OR
The above table shows the relationship between machine language codes and machine language instructions. D3–D0 show the low-order
4 bits of the machine language code, and D9–D4 show the high-order 6 bits of the machine language code. The hexadecimal representation of the code is also provided. There are one-word instructions and two-word instructions, but only the first word of each instruction is
shown. Do not use code marked “–.”
The codes for the second word of a two-word instruction are described below.
BL
BML
BLA
BMLA
SEA
SZD
The second word
10 0aaa aaaa
10 0aaa aaaa
10 0p00 pppp
10 0p00 pppp
00 0111 nnnn
00 0010 1011
Rev.3.01 2005.02.07
REJ03B0106-0301
• * cannot be used in the M34506M2-XXXFP.
page 100 of 111
4506 Group
INSTRUCTION CODE TABLE (continued)
D9–D4 100000 100001 100010 100011 100100 100101 100110 100111 101000 101001 101010 101011 101100 101101 101110 101111
110000
111111
Hex.
D3–D0 notation
20
21
22
23
24
25
0000
0
–
–
OP0A T1AB
–
0001
1
–
–
OP1A T2AB
–
0010
2
–
–
OP2A
–
–
0011
3
–
TW6A
–
–
–
TAI1
0100
4
TQ1A TK1A
–
–
TAQ1
0101
5
–
TK2A
–
–
0110
6
–
TMRA
–
0111
7
–
TI1A
1000
8
–
1001
9
1010
26
27
28
TAW6 IAP0 TAB1 SNZT1
–
IAP1 TAB2 SNZT2
29
2A
2B
2C
2D
2E
2F
30–3F
–
WRST
TMA
0
TAM XAM XAMI XAMD LXY
0
0
0
0
–
–
TMA
1
TAM XAM XAMI XAMD LXY
1
1
1
1
–
–
–
–
TMA
2
TAM XAM XAMI XAMD LXY
2
2
2
2
–
–
–
–
–
TMA
3
TAM XAM XAMI XAMD LXY
3
3
3
3
–
–
–
–
–
–
TMA
4
TAM XAM XAMI XAMD LXY
4
4
4
4
–
–
–
–
–
–
–
TMA
5
TAM XAM XAMI XAMD LXY
5
5
5
5
–
–
TAK0
–
–
–
–
–
TMA
6
TAM XAM XAMI XAMD LXY
6
6
6
6
–
–
–
–
–
–
SNZAD
–
–
TMA
7
TAM XAM XAMI XAMD LXY
7
7
7
7
–
–
–
–
–
–
–
–
–
–
TMA
8
TAM XAM XAMI XAMD LXY
8
8
8
8
–
–
–
–
–
TMA
9
TAM XAM XAMI XAMD LXY
9
9
9
9
A
–
–
–
–
–
TAK2
–
–
–
CMCK
–
TMA
10
TAM XAM XAMI XAMD LXY
10
10
10
10
1011
B
–
TK0A
–
–
TAW1
–
–
–
–
CRCK
–
TMA
11
TAM XAM XAMI XAMD LXY
11
11
11
11
1100
C
–
–
–
–
TAW2
–
–
–
RCP DWDT
–
TMA
12
TAM XAM XAMI XAMD LXY
12
12
12
12
1101
D
–
–
TPU0A
–
–
–
–
–
SCP
–
–
TMA
13
TAM XAM XAMI XAMD LXY
13
13
13
13
1110
E
TW1A
–
TPU1A
–
–
–
–
–
–
–
–
TMA
14
TAM XAM XAMI XAMD LXY
14
14
14
14
1111
F
TW2A OKA TPU2ATR1AB
–
–
IAK
–
–
ADST
–
TMA
15
TAM XAM XAMI XAMD
LXY
15
15
15
15
TAMR IAP2
TADAB TALA TAK1
–
TABAD SNZCP
The above table shows the relationship between machine language codes and machine language instructions. D3–D0 show the loworder 4 bits of the machine language code, and D9–D4 show the high-order 6 bits of the machine language code. The hexadecimal
representation of the code is also provided. There are one-word instructions and two-word instructions, but only the first word of
each instruction is shown. Do not use code marked “–.”
The codes for the second word of a two-word instruction are described below.
BL
BML
BLA
BMLA
SEA
SZD
The second word
10 0aaa aaaa
10 0aaa aaaa
10 0p00 pppp
10 0p00 pppp
00 0111 nnnn
00 0010 1011
Rev.3.01 2005.02.07
REJ03B0106-0301
page 101 of 111
4506 Group
Electrical characteristics
Absolute maximum ratings
Parameter
Symbol
VDD
VI
Supply voltage
VI
Input voltage AIN0–AIN1
VO
Output voltage P0, P1, P2, D 0, D1, D2/C, D3/K,
Input voltage P0, P1, P2, D0, D1, D2/C, D3/K,
RESET, XIN
RESET
VO
Pd
Conditions
Output transistors in cut-off state
Output voltage XOUT
Topr
Power dissipation
Operating temperature range
Tstg
Storage temperature range
Rev.3.01 2005.02.07
REJ03B0106-0301
page 102 of 111
Ta = 25 °C
Ratings
–0.3 to 6.5
–0.3 to VDD+0.3
Unit
V
V
–0.3 to VDD+0.3
–0.3 to VDD+0.3
V
V
–0.3 to VDD+0.3
300
–20 to 85
–40 to 125
V
mW
°C
°C
4506 Group
Recommended operating conditions 1
(Ta = –20 °C to 85 °C, VDD = 2.0 to 5.5 V, unless otherwise noted)
Symbol
VDD
Parameter
Conditions
Limits
Typ.
Supply voltage
High-speed mode
f(XIN) ≤ 4.4 MHz
2.7
Max.
5.5
(with a ceramic resonator)
Middle-speed mode
f(XIN) ≤ 4.4 MHz
2.0
5.5
f(XIN) ≤ 4.4 MHz
2.7
5.5
Min.
Unit
V
Low-speed mode
Default mode
VDD
Supply voltage
High-speed mode
(with RC oscillation)
Middle-speed mode
Low-speed mode
V
Default mode
VRAM
RAM back-up voltage
VSS
Supply voltage
(at RAM back-up)
VIH
“H” level input voltage
P0, P1, P2, D0–D3, XIN
VIH
VIH
“H” level input voltage
“H” level input voltage
RESET
V
V
1.8
0
C, K
0.8VDD
VDD
V
0.85VDD
VDD
VDD
V
VDD = 4.0 to 5.5 V
0.5VDD
VDD = 2.0 to 5.5 V
0.7VDD
0.85VDD
VDD
VDD
V
VIH
“H” level input voltage
CNTR, INT
VIL
“L” level input voltage
P0, P1, P2, D0–D3, XIN
0
0.2VDD
V
V
VIL
“L” level input voltage
C, K
0
0.16VDD
V
VIL
VIL
“L” level input voltage
“L” level input voltage
RESET
0
V
CNTR, INT
0
0.3VDD
0.15VDD
IOL(peak)
“L” level peak output current
P2, RESET
VDD = 5.0 V
10
mA
“L” level peak output current
D 0 , D1
VDD = 3.0 V
VDD = 5.0 V
4.0
IOL(peak)
40
mA
VDD = 3.0 V
VDD = 5.0 V
30
24
mA
VDD = 3.0 V
12
P0, P1
VDD = 5.0 V
24
12
P2, RESET (Note)
VDD = 3.0 V
VDD = 5.0 V
IOL(peak)
IOL(peak)
IOL(avg)
“L” level peak output current
“L” level peak output current
“L” level average output current
D2/C, D3/K
IOL(avg)
IOL(avg)
ΣIOL(avg)
“L” level average output current
“L” level average output current
“L” level average output current
“L” level total average current
D0, D1 (Note)
mA
VDD = 5.0 V
2.0
30
mA
VDD = 3.0 V
15
D2/C, D3/K (Note)
VDD = 5.0 V
15
7.0
P0, P1 (Note)
VDD = 3.0 V
VDD = 5.0 V
12
mA
VDD = 3.0 V
6.0
80
mA
P2, D, RESET
P0, P1
Note : The average output current (IOH, IOL) is the average value during 100 ms.
Rev.3.01 2005.02.07
REJ03B0106-0301
page 103 of 111
mA
5.0
VDD = 3.0 V
IOL(avg)
V
80
mA
4506 Group
Except ceramic resonator and high-speed mode
Ceramic resonator and high-speed mode selected
f [MHz]
f [MHz]
4.4
4.4
Recommended operating
condition
Recommended operating
condition
2.2
2.0
2.7
5.5
VDD[V]
2.0
5.5
VDD[V]
External clock input, high-speed mode selected
(ceramic resonator selected)
RC oscillation circuit selected
f [MHz]
f [MHz]
4.4
3.2
Recommended operating
condition
Recommended operating
condition
1.6
2.7
5.5
VDD[V]
Except external clock input, high-speed mode
(ceramic resonator selected)
f [MHz]
3.2
Recommended operating
condition
2.0
Rev.3.01 2005.02.07
REJ03B0106-0301
5.5
page 104 of 111
VDD[V]
2.0
2.7
5.5
VDD[V]
4506 Group
Recommended operating conditions 2
(Ta = –20 °C to 85 °C, VDD = 2.0 to 5.5 V, unless otherwise noted)
Symbol
f(XIN)
Parameter
Oscillation frequency
(with a ceramic resonator)
Conditions
High-speed mode
Middle-speed mode
Min.
Limits
Typ.
Max.
4.4
VDD = 2.7 V to 5.5 V
VDD = 2.0 V to 5.5 V
Unit
MHz
VDD = 2.0 V to 5.5 V
2.2
4.4
VDD = 2.7 V to 5.5 V
4.4
MHz
VDD = 2.7 V to 5.5 V
3.2
MHz
VDD = 2.0 V to 5.5 V
1.6
VDD = 2.0 V to 5.5 V
3.2
Low-speed mode
Default mode
f(XIN)
Oscillation frequency
High-speed mode
(with RC oscillation) (Note)
Middle-speed mode
Low-speed mode
Default mode
f(XIN)
Oscillation frequency
High-speed mode
(with a ceramic resonator selected,
external clock input)
Middle-speed mode
Low-speed mode
Default mode
∆ f(XIN)
Oscillation frequency error
VDD = 5.0 V ±10 %, Ta = 25 °C, –20 to 85 °C
±17
VDD = 3.0 V ±10 %, Ta = 25 °C, –20 to 85 °C
±17
%
(at RC oscillation, error value of
exteranal R, C not included)
Note: use 30 pF capacitor and vary external R
f(CNTR)
Timer external input frequency
High-speed mode
f(XIN)/6
Middle-speed mode
f(XIN)/12
f(XIN)/24
Low-speed mode
tw(CNTR) Timer external input period
(“H” and “L” pulse width)
Default mode
High-speed mode
f(XIN)/48
3/f(XIN)
Low-speed mode
6/f(XIN)
12/f(XIN)
Default mode
24/f(XIN)
Middle-speed mode
Hz
s
Note: The frequency at RC oscillation is affected by a capacitor, a resistor and a microcomputer. So, set the constants within the range of the frequency limits.
Rev.3.01 2005.02.07
REJ03B0106-0301
page 105 of 111
4506 Group
Electrical characteristics
Symbol
VOL
(Ta = –20 °C to 85 °C, VDD = 2.0 to 5.5 V, unless otherwise noted)
Parameter
“L” level output voltage
P0, P1
Test conditions
VDD = 5.0 V
“L” level output voltage
“L” level output voltage
IOL = 6.0 mA
0.9
IOL = 2.0 mA
0.6
VDD = 5.0 V
IOL = 5.0 mA
2.0
0.6
VDD = 3.0 V
IOL = 1.0 mA
IOL = 2.0 mA
VDD = 5.0 V
IOL = 30 mA
0.9
2.0
IOL = 10 mA
0.9
IOL = 15 mA
2.0
IOL = 5.0 mA
0.9
IOL = 15 mA
IOL = 5.0 mA
2.0
D0, D1
VDD = 3.0 V
VOL
“L” level output voltage
VDD = 5.0 V
D2/C, D3/K
VDD = 3.0 V
IIH
“H” level input current
IOL = 12 mA
Max.
2.0
0.9
P2, RESET
VOL
Typ.
IOL = 4.0 mA
VDD = 3.0 V
VOL
Limits
Min.
IOL = 9.0 mA
0.9
2.0
IOL = 3.0 mA
0.9
Unit
V
V
V
V
VI = VDD
1.0
µA
1.0
µA
P0, P1, P2, RESET
IIH
“H” level input current
VI = VDD
IIL
D0, D1, D2/C, D3/K
“L” level input current
VI = 0 V P0, P1, P2 No pull-up
–1.0
µA
VI = 0 V, D2/C, D3/K, No pull-up
–1.0
µA
P0, P1, P2
IIL
“L” level input current
IDD
D0, D1, D2/C, D3/K
Supply current at active mode
(Note 1)
VDD = 5.0 V
f(XIN) = 4.0 MHz
High-speed mode
Middle-speed mode
1.7
Low-speed mode
Default mode
1.0
3.0
VDD = 3.0 V
High-speed mode
0.5
1.5
f(XIN) = 2.0 MHz
Middle-speed mode
0.4
1.2
Low-speed mode
Default mode
0.35
1.1
0.9
0.3
0.1
at RAM back-up mode
Ta = 25 °C
(POF2 instruction execution) VDD = 5.0 V
Pull-up resistor value
VI = 0 V
P0, P1, P2, D2/C, D3/K, RESET
VT+ – VT– Hysteresis INT, CNTR
VDD = 5.0 V
VT+ – VT– Hysteresis RESET
VDD = 3.0 V
VDD = 5.0 V
On-chip oscillator clock frequency (Note VDD = 5.0 V
2)
VDD = 3.0 V
3.3
1.0
µA
6.0
VDD = 5.0 V
30
60
150
VDD = 3.0 V
50
120
300
VDD = 3.0 V
f(RING)
mA
10
VDD = 3.0 V
RPU
5.0
3.9
1.3
1.1
kΩ
0.25
0.25
V
1.2
V
0.5
1.0
2.0
3.0
0.5
1.0
1.8
MHz
Notes 1: When the A/D converter is used, the A/D operation current (IADD) is included.
2: When system operates by the on-chip oscillator, the system clock frequency is the on-chip oscillator clock divided by the dividing ratio selected with
register MR.
Rev.3.01 2005.02.07
REJ03B0106-0301
page 106 of 111
4506 Group
A/D converter recommended operating conditions
(Comparator mode included, Ta = –20 °C to 85 °C, unless otherwise noted)
Symbol
Parameter
VDD
Supply voltage
VIA
f(XIN)
Analog input voltage
Oscillation frequency
Conditions
Limits
Typ.
Max.
Ta = 25 °C
Min.
2.7
Ta = –20 °C to 85 °C
3.0
5.5
5.5
0
VDD+2LSB
VDD = 2.7 V to 5.5 V
High-speed mode
0.1
Middle-speed mode
0.2
Low-speed mode
Default mode
0.4
0.8
Unit
V
V
MHz
A/D converter characteristcs
(Comparator mode included, Ta = –20 °C to 85 °C, unless otherwise noted)
Symbol
–
Test conditions
Parameter
Min.
Limits
Typ.
bits
LSB
±0.9
LSB
20
9
30
mV
5125
5135
3069
3075
0.3
0.9
0.3
mA
High-speed mode
Middle-speed mode
46.5
µs
Low-speed mode
186
Default mode
372
Ta = 25 °C, VDD = 2.7 V to 5.5 V
Linearity error
Unit
10
±2.0
Resolution
–
Max.
Ta = –25 °C to 85 °C, VDD = 3.0 V to 5.5 V
–
Differential non-linearity error
Ta = 25 °C, VDD = 2.7 V to 5.5 V
Ta = –25 °C to 85 °C, VDD = 3.0 V to 5.5 V
V0T
Zero transition voltage
VDD = 5.12 V
VDD = 3.072 V
10
VFST
Full-scale transition voltage
VDD = 5.12 V
5115
3063
IADD
A/D operating current (Note 1)
TCONV
A/D conversion time
3
VDD = 3.072 V
VDD = 5.0 V
VDD = 3.0 V
–
–
–
f(XIN) = 4.0 MHz
Comparator resolution
Comparator error (Note 2)
VDD = 5.12 V
Comparator comparison time
VDD = 3.072 V
f(XIN) = 4.0 MHz
0.1
15
mV
93.0
8
±20
bits
mV
±15
High-speed mode
6.0
Middle-speed mode
12
Low-speed mode
24
Default mode
48
µs
Notes 1: When the A/D converter is used, the IADD is included to IDD.
2: As for the error from the logic value in the comparator mode, when the contents of the comparator register is n, the logic value of the comparison
voltage Vref which is generated by the built-in DA converter can be obtained by the following formula.
Logic value of comparison voltage Vref
Vref =
VDD
256
✕n
n = Value of register AD (n = 0 to 255)
Rev.3.01 2005.02.07
REJ03B0106-0301
page 107 of 111
4506 Group
Basic timing diagram
Machine cycle
Parameter
Pin name
Clock
XIN : high-speed mode
(System clock = f(XIN))
XIN : middle-speed mode
(System clock = f(XIN)/2)
XIN : low-speed mode
(System clock = f(XIN)/4)
XIN : default mode
(System clock = f(XIN)/8)
Port D output
D0, D1, D2/C, D3/K
Port D input
D0, D1, D2/C, D3/K
Port P0, P1, P2
output
P00–P03
P10–P13
P20, P21
Port P0, P1, P2
input
P00–P03
P10–P13
P20, P21
Timer output
CNTR
Timer input
CNTR
Interrupt input
INT
Rev.3.01 2005.02.07
REJ03B0106-0301
page 108 of 111
Mi
Mi+1
4506 Group
BUILT-IN PROM VERSION
In addition to the mask ROM versions, the 4506 Group has the
One Time PROM versions whose PROMs can only be written to
and not be erased.
The built-in PROM version has functions similar to those of the
mask ROM versions, but it has PROM mode that enables writing to
built-in PROM.
Table 20 shows the product of built-in PROM version. Figure 54
shows the pin configurations of built-in PROM versions.
The One Time PROM version has pin-compatibility with the mask
ROM version.
Table 20 Product of built-in PROM version
PROM size
Part number
(✕ 10 bits)
M34506E4FP
4096 words
RAM size
(✕ 4 bits)
256 words
Package
PRSP0020DA-A
ROM type
One Time PROM [shipped in blank]
(1) PROM mode
The 4506 Group has a PROM mode in addition to a normal operation mode. It has a function to serially input/output the command
codes, addresses, and data required for operation (e.g., read and
program) on the built-in PROM using only a few pins. This mode
can be selected by setting pins SDA (serial data input/output),
SCLK (serial clock input), PGM to “H” after connecting wires as
shown in Figure 54 and powering on the VDD pin, and then applying 12 V to the VPP pin.
In the PROM mode, three types of software commands (read, program, and program verify) can be used. Clock-synchronous serial
I/O is used, beginning from the LSB (LSB first).
Use the special-perpose serial programmer when performing serial
read/program.
As for the serial programmer for the single-chip microcomputer (serial programmer and control software), refer to the “Renesas
Microcomputer Development Support Tools” Hompage (http://
www.renesas.com/en/tools).
(2) Notes on handling
➀A high-voltage is used for writing. Take care that overvoltage is
not applied. Take care especially at turning on the power.
➁For the One Time PROM version shipped in blank, Renesas
corp. does not perform PROM writing test and screening in the
assembly process and following processes. In order to improve
reliability after writing, performing writing and test according to
the flow shown in Figure 53 before using is recommended (Products shipped in blank: PROM contents is not written in factory
when shipped).
Rev.3.01 2005.02.07
REJ03B0106-0301
page 109 of 111
Writing with PROM programmer
Screening (Leave at 150 °C for 40 hours) (Note)
Verify test with PROM programmer
Function test in target device
Note: Since the screening temperature is higher
than storage temperature, never expose the
microcomputer to 150 °C exceeding 100
hours.
Fig. 53 Flow of writing and test of the product shipped in blank
4506 Group
PIN CONFIGURATION (TOP VIEW)
VDD
1
20
P00
VSS
VSS
2
19
P01
XIN
3
18
P02
XOUT
4
17
P03
CNVSS
5
16
P10
RESET
6
15
P11
P21/AIN1
7
14
P12/CNTR
13
P13/INT
VPP
SCLK
VDD
M34506E4FP
VDD
SDA
P20/AIN0
8
PGM
D3/K
9
12
D0
D2/C
10
11
D1
Outline PRSP0020DA-A (20P2N-A)
Fig. 54 Pin configuration of built-in PROM version
Rev.3.01 2005.02.07
REJ03B0106-0301
page 110 of 111
4506 Group
Package outline
JEITA Package Code
RENESAS Code
Previous Code
MASS[Typ.]
P-SOP20-5.3x12.6-1.27
PRSP0020DA-A
20P2N-A
0.3g
20
E
*1
HE
11
F
1
NOTE)
1. DIMENSIONS "*1" AND "*2"
DO NOT INCLUDE MOLD FLASH.
2. DIMENSION "*3" DOES NOT
INCLUDE TRIM OFFSET.
10
c
Index mark
*2
A2
D
A1
L
A
Reference
Symbol
Nom
Max
D
12.5
12.6
12.7
E
5.2
5.3
5.4
A2
*3
e
Dimension in Millimeters
Min
bp
0
0.1
0.2
bp
0.35
0.4
0.5
c
0.18
0.2
0.25
A1
y
1.8
A
Detail F
2.1
0°
8°
HE
7.5
7.8
8.1
e
1.12
1.27
1.42
0.4
0.6
0.8
y
L
Rev.3.01 2005.02.07
REJ03B0106-0301
page 111 of 111
0.1
REVISION DESCRIPTION LIST
Rev.
No.
4506 GROUP DATA SHEET
Revision Description
Rev.
date
1.0
First Edition
000808
1.1
Pages 3, 4, 22, 38 : Character fonts errors revised
000905
2.0
The 4506/4507 Group data sheet is separated.
010531
Page 10: Port block diagram (3); Block diagram of P12/CNTR pin revised.
Page 26: Fig. 22 Timers structure; Block diagram of P12/CNTR pin revised.
Page 29:
(9) Precautions → (8) Precautions
(8) Timer input/output pin (P12/CNTR pin) added.
Fig. 23 added.
Page 30:
WATCHDOG TIMER revised all.
Page 31:
Fig. 24 → Fig. 25, Fig. 25 → Fig. 26
Fig. 26 NOP instruction added. POF → POF2
Page 49:
Fig. 46 POF → POF2
Page 61:
BL p, a, BLA p instructions revised.
Page 62:
BML p, a, BMLA p instructions revised.
Page 76:
TABP p instruction revised.
Page 90:
TABP p instruction revised.
Page 92:
BL p, a, BLA p, BML p, a, BMLA p instructions revised.
Page 100: BL, BML, BLA, BMLA instructions; The second word revised.
Page 101: BL, BML, BLA, BMLA instructions; The second word revised.
Page 102: ABSOLUTE MAXIMUM RATINGS; VDD –0.3 to 6.0 → –0.3 to 6.5
Page 104: RECOMMENDED OPERATING CONDITIONS 1;
Operating condition map added.
3.0
All pages: Words standardized: On-chip oscillator, A/D converter
Page 3:
Power dissipation “Ta=25°C” added.
Page 4:
Description of RESET pin revised.
Page 24:
Table 9 : Control register of timer 1 and timer 2 revised.
Page 25:
Fig.22 : Note 5 added.
Page 29:
Some description revised.
Page 30:
Fig.25 : “DI” instruction added.
Page 31:
Table 11: Revised.
Page 39:
Table 15 : Port level and Note 4 revised, Note 5 added.
Page 50:
21
Electric Characteristic Differences Between Mask ROM and One Time PROM Version MCU,
22
Note on Power Source Voltage added.
____________
Page 76:
TABAD : Description revised.
Page 99:
TABAD : Description revised.
(1/2)
040827
REVISION DESCRIPTION LIST
Rev.
Revision Description
No.
3.01
4506 GROUP DATA SHEET
Page 1, 3: Package name revised.
date
050207
Page 28:
•Timer 1 and timer 2 count start timing and count time when operation starts added.
Page 47:
10
Timer 1 and timer 2 count start timing and count time when operation starts added.
P109, 110: Package name revised.
P111:
Rev.
Package outline revised.
(2/2)
Sales Strategic Planning Div.
Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100-0004, Japan
Keep safety first in your circuit designs!
1. Renesas Technology Corp. puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble
may occur with them. Trouble with semiconductors may lead to personal injury, fire or property damage.
Remember to give due consideration to safety when making your circuit designs, with appropriate measures such as (i) placement of substitutive, auxiliary circuits,
(ii) use of nonflammable material or (iii) prevention against any malfunction or mishap.
Notes regarding these materials
1. These materials are intended as a reference to assist our customers in the selection of the Renesas Technology Corp. product best suited to the customer's
application; they do not convey any license under any intellectual property rights, or any other rights, belonging to Renesas Technology Corp. or a third party.
2. Renesas Technology Corp. assumes no responsibility for any damage, or infringement of any third-party's rights, originating in the use of any product data,
diagrams, charts, programs, algorithms, or circuit application examples contained in these materials.
3. All information contained in these materials, including product data, diagrams, charts, programs and algorithms represents information on products at the time of
publication of these materials, and are subject to change by Renesas Technology Corp. without notice due to product improvements or other reasons. It is
therefore recommended that customers contact Renesas Technology Corp. or an authorized Renesas Technology Corp. product distributor for the latest product
information before purchasing a product listed herein.
The information described here may contain technical inaccuracies or typographical errors.
Renesas Technology Corp. assumes no responsibility for any damage, liability, or other loss rising from these inaccuracies or errors.
Please also pay attention to information published by Renesas Technology Corp. by various means, including the Renesas Technology Corp. Semiconductor
home page (http://www.renesas.com).
4. When using any or all of the information contained in these materials, including product data, diagrams, charts, programs, and algorithms, please be sure to
evaluate all information as a total system before making a final decision on the applicability of the information and products. Renesas Technology Corp. assumes
no responsibility for any damage, liability or other loss resulting from the information contained herein.
5. Renesas Technology Corp. semiconductors are not designed or manufactured for use in a device or system that is used under circumstances in which human life
is potentially at stake. Please contact Renesas Technology Corp. or an authorized Renesas Technology Corp. product distributor when considering the use of a
product contained herein for any specific purposes, such as apparatus or systems for transportation, vehicular, medical, aerospace, nuclear, or undersea repeater
use.
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7. If these products or technologies are subject to the Japanese export control restrictions, they must be exported under a license from the Japanese government and
cannot be imported into a country other than the approved destination.
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