DATA SHEET MOS INTEGRATED CIRCUIT µPD750104,750106,750108,750104(A),750106(A),750108(A) 4 BIT SINGLE-CHIP MICROCONTROLLER The µ PD750108 is one of the 75XL series 4-bit single-chip microcontrollers, which provide data processing capability equal to that of an 8-bit microcontroller. The µ PD750108 is produced by replacing the main system clock oscillator of the µPD750008 with an RC oscillator, enabling operation at a relatively low voltage of 1.8 V. In addition, it is best suited to applications using batteries. The µPD750108(A) has a higher reliability than the µ PD750108. A built-in one-time PROM product, µ PD75P0116, is also available. It is suitable for small-scale production and evaluation of application systems. The following user’s manual describes the details of the functions of the µPD750108. Be sure to read it before designing application systems. µPD750108 User’s Manual: U11330E FEATURES • Built-in RC oscillator • Enables the immediate start of processing after the release of standby mode • Capable of low-voltage operation: VDD = 1.8 to 5.5 V • Internal memory Program memory (ROM) : 4,096 × 8 bits ( µ PD750104 and µ PD750104(A)) : 6,144 × 8 bits ( µ PD750106 and µ PD750106(A)) : 8,192 × 8 bits ( µ PD750108 and µ PD750108(A)) • Function for specifying the instruction execution time (useful for saving power) 4 µ s, 8 µs, 16 µs, 64 µ s (when operating at 1.0 MHz) 2 µs, 4 µ s, 8 µ s, 32 µs (when operating at 2.0 MHz) 122 µ s (when operating at 32.768 kHz) • Enhanced timer function (4 channels) • Can be easily substituted for the µ PD750008 because this product succeeds to the functions and instructions of the µPD750008. Data memory (RAM) : 512 × 4 bits APPLICATIONS • µPD750104, µPD750106, and µ PD750108 Cameras, meters, and pagers • µPD750104(A), µ PD750106(A), and µPD750108(A) Electrical equipment for automobiles The µ PD750104, µ PD750106, µ PD750108, µPD750104(A), µPD750106(A), and µPD750108(A) differ only in quality grade. In this manual, the µ PD750108 is described unless otherwise specified. Users of other than the µPD750108 should read µ PD750108 as referring to the pertinent product. When the description differs among µPD750104, µ PD750106, and µ PD750108, they also refer to the pertinent (A) products. µPD750104 → µ PD750104(A), µ PD750106 → µPD750106(A), µ PD750108 → µPD750108(A) The information in this document is subject to change without notice. Document No. U12301EJ1V0DS00 (1st edition) Date Published July 1997 J Printed in Japan © 1990 1997 µPD750104, 750106, 750108, 750104(A), 750106(A), 750108(A) ORDERING INFORMATION Part number Package Quality grade µ PD750104CU-××× 42-pin plastic shrink DIP (600 mil, 1.778-mm pitch) Standard µ PD750104GB-×××-3BS-MTX 44-pin plastic QFP (10 × 10 mm, 0.8-mm pitch) Standard µ PD750106CU-××× 42-pin plastic shrink DIP (600 mil, 1.778-mm pitch) Standard µ PD750106GB-×××-3BS-MTX 44-pin plastic QFP (10 × 10 mm, 0.8-mm pitch) Standard µ PD750108CU-××× 42-pin plastic shrink DIP (600 mil, 1.778-mm pitch) Standard µ PD750108GB-×××-3BS-MTX 44-pin plastic QFP (10 × 10 mm, 0.8-mm pitch) Standard µ PD750104CU(A)-××× 42-pin plastic shrink DIP (600 mil, 1.778-mm pitch) Special µ PD750104GB(A)-×××-3BS-MTX 44-pin plastic QFP (10 × 10 mm, 0.8-mm-pitch) Special µ PD750106CU(A)-××× 42-pin plastic shrink DIP (600 mil, 1.778-mm pitch) Special µ PD750106GB(A)-×××-3BS-MTX 44-pin plastic QFP (10 × 10 mm, 0.8-mm pitch) Special µ PD750108CU(A)-××× 42-pin plastic shrink DIP (600 mil, 1.778-mm pitch) Special µ PD750108GB(A)-×××-3BS-MTX 44-pin plastic QFP (10 × 10 mm, 0.8-mm pitch) Special Remark ××× is a mask ROM code number. Please refer to "Quality Grades on NEC Semiconductor Devices" (Document No. C11531E) published by NEC Corporation to know the specification of quality grade on the devices and its recommended applications. DIFFERENCES BETWEEN µPD75010× AND µPD75010×(A) Product number Item Quality grade 2 µPD750104 µPD750104(A) µPD750106 µPD750106(A) µPD750108 µPD750108(A) Standard Special µPD750104, 750106, 750108, 750104(A), 750106(A), 750108(A) FUNCTIONS Function Item Command execution time • 4, 8, 16, or 64 µs (when the main system clock operates at 1.0 MHz) • 2, 4, 8, or 32 µs (when the main system clock operates at 2.0 MHz) • 122 µs (when the subsystem clock operates at 32.768 kHz) Internal memory 4,096 × 8 bits (µ PD750104) ROM 6,144 × 8 bits (µ PD750106) 8,192 × 8 bits (µ PD750108) RAM General-purpose register I/O port CMOS input 512 × 4 bits • When operating in 4 bits: 8 × 4 banks • When operating in 8 bits: 4 × 4 banks 8 Can incorporate 7 pull-up resistors that are specified with the software. CMOS I/O 18 Can directly drive the LED. Can incorporate 18 pull-up resistors that are specified with the software. N-ch open drain I/O 8 Can directly drive the LED. Can withstand 13 V. Can incorporate pull-up resistors that are specified with the mask option. Total 34 Timer 4 channels • 8-bit timer/event counter: 1 channel • 8-bit timer counter: 1 channel • Basic interval timer/watchdog timer: 1 channel • lock timer: 1 channel Serial interface • Three-wire serial I/O mode ... switchable between the start LSB and the start MSB • Two-wire serial I/O mode • SBI mode Bit sequential buffer (BSB) 16 bits Clock output (PCL) • Φ, 125, 62.5, or 15.6 kHz (when the main system clock operates at 1.0 MHz) • Φ, 250, 125, or 31.3 kHz (when the main system clock operates at 2.0 MHz) Buzzer output (BUZ) • 2, 4, or 32 kHz (when the subsystem clock operates at 32.768 kHz) • 0.488, 0.977, or 7.813 kHz (when the main system clock operates at 1.0 MHz) • 0.977, 1.953, or 15.625 kHz (when the main system clock operates at 2.0 MHz) Vectored interrupt External : Internal : 3 4 Test input External : Internal : 1 1 System clock oscillator • • Standby STOP/HALT mode Operating ambient temperature range TA = -40 to +85 °C Supply voltage VDD = 1.8 to 5.5 V Package 42-pin plastic shrink DIP (600 mil, 1.778-mm pitch) RC oscillator for main system clock (with external resistor and capacitor) Crystal oscillator for subsystem clock 44-pin plastic QFP (10 × 10 mm, 0.8-mm pitch) 3 µPD750104, 750106, 750108, 750104(A), 750106(A), 750108(A) CONTENTS 1. PIN CONFIGURATION (TOP VIEW) ......................................................................................... 6 2. BLOCK DIAGRAM ..................................................................................................................... 8 3. PIN FUNCTIONS ........................................................................................................................ 9 3.1 Port Pins ......................................................................................................................................... 9 3.2 Non-Port Pins ................................................................................................................................. 10 3.3 Pin Input/Output Circuits .............................................................................................................. 11 3.4 Connection of Unused Pins ......................................................................................................... 13 Mk Ι MODE/Mk ΙΙ MODE SWITCH FUNCTION ........................................................................ 14 4.1 Differences between Mk Ι Mode and Mk ΙΙ Mode ...................................................................... 14 4.2 Setting of the Stack Bank Selection Register (SBS) ................................................................ 15 5. MEMORY CONFIGURATION .................................................................................................... 16 6. PERIPHERAL HARDWARE FUNCTIONS ................................................................................ 21 6.1 Digital I/O Ports .............................................................................................................................. 21 6.2 Clock Generator ............................................................................................................................. 21 6.3 Control Functions of Subsystem Clock Oscillator ................................................................... 23 6.4 Clock Output Circuit ...................................................................................................................... 24 6.5 Basic Interval Timer/Watchdog Timer ........................................................................................ 25 6.6 Clock Timer ..................................................................................................................................... 26 6.7 Timer/Event Counter ..................................................................................................................... 27 6.8 Serial Interface ............................................................................................................................... 30 6.9 Bit Sequential Buffer ..................................................................................................................... 32 7. INTERRUPT FUNCTIONS AND TEST FUNCTIONS ............................................................... 33 8. STANDBY FUNCTION ............................................................................................................... 35 9. RESET FUNCTION ..................................................................................................................... 36 10. MASK OPTION ........................................................................................................................... 39 11. INSTRUCTION SET .................................................................................................................... 40 12. ELECTRICAL CHARACTERISTICS ......................................................................................... 53 13. CHARACTERISTIC CURVE (REFERENCE VALUES) ............................................................ 65 4. 4 µPD750104, 750106, 750108, 750104(A), 750106(A), 750108(A) 14. EXAMPLES OF RC OSCILLATOR FREQUENCY CHARACTERISTICS (REFERENCE VALUES) ..................................................................................................................................... 66 15. PACKAGE DRAWINGS ............................................................................................................. 68 16. RECOMMENDED SOLDERING CONDITIONS ........................................................................ 70 APPENDIX A FUNCTIONS OF THE µPD750008, µPD750108, AND µPD75P0116 .................. 71 APPENDIX B DEVELOPMENT TOOLS ........................................................................................ 73 APPENDIX C RELATED DOCUMENTS ........................................................................................ 77 5 µPD750104, 750106, 750108, 750104(A), 750106(A), 750108(A) 1. PIN CONFIGURATION (TOP VIEW) • 42-pin plastic shrink DIP (600 mil, 1.778-mm pitch) µ PD750104CU-×××, µPD750104CU(A)-××× µ PD750106CU-×××, µPD750106CU(A)-××× µPD750108CU-×××, µPD750108CU(A)-××× XT1 1 42 VSS XT2 2 41 P40 RESET 3 40 P41 CL1 4 39 P42 CL2 5 38 P43 P33 6 37 P50 P32 7 36 P51 P31 8 35 P52 P30 9 34 P53 P81 10 33 P60/KR0 P80 11 32 P61/KR1 P03/SI/SB1 12 31 P62/KR2 P02/SO/SB0 13 30 P63/KR3 P01/SCK 14 29 P70/KR4 P00/INT4 15 28 P71/KR5 P13/TI0 16 27 P72/KR6 P12/INT2 17 26 P73/KR7 P11/INT1 18 25 P20/PTO0 P10/INT0 19 24 P21/PTO1 IC 20 23 P22/PCL VDD 21 22 P23/BUZ IC : Internally connected (Connect directly to V DD.) 6 µPD750104, 750106, 750108, 750104(A), 750106(A), 750108(A) • 44-pin plastic QFP (10 × 10 mm, 0.8-mm pitch) µ PD750104GB-×××-3BS-MTX, µPD750104GB(A)-×××-3BS-MTX µ PD750106GB-×××-3BS-MTX, µPD750106GB(A)-×××-3BS-MTX P73/KR7 P20/PTO0 P21/PTO1 P22/PCL P23/BUZ VDD IC P10/INT0 P11/INT1 P12/INT2 NC µ PD750108GB-×××-3BS-MTX, µPD750108GB(A)-×××-3BS-MTX 44 43 42 41 40 39 38 37 36 35 34 1 33 P13/TI0 P71/KR5 2 32 P00/INT4 P70/KR4 3 31 P01/SCK P63/KR3 4 30 P02/SO/SB0 P62/KR2 5 29 P03/SI/SB1 P61/KR1 6 28 P80 P60/KR0 7 27 P81 P53 8 26 P30 P52 P51 P50 9 25 10 24 11 23 12 13 14 15 16 17 18 19 20 21 22 P31 P32 P33 NC P43 P42 P41 P40 VSS XT1 XT2 RESET CL1 CL2 P72/KR6 IC : Internally connected (Connect directly to V DD.) PIN NAMES BUZ : Buzzer Clock P70-P73 : Port 7 CL1, CL2 : Main System Clock (RC) P80, P81 : Port 8 IC Internally Connected PCL : Programmable Clock INT0, 1, 4 : External Vectored Interrupt 0, 1, 4 PTO0, PTO1 : Programmable Timer Output 0, 1 INT2 : External Test Input 2 RESET : Reset KR0-KR7 : Key Return 0-7 SB0, SB1 : Serial Bus 0, 1 NC : No connection SCK : Serial Clock P00-P03 : Port 0 SI : Serial Input P10-P13 : Port 1 SO : Serial Output P20-P23 : Port 2 TI0 : Timer Input 0 P30-P33 : Port 3 VDD : Positive Power Supply P40-P43 : Port 4 VSS : Ground P50-P53 : Port 5 XT1, XT2 : Subsystem Clock (Crystal) P60-P63 : Port 6 : 7 µPD750104, 750106, 750108, 750104(A), 750106(A), 750108(A) 2. BLOCK DIAGRAM BIT SEQ. BUFFER (16) BASIC INTERVAL TIMER/ WATCHDOG TIMER INTBT RESET PROGRAM COUNTER SP (8) CY 8-BIT TIMER/EVENT COUNTER #0 TI0/P13 PTO0/P20 ALU BANK INTT0 SI/SB1/P03 CLOCKED SERIAL INTERFACE SCK/P01 P00 - P03 PORT 1 4 P10 - P13 PORT 2 4 P20 - P23 PORT 3 4 P30 - P33 PORT 4 4 P40 - P43 PORT 5 4 P50 - P53 PORT 6 4 P60 - P63 PORT 7 4 P70 - P73 PORT 8 2 P80, P81 GENERAL REGISTER INTT1 SO/SB0/P02 4 TOUT0 8-BIT TIMER COUNTER #1 PTO1/P21 PORT 0 SBS INTCSI PROGRAM MEMORYNote (ROM) DECODE AND CONTROL DATA MEMORY (RAM) 512 × 4 BITS TOUT0 INT0/P10 INT1/P11 INTERRUPT CONTROL INT2/P12 INT4/P00 KR0/P60KR7/P73 8 fx/2N BUZ/P23 WATCH TIMER INTW CLOCK CLOCK OUTPUT DIVIDER CONTROL PCL/P22 CPU CLOCK Φ SYSTEM CLOCK GENERATOR SUB MAIN XT1 XT2 CL1 CL2 Note The ROM capacity depends on the product. 8 STAND BY CONTROL IC VDD VSS RESET µPD750104, 750106, 750108, 750104(A), 750106(A), 750108(A) 3. PIN FUNCTIONS 3.1 Port Pins Pin name Input/ output Shared pin P00 Input INT4 P01 I/O SCK P02 I/O SO/SB0 P03 I/O SI/SB1 P10 Input INT0 P11 INT1 P12 INT2 P13 TI0 P20 I/O PTO0 P21 PTO1 P22 PCL P23 BUZ Function 4-bit input port (PORT0). For P01 - P03, built-in pull-up resistors can be connected by software in units of 3 bits. 8-bit I/O When reset I/O circuit typeNote 1 × Input B F -A F -B M -C -C 4-bit input port (PORT1). Built-in pull-up resistors can be connected by software in units of 4 bits. A noise eliminator can be selected only when the P10/INT0 pin is used. × Input B 4-bit I/O port (PORT2). Built-in pull-up resistors can be connected by software in units of 4 bits. × Input E-B × Input E-B P30 - P33 I/O - Programmable 4-bit I/O port (PORT3). I/O can be specified bit by bit. Built-in pull-up resistors can be connected by software in units of 4 bits. P40 - P43 Note 2 I/O - N-ch open-drain 4-bit I/O port (PORT4). A pull-up resistor can be provided bit by bit (mask option). Withstand voltage is 13 V in open-drain mode. High level (when pull-up resistors are provided) or high impedance M-D P50 - P53 Note 2 I/O - N-ch open-drain 4-bit I/O port (PORT5). A pull-up resistor can be provided bit by bit (mask option). Withstand voltage is 13 V in open-drain mode. High level (when pull-up resistors are provided) or high impedance M-D P60 I/O KR0 P61 KR1 P62 KR2 P63 KR3 P70 I/O KR4 P71 KR5 P72 KR6 P73 KR7 P80 I/O - P81 Notes 1. The circle ( Programmable 4-bit I/O port (PORT6). I/O can be specified bit by bit. Built-in pull-up resistors can be connected by software in units of 4 bits. Input F -A 4-bit I/O port (PORT7). Built-in pull-up resistors can be connected by software in units of 4 bits. Input F -A Input E-B 2-bit I/O port (PORT8). Built-in pull-up resistors can be connected by software in units of 2 bits. × ) indicates the Schmitt trigger input. 2. When pull-up resistors that can be specified with the mask option are not incorporated (when pins are used as N-ch open-drain input ports), the input leak low current increases when an input instruction or bit operation instruction is executed. 9 µPD750104, 750106, 750108, 750104(A), 750106(A), 750108(A) 3.2 Non-Port Pins Pin name TI0 Input/ output Shared pin Function When reset I/O circuit typeNote 1 Input P13 Inputs external event pulse to the timer/event counter Input B Output P20 Timer/event counter output Input E-B PTO1 P21 Timer counter output PCL P22 Clock output BUZ P23 Arbitrary frequency output (for buzzer output or system clock trimming) P01 Serial clock I/O Input F -A SO/SB0 P02 Serial data output Serial data bus I/O F -B SI/SB1 P03 Serial data input Serial data bus I/O M -C PTO0 SCK I/O INT4 Input P00 Edge detection vectored interrupt input (both rising and falling edges are detected) INT0 Input P10 P11 Edge detection vectored interrupt input Note 2 (detection edge selectable). A noise eliminator Note 3 can be selected when INT0/P10 is used. INT1 -C B Input B -C INT2 Input P12 Rising edge detection testable input KR0 - KR3 Input P60 - P63 Falling edge detection testable input Input F -A KR4 - KR7 Input P70 - P73 Falling edge detection testable input Input F -A CL1 - - - - CL2 - Pin for connecting a resistor (R) or capacitor (C) for main system clock oscillation. An external clock cannot be input. XT1 Input - - - XT2 - Crystal connection pin for subsystem clock generation. When external clock signal is used, it is applied to XT1, and it reverse phase signal is applied to XT2. XT1 can be used as a 1-bit input (test). Input - System reset input (active low) - B IC - - Internally connected. (To be connected directly to VDD) - - VDD - - Positive power supply - - VSS - - Ground potential - - RESET Notes 1. The circle ( ) indicates the Schmitt trigger input. 2. With a noise eliminator/asynchronously selectable 3. Asynchronous 10 Note 3 µPD750104, 750106, 750108, 750104(A), 750106(A), 750108(A) 3.3 Pin Input/Output Circuits The input/output circuit of each µ PD750108 pin is shown below in a simplified manner. Type A (1/2) Type D VDD VDD Data P-ch P-ch OUT IN N-ch CMOS input buffer Type B Output disable N-ch Push-pull output which can be set to high-impedance output (off for both P-ch and N-ch) Type E-B VDD P.U.R. P.U.R. enable P-ch IN Data IN/OUT Type D Output disable Type A Schmitt trigger input with hysteresis P.U.R.: Pull-Up Resistor Type B-C Type F-A VDD VDD P.U.R. P.U.R. enable P.U.R. P-ch P.U.R. enable P-ch Data Type D IN/OUT Output disable IN Type B P.U.R.: Pull-Up Resistor P.U.R.: Pull-Up Resistor 11 µPD750104, 750106, 750108, 750104(A), 750106(A), 750108(A) (2/2) Type F-B Type M-C VDD VDD P.U.R. P.U.R. enable P.U.R. P-ch Output disable (P) P.U.R. enable VDD P-ch IN/OUT P-ch IN/OUT Data Output disable Data N-ch Output disable N-ch Output disable (N) P.U.R.: Pull-Up Resistor P.U.R.: Pull-Up Resistor Type M-D VDD P.U.R. (Mask option) N-ch (Withstand voltage: +13 V) Data Output disable Input instruction IN/OUT VDD P-ch P.U.RNote Voltage restriction circuit (Withstand voltage: +13 V) P.U.R.: Pull-Up Resistor Note Pull-up resistor that operates only when pull-up resistors that can be specified with the mask option are not incorporated and an input instruction is executed. (When the pin is low, the current flows from VDD to the pin.) 12 µPD750104, 750106, 750108, 750104(A), 750106(A), 750108(A) 3.4 Connection of Unused Pins Table 3-1. Connection of Unused Pins Pin name Recommended connection P00/INT4 To be connected to VSS or VDD P01/SCK To be connected to VSS or VDD through a separate resistor P02/SO/SB0 P03/SI/SB1 To be connected to VSS P10/INT0 - P12/INT2 To be connected to VSS or VDD P13/TI0 P20/PTO0 Input state : To be connected to VSS or VDD through a separate resistor P21/PTO1 Output state : To be left open P22/PCL P23/BUZ P30 - P33 P40 - P43 Input state : To be connected to VSS Output state : To be connected to VSS (Do not connect to a pull-up resistor specified with a mask option.) P50 - P53 P60/KR0 - P63/KR3 Input state : To be connected to VSS or VDD through a separate resistor P70/KR4 - P73/KR7 Output state : To be left open P80, P81 XT1Note To be connected to VSS or VDD XT2Note To be left open IC To be connected directly to VDD Note When the subsystem clock is not used, set SOS.0 to 1 (not to use the builtin feedback resistor). 13 µPD750104, 750106, 750108, 750104(A), 750106(A), 750108(A) 4. Mk Ι MODE/Mk ΙΙ MODE SWITCH FUNCTION 4.1 Differences between Mk Ι Mode and Mk ΙΙ Mode The CPU of the µ PD750108 has two modes (Mk Ι mode and Mk ΙΙ mode) and which mode is used is selectable. Bit 3 of the stack bank selection register (SBS) determines the mode. • Mk Ι mode: This mode has the upward compatibility with the 75X series. It can be used in the 75XL CPUs having a ROM of up to 16 KB. • Mk ΙΙ mode: This mode is not compatible with the 75X series. It can be used in all 75XL CPUs, including those having a ROM of 16 KB or more. Table 4-1 shows the differences between Mk Ι mode and Mk ΙΙ mode. Table 4-1. Differences between Mk Ι Mode and Mk ΙΙ Mode Mk Ι mode Mk ΙΙ mode Number of stack bytes in a subroutine instruction 2 bytes 3 bytes BRA !addr1 instruction CALLA !addr1 instruction None Available CALL !addr instruction 3 machine cycles 4 machine cycles CALLF !faddr instruction 2 machine cycles 3 machine cycles Caution Mk ΙΙ mode can be used to support a program area larger than 16K bytes in the 75X series or 75XL series. This mode enhances a software compatibility with products whose program area is larger than 16K bytes. If Mk ΙΙ mode is selected, when the subroutine call instruction is executed, the number of stack bytes (use area) will be increased by one byte for each stack, compared to Mk Ι mode. When a CALL !addr or CALLF !faddr instruction is executed, it takes one more machine cycle. Therefore, Mk Ι mode should be used for applications for which RAM efficiency or processing capabilities is more critical than a software compatibility. 14 µPD750104, 750106, 750108, 750104(A), 750106(A), 750108(A) 4.2 Setting of the Stack Bank Selection Register (SBS) The Mk Ι mode and Mk ΙΙ mode are switched by stack bank selection register. Figure 4-1 shows the register configuration. The stack bank selection register is set with a 4-bit memory operation instruction. To use the CPU in Mk Ι mode, initialize the register to 100×BNote at the beginning of the program. To use the CPU in Mk ΙΙ mode, initialize it to 000×BNote. Note Specify the desired value in ×. Figure 4-1. Stack Bank Selection Register Format Address 3 2 1 0 Symbol F84H SBS3 SBS2 SBS1 SBS0 SBS Stack area designation 0 0 Memory bank 0 0 1 Memory bank 1 Other settings are inhibited. 0 Bit 2 must be set to 0. Mode switching designation 0 Mk ΙΙ mode 1 Mk Ι mode Caution The CPU operates in Mk Ι mode after the RESET signal is issued, because bit 3 of SBS is set to 1. Set bit 3 of SBS to 0 (Mk ΙΙ mode) to use the CPU in Mk ΙΙ mode. 15 µPD750104, 750106, 750108, 750104(A), 750106(A), 750108(A) 5. MEMORY CONFIGURATION • Program memory (ROM) : 4,096 × 8 bits (0000H-0FFFH): µ PD750104 6,144 × 8 bits (0000H-17FFH): µ PD750106 8,192 × 8 bits (0000H-1FFFH): µ PD750108 • 0000H to 0001H Vector address table for holding the RBE and MBE values and program start address when a RESET signal is issued (allowing a reset start at an arbitrary address) • 0002H to 000DH Vector address table for holding the RBE and MBE values and program start address for each vectored interrupt (allowing interrupt processing to be started at an arbitrary address) • 0020H to 007FH Table area referenced by the GETI instructionNote Note The GETI instruction requires only one byte to represent an arbitrary two-byte or three-byte instruction or two one-byte instructions, reducing the number of program bytes. • Data memory (RAM) • Data area : 512 × 4 bits (000H to 1FFH) • Peripheral hardware area: 128 × 4 bits (F80H to FFFH) 16 µPD750104, 750106, 750108, 750104(A), 750106(A), 750108(A) Figure 5-1. Program Memory Map (in µ PD750104) Address 7 6 0 0 0 H MBE RBE 0 0 2 H MBE RBE 0 0 4 H MBE RBE 0 0 6 H MBE RBE 0 0 8 H MBE RBE 0 0 A H MBE RBE 0 0 C H MBE RBE 5 4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Internal reset start address (high-order 4 bits) Internal reset start address (low-order 8 bits) INTBT/INT4 start address (high-order 4 bits) INTBT/INT4 start address (low-order 8 bits) INT0 start address (high-order 4 bits) INT0 start address (low-order 8 bits) INT1 start address (high-order 4 bits) INT1 start address (low-order 8 bits) INTCSI start address (high-order 4 bits) INTCSI start address (low-order 8 bits) INTT0 start address (high-order 4 bits) INTT0 start address (low-order 8 bits) INTT1 start address (high-order 4 bits) INTT1 start address (low-order 8 bits) 020H GETI instruction reference table CALLF ! faddr instruction entry address Branch address of BR BCXA, BR BCDE, BR !addr, BRA !addr1Note or CALLA !addr1Note instruction CALL !addr instruction subroutine entry address BR $addr instruction relative branch address -15 to -1, +2 to +16 BRCB !caddr instruction branch address 07FH 080H Branch destination address and subroutine entry address when GETI instruction is executed 7FFH 800H FFFH Note Can be used only in the Mk ΙΙ mode. Remark In addition to the above, the BR PCDE and BR PCXA instructions can cause a branch to an address with only the 8 low-order bits of the PC changed. 17 µPD750104, 750106, 750108, 750104(A), 750106(A), 750108(A) Figure 5-2. Program Memory Map (in µ PD750106) Address 7 6 0 0 0 0 H MBE RBE 0 0 0 2 H MBE RBE 0 0 0 4 H MBE RBE 0 0 0 6 H MBE RBE 0 0 0 8 H MBE RBE 0 0 0 A H MBE RBE 0 0 0 C H MBE RBE 5 0 0 0 0 0 0 0 0 Internal reset start address (high-order 5 bits) Internal reset start address (low-order 8 bits) INTBT/INT4 start address (high-order 5 bits) INTBT/INT4 start address (low-order 8 bits) INT0 start address (high-order 5 bits) INT0 start address (low-order 8 bits) INT1 start address (high-order 5 bits) INT1 start address (low-order 8 bits) INTCSI start address (high-order 5 bits) INTCSI start address (low-order 8 bits) INTT0 start address (high-order 5 bits) INTT0 start address (low-order 8 bits) INTT1 start address (high-order 5 bits) INTT1 start address (low-order 8 bits) CALLF !faddr instruction entry address Branch address of BR BCXA, BR BCDE, BR !addr, BRA !addr1Note or CALLA !addr1Note instruction CALL !addr instruction subroutine entry address BR $addr instruction relative branch address -15 to -1, +2 to +16 BRCB !caddr instruction branch address 0020H GETI instruction reference table 007FH 0080H Branch destination address and subroutine entry address when GETI instruction is executed 07FFH 0800H 0FFFH 1000H BRCB !caddr instruction branch address 17FFH Note Can be used only in the Mk ΙΙ mode. Remark In addition to the above, the BR PCDE and BR PCXA instructions can cause a branch to an address with only the 8 low-order bits of the PC changed. 18 µPD750104, 750106, 750108, 750104(A), 750106(A), 750108(A) Figure 5-3. Program Memory Map (in µ PD750108) Address 7 6 0 0 0 0 H MBE RBE 0 0 0 2 H MBE RBE 0 0 0 4 H MBE RBE 0 0 0 6 H MBE RBE 0 0 0 8 H MBE RBE 0 0 0 A H MBE RBE 0 0 0 C H MBE RBE 5 0 0 0 0 0 0 0 0 Internal reset start address (high-order 5 bits) Internal reset start address (low-order 8 bits) INTBT/INT4 start address (high-order 5 bits) INTBT/INT4 start address (low-order 8 bits) INT0 start address (high-order 5 bits) INT0 start address (low-order 8 bits) INT1 start address (high-order 5 bits) INT1 start address (low-order 8 bits) INTCSI start address (high-order 5 bits) INTCSI start address (low-order 8 bits) INTT0 start address (high-order 5 bits) INTT0 start address (low-order 8 bits) INTT1 start address (high-order 5 bits) INTT1 start address (low-order 8 bits) CALLF !faddr instruction entry address Branch address of BR BCXA, BR BCDE, BR !addr, BRA !addr1Note or CALLA !addr1Note instruction CALL !addr instruction subroutine entry address BR $addr instruction relative branch address -15 to -1, +2 to +16 BRCB !caddr instruction branch address 0020H GETI instruction reference table 007FH 0080H Branch destination address and subroutine entry address when GETI instruction is executed 07FFH 0800H 0FFFH 1000H BRCB !caddr instruction branch address 1FFFH Note Can be used only in the Mk ΙΙ mode. Remark In addition to the above, the BR PCDE and BR PCXA instructions can cause a branch to an address with only the 8 low-order bits of the PC changed. 19 µPD750104, 750106, 750108, 750104(A), 750106(A), 750108(A) Figure 5-4. Data Memory Map Data memory Area for 000H general-purpose register 01FH Memory bank (32 × 4) 020H 256 × 4 0 (224 × 4) Data area Static RAM (512 × 4) Stack areaNote 0FFH 100H 256 × 4 1 1FFH Not contained F80H Peripheral hardware area 128 × 4 FFFH Note Memory bank 0 or 1 can be selected as the stack area. 20 15 µPD750104, 750106, 750108, 750104(A), 750106(A), 750108(A) 6. PERIPHERAL HARDWARE FUNCTIONS 6.1 Digital I/O Ports The µPD750108 has the following three types of I/O port: • 8 CMOS input pins (PORT0 and PORT1) • 18 CMOS I/O pins (PORT2, PORT3, and PORT6 to PORT8) • 8 N-ch open-drain I/O pins (PORT4 and PORT5) Total: 34 pins Table 6-1. Digital Ports and Their Features PORT0 4-bit input PORT1 PORT2 Operation and feature Function Port name 4-bit I/O PORT3 When the serial interface function is used, dual-function pins function as output pins in some operation modes. Also used as INT4, SCK, SO/SB0, or SI/SB1. 4-bit input port Also used as INT0, INTI, INT2 or TI0. Allows input or output mode setting in units of 4 bits. Also used as PTO0, PTO1, PCL, or BUZ. Allows input or output mode setting in units of 1 bit. PORT5 4-bit I/O (N-ch open-drain can withstand 13 V) Allows input or output mode setting in units of 4 bits. Whether to use pull-up resistors can be specified bit by bit with the mask option. Ports 4 and 5 can be paired, allowing data I/O in units of 8 bits. PORT6 4-bit I/O Allows input or output mode setting in units of 1 bit. Ports 6 and 7 can be paired, allowing data I/O in units of 8 bits. PORT4 Allows input or output mode setting in units of 4 bits. PORT7 PORT8 6.2 2-bit I/O Remarks Allows input or output mode setting in units of 2 bits. - Also used as one of KR0 to KR3. Also used as one of KR4 to KR7. - Clock Generator The clock generator generates clocks which are supplied to the peripheral hardware in the CPU. Figure 6-1 shows the configuration of the clock generator. Operation of the clock generator is specified by the processor clock control register (PCC) and system clock control register (SCC). The main system clock and subsystem clock are used. The instruction execution time can be made variable. • 4, 8, 16, or 64 µ s (when the main system clock is at 1.0 MHz) • 2, 4, 8, or 32 µ s (when the main system clock is at 2.0 MHz) • 122 µ s (when the subsystem clock is at 32.768 kHz) 21 µPD750104, 750106, 750108, 750104(A), 750106(A), 750108(A) Figure 6-1. Clock Generator Block Diagram • • • • • • • XT1 XT2 Subsystem clock generator fXT Main system clock generator RC oscillation fCC Clock timer Basic interval timer (BT) Timer/event counter Timer counter Serial interface Clock timer INT0 noise eliminator Clock output circuit CL1 CL2 1/1 to 1/4096 Frequency divider 1/2 1/4 1/16 WM.3 SCC Selector Oscillator disable signal Frequency divider SCC3 Selector 1/4 Internal bus SCC0 PCC PCC0 Φ • CPU • INT0 noise eliminator • Clock output circuit PCC1 4 HALT flip-flop Note PCC2 S HALT STOPNote PCC3 R PCC2, PCC3 clear signal STOP flip-flop Q Q Wait release signal from BT S RESET signal R Standby release signal from interrupt control circuit Note Instruction execution Remarks 1. fCC = Main system clock frequency 2. fXT = Subsystem clock frequency 3. Φ = CPU clock 4. PCC: Processor clock control register 5. SCC: System clock control register 6. One clock cycle (tCY) of the CPU clock (Φ) is equal to one machine cycle of an instruction. 22 µPD750104, 750106, 750108, 750104(A), 750106(A), 750108(A) 6.3 Control Functions of Subsystem Clock Oscillator The subsystem clock oscillator of the µ PD750108 has two control functions to decrease the supply current. • The function to select with the software whether to use the built-in feedback resistorNote • The function to suppress the supply current by reducing the drive current of the built-in inverter when the supply voltage is high (VDD ≥ 2.7 V) Note When the subsystem clock is not used, set SOS.0 to 1 (not to use the built-in feedback resistor), connect XT1 to VSS or V DD, and open XT2. This makes it possible to reduce the supply current required by the subsystem clock oscillator. Each function can be used by switching bits 0 and 1 in the sub-oscillator control register (SOS). (See Figure 62.) Figure 6-2. Subsystem Clock Oscillator SOS.0 Feedback resistor Inverter SOS.1 XT1 XT2 23 µPD750104, 750106, 750108, 750104(A), 750106(A), 750108(A) 6.4 Clock Output Circuit The clock output circuit outputs a clock pulse from the P22/PCL pin. This clock pulse is used for remote control waveform output, peripheral LSIs, etc. • Clock output (PCL): Φ, 125, 62.5, or 15.6 kHz (at 1.0 MHz) Φ, 250, 125, or 31.3 kHz (at 2.0 MHz) Figure 6-3. Clock Output Circuit Configuration From the clock generator Φ Output buffer fCC/23 Selector fCC/24 PCL/P22 6 fCC/2 PORT2.2 CLOM3 0 CLOM1 CLOM0 CLOM P22 output latch Bit 2 of PMGB Port 2 input/ output mode specification bit 4 Internal bus Remark Measures are taken to prevent outputting a narrow pulse when selecting clock output enable/disable. 24 µPD750104, 750106, 750108, 750104(A), 750106(A), 750108(A) 6.5 Basic Interval Timer/Watchdog Timer The basic interval timer/watchdog timer has these functions: • Interval timer operation which generates a reference timer interrupt • Operation as a watchdog timer for detecting program crashes and resetting the CPU • Selection of wait time for releasing the standby mode and counting the wait time • Reading out the count value Figure 6-4. Block Diagram of the Basic Interval Timer/Watchdog Timer From the clock generator Clear signal Clear signal fCC/25 Set signal 7 fCC/2 Basic interval timer (8-bit frequency divider) MPX 9 BT interrupt request flag fCC/2 fCC/212 BT 3 BTM3 SET1Note BTM2 BTM1 IRQBT Internal reset signal Wait release signal for standby release BTM0 4 BTM WDTM 8 Vectored interrupt request signal SET1 Note 1 Internal bus Note Instruction execution 25 µPD750104, 750106, 750108, 750104(A), 750106(A), 750108(A) 6.6 Clock Timer The µPD750108 contains one channel for a clock timer. The clock timer provides the following functions: • Sets the test flag (IRQW) with a 0.5 sec interval (when WM0 = 1). • The standby mode can be released by IRQW. • The 0.5 second interval can be generated from the subsystem clock (32.768 kHz). • The time interval can be made 128 times faster by selecting the fast mode. This is convenient for program debugging, testing, etc. • Any of the frequencies (fW/2 4, fW /23 , or fW can be output to the P23/BUZ pin. This can be used for beep and system clock frequency trimming. • The clock can be started from zero seconds by clearing the frequency divider. Figure 6-5. Clock Timer Block Diagram fw 27 From the clock generator fCC Note 128 (7.8125 kHz) Selector fW 32.768 kHz or 7.8125 kHz fw 214 INTW IRQW set signal Selector Frequency divider fXT (32.768 kHz) fw fw 23 24 Clear Selector Output buffer P23/BUZ WM WM7 PORT2.3 0 WM5 WM4 WM3 8 WM2 WM1 WM0 P23 output latch Bit 2 of PMGB Port 2 input/ output mode Bit test instruction Internal bus Note When a frequency-divided main system clock is used, 32.768 kHz cannot be selected as the source clock frequency. Remark The values in parentheses in the figure above are for fCC = 1.0 MHz, fXT = 32.768 kHz. 26 µPD750104, 750106, 750108, 750104(A), 750106(A), 750108(A) 6.7 Timer/Event Counter The µPD750108 contains one channel for a timer/event counter and one channel for a timer counter. Figures 6-6 and 6-7 show their configurations. The timer/event counter provides the following functions: • Programmable interval timer operation • Outputs square-wave signal of an arbitrary frequency to the PTOn pin (n = 0, 1) • Event counter operation (channel 0 only) • Divides the TI0 pin input by N and outputs to the PTO0 pin (frequency divider operation) (channel 0 only) • Supplies serial shift clock to the serial interface circuit (channel 0 only) • Count read function 27 28 Figure 6-6. Timer/Event Counter Block Diagram Internal bus 8 SET1Note TM0 8 8 TOE0 TMOD0 TM06 TM05 TM04 TM03 TM02 T0 enable flag Modulo register (8) 8 Bit 2 of PMGB Port 2 input/ output mode To serial interface TOUT0 Match Comparator (8) 8 TOUT flip-flop Reset Input buffer PTO0/P20 Output buffer T0 INTT0 TI0/P13 fCC/24 6 From the clock fCC/2 generator fCC/28 fCC/210 Count register (8) CP MPX Clear signal IRQT0 set signal Timer operation start signal RESET IRQT0 clear signal Note Instruction execution µPD750104, 750106, 750108, 750104(A), 750106(A), 750108(A) Port input buffer PORT2.0 P20 output latch signal Figure 6-7. Timer Counter Block Diagram Internal bus SET1 Note 8 TM1 8 8 TOE1 TMOD1 TM16 TM15 TM14 TM13 TM12 T1 enable flag Modulo register (8) PORT2.1 Bit 2 of PMGB Port 2 input/ output mode 8 Match Comparator (8) 8 From the clock generator TOUT flip-flop Reset PTO1/P21 Output buffer T1 fCC/26 fCC/28 fCC/210 fCC/212 INTT1 Count register (8) CP MPX Clear signal IRQT1 set signal Timer operation start signal RESET IRQT1 clear signal Note Instruction execution 29 µPD750104, 750106, 750108, 750104(A), 750106(A), 750108(A) P21 output latch µPD750104, 750106, 750108, 750104(A), 750106(A), 750108(A) 6.8 Serial Interface µ PD750108 has an 8-bit synchronous serial interface. The serial interface has the following four types of mode. • Operation stop mode • Three-wire serial I/O mode • Two-wire serial I/O mode • SBI mode 30 Figure 6-8. Serial Interface Block Diagram Internal bus 8/4 CSIM Bit test 8 8 Bit manipulation Bit test 8 SBIC Slave address register (SVA) (8) Address comparator CMDT (8) P03/SI/SB1 SET CLR SO latch D Q BSYE (8) ACKE Shift register (SIO) ACKT Selector P02/SO/SB0 Busy/ acknowledge output circuit Selector Bus release/ command/ acknowledge detection circuit RELD CMDD ACKD INTCSI P01/SCK Serial clock counter P01 output latch Serial clock control circuit INTCSI control circuit IRQCSI set signal Serial clock selector External SCK fCC/23 fCC/24 fCC/26 TOUT0 (from timer/event counter) 31 µPD750104, 750106, 750108, 750104(A), 750106(A), 750108(A) Coincidence RELT signal µPD750104, 750106, 750108, 750104(A), 750106(A), 750108(A) 6.9 Bit Sequential Buffer: 16 Bits The bit sequential buffer (BSB) is a data memory specifically provided for bit manipulation. With this buffer, addresses and bit specifications can be sequentially updated by bit manipulation operation. Therefore, this buffer is very useful for processing long data in bit units. Figure 6-9. Bit Sequential Buffer Format FC3H Address 3 Bit 1 0 3 BSB3 Symbol L register 2 FC2H L = FH 2 1 FC1H 0 3 BSB2 L = CH L = BH 2 FC0H 1 0 3 BSB1 L = 8H L = 7H 2 1 0 BSB0 L = 4H L = 3H L = 0H DECS L INCS L Remarks 1. In pmem.@L addressing, bit specification is shifted according to the L register. 2. In pmem.@L addressing, the bit sequential buffer can be manipulated at any time regardless of MBE/ MBS specification. 32 µPD750104, 750106, 750108, 750104(A), 750106(A), 750108(A) 7. INTERRUPT FUNCTIONS AND TEST FUNCTIONS The µ PD750108 has seven interrupt sources and two test sources. One test source, INT2, has two types of edge detection testable input pins. The interrupt control circuit of the µPD750108 has the following functions. (1) Interrupt functions • Hardware controlled vectored interrupt function which can control whether or not to accept an interrupt using the interrupt flag (IE×××) and interrupt master enable flag (IME). • The interrupt start address can be set arbitrarily. • Multiple interrupt function which can specify the priority by the interrupt priority specification register (IPS) • Test function of an interrupt request flag (IRQ×××) (The software can confirm that an interrupt occurred.) • Release of the standby mode (Interrupts released by an interrupt enable flag can be selected.) (2) Test functions • Whether test request flags (IRQ×××) are issued can be checked with software. • Release of the standby mode (A test source to be released can be selected with test enable flags.) 33 34 Figure 7-1. Interrupt Control Circuit Block Diagram Internal bus 2 1 4 IM2 IM1 IM0 IME IPS IST1 IST0 Interrupt enable flag (IE×××) Both-edge detector INT0/P10 INT1/P11 INT2/P12 KR0/P60 KR7/P73 Note Selector INT4/P00 Edge detector Decoder IRQBT IRQ4 VRQn IRQ0 Edge detector IRQ1 INTCSI IRQCSI INTT0 IRQT0 INTT1 IRQT1 INTW IRQW Rising edge detector Selector IRQ2 Falling edge detector IM2 Note Noise eliminator (Standby release is not possible when the noise eliminator is selected.) Priority control circuit Vector table address generator Standby release signal µPD750104, 750106, 750108, 750104(A), 750106(A), 750108(A) INTBT µPD750104, 750106, 750108, 750104(A), 750106(A), 750108(A) 8. STANDBY FUNCTION The µ PD750108 has two different standby modes (STOP mode and HALT mode) to reduce power dissipation while waiting for program execution. Table 8-1. Standby Mode Statuses Mode Item STOP mode HALT mode Instruction for setting STOP instruction HALT instruction System clock for setting Can be set only when operating on the main system clock. Can be set either with the main system clock or the subsystem clock. Operation status Clock oscillator The main system clock stops its operation. Only the CPU clock Φ stops its operation (oscillation continues). Basic interval timer/watchdog timer Does not operate. Can operate only at main system clock oscillation. BT mode : IRQBT is set at the reference interval. WT mode : A reset signal is generated when the BT overflows. Serial interface Can operate only when the external SCK input is selected for the serial clock. Can operate only when external SCK input is selected as the serial clock or at main system clock oscillation. Timer/event counter Can operate only when the TI0 pin input is selected for the count clock. Can operate only when TI0 pin input is specified as the count clock or at main system clock oscillation. Timer counter Does not operate. Can operate.Note 1 Clock timer Can operate when f XT is selected as the count clock. Can operate. External interrupt INT1, INT2, and INT4 can operate. Only INT0 cannot operate. Note 2 CPU Does not operate. Release signal An interrupt request signal from hardware whose operation is enabled by the interrupt enable flag or the generation of a RESET signal Notes 1. Operation is possible only when the main system clock operates. 2. Operation is possible only when the noise eliminator is not selected by bit 2 of the edge detection mode register (IM0) (when IM02 = 1). 35 µPD750104, 750106, 750108, 750104(A), 750106(A), 750108(A) 9. RESET FUNCTION The µPD750108 is reset with the external reset signal (RESET) or the reset signal received from the basic interval timer/watchdog timer. When either reset signal is input, the internal reset signal is generated. Figure 9-1 shows the configuration of the reset circuit. Figure 9-1. Configuration of Reset Functions RESET Internal reset signal Reset signal from basic interval timer/watchdog timer WDTM Internal bus When the RESET signal is generated, all hardware is initialized as indicated in Table 9-1. Figure 9-2 shows the reset operation timing. Figure 9-2. Reset Operation by Generation of RESET Signal Wait Note RESET signal is generated Operating mode or standby mode Internal reset operation Note 56/fCC (28 µ s at 2.0 MHz, 56 µ s at 1.0 MHz) 36 HALT mode Operating mode µPD750104, 750106, 750108, 750104(A), 750106(A), 750108(A) Table 9-1. Status of the Hardware after a Reset (1/2) Generation of a RESET signal in a standby mode Generation of a RESET signal during operation µPD750104 4 low-order bits at address 0000H in program memory are set in PC bits 11 to 8, and the data at address 0001H are set in PC bits 7 to 0. 4 low-order bits at address 0000H in program memory are set in PC bits 11 to 8, and the data at address 0001H are set in PC bits 7 to 0. µPD750106, 750108 5 low-order bits at address 0000H in program memory are set in PC bits 12 to 8, and the data at address 0001H are set in PC bits 7 to 0. 5 low-order bits at address 0000H in program memory are set in PC bits 12 to 8, and the data at address 0001H are set in PC bits 7 to 0. Held Undefined Skip flags (SK0 to SK2) 0 0 Interrupt status flags (IST0, IST1) 0 0 Hardware Program counter (PC) PSW Carry flag (CY) Bank enable flags (MBE, RBE) Bit 6 at address 0000H in program memory is set in RBE, and bit 7 is set in MBE. Bit 6 at address 0000H in program memory is set in RBE, and bit 7 is set in MBE. Undefined Undefined 1000B 1000B Data memory (RAM) Held Undefined General-purpose registers (X, A, H, L, D, E, B, C) Held Undefined Bank selection register (MBS, RBS) 0, 0 0, 0 Undefined Undefined Mode register (BTM) 0 0 Watchdog timer enable flag (WDTM) 0 0 Counter (T0) 0 0 FFH FFH Mode register (TM0) 0 0 TOE0, TOUT flip-flop 0, 0 0, 0 0 0 FFH FFH Mode register (TM1) 0 0 TOE1, TOUT flip-flop 0, 0 0, 0 Clock timer Mode register (WM) 0 0 Serial interface Shift register (SIO) Held Undefined Operation mode register (CSIM) 0 0 SBI control register (SBIC) 0 0 Held Undefined Stack pointer (SP) Stack bank selection register (SBS) Basic interval timer/ watchdog timer Timer/event counter Timer counter Counter (BT) Modulo register (TMOD0) Counter (T1) Modulo register (TMOD1) Slave address register (SVA) 37 µPD750104, 750106, 750108, 750104(A), 750106(A), 750108(A) Table 9-1. Status of the Hardware after a Reset (2/2) Generation of a RESET signal in a standby mode Generation of a RESET signal during operation Processor clock control register (PCC) 0 0 System clock control register (SCC) 0 0 Clock output mode register (CLOM) 0 0 0 0 Reset (0) Reset (0) Interrupt enable flag (IE×××) 0 0 Priority selection register (IPS) 0 0 0, 0, 0 0, 0, 0 Output buffer Off Off Output latch Hardware Clock generator, clock output circuit Sub-oscillator control register (SOS) Interrupt Interrupt request flag (IRQ×××) INT0, INT1, and INT2 mode registers (IM0, IM1, IM2) Digital ports Clear (0) Clear (0) I/O mode registers (PMGA, PMGB, PMGC) 0 0 Pull-up resistor specification registers (POGA, POGB) 0 0 Held Undefined Bit sequential buffers (BSB0 to BSB3) 38 µPD750104, 750106, 750108, 750104(A), 750106(A), 750108(A) 10. MASK OPTION The µPD750108 has the following mask options: • Mask option of P40 to P43 and P50 to P53 Can specify whether to incorporate the pull-up resistor. 1 The pull-up resistor is incorporated bit by bit. 2 The pull-up resistor is not incorporated. • Mask option of standby function Can specify the wait time when STOP mode was released by an interrupt. 1 29/f CC (256 µ s at 2.0 MHz, 512 µ s at 1.0 MHz) 2 No wait • Mask option of subsystem clock Can specify whether to enable the built-in feedback resistor. 1 The built-in feedback resistor is enabled (it is turned on or off by software). 2 The built-in feedback resistor is disabled (it is cut by hardware). 39 µPD750104, 750106, 750108, 750104(A), 750106(A), 750108(A) 11. INSTRUCTION SET (1) Operand identifier and its descriptive method The operands are described in the operand column of each instruction according to the descriptive method for the operand format of the appropriate instructions. (For details, refer to the RA75X Assembler Package User's Manual: Language (EEU-1363).) For descriptions in which alternatives exist, one element should be selected. Capital letters and plus and minus signs are keywords; therefore, they should be described as they are. For immediate data, the appropriate numerical values or labels should be described. The symbols of register flags can be used as a label instead of mem, fmem, pmem, and bit. (For details, refer to the µPD750108 User’s Manual (U11330E).) However, there are some restrictions on usable labels for fmem and pmem. Representation format Description reg reg1 X, A, B, C, D, E, H, L X, B, C, D, E, H, L rp rp1 rp2 rp' rp'1 XA, BC, DE, HL BC, DE, HL BC, DE XA, BC, DE, HL, XA', BC', DE', HL' BC, DE, HL, XA', BC', DE', HL' rpa rpa1 HL, HL+, HL-, DE, DL DE, DL n4 n8 4-bit immediate data or label 8-bit immediate data or label mem bit 8-bit immediate data or labelNote 2-bit immediate data or label fmem pmem FB0H - FBFH, FF0H - FFFH immediate data or label FC0H - FFFH immediate data or label addr 0000H - 0FFFH immediate data or label (µ PD750104) 0000H - 17FFH immediate data or label ( µPD750106) 0000H - 1FFFH immediate data or label (µ PD750108) addr1(for Mk ΙΙ mode only) 0000H - 0FFFH immediate data or label (µ PD750104) 0000H - 17FFH immediate data or label ( µPD750106) 0000H - 1FFFH immediate data or label (µ PD750108) caddr 12-bit immediate data or label faddr 11-bit immediate data or label taddr 20H - 7FH immediate data (however, bit 0 = 0) or label PORTn IE××× RBn MBn PORT0 - PORT8 IEBT, IET0, IET1, IE0 - IE2, IE4, IECSI, IEW RB0 - RB3 MB0, MB1, MB15 Note Only even address can be specified for 8-bit data processing. 40 µPD750104, 750106, 750108, 750104(A), 750106(A), 750108(A) (2) Symbol definitions in operation description A : A register; 4-bit accumulator B : B register C : C register D : D register E : E register H : H register L : L register X : X register XA : Register pair (XA); 8-bit accumulator BC : Register pair (BC) DE : Register pair (DE) HL : Register pair (HL) XA' : Extended register pair (XA') BC' : Extended register pair (BC') DE' : Extended register pair (DE') HL' : Extended register pair (HL') PC : Program counter SP : Stack pointer CY : Carry flag; Bit accumulator PSW : Program status word MBE : Memory bank enable flag RBE : Register bank enable flag PORTn : Port n (n = 0 to 8) IME : Interrupt master enable flag IPS : Interrupt priority specification register IE××× : Interrupt enable flag RBS : Register bank selection register MBS : Memory bank selection register PCC : Processor clock control register . : Address bit delimiter (××) : Contents addressed by ×× ××H : Hexadecimal data 41 µPD750104, 750106, 750108, 750104(A), 750106(A), 750108(A) (3) Symbols used for the addressing area column *1 MB = MBE • MBS (MBS = 0, 1, 15) *2 MB = 0 *3 MBE = 0 : MB = 0 (000H - 07FH), MB = 15 (F80H - FFFH) Data memory addressing MBE = 1 : MB = MBS (MBS = 0, 1, 15) *4 MB = 15, fmem = FB0H - FBFH, FF0H - FFFH *5 MB = 15, pmem = FC0H - FFFH *6 addr = 0000H - 0FFFH (µPD750104), 0000H - 17FFH ( µPD750106) 0000H - 1FFFH (µPD750108) *7 addr, addr1 = (Current PC) - 15 to (Current PC) - 1 (Current PC) + 2 to (Current PC) + 16 *8 caddr = 0000H - 0FFFH (µ PD750104) 0000H - 0FFFH (PC12 = 0: µPD750106, 750108) Program memory addressing 1000H - 17FFH (PC12 = 1: µPD750106) 1000H - 1FFFH (PC12 = 1: µ PD750108) *9 faddr = 0000H - 07FFH * 10 taddr = 0020H - 007FH * 11 Mk ΙΙ mode only addr1 = 0000H - 0FFFH ( µ PD750104) 0000H - 17FFH (µPD750106) 0000H - 1FFFH ( µPD750108) Remarks 1. MB indicates the memory bank that can be accessed. 2. For *2, MB = 0 regardless of MBE and MBS settings. 3. For *4 and *5, MB = 15 regardless of MBE and MBS settings. 4. For *6 to *11, each addressable area is indicated. (4) Description of machine cycle column S indicates the number of machine cycles necessary for skipping any skip instruction. The value of S changes as follows: • When no skip is performed : S=0 • When a 1-byte or 2-byte instruction is skipped : S = 1 • When a 3-byte instructionNote is skipped : S=2 Note 3-byte instruction: BR !addr, BRA !addr1, CALL !addr, and CALLA !addr1 instructions. Caution The GETI instruction is skipped in one machine cycle. One machine cycle is equal to one cycle (= tCY) of the CPU clock (Φ), and four types of times are available for selection according to the PCC setting. 42 µPD750104, 750106, 750108, 750104(A), 750106(A), 750108(A) Group Transfer Mnemonic MOV XCH Table reference MOVT Operand MachinBytes ing cycle Operation Addressing area Skip condition A, #n4 1 1 A ← n4 reg1, #n4 2 2 reg1 ← n4 XA, #n8 2 2 XA ← n8 String A HL, #n8 2 2 HL ← n8 String B rp2, #n8 2 2 rp2 ← n8 A, @HL 1 1 A ← (HL) *1 A, @HL+ 1 2+S A ← (HL), then L ← L + 1 *1 L=0 A, @HL- 1 2+S A ← (HL), then L ← L - 1 *1 L = FH A, @rpa1 1 1 A ← (rpa1) *2 XA, @HL 2 2 XA ← (HL) *1 @HL, A 1 1 (HL) ← A *1 @HL, XA 2 2 (HL) ← XA *1 A, mem 2 2 A ← (mem) *3 XA, mem 2 2 XA ← (mem) *3 mem, A 2 2 (mem) ← A *3 mem, XA 2 2 (mem) ← XA *3 A, reg 2 2 A ← reg XA, rp' 2 2 XA ← rp' reg1, A 2 2 reg1 ← A rp'1, XA 2 2 rp'1 ← XA A, @HL 1 1 A ↔ (HL) *1 A, @HL+ 1 2+S A ↔ (HL), then L ← L + 1 *1 L=0 A, @HL- 1 2+S A ↔ (HL), then L ← L - 1 *1 L = FH A, @rpa1 1 1 A ↔ (rpa1) *2 XA, @HL 2 2 XA ↔ (HL) *1 A, mem 2 2 A ↔ (mem) *3 XA, mem 2 2 XA ↔ (mem) *3 A, reg1 1 1 A ↔ reg1 XA, rp' 2 2 XA ↔ rp' XA, @PCDE 1 3 • µPD750104 XA ← (PC11-8 + DE) ROM String A • µPD750106, 750108 XA ← (PC12-8 + DE) ROM XA, @PCXA 1 3 • µPD750104 XA ← (PC11-8 + XA) ROM • µPD750106, 750108 XA ← (PC12-8 + XA) ROM XA, @BCDE XA, @BCXA 1 1 3 XA ← (BCDE) ROMNote *6 3 XA ← *6 (BCXA) ROM Note Note Set register B to 0 in the µPD750104. Only the LSB is valid in register B in the µ PD750106 and µPD750108. 43 µPD750104, 750106, 750108, 750104(A), 750106(A), 750108(A) Group Mnemonic Bit transfer MOV1 Arithmetic ADDS ADDC SUBS SUBC AND OR XOR Operand MachinBytes ing cycle Operation Addressing area Skip condition CY, fmem.bit 2 2 CY ← (fmem.bit) *4 CY, pmem.@L 2 2 CY ← (pmem 7-2 + L 3-2.bit(L1-0)) *5 CY, @H+mem.bit 2 2 CY ← (H + mem3-0.bit) *1 fmem.bit, CY 2 2 (fmem.bit) ← CY *4 pmem.@L, CY 2 2 (pmem7-2 + L3-2.bit(L1-0)) ← CY *5 @H+mem.bit, CY 2 2 (H + mem 3-0.bit) ← CY *1 A, #n4 1 1+S A ← A + n4 carry XA, #n8 2 2+S XA ← XA + n8 carry A, @HL 1 1+S A ← A + (HL) XA, rp' 2 2+S XA ← XA + rp' carry rp'1, XA 2 2+S rp'1 ← rp'1 + XA carry A, @HL 1 1 A, CY ← A + (HL) + CY XA, rp' 2 2 XA, CY ← XA + rp' + CY rp'1, XA 2 2 rp'1, CY ← rp'1 + XA + CY A, @HL 1 1+S A ← A - (HL) XA, rp' 2 2+S XA ← XA - rp' borrow rp'1, XA 2 2+S rp'1 ← rp'1 - XA borrow A, @HL 1 1 A, CY ← A - (HL) - CY XA, rp' 2 2 XA, CY ← XA - rp' - CY rp'1, XA 2 2 rp'1, CY ← rp'1 - XA - CY A, #n4 2 2 A, @HL 1 1 XA, rp' 2 2 rp'1, XA 2 2 A, #n4 2 2 A, @HL 1 1 XA, rp' 2 2 rp'1, XA 2 2 A, #n4 2 2 A, @HL 1 1 XA, rp' 2 2 rp'1, XA 2 2 ∧ n4 A ← A ∧ (HL) XA ← XA ∧ rp' rp'1 ← rp'1 ∧ XA A ← A ∨ n4 A ← A ∨ (HL) XA ← XA ∨ rp' rp'1 ← rp'1 ∨ XA A ← A ∨ n4 A ← A ∨ (HL) XA ← XA ∨ rp' rp'1 ← rp'1 ∨ XA *1 carry *1 *1 borrow *1 A←A *1 *1 *1 Accumulator RORC A 1 1 CY ← A 0, A3 ← CY, An-1 ← A n manipulation NOT A 2 2 A←A Increment/ INCS reg 1 1+S reg ← reg + 1 reg = 0 rp1 1 1+S rp1 ← rp1 + 1 rp1 = 00H @HL 2 2+S (HL) ← (HL) + 1 *1 (HL) = 0 mem 2 2+S (mem) ← (mem) + 1 *3 (mem) = 0 reg 1 1+S reg ← reg - 1 reg = FH rp' 2 2+S rp' ← rp' - 1 rp' = FFH decrement DECS 44 µPD750104, 750106, 750108, 750104(A), 750106(A), 750108(A) Group Comparison Carry flag manipulation Memory bit manipulation Mnemonic Operand MachinBytes ing cycle Operation Addressing area Skip condition reg, #n4 2 2+S Skip if reg = n4 @HL, #n4 2 2+S Skip if (HL) = n4 *1 (HL) = n4 A, @HL 1 1+S Skip if A = (HL) *1 A = (HL) XA, @HL 2 2+S Skip if XA = (HL) *1 XA = (HL) A, reg 2 2+S Skip if A = reg A = reg XA, rp' 2 2+S Skip if XA = rp' XA = rp' SET1 CY 1 1 CY ← 1 CLR1 CY 1 1 CY ← 0 SKT CY 1 1+S NOT1 CY 1 1 CY ← CY SET1 mem.bit 2 2 (mem.bit) ← 1 *3 fmem.bit 2 2 (fmem.bit) ← 1 *4 pmem. @L 2 2 (pmem7-2 + L3-2.bit(L1-0)) ← 1 *5 @H+mem.bit 2 2 (H + mem 3-0.bit) ← 1 *1 mem.bit 2 2 (mem.bit) ← 0 *3 fmem.bit 2 2 (fmem.bit) ← 0 *4 pmem. @L 2 2 (pmem7-2 + L3-2.bit(L1-0)) ← 0 *5 @H+mem.bit 2 2 (H + mem 3-0.bit) ← 0 *1 mem.bit 2 2+S Skip if (mem.bit) = 1 *3 (mem.bit) = 1 fmem.bit 2 2+S Skip if (fmem.bit) = 1 *4 (fmem.bit) = 1 pmem. @L 2 2+S Skip if (pmem7-2 + L3-2.bit(L1-0)) = 1 *5 (pmem.@L) = 1 @H+mem.bit 2 2+S Skip if (H + mem3-0.bit) = 1 *1 (@H + mem.bit) = 1 mem.bit 2 2+S Skip if (mem.bit) = 0 *3 (mem.bit) = 0 fmem.bit 2 2+S Skip if (fmem.bit) = 0 *4 (fmem.bit) = 0 pmem. @L 2 2+S Skip if (pmem7-2 + L3-2.bit(L1-0)) = 0 *5 (pmem.@L) = 0 @H+mem.bit 2 2+S Skip if (H + mem3-0.bit) = 0 *1 (@H + mem.bit) = 0 fmem.bit 2 2+S Skip if (fmem.bit) = 1 and clear *4 (fmem.bit) = 1 pmem. @L 2 2+S Skip if (pmem7-2 + L3-2 .bit(L1-0 )) = 1 and clear *5 (pmem.@L) = 1 @H+mem.bit 2 2+S Skip if (H + mem3-0.bit) = 1 and clear *1 (@H + mem.bit) = 1 CY, fmem.bit 2 2 CY ← CY CY, pmem. @L 2 2 CY ← CY CY, @H+mem.bit 2 2 CY ← CY CY, fmem.bit 2 2 CY ← CY CY, pmem. @L 2 2 CY ← CY CY, @H+mem.bit 2 2 CY ← CY CY, fmem.bit 2 2 CY ← CY CY, pmem.@L 2 2 CY ← CY CY, @H+mem.bit 2 2 CY ← CY SKE CLR1 SKT SKF SKTCLR AND1 OR1 XOR1 reg = n4 CY = 1 Skip if CY = 1 ∧ (fmem.bit) ∧ (pmem7-2 + L 3-2.bit(L1-0 )) ∧ (H + mem3-0.bit) ∨ (fmem.bit) ∨ (pmem7-2 + L 3-2.bit(L1-0 )) ∨ (H + mem3-0.bit) ∨ (fmem.bit) ∨ (pmem7-2 + L3-2 .bit(L1-0)) ∨ (H + mem3-0.bit) *4 *5 *1 *4 *5 *1 *4 *5 *1 45 µPD750104, 750106, 750108, 750104(A), 750106(A), 750108(A) Group Branch Mnemonic BR Note Operand addr MachinBytes ing cycle - - Operation • µ PD750104 Addressing area Skip condition *6 PC 11-0 ← addr The assembler selects the most adequate instruction from BR !addr, BRCB !caddr, or BR $addr. • µ PD750106, 750108 PC 12-0 ← addr The assembler selects the most adequate instruction from BR !addr, BRCB !caddr, or BR $addr. addr1 - - • µ PD750104 *11 PC 11-0 ← addr1 The assembler selects the most adequate instruction from instructions below. • • • • BR !addr BRA !addr1 BRCB !caddr BR $addr1 • µ PD750106, 750108 PC 12-0 ← addr1 The assembler selects the most adequate instruction from instructions below. • • • • !addr 3 3 BR !addr BRA !addr1 BRCB !caddr BR $addr1 • µ PD750104 *6 PC 11-0 ← addr • µ PD750106, 750108 PC 12-0 ← addr $addr 1 2 • µ PD750104 *7 PC 11-0 ← addr • µ PD750106, 750108 PC 12-0 ← addr $addr1 1 2 • µ PD750104 PC 11-0 ← addr1 • µ PD750106, 750108 PC 12-0 ← addr1 Note The shaded portion is supported in Mk ΙΙ mode only. The other portions are supported in Mk Ι mode only. 46 µPD750104, 750106, 750108, 750104(A), 750106(A), 750108(A) Group Branch Mnemonic BR Operand PCDE MachinBytes ing cycle 2 3 Operation Addressing area Skip condition • µ PD750104 PC 11-0 ← PC11-8 + DE • µ PD750106, 750108 PC 12-0 ← PC12-8 + DE PCXA 2 3 • µ PD750104 PC 11-0 ← PC11-8 + XA • µ PD750106, 750108 PC 12-0 ← PC12-8 + XA BCDE 2 3 • µ PD750104 PC 11-0 ← *6 BCDENote 1 • µ PD750106, 750108 PC 12-0 ← BCDENote 2 BCXA 2 3 • µ PD750104 PC 11-0 ← *6 BCXANote 1 • µ PD750106, 750108 PC 12-0 ← BCXANote 2 BRA Note 3 !addr1 3 3 • µ PD750104 *11 PC 11-0 ← addr1 • µ PD750106, 750108 PC 12-0 ← addr1 BRCB !caddr 2 2 • µ PD750104 *8 PC 11-0 ← caddr11-0 • µ PD750106, 750108 PC 12-0 ← PC12 + caddr11-0 Subroutine stack control CALLANote 3 !addr1 3 3 • µ PD750104 *11 (SP - 2) ← ×, ×, MBE, RBE (SP - 6) (SP - 3) (SP - 4) ← PC11-0 (SP - 5) ← 0, 0, 0, 0 PC 11-0 ← addr1, SP ← SP - 6 • µ PD750106, 750108 (SP - 2) ← ×, ×, MBE, RBE (SP - 6) (SP - 3) (SP - 4) ← PC11-0 (SP - 5) ← 0, 0, 0, PC12 PC 12-0 ← addr1, SP ← SP - 6 Notes 1. Set register B to 0. 2. Only the LSB is valid in register B. 3. The shaded portion is supported in Mk ΙΙ mode only. The other portions are supported in Mk Ι mode only. 47 µPD750104, 750106, 750108, 750104(A), 750106(A), 750108(A) Group Subroutine stack control Mnemonic CALLNote Operand !addr MachinBytes ing cycle 3 3 Operation • µ PD750104 Addressing area Skip condition *6 (SP - 3) ← MBE, RBE, 0, 0 (SP - 4) (SP - 1) (SP - 2) ← PC11-0 PC 11-0 ← addr, SP ← SP - 4 • µ PD750106, 750108 (SP - 3) ← MBE, RBE, 0, PC12 (SP - 4) (SP - 1) (SP - 2) ← PC11-0 PC 12-0 ← addr, SP ← SP - 4 4 • µ PD750104 (SP - 2) ← ×, ×, MBE, RBE (SP - 6) (SP - 3) (SP - 4) ← PC11-0 (SP - 5) ← 0, 0, 0, 0 PC 11-0 ← addr, SP ← SP - 6 • µ PD750106, 750108 (SP - 2) ← ×, ×, MBE, RBE (SP - 6) (SP - 3) (SP - 4) ← PC11-0 (SP - 5) ← 0, 0, 0, PC12 PC 12-0 ← addr, SP ← SP - 6 CALLFNote !faddr 2 2 • µ PD750104 *9 (SP - 3) ← MBE, RBE, 0, 0 (SP - 4) (SP - 1) (SP - 2) ← PC11-0 PC 11-0 ← 0 + faddr, SP ← SP - 4 • µ PD750106, 750108 (SP - 3) ← MBE, RBE, 0, PC12 (SP - 4) (SP - 1) (SP - 2) ← PC11-0 PC 12-0 ← 00 + faddr, SP ← SP - 4 3 • µ PD750104 (SP - 2) ← ×, ×, MBE, RBE (SP - 6) (SP - 3) (SP - 4) ← PC11-0 (SP - 5) ← 0, 0, 0, 0 PC 11-0 ← 0 + faddr, SP ← SP - 6 • µ PD750106, 750108 (SP - 2) ← ×, ×, MBE, RBE (SP - 6) (SP - 3) (SP - 4) ← PC11-0 (SP - 5) ← 0, 0, 0, PC12 PC 12-0 ← 00 + faddr, SP ← SP - 6 Note The shaded portion is supported in Mk ΙΙ mode only. The other portions are supported in Mk Ι mode only. 48 µPD750104, 750106, 750108, 750104(A), 750106(A), 750108(A) Group Subroutine stack control Mnemonic RETNote Operand MachinBytes ing cycle 1 3 Operation Addressing area Skip condition • µPD750104 PC 11-0 ← (SP) (SP + 3) (SP + 2) MBE, RBE, 0, 0 ← (SP + 1), SP ← SP + 4 • µPD750106, 750108 PC 11-0 ← (SP) (SP + 3) (SP + 2) MBE, RBE, 0, PC 12 ← (SP + 1) SP ← SP + 4 3 • µPD750104 ×, ×, MBE, RBE ← (SP + 4) 0, 0, 0, 0 ← (SP + 1) PC 11-0 ← (SP) (SP + 3) (SP + 2) SP ← SP + 6 • µPD750106, 750108 ×, ×, MBE, RBE ← (SP + 4) MBE, 0, 0, PC 12 ← (SP + 1) PC 11-0 ← (SP) (SP + 3) (SP + 2) SP ← SP + 6 RETS Note 1 3+S • µPD750104 Uncondition MBE, RBE, 0, 0 ← (SP + 1) PC 11-0 ← (SP) (SP + 3) (SP + 2) SP ← SP + 4 then skip unconditionally • µPD750106, 750108 MBE, RBE, 0 ← PC12 ← (SP + 1) PC 11-0 ← (SP) (SP + 3) (SP + 2) SP ← SP + 4 then skip unconditionally 3+S • µPD750104 0, 0, 0, 0 ← (SP + 1) PC 11-0 ← (SP) (SP + 3) (SP + 2) ×, ×, MBE, RBE ← (SP + 4) SP ← SP + 6 then skip unconditionally • µPD750106, 750108 0, 0, 0, PC12 ← (SP + 1) PC 11-0 ← (SP) (SP + 3) (SP + 2) ×, ×, MBE, RBE ← (SP + 4) SP ← SP + 4 then skip unconditionally Note The shaded portion is supported in Mk ΙΙ mode only. The other portions are supported in Mk Ι mode only. 49 µPD750104, 750106, 750108, 750104(A), 750106(A), 750108(A) Group Subroutine stack control Mnemonic Operand MachinBytes ing cycle 1 RETINote 1 3 Addressing area Operation Skip condition • µ PD750104 MBE, RBE, 0, 0 ← (SP + 1) PC 11-0 ← (SP) (SP + 3) (SP + 2) PSW ← (SP + 4) (SP + 5), SP ← SP + 6 • µ PD750106, 750108 MBE, RBE, 0, PC 12 ← (SP + 1) PC 11-0 ← (SP) (SP + 3) (SP + 2) PSW ← (SP + 4) (SP + 5), SP ← SP + 6 • µ PD750104 0, 0, 0, 0 ← (SP + 1) PC 11-0 ← (SP) (SP + 3) (SP + 2) PSW ← (SP + 4) (SP + 5), SP ← SP + 6 • µ PD750106, 750108 0, 0, 0, PC12 ← (SP + 1) PC 11-0 ← (SP) (SP + 3) (SP + 2) PSW ← (SP + 4) (SP + 5), SP ← SP + 6 rp 1 1 (SP - 1)(SP - 2) ← rp, SP ← SP - 2 BS 2 2 (SP - 1) ← MBS, (SP - 2) ← RBS, SP ← SP - 2 rp 1 1 rp ← (SP + 1)(SP), SP ← SP + 2 BS 2 2 MBS ← (SP + 1), RBS ← (SP), SP ← SP + 2 2 2 IME (IPS.3) ← 1 2 2 IE××× ← 1 2 2 IME (IPS.3) ← 0 IE××× 2 2 IE××× ← 0 A, PORTn 2 2 A ← PORTn XA, PORTn 2 2 XA ← PORTn+1,PORTn PORTn, A 2 2 PORTn ← A PORTn, XA 2 2 PORTn+1 ,PORTn ← XA HALT 2 2 Set HALT Mode (PCC.2 ← 1) STOP 2 2 Set STOP Mode (PCC.3 ← 1) NOP 1 1 No Operation PUSH POP Interrupt control EI IE××× DI Input/ output INNote 2 OUTNote 2 CPU control (n = 0 - 8) (n = 4, 6) (n = 2 - 8) (n = 4, 6) Notes 1. The shaded portion is supported in Mk ΙΙ mode only. The other portions are supported in Mk Ι mode only. 2. When executing the IN/OUT instruction, MBE must be set to 0 or MBE and MBS must be set to 1 and 15, respectively. 50 µPD750104, 750106, 750108, 750104(A), 750106(A), 750108(A) Group Special Mnemonic SEL GETINotes 1, 2 Operand MachinBytes ing cycle Operation RBn 2 2 RBS ← n (n = 0 - 3) MBn 2 2 MBS ← n (n = 0, 1, 15) taddr 1 3 • µ PD750104 Addressing area Skip condition *10 When the TBR instruction is used PC 11-0 ← (taddr)3-0 + (taddr + 1) ........................................................ When the TCALL instruction is used (SP - 4) (SP - 1) (SP - 2) ← PC 11-0 (SP - 3) ← MBE, RBE, 0, 0 PC 11-0 ← (taddr)3-0 + (taddr + 1) SP ← SP - 4 ........................................................ ..................... When an instruction other than the TBR and TCALL instructions is used Depends on the referenced instruction. Execution of (taddr)(taddr + 1) instruction • µ PD750106, 750108 When the TBR instruction is used PC 12-0 ← (taddr)4-0 + (taddr + 1) ........................................................ When the TCALL instruction is used (SP - 4) (SP - 1) (SP - 2) ← PC 11-0 (SP - 3) ← MBE, RBE, 0, PC12 PC 12-0 ← (taddr)4-0 + (taddr + 1) SP ← SP - 4 ..................... ........................................................ When an instruction other than the TBR and TCALL instructions is used Depends on the referenced instruction. Execution of (taddr)(taddr + 1) instruction 3 • µ PD750104 *10 When the TBR instruction is used PC 11-0 ← (taddr)3-0 + (taddr + 1) ....................................................................... 4 When the TCALL instruction is used (SP - 6) (SP - 3) (SP - 4) ← PC 11-0 (SP - 5) ← 0, 0, 0, 0 (SP - 2) ← ×, ×, MBE, RBE PC 11-0 ← (taddr)3-0 + (taddr + 1) SP ← SP - 6 ....................................................................... 3 When an instruction other than the TBR and TCALL instructions is used Execution of (taddr)(taddr + 1) instruction ..................... Depends on the referenced instruction. Notes 1. The shaded portion is supported in Mk ΙΙ mode only. The other portions are supported in Mk Ι mode only. 2. TBR and TCALL instructions are assembler pseudo instructions to define tables used for GETI instructions. 51 µPD750104, 750106, 750108, 750104(A), 750106(A), 750108(A) Group Special Mnemonic GETINotes 1, 2 Operand taddr MachinBytes ing cycle 1 3 Operation • µ PD750106, 750108 Addressing area Skip condition *10 When the TBR instruction is used PC 12-0 ← (taddr)4-0 + (taddr + 1) ....................................................................... 4 When the TCALL instruction is used (SP - 6) (SP - 3) (SP - 4) ← PC 11-0 (SP - 5) ← 0, 0, 0, PC12 (SP - 2) ← ×, ×, MBE, RBE PC 12-0 ← (taddr)4-0 + (taddr + 1) SP ← SP - 6 ....................................................................... 3 When an instruction other than the TBR and TCALL instructions is used Execution of (taddr)(taddr + 1) instruction ..................... Depends on the referenced instruction. Notes 1. The shaded portion is supported in Mk ΙΙ mode only. 2. TBR and TCALL instructions are assembler pseudo instructions to define tables used for GETI instructions. 52 µPD750104, 750106, 750108, 750104(A), 750106(A), 750108(A) 12. ELECTRICAL CHARACTERISTICS ABSOLUTE MAXIMUM RATINGS (TA = 25 °C) Parameter Conditions Symbol Rated value Unit -0.3 to +7.0 V Supply voltage VDD Input voltage VI1 Other than ports 4 and 5 -0.3 to VDD + 0.3 V VI2 Ports With a built-in pull-up resistor -0.3 to VDD + 0.3 V 4 and 5 With N-ch open drain -0.3 to +14.0 V -0.3 to VDD + 0.3 V Each pin -10 mA Total of all pins -30 mA 30 mA 220 mA Output voltage VO High-level output current IOH Low-level output current Each pin IOL Total of all pins Operating ambient temperature TA -40 to +85 °C Storage temperature Tstg -65 to +150 °C Caution Absolute maximum ratings are rated values beyond which physical damage will be caused to the product; if the rated value of any of the parameters in the above table is exceeded, even momentarily, the quality of the product may deteriorate. Always use the product within its rated values. CAPACITANCE (TA = 25 °C, VDD = 0 V) Parameter Symbol Input capacitance CIN Output capacitance COUT I/O capacitance CIO Conditions f = 1 MHz 0 V for pins other than pins to be measured MIN. TYP. MAX. Unit 15 pF 15 pF 15 pF 53 µPD750104, 750106, 750108, 750104(A), 750106(A), 750108(A) CHARACTERISTICS OF THE MAIN SYSTEM CLOCK OSCILLATOR (TA = -40 to +85 °C, VDD = 1.8 to 5.5 V) Resonator RC oscillator Recommended constant Parameter Conditions Oscillator frequency (fCC) Note CL1 MIN. 0.4 TYP. MAX. Unit 2.0 MHz CL2 Note The oscillator frequency indicates only the oscillator characteristics. See AC characteristics for the instruction execution time and oscillator frequency characteristics. Caution When the main system clock oscillator is used, conform to the following guidelines when wiring at the portions surrounded by dotted lines in the figures above to eliminate the influence of the wiring capacity. • The wiring must be as short as possible. • Other signal lines must not run in these areas. • Any line carrying a high fluctuating current must be kept away as far as possible. • The grounding point of the capacitor of the oscillator must have the same potential as that of VSS. • It must not be grounded to ground patterns carrying a large current. • No signal must be taken from the oscillator. 54 µPD750104, 750106, 750108, 750104(A), 750106(A), 750108(A) CHARACTERISTICS OF THE SUBSYSTEM CLOCK OSCILLATOR (TA = -40 to +85 °C, VDD = 1.8 to 5.5 V) Resonator Recommended constant Parameter Conditions Oscillator frequency (fXT) Note 1 Crystal XT1 MIN. TYP. MAX. Unit 32 32.768 35 kHz 1.0 2 s 10 s XT2 R C3 External clock C4 XT1 XT2 Oscillation settling time Note 2 VDD = 4.5 to 5.5 V (fXT) Note 1 32 100 kHz XT1 input high/low level width (tXTH , tXTL) 5 15 µs XT1 input frequency Notes 1. The oscillator frequency and input frequency indicate only the oscillator characteristics. See the item of AC characteristics for the instruction execution time. 2. The oscillation settling time means the time required for the oscillation to settle after VDD is applied. Caution When the subsystem clock oscillator is used, conform to the following guidelines when wiring at the portions of surrounded by dotted lines in the figures above to eliminate the influence of the wiring capacity. • The wiring must be as short as possible. • Other signal lines must not run in these areas. • Any line carrying a high fluctuating current must be kept away as far as possible. • The grounding point of the capacitor of the oscillator must have the same potential as that of VSS • It must not be grounded to ground patterns carrying a large current. • No signal must be taken from the oscillator. When the subsystem clock is used, pay special attention to its wiring; the subsystem clock oscillator has low amplification to minimize current consumption and is more likely to malfunction due to noise than the main system clock oscillator. 55 µPD750104, 750106, 750108, 750104(A), 750106(A), 750108(A) DC CHARACTERISTICS (T A = -40 to +85 °C, VDD = 1.8 to 5.5 V) Parameter Symbol Low-level output current IOL High-level input voltage VIH1 MIN. VIH3 Each pin Ports 2, 3, and 8 15 mA 150 mA 2.7 V ≤ VDD ≤ 5.5 V 0.7VDD VDD V 1.8 V ≤ VDD < 2.7 V 0.9VDD VDD V 0.8VDD VDD V 0.9VDD VDD V 2.7 V ≤ VDD ≤ 5.5 V 0.7VDD VDD V 1.8 V ≤ VDD < 2.7 V 0.9VDD VDD V With N-ch open drain 2.7 V ≤ VDD ≤ 5.5 V 0.7VDD 13 V 1.8 V ≤ VDD < 2.7 V 0.9VDD 13 V VDD - 0.1 VDD V 2.7 V ≤ VDD ≤ 5.5 V 0 0.3VDD V 1.8 V ≤ VDD < 2.7 V 0 0.1VDD V 2.7 V ≤ VDD ≤ 5.5 V 0 0.2VDD V 1.8 V ≤ VDD < 2.7 V 0 0.1VDD V 0 0.1 V XT1 VIL1 Ports 2 to 5, and 8 Ports 0, 1, 6, and 7 and RESET VIL3 XT1 High-level output voltage VOH SCK, SO, and ports 2, 3, and 6 to 8 I OH = -1.0 mA Low-level output voltage VOL1 SCK, SO, and ports 2 to 8 I OL = 1.6 mA VOL2 SB0, SB1 N-ch open drain ILIH1 VIN = VDD Low-level input leakage current Unit 2.7 V ≤ VDD ≤ 5.5 V Ports 4 and With a Built-in pull-up 5 resistor ILIH2 MAX. 1.8 V ≤ VDD < 2.7 V Ports 0, 1, 6, and 7 and RESET VIH4 VIL2 High-level input leakage current TYP. Total of all pins VIH2 Low-level input voltage Conditions VDD - 0.5 I OL = 15 mA, VDD = 5.0 V ± 10% V 2.0 V 0.4 V 0.2VDD V Other than XT1 3 µA XT1 20 µA 0.2 Pull-up resistor ≥ 1 kΩ ILIH3 VIN = 13 V Ports 4 and 5 (With N-ch open drain) 20 µA ILIL1 VIN = 0 V Other than XT1 and ports 4 and 5 -3 µA -20 µA -3 µA -30 µA ILIL2 XT1 ILIL3 Ports 4 and 5 (With N-ch open drain) At other than input instruction execution Ports 4 and 5 (With N-ch open drain) When the input instruction is executed VDD = 5.0 V -10 -27 µA VDD = 3.0 V -3 -8 µA 3 µA ILOH1 VOUT = VDD ILOH2 VOUT = 13 V Ports 4 and 5 (With N-ch open drain) 20 µA Low-level output leakage current ILOL VOUT = 0 V -3 µA Built-in pull-up resistor RL1 VIN = 0 V High-level output leakage current 56 RL2 SCK, SO/SB0, SB1, and ports 2, 3, and 6 to 8 Ports 4 and 5 (With a built-in pull-up resistor) Ports 0 to 3 and 6 to 8 (except P00 pin) 50 100 200 kΩ Ports 4 and 5 (mask option) 15 30 60 kΩ µPD750104, 750106, 750108, 750104(A), 750106(A), 750108(A) DC CHARACTERISTICS (TA = -40 to +85 °C, VDD = 1.8 to 5.5 V) Symbol Parameter Power supply current Note 1 IDD1 IDD2 TYP. MAX. Unit 10%Note 3 0.65 1.6 mA VDD = 3.0 V ± 10%Note 4 180 360 µA V DD = 5.0 V ± 10% 370 920 µA V DD = 3.0 V ± 10% 170 340 µA V DD = 3.0 V ± 10% 11.0 40.0 µA V DD = 2.0 V ± 10% 5.5 18.0 µA V DD = 3.0 V, TA = 25 °C 11.0 18.0 µA V DD = 3.0 V ± 10% 8.0 24.0 µA V DD = 3.0 V, TA = 25 °C 8.0 14.0 µA Conditions 1.0 MHzNote 2 RC oscillation R = 22 kΩ, VDD = 5.0 V ± HALT mode C = 22 pF IDD3 32.768 kHz Note 5 crystal oscillation Low-voltage modeNote 6 Low-currentdrain modeNote 7 IDD4 MIN. VDD = 3.0 V ± 10% 5.0 30.0 µA tage VDD = 3.0 V, modeNote 6 TA = -40 to +50 °C 5.0 12.0 µA VDD = 2.0 V ± 10% 2.5 10.0 µA VDD = 3.0 V, TA = 25 °C 5.0 10.0 µA 4.0 15.0 µA 4.0 8.0 µA 4.0 7.0 µA VDD = 5.0 V ± 10% 0.05 5.0 µA VDD = 3.0 V ± 10% 0.02 2.5 µA 0.02 0.2 µA HALT mode Low-vol- Low-curVDD = 3.0 V ± 10% rent-drain Note 7 mode VDD = 3.0 V, TA = -40 to +50 °C VDD = 3.0 V, TA = 25 °C IDD5 XT1 = 0 VNote 8 STOP mode TA = 25 °C Notes 1. This current excludes the current which flows through the built-in pull-up resistors. 2. This value applies also when the subsystem clock oscillates. 3. Value when the processor clock control register (PCC) is set to 0011 and the µPD750108 is operated in the high-speed mode. 4. Value when the PCC is set to 0000 and the µPD750108 is operated in the low-speed mode. 5. This value applies when the system clock control register (SCC) is set to 1001 to stop the main system clock pulse and to start the subsystem clock pulse. 6. Mode when the sub-oscillator control register (SOS) is set to 0000. 7. Mode when the SOS is set to 0010. 8. This value applies when the SOS is set to 00×1 and the sub-oscillator feedback resistor is not used (× = don’t care). 57 µPD750104, 750106, 750108, 750104(A), 750106(A), 750108(A) AC CHARACTERISTICS (TA = -40 to +85 °C, VDD = 1.8 to 5.5 V) Parameter t CY CPU clock cycle time Note 1 (minimum instruction execution time = 1 machine cycle) TI0 input frequency Conditions Symbol f TI µs 125 µs 0 1 MHz 0 275 kHz 114 VDD = 2.7 to 5.5 V TYP. 122 0.48 µs 1.8 µs IM02 = 0 Note 2 µs IM02 = 1 10 µs INT1, INT2, and INT4 10 µs KR0 to KR7 10 µs 10 µs Interrupt input high/low level width t INTH, t INTL INT0 f CC 128 Operated by subsystem clock pulse VDD = 2.7 to 5.5 V RC oscillator frequency Unit 2.0 t TIH, t TIL t RSL MAX. Operated by main system clock pulse TI0 input high/low level width RESET low level width MIN. R = 22 kΩ, VDD = 2.7 to 5.5 V 0.90 1.00 1.30 MHz C = 22 pF VDD = 2.7 to 5.5 V 0.55 1.00 1.30 MHz Notes 1. When the main system clock is used, the tCY vs. VDD cycle time of the CPU clock (Φ) (minimum instruction execution time) depends on the time constants of connected resistors (R) (Main system clock in operation) 128 and capacitors (C) and the processor clock 6 control register (PCC). 5 When the subsystem clock is used, the cycle quency of the connected resonator (and external clock), the system clock control register (SCC), and the processor clock control register (PCC). Cycle time tCY [µs] tion execution time) depends on the fre- Operation guaranteed range 4 time of the CPU clock (Φ) (minimum instruc- 3 2 The figure on the right side shows the cycle time tCY characteristics for the supply voltage 1 VDD during main system clock operation. 2. This value becomes 2tCY or 128/fCC according to the setting of the interrupt mode register (IM0). 58 0.5 0 1 1.8 2 3 4 5 5.5 6 Power supply voltage VDD [V] µPD750104, 750106, 750108, 750104(A), 750106(A), 750108(A) SERIAL TRANSFER OPERATION Two-wire and three-wire serial I/O modes (SCK: Internal clock output): (TA = -40 to +85 °C, VDD = 1.8 to 5.5 V) Parameter SCK cycle time Symbol t KCY1 Conditions VDD = 2.7 to 5.5 V SCK high/low level width t KL1, tKH1 VDD = 2.7 to 5.5 V SI Note 1 setup time (referred to SCK↑) tSIK1 VDD = 2.7 to 5.5 V SI Note 1 hold time (referred to SCK↑) tKSI1 Delay time from SCK↓ to SO Note 1 output tKSO1 VDD = 2.7 to 5.5 V RL = 1 kΩ Note 2 CL = 100 pF MIN. TYP. MAX. Unit 1,300 ns 3,800 ns tKCY1/2 - 50 ns t KCY1/2 - 150 ns 150 ns 500 ns 400 ns 600 ns VDD = 2.7 to 5.5 V 0 250 ns 0 1,000 ns Notes 1. In two-wire serial I/O mode, SO should be read as SB0 or SB1. 2. RL is the resistance of the SO output line load, while CL is the capacitance. Two-wire and three-wire serial I/O modes (SCK: External clock input): (TA = -40 to +85 °C, VDD = 1.8 to 5.5 V) Parameter SCK cycle time Symbol t KCY2 Conditions VDD = 2.7 to 5.5 V SCK high/low level width t KL2, t KH2 VDD = 2.7 to 5.5 V SI Note 1 setup time (referred to SCK↑) t SIK2 VDD = 2.7 to 5.5 V SI Note 1 hold time (referred to SCK↑) t KSI2 Delay time from SCK↓ to SO Note 1 output t KSO2 VDD = 2.7 to 5.5 V kΩ Note 2 RL = 1 CL = 100 pF MIN. TYP. MAX. Unit 800 ns 3,200 ns 400 ns 1,600 ns 100 ns 150 ns 400 ns 600 ns VDD = 2.7 to 5.5 V 0 300 ns 0 1,000 ns Notes 1. In two-wire serial I/O mode, SO should be read as SB0 or SB1. 2. RL is the resistance of the SO output line load, while CL is the capacitance. 59 µPD750104, 750106, 750108, 750104(A), 750106(A), 750108(A) SBI mode (SCK: Internal clock output (master)): (TA = -40 to +85 °C, VDD = 1.8 to 5.5 V) Parameter SCK cycle time Symbol t KCY3 Conditions VDD = 2.7 to 5.5 V SCK high/low level width t KL3, tKH3 VDD = 2.7 to 5.5 V SB0/SB1 setup time (referred to SCK↑) tSIK3 VDD = 2.7 to 5.5 V SB0/SB1 hold time (referred to SCK↑) tKSI3 Delay time from SCK↓ to SB0/SB1 output tKSO3 RL = 1 kΩ Note CL = 100 pF VDD = 2.7 to 5.5 V MIN. TYP. MAX. Unit 1,300 ns 3,800 ns tKCY3/2 - 50 ns t KCY3/2 - 150 ns 150 ns 500 ns tKCY3/2 ns 0 250 ns 0 1,000 ns From SCK↑ to SB0/SB1↓ tKSB tKCY3 ns From SB0/SB1↓ to SCK↓ tSBK tKCY3 ns SB0/SB1 low level width tSBL tKCY3 ns t SBH tKCY3 ns SB0/SB1 high level width Note RL is the resistance of the SB0/SB1 output line load, while CL is the capacitance. SBI mode (SCK: External clock input (slave)): (TA = -40 to +85 °C, VDD = 1.8 to 5.5 V) Parameter SCK cycle time Symbol t KCY4 Conditions VDD = 2.7 to 5.5 V SCK high/low level width t KL4, tKH4 VDD = 2.7 to 5.5 V SB0/SB1 setup time (referred to SCK↑) tSIK4 VDD = 2.7 to 5.5 V SB0/SB1 hold time (referred to SCK↑) tKSI4 Delay time from SCK↓ to SB0/SB1 output tKSO4 RL = 1 kΩ Note CL = 100 pF VDD = 2.7 to 5.5 V MIN. TYP. MAX. Unit 800 ns 3,200 ns 400 ns 1,600 ns 100 ns 150 ns tKCY4/2 ns 0 300 ns 0 1,000 ns From SCK↑ to SB0/SB1↓ tKSB tKCY4 ns From SB0/SB1↓ to SCK↓ tSBK tKCY4 ns SB0/SB1 low level width tSBL tKCY4 ns t SBH tKCY4 ns SB0/SB1 high level width Note RL is the resistance of the SB0/SB1 output line load, while CL is the capacitance. 60 µPD750104, 750106, 750108, 750104(A), 750106(A), 750108(A) AC timing measurement points (excluding XT1 input) VIH (MIN.) VIH (MIN.) VIL (MAX.) VIL (MAX.) VOH (MIN.) VOH (MIN.) VOL (MAX.) VOL (MAX.) Clock timing 1/fXT tXTL tXTH VDD - 0.1 V XT1 input 0.1 V TI0 timing 1/fTI tTIL tTIH TI0 61 µPD750104, 750106, 750108, 750104(A), 750106(A), 750108(A) Serial transfer timing Three-wire serial I/O mode: tKCY1 tKCY2 tKL1 tKL2 tKH1 tKH2 SCK tSIK1 tSIK2 tKSI1 tKSI2 Input data SI tKSO1 tKSO2 Output data SO Two-wire serial I/O mode: tKCY1 tKCY2 tKL1 tKL2 tKH1 tKH2 SCK tSIK1 tSIK2 SB0 and SB1 tKSO1 tKSO2 62 tKSI1 tKSI2 µPD750104, 750106, 750108, 750104(A), 750106(A), 750108(A) Serial transfer timing Bus release signal transfer: tKCY3 tKCY4 tKL3 tKL4 tKH3 tKH4 SCK tKSB tSBL tSBH tSIK3 tSIK4 tSBK tKSI3 tKSI4 SB0 and SB1 tKSO3 tKSO4 Command signal transfer: tKCY3 tKCY4 tKL3 tKL4 tKH3 tKH4 SCK tKSB tSIK3 tSIK4 tSBK tKSI3 tKSI4 SB0 and SB1 tKSO3 tKSO4 Interrupt input timing tINTL tINTH INT0, INT1, INT2, and INT4 KR0 - KR7 RESET input timing tRSL RESET 63 µPD750104, 750106, 750108, 750104(A), 750106(A), 750108(A) DATA HOLD CHARACTERISTICS BY LOW SUPPLY VOLTAGE IN DATA MEMORY STOP MODE (TA = -40 to +85 °C) Parameter Symbol Release signal setting time t SREL time Note 1 tWAIT Oscillation settling Conditions MIN. TYP. MAX. Unit µs 0 Release by RESET 56/fCC µs Release by interrupt request Note 2 µs Notes 1. CPU operation stop time for preventing unstable operation at the beginning of oscillation. 2. Select either 512/fCC or no wait with the mask option. Data hold timing (STOP mode release by RESET) Internal reset operation HALT mode Operation mode STOP mode Data hold mode VDD tSREL STOP instruction execution RESET tWAIT Data hold timing (standby release signal: STOP mode release by interrupt signal) HALT mode Operation mode STOP mode Data hold mode VDD tSREL STOP instruction execution Standby release signal (Interrupt request) tWAIT 64 µPD750104, 750106, 750108, 750104(A), 750106(A), 750108(A) 13. CHARACTERISTIC CURVE (REFERENCE VALUES) IDD vs. VDD (When the main system clock is operating at 1.0 MHz with an RC oscillation) (TA = 25 ˚C) 10 5.0 1.0 PCC = 0011 PCC = 0010 PCC = 0001 PCC = 0000 Main system clock HALT mode + 32 kHz oscillation Supply current IDD (mA) 0.5 0.1 0.05 Subsystem clock operating mode (SOS.1 = 0) Subsystem clock HALT mode (SOS.1 = 0) and main system clock STOP mode + 32 kHz oscillation (SOS.1 =0) Subsystem clock HALT mode (SOS.1 = 1) and main system clock STOP mode + 32 kHz oscillation (SOS.1 =1) 0.01 0.005 CL1 CL2 XT1 RC oscillation 22 kΩ 22 pF 0.001 0 1 2 3 4 5 XT2 Crystal 32.768 kHz 33 pF 6 220 kΩ 33 pF 7 8 Supply voltage VDD (V) 65 µPD750104, 750106, 750108, 750104(A), 750106(A), 750108(A) 14. EXAMPLES OF RC OSCILLATOR FREQUENCY CHARACTERISTICS (REFERENCE VALUES) fCC vs. VDD (RC oscillation , R = 22 kΩ, C = 22 pF) (TA = -40 ˚C) Main system clock frequency fCC (MHz) 2.0 CL1 CL2 22 kΩ 22 pF 1.0 Sample A Sample B Sample C 0.5 1 0 2 3 5 4 Supply voltage VDD (V) 6 Main system clock frequency fCC (MHz) CL1 CL2 22 kΩ 22 pF 1.0 Sample A Sample B Sample C 0.5 0 1 2 3 5 4 Supply voltage VDD (V) 6 7 8 (TA = 85 ˚C) 2.0 Main system clock frequency fCC (MHz) 8 (TA = 25 ˚C) 2.0 CL1 CL2 22 kΩ 22 pF 1.0 Sample A Sample B Sample C 0.5 66 7 0 1 2 3 5 4 Supply voltage VDD (V) 6 7 8 µPD750104, 750106, 750108, 750104(A), 750106(A), 750108(A) fCC vs. TA (RC oscillation, R = 22 kΩ, C = 22 pF) (Sample A) Main system clock frequency fCC (MHz) 2.0 CL1 CL2 22 kΩ 22 pF VDD = 5.0 V VDD = 3.0 V VDD = 2.2 V VDD = 1.8 V 1.0 0.5 -60 -40 -20 0 +20 +40 Operating ambient temperature TA (˚C) +60 Main system clock frequency fCC (MHz) +100 (Sample B) 2.0 CL1 CL2 22 kΩ 22 pF VDD = 5.0 V VDD = 3.0 V VDD = 2.2 V VDD = 1.8 V 1.0 0.5 -60 -40 -20 +40 0 +20 Operating ambient temperature TA (˚C) +60 +80 +100 (Sample C) 2.0 Main system clock frequency fCC (MHz) +80 CL1 CL2 22 kΩ 22 pF VDD = 5.0 V VDD = 3.0 V VDD = 2.2 V 1.0 VDD = 1.8 V 0.5 -60 -40 -20 0 +20 +40 Operating ambient temperature TA (˚C) +60 +80 +100 67 µPD750104, 750106, 750108, 750104(A), 750106(A), 750108(A) 15. PACKAGE DRAWINGS 44 PIN PLASTIC QFP ( 10) A B 23 22 33 34 detail of lead end C D S R Q 12 11 44 1 F J G H I M K M P N L NOTE Each lead centerline is located within 0.16 mm (0.007 inch) of its true position (T.P.) at maximum material condition. 68 ITEM MILLIMETERS INCHES A 13.2±0.2 0.520 +0.008 –0.009 B 10.0±0.2 0.394 +0.008 –0.009 C 10.0±0.2 0.394 +0.008 –0.009 D 13.2±0.2 0.520 +0.008 –0.009 F 1.0 0.039 G 1.0 0.039 H 0.37 +0.08 –0.07 0.015 +0.003 –0.004 I 0.16 0.007 J 0.8 (T.P.) 0.031 (T.P.) K 1.6±0.2 0.063±0.008 L 0.8±0.2 0.031 +0.009 –0.008 M 0.17 +0.06 –0.05 0.007 +0.002 –0.003 N 0.10 0.004 P 2.7 0.106 Q 0.125±0.075 R 3° +7° –3° 0.005±0.003 3° +7° –3° S 3.0 MAX. 0.119 MAX. S44GB-80-3BS µPD750104, 750106, 750108, 750104(A), 750106(A), 750108(A) 42PIN PLASTIC SHRINK DIP (600 mil) 42 22 1 21 A K H G J I L F B D N R M C M NOTES 1) Each lead centerline is located within 0.17 mm (0.007 inch) of its true position (T.P.) at maximum material condition. 2) Item "K" to center of leads when formed parallel. ITEM MILLIMETERS INCHES A 39.13 MAX. 1.541 MAX. B 1.78 MAX. 0.070 MAX. C 1.778 (T.P.) 0.070 (T.P.) D 0.50±0.10 0.020 +0.004 –0.005 F 0.9 MIN. 0.035 MIN. G 3.2±0.3 0.126±0.012 H 0.51 MIN. 0.020 MIN. I 4.31 MAX. 0.170 MAX. J 5.08 MAX. 0.200 MAX. K L 15.24 (T.P.) 13.2 0.600 (T.P.) 0.520 M 0.25 +0.10 –0.05 0.010 +0.004 –0.003 N 0.17 0.007 R 0~15° 0~15° P42C-70-600A-1 69 µPD750104, 750106, 750108, 750104(A), 750106(A), 750108(A) 16. RECOMMENDED SOLDERING CONDITIONS The µ PD750104, µPD750106, and µ PD750108 should be soldered and mounted under the conditions recommended in the table below. For detail of recommended soldering conditions, refer to the information document SMD Surface Mount Technology Manual (C10535E). For soldering methods and conditions other than those recommended below, contact our sales personnel. Table 16-1. Surface Mounting Type Soldering Conditions µ PD750104GB-×××-3BS-MTX : 44-pin plastic QFP (10 × 10 mm, 0.8-mm pitch) µ PD750106GB-×××-3BS-MTX : 44-pin plastic QFP (10 × 10 mm, 0.8-mm pitch) µ PD750108GB-×××-3BS-MTX : 44-pin plastic QFP (10 × 10 mm, 0.8-mm pitch) µ PD750104GB(A)-×××-3BS-MTX : 44-pin plastic QFP (10 × 10 mm, 0.8-mm pitch) µ PD750106GB(A)-×××-3BS-MTX : 44-pin plastic QFP (10 × 10 mm, 0.8-mm pitch) µ PD750108GB(A)-×××-3BS-MTX : 44-pin plastic QFP (10 × 10 mm, 0.8-mm pitch) Soldering method Symbol Soldering conditions Infrared reflow Package peak temperature: 235 °C Duration: 30 seconds max. (at 210 °C or above) Maximum allowable number of reflow processes: 3 IR35-00-3 VPS Package peak temperature: 215 °C Duration: 40 seconds max. (at 200 °C or above) Maximum allowable number of reflow processes: 3 VP15-00-3 Wave soldering Solder bath temperature: 260 °C max. Duration: 10 seconds max. Number of times: 1 Preliminary heat temperature: 120 °C max. (package surface temperature) WS60-00-1 Partial heating method Terminal temperature: 300 °C max. Duration: 3 seconds max. (per device side) - Caution Use of more than one soldering method should be avoided (except for partial heating method). Table 16-2. Insertion Type Soldering Conditions µ PD750104CU-××× : 42-pin plastic shrink DIP (600 mil, 1.778-mm pitch) µ PD750106CU-××× : 42-pin plastic shrink DIP (600 mil, 1.778-mm pitch) µ PD750108CU-××× : 42-pin plastic shrink DIP (600 mil, 1.778-mm pitch) µ PD750104CU(A)-××× : 42-pin plastic shrink DIP (600 mil, 1.778-mm pitch) µ PD750106CU(A)-××× : 42-pin plastic shrink DIP (600 mil, 1.778-mm pitch) µ PD750108CU(A)-××× : 42-pin plastic shrink DIP (600 mil, 1.778-mm pitch) Soldering method Soldering conditions Wave soldering (terminal only) Solder bath temperature: 260 °C max., Duration: 10 seconds max. Partial heating method Terminal temperature: 300 °C max., Duration: 3 seconds max. (for each pin) Caution Apply wave soldering to terminals only. See to it that the jet solder does not contact with the chip directly. 70 µPD750104, 750106, 750108, 750104(A), 750106(A), 750108(A) APPENDIX A FUNCTIONS OF THE µPD750008, µPD750108, AND µPD75P0116 (1/2) µ PD750008 Item µ PD750108 µ PD75P0116 Masked ROM 0000H - 1FFFH (8,192 × 8 bits) Data memory 000H - 1FFH (512 × 4 bits) CPU 75XL CPU General-purpose register (4 bits × 8 or 8 bits × 4) × 4 banks Main system clock oscillator Crystal/ceramic oscillator RC oscillator (with external resistor and capacitor) Time required for start after reset 2 17/f X, 2 15/f X (selected using a mask option) Fixed to 56/f CC Wait time applied when STOP mode is released by an interrupt 2 20/f X, 2 17/f X, 2 15/f X, 2 13/f X (selected according to BTM setting) 2 9/fCC or no wait (selected using a mask option) Subsystem clock oscillator Crystal oscillator I/O port Instruction execution time Program memory Timer One-time PROM 0000H - 3FFFH (16,384 × 8 bits) Fixed to 29 /f CC 15.3 • 4, 8, 16, or 64 µ s (when operating at fCC = 1.0 MHz) at • 2, 4, 8, or 32 µs (when operating at f CC = 2.0 MHz) 10.7 at When selecting the main system clock • 0.95, 1.91, 3.81, or µ s (when operating f X =4.19 MHz) • 0.67, 1.33, 2.67, or µ s (when operating f X = 6.0 MHz) When selecting the subsystem clock 122 µ s (when operating at 32.768 kHz) CMOS input 8 (Built-in pull-up resistors that can be connected by software: 7) CMOS I/O 18 (Built-in pull-up resistors that can be connected by software) N-ch open-drain I/O 8 (Pull-up resistors that can be incorporated by mask option) Withstand voltage of 13 V Total 34 4 channels • 8-bit timer counter: 1 • 8-bit timer/event counter: 1 • Basic interval timer/ watchdog timer: 1 • Clock timer: 1 8 (No mask option) Withstand voltage of 13 V 4 channels • 8-bit timer counter (clock timer output function provided): 1 • 8-bit timer/event counter: 1 • Basic interval timer/watchdog timer: 1 • Clock timer: 1 71 µPD750104, 750106, 750108, 750104(A), 750106(A), 750108(A) (2/2) Item µPD750008 µ PD750108 µ PD75P0116 Serial interface 3 modes supported • Three-wire serial I/O mode: First transferred bit switchable between LSB and MSB • Two-wire serial I/O mode • SBI mode Clock output (PCL) • Φ, 524, 262, or 65.5 kHz • Φ , 125, 62.5, or 15.6 kHz (when the main system (when the main system clock operates at 1.0 MHz) clock operates at 4.19 MHz) • Φ , 750, 375, or 93.8 kHz • Φ , 250, 125, or 31.3 kHz (when the main system (when the main system clock operates at 2.0 MHz) clock operates at 6.0 MHz) Buzzer output (BUZ) • 2, 4, or 32 kHz (when the • 2, 4, or 32 kHz (when the subsystem clock main system clock operates at 32.768 kHz) operates at 4.19 MHz • 0.488, 0.977, or 7.813 kHz (when the main or the subsystem clock system clock operates at 1.0 MHz) operates at 32.768 kHz) • 0.977, 1.953, or 15.625 kHz (when the main • 2.93, 5.86, or 46.9 kHz system clock operates at 2.0 MHz) (when the main system clock operates at 6.0 MHz) Vectored interrupt External: 3, internal: 4 Test input External: 1, internal: 1 Supply voltage V DD = 2.2 to 5.5 V Operating ambient temperature T A = -40 to +85 °C Package • 42-pin plastic shrink DIP (600 mil, 1.778-mm pitch) • 44-pin plastic QFP (10 × 10 mm, 0.8-mm pitch) 72 VDD = 1.8 to 5.5 V µPD750104, 750106, 750108, 750104(A), 750106(A), 750108(A) APPENDIX B DEVELOPMENT TOOLS The following development tools are provided for the development of a system which employs the µPD750108. In the 75XL series, use the common relocatable assembler together with a device file of each model. Language processors RA75X relocatable assembler Part number Host machine OS 3.5-inch 2HD µS5A13RA75X 5.25-inch 2HD µS5A10RA75X IBM PC/AT TM and See "OS for IBM PC." 3.5-inch 2HC compatibles 5.25-inch 2HC µS7B13RA75X PC-9800 series Device file Distribution media MS-DOSTM Ver. 3.30 to Ver. 6.2 Note Host machine Part number OS PC-9800 series IBM PC/AT and compatibles µS7B10RA75X MS-DOS Ver. 3.30 to Ver. 6.2Note Distribution media 3.5-inch 2HD µ S5A13DF750008 5.25-inch 2HD µ S5A10DF750008 See "OS for IBM PC." 3.5-inch 2HC 5.25-inch 2HC µ S7B13DF750008 µ S7B10DF750008 Note These software products cannot use the task swap function, which is available in MS-DOS Ver. 5.00 or later. Remark The operations of the assembler and device file are guaranteed only on the above host machines and OSs. 73 µPD750104, 750106, 750108, 750104(A), 750106(A), 750108(A) PROM programming tools Hardware Software PG-1500 The PG-1500 PROM programmer is used together with an accessory board and optional program adapter. It allows the user to program a single chip microcontroller containing PROM from a standalone terminal or a host machine. The PG-1500 can be used to program typical 256K-bit to 4M-bit PROMs. PA-75P008CU The PA-75P008CU is a PROM programmer adapter provided for the µPD75P0116CU/GB. It is used in conjunction with the PG-1500. PG-1500 controller This program enables the host machine to control the PG-1500 through the serial and parallel interfaces. Part number Host machine OS PC-9800 series IBM PC/AT and compatibles Distribution media MS-DOS Ver. 3.30 to Ver. 6.2Note 3.5-inch 2HD µS5A13PG1500 5.25-inch 2HD µS5A10PG1500 See "OS for IBM PC." 3.5-inch 2HD µS7B13PG1500 5.25-inch 2HC µS7B10PG1500 Note These software products cannot use the task swap function, which is available in MS-DOS Ver. 5.00 or later. Remark Operation of the PG-1500 controller is guaranteed only on the above host machines and OSs. 74 µPD750104, 750106, 750108, 750104(A), 750106(A), 750108(A) Debugging tools The in-circuit emulators (IE-75000-R and IE-75001-R) are provided to debug programs used for the µ PD750108. The system configuration is shown below. IE-75000-RNote 1 The IE-75000-R is an in-circuit emulator used to debug hardware and software when developing an application system using the 75X series and 75XL series. Use this emulator together with optional emulation board IE-75300-R-EM and emulation probe EP-75008CU-R or EP-75008GB-R to develop application systems of the µ PD750108 subseries. For efficient debugging, connect the emulator to the host machine and a PROM programmer. The IE-75000-R contains emulation board IE-75000-R-EM. The board is connected to the IE-75000-R. Hardware IE-75001-R The IE-75001-R is an in-circuit emulator used to debug hardware and software when developing an application system using the 75X series and 75XL series. Use this emulator together with optional emulation board IE-75300-R-EM and emulation probe EP-75008CU-R or EP-75008GB-R to develop application systems of the µ PD750108 subseries. For efficient debugging, connect the emulator to the host machine and a PROM programmer. IE-75300-R-EM The IE-75300-R-EM is an emulation board used to evaluate an application system using the µPD750108 subseries. Use this board together with the IE-75000-R or IE-75001-R. EP-75008CU-R The EP-75008CU-R is an emulation probe for the µPD750108CU. Connect this emulation probe to the IE-75000-R or IE-75001-R, and the IE-75300-REM. EP-75008GB-R EV-9200G-44 IE control program The EP-75008GB-R is an emulation probe for the µPD750108GB. Connect this emulation probe to the IE-75000-R or IE-75001-R, and the IE-75300-REM. A 44-pin conversion socket, the EV-9200G-44, supplied with this probe facilitates the connection of the probe to the target system. This program enables the host machine to control the IE-75000-R or IE-75001-R through the RS-232-C and Centronics interface. Host machine Software OS PC-9800 series IBM PC/AT and compatibles MS-DOS Ver. 3.30 to Ver. 6.2Note 2 Distribution media Part number 3.5-inch 2HD µ S5A13IE75X 5.25-inch 2HD µ S5A10IE75X See "OS for IBM PC." 3.5-inch 2HC 5.25-inch 2HC µ S7B13IE75X µ S7B10IE75X Notes 1. Maintenance service only 2. These software products cannot use the task swap function, which is available in MS DOS Ver. 5.00 or later. Remarks 1. Operation of the IE control program is guaranteed only on the above host machines and OSs. 2. The µ PD750104, µ PD750106, µ PD750108, and µPD75P0116 are collectively called the µ PD750108 subseries. 75 µPD750104, 750106, 750108, 750104(A), 750106(A), 750108(A) OS for IBM PC The following IBM PC OSs are supported. OS PC DOSTM Version Ver. 5.02 to Ver. 6.3 J6.1/V Note to J6.3/VNote MS-DOS Ver. 5.0 to Ver. 6.22 5.0/V Note to 6.2/V Note IBM DOSTM J5.02/V Note Note Only English version is supported. Caution These software products cannot use the task swap function, which is available in MS-DOS Ver. 5.0 or later. 76 µPD750104, 750106, 750108, 750104(A), 750106(A), 750108(A) APPENDIX C RELATED DOCUMENTS Some documents are preliminary editions, but they are not so specified in the tables below. Documents related to devices Document name Document number Japanese English µPD750104, 750106, 750108, 750104(A), 750106(A), 750108(A) Data Sheet U12301J U12301E (This manual) µPD75P0116 Data Sheet U12603J U12603E µPD750108 User’s Manual U11330J U11330E µPD750008, 750108 Instruction List U11456J 75XL Series Selection Guide U10453J U10453E Documents related to development tools Document number Document name Japanese Hardware Software English IE-75000-R/IE-75001-R User's Manual EEU-846 EEU-1416 IE-75300-R-EM User's Manual U11354J U11354E EP-75008CU-R User's Manual EEU-699 EEU-1317 EP-75008GB-R User's Manual EEU-698 EEU-1305 PG-1500 User's Manual U11940J EEU-1335 Operation EEU-731 EEU-1346 Language EEU-730 EEU-1363 PC-9800 series (MS-DOS) base EEU-704 EEU-1291 IBM PC series (PC DOS) base EEU-5008 U10540E RA75X Assembler Package User's Manual PG-1500 Controller User's Manual Other related documents Document number Document name Japanese English IC Package Manual C10943X Semiconductor Device Mounting Technology Manual C10535J C10535E Quality Grade on NEC Semiconductor Devices C11531J C11531E Reliability and Quality Control of NEC Semiconductor Devices C10983J C10983E Electrostatic Discharge (ESD) Test MEM-539 Semiconductor Device Quality Guarantee Guide C11893J Microcontroller-Related Products Guide - by third parties U11416J MEI-1202 - Caution The above related documents are subject to change without notice. Be sure to use the latest edition when you design your system. 77 µPD750104, 750106, 750108, 750104(A), 750106(A), 750108(A) NOTES FOR CMOS DEVICES 1 PRECAUTION AGAINST ESD FOR SEMICONDUCTORS Note: Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and ultimately degrade the device operation. Steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it once, when it has occurred. Environmental control must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using insulators that easily build static electricity. Semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. All test and measurement tools including work bench and floor should be grounded. The operator should be grounded using wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need to be taken for PW boards with semiconductor devices on it. 2 HANDLING OF UNUSED INPUT PINS FOR CMOS Note: No connection for CMOS device inputs can be cause of malfunction. If no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. CMOS device behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused pin should be connected to VDD or GND with a resistor, if it is considered to have a possibility of being an output pin. All handling related to the unused pins must be judged device by device and related specifications governing the devices. 3 STATUS BEFORE INITIALIZATION OF MOS DEVICES Note: Power-on does not necessarily define initial status of MOS device. Production process of MOS does not define the initial operation status of the device. Immediately after the power source is turned ON, the devices with reset function have not yet been initialized. Hence, power-on does not guarantee out-pin levels, I/O settings or contents of registers. Device is not initialized until the reset signal is received. Reset operation must be executed immediately after power-on for devices having reset function. 78 µPD750104, 750106, 750108, 750104(A), 750106(A), 750108(A) Regional Information Some information contained in this document may vary from country to country. Before using any NEC product in your application, please contact the NEC office in your country to obtain a list of authorized representatives and distributors. They will verify: • Device availability • Ordering information • Product release schedule • Availability of related technical literature • Development environment specifications (for example, specifications for third-party tools and components, host computers, power plugs, AC supply voltages, and so forth) • Network requirements In addition, trademarks, registered trademarks, export restrictions, and other legal issues may also vary from country to country. NEC Electronics Inc. (U.S.) NEC Electronics (Germany) GmbH NEC Electronics Hong Kong Ltd. Santa Clara, California Tel: 800-366-9782 Fax: 800-729-9288 Benelux Office Eindhoven, The Netherlands Tel: 040-2445845 Fax: 040-2444580 Hong Kong Tel: 2886-9318 Fax: 2886-9022/9044 NEC Electronics (Germany) GmbH Duesseldorf, Germany Tel: 0211-65 03 02 Fax: 0211-65 03 490 NEC Electronics Hong Kong Ltd. Velizy-Villacoublay, France Tel: 01-30-67 58 00 Fax: 01-30-67 58 99 Seoul Branch Seoul, Korea Tel: 02-528-0303 Fax: 02-528-4411 NEC Electronics (France) S.A. NEC Electronics Singapore Pte. Ltd. Spain Office Madrid, Spain Tel: 01-504-2787 Fax: 01-504-2860 United Square, Singapore 1130 Tel: 253-8311 Fax: 250-3583 NEC Electronics (France) S.A. NEC Electronics (UK) Ltd. Milton Keynes, UK Tel: 01908-691-133 Fax: 01908-670-290 NEC Electronics Italiana s.r.1. Milano, Italy Tel: 02-66 75 41 Fax: 02-66 75 42 99 NEC Electronics Taiwan Ltd. NEC Electronics (Germany) GmbH Scandinavia Office Taeby, Sweden Tel: 08-63 80 820 Fax: 08-63 80 388 Taipei, Taiwan Tel: 02-719-2377 Fax: 02-719-5951 NEC do Brasil S.A. Sao Paulo-SP, Brasil Tel: 011-889-1680 Fax: 011-889-1689 J96. 8 79 µPD750104, 750106, 750108, 750104(A), 750106(A), 750108(A) MS-DOS is a registered trademark or trademark of Microsoft Corporation in the United States and/or other countries. IBM DOS, PC/AT, and PC DOS are trademarks of IBM Corporation. The export of this product from Japan is regulated by the Japanese government. To export this product may be prohibited without governmental license, the need for which must be judged by the customer. The export or re-export of this product from a country other than Japan may also be prohibited without a license from that country. Please call an NEC sales representative. No part of this document may be copied or reproduced in any form or by any means without the prior written consent of NEC Corporation. NEC Corporation assumes no responsibility for any errors which may appear in this document. NEC Corporation does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from use of a device described herein or any other liability arising from use of such device. No license, either express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of NEC Corporation or others. While NEC Corporation has been making continuous effort to enhance the reliability of its semiconductor devices, the possibility of defects cannot be eliminated entirely. To minimize risks of damage or injury to persons or property arising from a defect in an NEC semiconductor device, customers must incorporate sufficient safety measures in its design, such as redundancy, fire-containment, and anti-failure features. NEC devices are classified into the following three quality grades: "Standard", "Special", and "Specific". The Specific quality grade applies only to devices developed based on a customer designated "quality assurance program" for a specific application. The recommended applications of a device depend on its quality grade, as indicated below. Customers must check the quality grade of each device before using it in a particular application. Standard: Computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots Special: Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support) Specific: Aircrafts, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems or medical equipment for life support, etc. The quality grade of NEC devices is "Standard" unless otherwise specified in NEC's Data Sheets or Data Books. If customers intend to use NEC devices for applications other than those specified for Standard quality grade, they should contact an NEC sales representative in advance. Anti-radioactive design is not implemented in this product. M4 96. 5 80