M24L16161DA

ESMT
M24L16161DA
PSRAM
16-Mbit (1M x 16)
Async / Page Pseudo Static RAM
Features
• Voltage range: 2.7V – 3.3 V
• Access Time: 70 ns
• Ultra-low active power
— Maximum active current: 20 mA (for random Read/ Write)
— Maximum active current: 20 mA (for page Read)
• Ultra low standby power
• 16-word Page Mode
• CMOS for optimum speed/power
• Operating Temperature (TC): –25°C to +85°C (Extended)
Ordering Information
Product ID
M24L16161DA-70BEG
Speed
(ns)
Package
Operating
Temperature
Comments
70
48-ball BGA
Extended
Pb-free
Functional Description
The device is a high-performance CMOS Pseudo Static RAM
organized as 1M words by 16 bits that supports an
asynchronous memory interface. This device features
advanced circuit design to provide ultra-low active current.
This is ideal for portable applications such as cellular
telephones.
Elite Semiconductor Memory Technology Inc.
Publication Date : Dec. 2010
Revision: 1.0
1/15
ESMT
M24L16161DA
Product Portfolio
Power Dissipation
VCC Range(V)
Product
Speed
(ns)
Min.
Max.
2.7
3.3
M24L16161DA
70
Operating Current
Standby, ISB (µA)
ICC1 (mA)
ICC1P (mA)
Max.
Max.
Max.
20
20
140
Logic Block Diagram
A[19;0]
Address Decode
Logic
1Mx16
Memory
Array
Input/
Output
MUX
And
Buffers
DQ[7:0]
DQ[15:8]
CE1
CE2
WE
OE
Control
Logic
BHE
BLE
Elite Semiconductor Memory Technology Inc.
Publication Date : Dec. 2010
Revision: 1.0
2/15
ESMT
M24L16161DA
BALL CONFIGURATION (TOP VIEW)
(BGA48, 6mmX8mmX1mm Body, 0.8mm Ball Pitch)
1
2
3
4
5
6
A
BLE
OE
A0
A1
A2
CE2
B
DQ8
BHE
A3
A4
CE1
DQ0
C
DQ9
DQ10
A5
A6
DQ1
DQ2
D
VSSQ
DQ11
A17
A7
DQ3
VCC
E
VCCQ
DQ12
NC
A16
DQ4
VSS
F
DQ14
DQ13
A14
A15
DQ5
DQ6
G
DQ15
A19
A12
A13
WE
DQ7
H
A18
A8
A9
A10
A11
NC
Ball Function Description
Ball Name
Type
Description
A[19:0]
Input
Address inputs: Inputs for the address accessed during READ or WRITE operations.
CE 1
Input
CE2
Input
Chip enable 1: Activates the device when LOW. When CE 1 is HIGH, the device is disabled
and goes into standby power mode.
Chip enable 2: Activates the device when HIGH. When CE2 is LOW, the device is disabled
and goes into standby power mode.
BLE
Input
Lower byte enable: DQ[7:0].
OE
Input
Output enable: Enables the output buffers when LOW. When OE is HIGH, the output
buffers are disabled.
BHE
Input
Upper byte enable: DQ[15:8].
WE
DQ[15:0]
NC
VCC
VCCQ
VSS
VSSQ
Input
Write enable: Enables WRITE operations when LOW.
Input / Output
Supply
Supply
Supply
Supply
Data inputs/outputs.
Not internally connected.
Device power supply: Power supply for device core operation.
I/O power supply: Power supply for input/output buffers.
VSS must be connected to ground.
VSSQ must be connected to ground.
Elite Semiconductor Memory Technology Inc.
Publication Date : Dec. 2010
Revision: 1.0
3/15
ESMT
M24L16161DA
Absolute Maximum Ratings
Parameter
Voltage to any ball except VCC, VCCQ relative to VSS
Voltage on VCC supply relative to VSS
Voltage on VCCQ supply relative to VSS
Storage temperature
Rating
Unit
-0.3 to VCCQ + 0.3
-0.2 to +2.45
-0.2 to +2.45
-55 to +150
V
V
V
℃
-25 to +85
℃
Operating temperature (case) - Extended
Soldering temperature and time
℃
+260
10 seconds (solder ball only)
Note: Stresses greater than those listed in the above table may cause permanent damage to the device. This is a stress rating only,
and functional operation of the device at these or any other conditions above those indicated in the operational sections of
this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
DC Electrical Characteristics
Symbol
Description
Test Conditions
VCC
VCCQ
VOH
VOL
VIH
VIL
ILI
Supply Voltage
I/O Supply Voltage
Output HIGH Voltage
Output LOW Voltage
Input HIGH Voltage
Input LOW Voltage
Input Leakage Current
VIN = 0 to VCCQ
ILO
Output Leakage Current
ICC1
-70
Min.
Max.
2.7
2.7
0.8 x VCCQ
3.3
3.3
Unit
Note
0.2 x VCCQ
VCCQ + 0.2
0.4
1
V
V
V
V
V
V
µA
OE = VIH or Chip disabled
1
µA
Asynchronous random
Read/Write
VIN = VCCQ or 0V, Chip enabled,
IOUT = 0 mA,
20
mA
4
ICC1P
Asynchronous Page
Read
VIN = VCCQ or 0V, Chip enabled,
IOUT = 0 mA,
20
mA
4
ISB
Standby current
VIN = VCCQ or 0V, CE 1= VCCQ or
CE2 = VSS
140
µA
5
IOH = −0.2 mA
IOL = 0.2 mA
VCCQ – 0.4
-0.2
1,2
3
Notes:
1. Input signals may overshoot to V CCQ + 1.0V for periods less than 2ns during transitions.
2. VIH (MIN) value is not aligned with PSRAM Workgroup 1.0 specification of V CCQ - 0.4V.
3. Input signals may undershoot to Vss - 1.0V for periods less than 2ns during transitions.
4. This parameter is specified with the outputs disabled to avoid external loading effects. The user must add the current required
to drive output capacitance expected in the actual system.
5. ISB (MAX) values measured with FULL ARRAY and at +85°C. In order to achieve low standby current, all inputs must be driven
to V CCQ or Vss. ISB may be slightly higher for up to 500ms after power-up or when entering standby mode.
Elite Semiconductor Memory Technology Inc.
Publication Date : Dec. 2010
Revision: 1.0
4/15
ESMT
M24L16161DA
Capacitance
Symbol
CIN
CIO
Description
Input Capacitance
Input/Output
Capacitance (DQ)
Test Conditions
TC = +25°C, f = 1 MHz,
VIN = 0 V
Min.
Max.
Unit
2.0
6
pF
3.5
6
pF
Note: These parameters are verified in device characterization and are not 100% tested.
AC Input/Output Reference Waveform
Notes:
1. AC test inputs are driven at VCCQ for a logic 1 and VSSQ for a logic 0. Input rise and fall times (10% to 90%) <1.6ns.
2. Input timing begins at VCCQ /2.
3. Output timing ends at VCCQ /2.
AC Output Load Circuit
Elite Semiconductor Memory Technology Inc.
Publication Date : Dec. 2010
Revision: 1.0
5/15
ESMT
M24L16161DA
Timing Parameters
Symbol
Description
–70
Min.
Max.
70
8000
70
Unit
Read Cycle
tRC
tAA
tOH
tCO
Read Cycle Time
Address to Data Valid
Data Hold from Address Change
CE 1 LOW and CE2 HIGH to Data Valid
70
ns
ns
ns
ns
tOE
OE LOW to Data Valid
20
ns
tOLZ
OE LOW to Low-Z
tOHZ
OE HIGH to High-Z
tLZ
CE 1 LOW and CE2 HIGH to Low-Z
tHZ
CE 1 HIGH and CE2 LOW to High-Z
tBA
BLE / BHE LOW to Data Valid
tBLZ
BLE / BHE LOW to Low-Z
tBHZ
BLE / BHE HIGH to High-Z
tASKEW
Address Skew
Page Read Cycle
tPC
Page Mode Read Cycle Time
tAPA
Page Mode Address Access
tCEM
Maximum CE 1 and CE2 pulse width
tASKEWP
Page Mode Access Address Skew
Write Cycle
tWC
Write Cycle Time
tCW
CE LOW and CE HIGH to Write End
tDW
tDH
tWHZ
3
ns
2
ns
1
ns
2
8
ns
1
70
ns
ns
2
8
10
ns
ns
1
5
8000
25
8
3
ns
ns
µs
ns
8000
ns
8
10
10
25
70
70
ns
Address Set-Up to Write End
Address Hold from Write End
Address Set-Up to Write Start
Write Pulse Width
70
0
0
45
ns
ns
ns
ns
BLE / BHE LOW to Write End
Data Set-Up to Write End
Data Hold from Write End
70
ns
20
0
ns
ns
1
tAW
tWR
tAS
tWP
tBW
5
2
8
WE LOW to High-Z
2
5
ns
tCPH
CE 1 HIGH and CE2 LOW timing during Write
5
ns
tPU
Chip Enable Low After Stable VCC
4
1
WE HIGH to Low-Z
10
3
ns
tOW
tWPH
Write pulse width HIGH
tASKEW
Address Skew
Power-up Initialization
Note
3
ns
ns
150
µs
5
Notes:
1. Low-Z to High-Z timings are tested with the circuit shown in “AC Output Load Circuit” figure. The High-Z timings measure a
100mV transition from either VOH or VOL toward VCCQ /2.
2. High-Z to Low-Z timings are tested with the circuit shown in “AC Output Load Circuit” figure. The Low-Z timings measure a
100mV transition away from the High-Z (VCCQ /2) level toward either VOH or VOL.
3. Page mode enabled only.
4.
WE LOW time must be limited to tCEM (max).
5.
Applies when control signals ( CE 1, CE2, BLE / BHE ) are active.
Elite Semiconductor Memory Technology Inc.
Publication Date : Dec. 2010
Revision: 1.0
6/15
ESMT
M24L16161DA
Power-up Characteristics
The initialization sequence is shown in figure below. Chip
Select must be CE 1 HIGH or CE2 LOW for at least tPU time
after VCC has reached a stable value. No access must be
attempted during this period of tPU.
Power up Initialization Period
Stable Power
VCC
CE1
First Address
tPU
Page Mode
This device can be operated in a page read mode. This is
accomplished by initiating a normal read of the device.
fixed. For a 16-word page access operation, all address bits
except for A3, A2, A1 and A0 should be fixed.
In order to operate the device in page mode, the upper order
address bits should be fixed for 4-word page access operation,
all address bits except for A1 and A0 should be fixed until the
page access is completed. For an 8-word page access
operation, all address bits except for A2, A1 and A0 should be
The supported page lengths are 4, 8 and 16 words. Random
page read is supported for all three 4, 8 and 16-word page
read options. Therefore, any address can be used as the
starting address. Please refer to “Page Read Modes Table” for
an overview of the page read modes.
Page Read Modes Table
Page Mode Feature
4-Word Mode
8-Word Mode
16-Word Mode
Page Length
4 words
8 words
16 words
Page Read Corresponding Addresses
A1, A0
A2, A1, A0
A3, A2, A1, A0
Page Read Start Address
Don't Care
Don't Care
Don't Care
Page Direction
Don't Care
Don't Care
Don't Care
Elite Semiconductor Memory Technology Inc.
Publication Date : Dec. 2010
Revision: 1.0
7/15
ESMT
M24L16161DA
Asynchronous Read Cycle
tRC
Valid Address
ADDRESS
tASKEW
tASKEW
tHZ
tAA
tASKEW
tCO
CE1
CE2
tBA
tBHZ
BLE / BHE
tOE
tOHZ
OE
tOLZ
WE
tBLZ
tLZ
High-Z
DATA
Valid Output
Don’t care
Undefined
Page Read Cycle
tRC
A[19:4]
Valid Address
tASKEW
A[3:0]
tASKEW
tASKEWP
tASKEW
Valid
Valid
Address Address
Valid
Address
Valid Address
tAA
tPC
tASKEW
tCO
tCEM
tHZ
CE1
CE2
tBA
tBHZ
BLE / BHE
tOE
tOHZ
OE
tOLZ
tBLZ
WE
tAPA
tLZ
DATA
High-Z
tOH
Valid
Output
Valid
Output
Valid
Output
Don’t care
Elite Semiconductor Memory Technology Inc.
Valid
Output
Undefined
Publication Date : Dec. 2010
Revision: 1.0
8/15
ESMT
M24L16161DA
Asynchronous Write Cycle — CE 1 or CE2 Controlled
tWC
ADDRESS
Valid Address
tAW
tAS
tWR
tCW
tCPH
CE1
CE2
tBW
BLE / BHE
OE
tWP
tWPH
WE
tDW
DATA IN
High-Z
tDH
Valid Input
tWHZ
DATA OUT
Don’t care
Asynchronous Write Cycle — WE Controlled
tWC
ADDRESS
Valid Address
tAW
tWR
tCW
CE1
CE2
tBW
BLE / BHE
OE
tAS
tWPH
tWP
WE
tDW
DATA IN
High-Z
tDH
Valid Input
tWHZ
tOW
DATA OUT
Don’t care
Elite Semiconductor Memory Technology Inc.
Publication Date : Dec. 2010
Revision: 1.0
9/15
ESMT
M24L16161DA
Asynchronous Write Cycle — BHE / BLE Controlled
tWC
ADDRESS
Valid Address
tAW
tAS
tWR
tCW
CE1
CE2
tBW
BLE / BHE
OE
tWP
tWPH
WE
tDW
High-Z
DATA IN
tDH
Valid Input
tWHZ
DATA OUT
Don’t care
Asynchronous Write Followed by Asynchronous Read Cycle
ADDRESS
Valid Address
Valid Address
tAW
tBW
Valid Address
tWR
tAA
tBHZ
tBLZ
BLE / BHE
tCPH
tCW
tHZ
CE1
CE2
tLZ
OE
tAS
tOHZ
tOE
tWC
tWP tWPH
WE
DATA
IN/OUT
High-Z
Data
tDH
Data
High-Z
tDW
tOLZ
Don’t care
Valid Output
Undefined
Note: tCPH is only required after Write cycle - CE 1 or CE2 controlled
Elite Semiconductor Memory Technology Inc.
Publication Date : Dec. 2010
Revision: 1.0
10/15
ESMT
M24L16161DA
Avoid Timing
ESMT Pseudo SRAM has a timing which is not supported at read operation, If your system has multiple invalid address signal
shorter than tRC during over 8μs at read operation shown as in Abnormal Timing, it requires a normal read timing at least during 8μs
shown as in Avoidable timing 1 or toggle CE 1 to high (≧tRC) one time at least shown as in Avoidable Timing 2.
Abnormal Timing
≧8μ s
CE1
WE
＜ tRC
Address
Avoidable Timing 1
≧8μ s
CE1
WE
≧ tRC
Address
Avoidable Timing 2
≧8μ s
CE1
≧ tRC
WE
＜ tRC
Address
Elite Semiconductor Memory Technology Inc.
Publication Date : Dec. 2010
Revision: 1.0
11/15
ESMT
M24L16161DA
Truth Table
CE 1
CE2
WE
OE
H
X
X
L
L
L
L
L
X
L
X
H
H
H
H
H
X
X
X
H
L
H
H
H
X
X
X
L
X
H
H
H
BHE /
BLE
X
X
H
L
L
L/L
H/L
L/H
DQ[15:0]
High-Z
High-Z
High-Z
Data Out
Data In
High-Z
High-Z
High-Z
Mode
Standby
Standby
Input/Output Disabled
Read
Write
Output Disabled
Output Disabled
Output Disabled
Power
Standby (ISB)
Standby (ISB)
Active (ICC)
Active (ICC)
Active (ICC)
Active (ICC)
Active (ICC)
Active (ICC)
Note
2, 5
4, 5
1, 4
1, 3, 4
4, 5
H = Logic HIGH, L = Logic LOW, X = Don’t Care
Note:
1.
When BLE and BHE are in select mode (LOW), DQ[15:0] are affected. When only BLE is in select mode, DQ[7:0]
2.
are affected. When only BHE is in the select mode, DQ[15:8] are affected.
When the device is in standby mode, address inputs, and data inputs/outputs are internally isolated from any external
influence.
3.
4.
5.
When WE is active, the OE input is internally disabled and has no effect on the I/Os.
The device will consume active power in this mode whenever addresses are changed.
VIN = VCCQ or 0V; all device balls must be static (unswitched) in order to achieve minimum standby current.
Elite Semiconductor Memory Technology Inc.
Publication Date : Dec. 2010
Revision: 1.0
12/15
ESMT
M24L16161DA
PACKING DIMENSIONS
48-BALL PSRAM (6 x 8 mm)
Symbol
Dimension in mm
Min
Norm
Max
A
1.00
A1
0.21
A2
0.66
Φb
0.30
D
5.90
6.00
6.10
E
7.90
8.00
8.10
D1
3.75
E1
5.25
e
0.75
Controlling dimension : Millimeter.
Elite Semiconductor Memory Technology Inc.
Dimension in inch
Min
Norm
Max
0.039
0.008
0.026
0.012
0.232
0.236
0.240
0.311
0.315
0.319
0.148
0.207
0.030
Publication Date : Dec. 2010
Revision: 1.0
13/15
ESMT
M24L16161DA
Revision History
Revision
Date
0.1
2010.02.11
0.2
2010.04.28
0.3
2010.11.03
1.0
2010.12.10
Elite Semiconductor Memory Technology Inc.
Description
Original
1. Modify title and product ID
2. Add package description into ball configuration
1. Modify the specification of ISB
2. Update the specification of tASKEW and tASKEWP
Delete Preliminary
Publication Date : Dec. 2010
Revision: 1.0
14/15
ESMT
M24L16161DA
Important Notice
All rights reserved.
No part of this document may be reproduced or duplicated in any form or by any means
without the prior permission of ESMT.
The contents contained in this document are believed to be accurate at the time of
publication. ESMT assumes no responsibility for any error in this document, and reserves
the right to change the products or specification in this document without notice.
The information contained herein is presented only as a guide or examples for the
application of our products. No responsibility is assumed by ESMT for any infringement of
patents, copyrights, or other intellectual property rights of third parties which may result
from its use. No license, either express , implied or otherwise, is granted under any
patents, copyrights or other intellectual property rights of ESMT or others.
Any semiconductor devices may have inherently a certain rate of failure. To minimize
risks associated with customer's application, adequate design and operating safeguards
against injury, damage, or loss from such failure, should be provided by the customer
when making application designs.
ESMT's products are not authorized for use in critical applications such as, but not limited
to, life support devices or system, where failure or abnormal operation may directly affect
human lives or cause physical injury or property damage. If products described here are
to be used for such kinds of application, purchaser must do its own quality assurance
testing appropriate to such applications.
Elite Semiconductor Memory Technology Inc.
Publication Date : Dec. 2010
Revision: 1.0
15/15