M24L16161ZA

ESMT
M24L16161ZA
PSRAM
16-Mbit (1M x 16)
Async / Page Pseudo Static RAM
Features
• Voltage range: 2.7V – 3.3 V
• Access Time: 70 ns
• Ultra-low active power
— Maximum active current: 20 mA (for random Read/ Write)
— Maximum active current: 20 mA (for page Read)
• Ultra low standby power
• 16-word Page Mode
• Low-power features:
— Temperature-compensated refresh (TCR)
— On-chip temperature sensor
— Partial-array refresh (PAR)
— Deep power-down (DPD) mode
• CMOS for optimum speed/power
• Operating Temperature (TC): –25°C to +85°C (Extended)
Ordering Information
Product ID
M24L16161ZA-70BEG
Speed
(ns)
Package
Operating
Temperature
Comments
70
48-ball BGA
Extended
Pb-free
Functional Description
The device is a high-performance CMOS Pseudo Static RAM
organized as 1M words by 16 bits that supports an
asynchronous memory interface. This device features
advanced circuit design to provide ultra-low active current.
This is ideal for portable applications such as cellular
telephones. A refresh configuration register (RCR) is used to
control how refresh is performed on the DRAM array. This
register is automatically loaded with default settings during
power-up and can be updated anytime during normal
operation.
uses an on-chip sensor to adjust the refresh rate to match the
device temperature. The refresh rate decreases at lower
temperatures to minimize current consumption during standby.
Setting sleep enable ( ZZ ) to LOW enables one of two
low-power modes: partial-array refresh (PAR) or deep
power-down (DPD). PAR limits refresh to only that part of the
DRAM array that contains essential data. DPD halts refresh
operation altogether and is used when no vital information is
stored in the device. The system-configurable refresh
mechanisms are accessed through the RCR.
There are three system-accessible mechanisms to minimize
refresh current. Temperature-compensated refresh (TCR)
Elite Semiconductor Memory Technology Inc.
Publication Date : Dec. 2010
Revision: 1.0
1/21
ESMT
M24L16161ZA
Product Portfolio
Power Dissipation
Product
M24L16161ZA
VCC Range(V)
Min.
Max.
2.7
3.3
Speed
(ns)
70
Operating Current
Deep Power-Down
ICC1 (mA)
ICC1P (mA)
Standby, ISB
(µA)
Max.
Max.
Max.
Max.
20
20
140
10
(µA)
Logic Block Diagram
Elite Semiconductor Memory Technology Inc.
Publication Date : Dec. 2010
Revision: 1.0
2/21
ESMT
M24L16161ZA
BALL CONFIGURATION (TOP VIEW)
(BGA48, 6mmX8mmX1mm Body, 0.8mm Ball Pitch)
1
2
3
4
5
6
A
BLE
OE
A0
A1
A2
ZZ
B
DQ8
BHE
A3
A4
CE
DQ0
C
DQ9
DQ10
A5
A6
DQ1
DQ2
D
VSSQ
DQ11
A17
A7
DQ3
VCC
E
VCCQ
DQ12
NC
A16
DQ4
VSS
F
DQ14
DQ13
A14
A15
DQ5
DQ6
G
DQ15
A19
A12
A13
WE
DQ7
H
A18
A8
A9
A10
A11
NC
Ball Function Description
Ball Name
Type
Description
A[19:0]
Input
Address inputs: Inputs for the address accessed during READ or WRITE operations. The
address lines are also used to define the value to be loaded into the RCR.
CE
Input
Chip enable: Activates the device when LOW. When CE is HIGH, the device is disabled
and goes into standby power mode.
BLE
Input
Lower byte enable: DQ[7:0].
OE
Input
Output enable: Enables the output buffers when LOW. When OE is HIGH, the output
buffers are disabled.
BHE
Input
Upper byte enable: DQ[15:8].
WE
Input
Write enable: Enables WRITE operations when LOW.
ZZ
Input
DQ[15:0]
NC
VCC
VCCQ
VSS
VSSQ
Input / Output
Supply
Supply
Supply
Supply
Sleep enable: When ZZ is LOW, the RCR can be loaded or the device can enter one of
two low-power modes (DPD or PAR).
Data inputs/outputs.
Not internally connected.
Device power supply: Power supply for device core operation.
I/O power supply: Power supply for input/output buffers.
VSS must be connected to ground.
VSSQ must be connected to ground.
Elite Semiconductor Memory Technology Inc.
Publication Date : Dec. 2010
Revision: 1.0
3/21
ESMT
M24L16161ZA
Absolute Maximum Ratings
Parameter
Voltage to any ball except VCC, VCCQ relative to VSS
Voltage on VCC supply relative to VSS
Voltage on VCCQ supply relative to VSS
Storage temperature
Rating
Unit
-0.3 to VCCQ + 0.3
-0.2 to +2.45
-0.2 to +2.45
-55 to +150
V
V
V
℃
-25 to +85
℃
Operating temperature (case) - Extended
Soldering temperature and time
℃
+260
10 seconds (solder ball only)
Note: Stresses greater than those listed in the above table may cause permanent damage to the device. This is a stress rating only,
and functional operation of the device at these or any other conditions above those indicated in the operational sections of
this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
DC Electrical Characteristics
Symbol
Description
Test Conditions
VCC
VCCQ
VOH
VOL
VIH
VIL
ILI
Supply Voltage
I/O Supply Voltage
Output HIGH Voltage
Output LOW Voltage
Input HIGH Voltage
Input LOW Voltage
Input Leakage Current
VIN = 0 to VCCQ
ILO
Output Leakage Current
ICC1
-70
Min.
Max.
2.7
2.7
0.8 x VCCQ
3.3
3.3
Unit
Note
0.2 x VCCQ
VCCQ + 0.2
0.4
1
V
V
V
V
V
V
µA
OE = VIH or Chip disabled
1
µA
Asynchronous random
Read/Write
VIN = VCCQ or 0V, Chip enabled,
IOUT = 0 mA,
20
mA
4
ICC1P
Asynchronous Page
Read
VIN = VCCQ or 0V, Chip enabled,
IOUT = 0 mA,
20
mA
4
ISB
Standby current
VIN = VCCQ or 0V, CE = VCCQ
140
µA
5
IZZ
Deep power-down
VIN = VCCQ or 0 V, +25°C, ZZ =
0V, RCR[4] =0
10
µA
IOH = −0.2 mA
IOL = 0.2 mA
VCCQ – 0.4
-0.2
1,2
3
Partial-Array Refresh Specifications and Conditions [6]
Symbol
IPAR
Standard power
(no designation)
Description
Partial-array
refresh standby
current
Conditions
VIN = VCCQ or 0V ;
CE = VCCQ
Array Partition
Max
Unit
Full
1/2
1/4
1/8
0
140
130
120
110
100
µA
Notes:
1. Input signals may overshoot to V CCQ + 1.0V for periods less than 2ns during transitions.
2. VIH (MIN) value is not aligned with PSRAM Workgroup 1.0 specification of V CCQ - 0.4V.
3. Input signals may undershoot to Vss - 1.0V for periods less than 2ns during transitions.
4. This parameter is specified with the outputs disabled to avoid external loading effects. The user must add the current required
to drive output capacitance expected in the actual system.
5. ISB (MAX) values measured with PAR set to FULL ARRAY and at +85°C. In order to achieve low standby current, all inputs
must be driven to V CCQ or Vss. ISB may be slightly higher for up to 500ms after power-up or when entering standby mode.
6. IPAR (MAX) values measured at 85°C. IPAR might be slightly higher for up to 500ms after changes to the PAR array partition or
when entering standby mode. In order to achieve low standby current, all inputs must be driven to either VCCQ or VSS.
Elite Semiconductor Memory Technology Inc.
Publication Date : Dec. 2010
Revision: 1.0
4/21
ESMT
M24L16161ZA
Capacitance
Symbol
CIN
CIO
Description
Input Capacitance
Input/Output
Capacitance (DQ)
Test Conditions
TC = +25°C, f = 1 MHz,
VIN = 0 V
Min.
Max.
Unit
2.0
6
pF
3.5
6
pF
Note: These parameters are verified in device characterization and are not 100% tested.
AC Input/Output Reference Waveform
Notes:
1. AC test inputs are driven at VCCQ for a logic 1 and VSSQ for a logic 0. Input rise and fall times (10% to 90%) <1.6ns.
2. Input timing begins at VCCQ /2.
3. Output timing ends at VCCQ /2.
AC Output Load Circuit
Elite Semiconductor Memory Technology Inc.
Publication Date : Dec. 2010
Revision: 1.0
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ESMT
M24L16161ZA
Timing Parameters
Symbol
Description
–70
Min.
Max.
70
8000
70
Unit
Read Cycle
tRC
tAA
tOH
tCO
Read Cycle Time
Address to Data Valid
Data Hold from Address Change
CE LOW to Data Valid
70
ns
ns
ns
ns
tOE
OE LOW to Data Valid
20
ns
tOLZ
OE LOW to Low-Z
tOHZ
OE HIGH to High-Z
tLZ
CE LOW to Low-Z
tHZ
CE HIGH to High-Z
tBA
BLE / BHE LOW to Data Valid
tBLZ
BLE / BHE LOW to Low-Z
tBHZ
BLE / BHE HIGH to High-Z
tASKEW
Address Skew
Page Read Cycle
tPC
Page Mode Read Cycle Time
tAPA
Page Mode Address Access
tCEM
Maximum CE pulse width
tASKEWP
Page Mode Access Address Skew
Write Cycle
tWC
Write Cycle Time
tCW
CE LOW to Write End
tAW
tWR
tAS
tWP
tBW
tDW
tDH
tWHZ
5
3
ns
2
ns
1
ns
2
8
ns
1
70
ns
ns
2
8
10
ns
ns
1
5
8000
25
8
3
ns
ns
µs
ns
8000
ns
8
10
10
25
70
70
ns
Address Set-Up to Write End
Address Hold from Write End
Address Set-Up to Write Start
Write Pulse Width
70
0
0
45
ns
ns
ns
ns
BLE / BHE LOW to Write End
Data Set-Up to Write End
Data Hold from Write End
70
ns
20
0
ns
ns
8
WE LOW to High-Z
4
1
2
WE HIGH to Low-Z
5
ns
tCPH
CE HIGH timing during Write
5
ns
tWPH
tASKEW
Write pulse width HIGH
Address Skew
10
3
3
ns
tOW
Elite Semiconductor Memory Technology Inc.
Note
ns
ns
5
Publication Date : Dec. 2010
Revision: 1.0
6/21
ESMT
M24L16161ZA
Timing Parameters (Continued)
Symbol
Description
–70
Min.
Max.
Unit
Note
Power-up Initialization
tPU
Chip Enable Low After Stable VCC
150
µs
8000
ns
ns
Load Refresh Configuration Register
tWC
Write Cycle Time
tAW
Address Set-up to Write End
70
70
tCW
CE LOW to Write End
70
ns
tWR
tAS
Address Hold from Write End
Address Set-up Write Start
0
0
ns
ns
tWP
WE Pulse Width
45
ns
tCDZZ
Chip deselect to ZZ low
5
ns
ZZ low to WE low
Deep Power-Down
10
tCDZZ
Chip deselect to ZZ low
5
ns
tZZ
Minimum ZZ plus width
10
µs
tR
Deep power-down recovery
150
µs
tZZWE
500
ns
Notes:
1. Low-Z to High-Z timings are tested with the circuit shown in “AC Output Load Circuit” figure. The High-Z timings measure a
100mV transition from either VOH or VOL toward VCCQ /2.
2. High-Z to Low-Z timings are tested with the circuit shown in “AC Output Load Circuit” figure. The Low-Z timings measure a
100mV transition away from the High-Z (VCCQ /2) level toward either VOH or VOL.
3. Page mode enabled only.
4. WE LOW time must be limited to tCEM (max).
5. Applies when control signals ( CE , BLE / BHE ) are active.
Elite Semiconductor Memory Technology Inc.
Publication Date : Dec. 2010
Revision: 1.0
7/21
ESMT
M24L16161ZA
Power-up Characteristics
The initialization sequence is shown in Figure below. Chip
Select ( CE ) should be HIGH for at least tPU time after VCC has
reached a stable value. No access must be attempted during
this period of tPU.
Power up Initialization Period
Stable Power
VCC
First Address
tPU
CE
Refresh Configuration Register Operation
The Refresh Configuration Register (RCR) defines how the
device performs its trans-parent self refresh. Altering the
refresh parameters can dramatically reduce current
consumption during standby mode. Page mode control is also
embedded into the RCR. This register can be updated any
time the device is operating in a standby state. At power-up,
the RCR is set to 0080h.
Access Using ZZ
The RCR can be loaded using a WRITE operation immediately
rising edge of CE or WE , whichever occurs first. BHE /
after ZZ makes a HIGH-to-LOW transition. The values
placed on addresses A[19:0] are latched into the RCR on the
BLE are “Don’t Care”. Access using ZZ is WRITE only.
Load Refresh Configuration Register Operation
tWC
OPCODE
ADDRESS
tAW
tCW
CE
tWR
BLE / BHE
tAS
tWP
WE
OE
tCDZZ tZZWE
ZZ
Elite Semiconductor Memory Technology Inc.
Publication Date : Dec. 2010
Revision: 1.0
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ESMT
M24L16161ZA
Software Access to the Refresh Configuration Register
The contents of the RCR can either be read or modified using
a software sequence. The nature of this access mechanism
may eliminate the need for the ZZ pin.
If the software mechanism is used, ZZ can simply be tied to
VCCQ. The port line typically used for ZZ control purposes will
no longer be required. However, ZZ should not be tied to
VCCQ if the system will use DPD; DPD cannot be enabled or
disabled using the software access sequence.
The RCR is loaded using a four-step sequence consisting of
two asynchronous READ operations followed by two
asynchronous WRITE operations. The read sequence is
virtually identical except that an asynchronous READ is
performed during the fourth operation. Note that a third READ
cycle of the highest address will cancel the access sequence
until a different address is read.
16Mb); the content of this address is not changed by using this
sequence. The data bus is used to transfer data into or out of
bits 15–0 of the RCR.
Writing to the RCR using the software sequence modifies the
function of the ZZ pin. After the software sequence loads the
RCR, the level of the ZZ pin no longer enables PAR
operation. PAR operation will be updated whenever the
software sequence loads a new value into the RCR. This ZZ
functionality will continue until the next time the device is
powered-up. The operation of the ZZ pin is not affected if the
software sequence is only used to read the contents of the
RCR. The use of the software sequence does not affect the
ability to perform the standard ( ZZ -controlled) method of
loading the RCR.
The address used during all READ and WRITE operations is
the highest address of the device being accessed (FFFFFh for
Software Access Load Refresh Configuration Register
ADDRESS
READ
READ
WRITE
WRITE
Address
(MAX)
Address
(MAX)
Address
(MAX)
Address
(MAX)
CE
OE
WE
BLE / BHE
DATA
XXXXh
XXXXh
0000h
RCR value
in
Don’t care
Elite Semiconductor Memory Technology Inc.
Publication Date : Dec. 2010
Revision: 1.0
9/21
ESMT
M24L16161ZA
Software Access Read Refresh Configuration Register
ADDRESS
READ
READ
WRITE
READ
Address
(MAX)
Address
(MAX)
Address
(MAX)
Address
(MAX)
CE
OE
WE
BLE / BHE
DATA
XXXXh
XXXXh
RCR value
out
0000h
Don’t care
Refresh Configuration Register Bit Mapping
Elite Semiconductor Memory Technology Inc.
Publication Date : Dec. 2010
Revision: 1.0
10/21
ESMT
M24L16161ZA
Partial-Array Refresh (RCR[2:0]) Default = Full-Array Refresh
The PAR bits restrict REFRESH operation to a portion of the total memory array. This feature allows the system to reduce current
by only refreshing that part of the memory array required by the host system. The refresh options are full array, one-half array,
one-quarter array, one-eighth array, or none of the array. The mapping of these partitions can start at either the beginning or the
end of the address map.
Sleep Mode (RCR[4]) Default = DPD Enabled, PAR Disabled
The sleep mode bit determines which low-power mode is to be entered when ZZ is driven LOW. If RCR[4] = 1, PAR operation is
enabled. If RCR[4] = 0, DPD operation is enabled. PAR can also be enabled directly by writing to the RCR using the software
access sequence. Note that this then disables ZZ initiation of PAR. DPD cannot be enabled or disabled using the software
access sequence; this should only be done using ZZ to access the RCR.
DPD operation disables all refresh-related activity. This mode will be used when the system does not require the storage provided
by the device. Any stored data will become corrupted when DPD is enabled. When refresh activity has been re-enabled, the device
will require tR to perform an initialization procedure before normal operation can resume. DPD should not be enabled using RCR
software access.
Page Mode READ Operation (RCR[7]) Default = Enabled
The page mode operation bit determines whether page mode READ operations are enabled. In the power-up default state, page
mode is enabled.
16Mb Address Patterns for PAR (RCR[4] = 1)
RCR[2]
RCR[1]
RCR[0]
Active Section
Address Space
Size
Density
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
Full die
One-half of die
One-quarter of die
One-eighth of die
None of die
One-half of die
One-quarter of die
One-eighth of die
00000h–FFFFFh
00000h–7FFFFh
00000h–3FFFFh
00000h–1FFFFh
0
80000h–FFFFFh
C0000h–FFFFFh
E0000h–FFFFFh
1 Meg x 16
512K x 16
256K x 16
128K x 16
0 Meg x 16
512K x 16
256K x 16
128K x 16
16Mb
8Mb
4Mb
2Mb
0Mb
8Mb
4Mb
2Mb
Elite Semiconductor Memory Technology Inc.
Publication Date : Dec. 2010
Revision: 1.0
11/21
ESMT
M24L16161ZA
Low-Power Operation
Temperature-Compensated Refresh (TCR)
Temperature-compensated refresh (TCR) allows for adequate
refresh at different temperatures. This device includes an
on-chip temperature sensor. It continually adjusts the refresh
rate according to the operating temperature.
Partial-Array Refresh (PAR)
The device only enters PAR mode if the SLEEP bit in the RCR
has been set HIGH (RCR[4] = 1). PAR can be initiated by
bring the ZZ to the LOW state for longer than 10μs. READ
and WRITE operations are ignored during PAR operation.
Returning ZZ to HIGH will cause an exit from PAR and the
entire array will be immediately available for READ and
WRITE operations.
Alternatively, PAR can be initiated using the RCR software
access sequence (see “Software Access to the Refresh
Configuration Register”). PAR is enabled immediately upon
setting RCR[4] to “1” using this method. However, using
software access to write to the RCR alters the function of ZZ
so that ZZ LOW no longer initiates PAR, although ZZ
continues to enable WRITEs to the RCR. This functional
change persists until the next time the device is powered up.
Software Access PAR Functionality
Elite Semiconductor Memory Technology Inc.
Publication Date : Dec. 2010
Revision: 1.0
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ESMT
M24L16161ZA
Deep Power-Down Operation (DPD)
Deep power-down (DPD) operation disables all refresh-related
activity. This mode is used when the system does not require
the storage provided by the device. Any stored data will
become corrupted when DPD is entered. When refresh activity
has been re-enabled, the device will require tR to perform an
initialization procedure before normal operations can resume.
READ and WRITE operations are ignored during DPD
operation.
The device can only enter DPD if the SLEEP bit in the RCR
has been set LOW (RCR[4] = 0). DPD is initiated by bringing
ZZ
HIGH will cause the device to exit DPD and begin a tR
initialization process. During the period of tR, the current
consumption will be higher than the specified standby levels
but considerably lower than the active current specification.
Driving ZZ LOW will place the device in the PAR mode if the
SLEEP bit in the RCR has been set HIGH (RCR[4] = 1).
The device should not be put into DPD using RCR software
access.
to the LOW state for longer than 10µs. Returning ZZ to
Deep Power-Down Entry and Exit
tCDZZ tZZ(MIN)
ZZ
tR
CE
Device ready for
normal operation
Don’t care
Page Mode
This device can be operated in a page read mode. This is
accomplished by initiating a normal read of the device.
fixed. For a 16-word page access operation, all address bits
except for A3, A2, A1 and A0 should be fixed.
In order to operate the device in page mode, the upper order
address bits should be fixed for 4-word page access operation,
all address bits except for A1 and A0 should be fixed until the
page access is completed. For an 8-word page access
operation, all address bits except for A2, A1 and A0 should be
The supported page lengths are 4, 8 and 16 words. Random
page read is supported for all three 4, 8 and 16-word page
read options. Therefore, any address can be used as the
starting address. Please refer to “Page Read Modes Table” for
an overview of the page read modes.
Page Read Modes Table
Page Mode Feature
4-Word Mode
8-Word Mode
16-Word Mode
Page Length
4 words
8 words
16 words
Page Read Corresponding Addresses
A1, A0
A2, A1, A0
A3, A2, A1, A0
Page Read Start Address
Don't Care
Don't Care
Don't Care
Page Direction
Don't Care
Don't Care
Don't Care
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Publication Date : Dec. 2010
Revision: 1.0
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ESMT
M24L16161ZA
Asynchronous Read Cycle
tRC
Valid Address
ADDRESS
tASKEW
tAA
tASKEW
tASKEW
tHZ
tCO
CE
tBA
tBHZ
BLE / BHE
tOE
tOHZ
OE
tOLZ
WE
tBLZ
tLZ
High-Z
DATA
Valid Output
Don’t care
Undefined
Page Read Cycle
tRC
Valid Address
A[19:4]
tASKEW
A[3:0]
tASKEW
tASKEWP
tASKEW
Valid
Valid
Address Address
Valid
Address
Valid Address
tAA
tPC
tASKEW
tCO
tCEM
tHZ
CE
tBA
tBHZ
BLE / BHE
tOE
tOHZ
OE
tOLZ
tBLZ
WE
tAPA
tLZ
DATA
High-Z
tOH
Valid
Output
Valid
Output
Valid
Output
Don’t care
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Valid
Output
Undefined
Publication Date : Dec. 2010
Revision: 1.0
14/21
ESMT
M24L16161ZA
Asynchronous Write Cycle — CE Controlled
tWC
ADDRESS
Valid Address
tAW
tWR
tAS
tCW
tCPH
CE
tBW
BLE / BHE
OE
tWP
tWPH
WE
tDW
DATA IN
High-Z
tDH
Valid Input
tWHZ
DATA OUT
Don’t care
Asynchronous Write Cycle — WE Controlled
tWC
ADDRESS
Valid Address
tAW
tWR
tCW
CE
tBW
BLE / BHE
OE
tAS
tWPH
tWP
WE
tDW
DATA IN
High-Z
tDH
Valid Input
tWHZ
tOW
DATA OUT
Don’t care
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Publication Date : Dec. 2010
Revision: 1.0
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M24L16161ZA
Asynchronous Write Cycle — BHE / BLE Controlled
tWC
ADDRESS
Valid Address
tAW
tAS
tWR
tCW
CE
tBW
BLE / BHE
OE
tWP
tWPH
WE
tDW
High-Z
DATA IN
tDH
Valid Input
tWHZ
DATA OUT
Don’t care
Asynchronous Write Followed by Asynchronous Read Cycle
ADDRESS
Valid Address
Valid Address
tAW
tBW
Valid Address
tWR
tAA
tBHZ
tBLZ
BLE / BHE
tCPH
tCW
tHZ
CE
tLZ
OE
tAS
tOHZ
tOE
tWC
tWP tWPH
WE
DATA
IN/OUT
High-Z
Data
tDH
Data
tDW
High-Z
tOLZ
Don’t care
Valid Output
Undefined
Note: tCPH is only required after Write cycle - CE controlled
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Publication Date : Dec. 2010
Revision: 1.0
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ESMT
M24L16161ZA
Avoid Timing
ESMT Pseudo SRAM has a timing which is not supported at read operation, If your system has multiple invalid address signal
shorter than tRC during over 8μs at read operation shown as in Abnormal Timing, it requires a normal read timing at least during 8μs
shown as in Avoidable timing 1 or toggle CE to high (≧tRC) one time at least shown as in Avoidable Timing 2.
Abnormal Timing
≧8μ s
CE
WE
＜ tRC
Address
Avoidable Timing 1
≧8μ s
CE
WE
≧ tRC
Address
Avoidable Timing 2
≧8μ s
CE
≧ tRC
WE
＜ tRC
Address
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M24L16161ZA
Truth Table
BHE /
DQ[15:0]
CE
WE
OE
H
L
L
L
X
H
L
X
X
L
X
X
X
L
L
X
H
H
H
H
High-Z
Data Out
Data In
X
L
L
X
X
L
High-Z
H
X
X
X
L
High-Z
BLE
ZZ
Mode
Standby
Read
Write
Not Operation
Load Refresh Configuration
Register
DPD/PAR
Power
Standby (ISB)
Active (ICC)
Active (ICC)
Idle
Note
2, 5
1, 4
1, 3, 4
4, 5
Active (ICC)
Deep Sleep (IZZ)/
Standby (IPAR)
6
H = Logic HIGH, L = Logic LOW, X = Don’t Care
Note:
1.
When BLE and BHE are in select mode (LOW), DQ[15:0] are affected. When only BLE is in select mode, DQ[7:0]
2.
are affected. When only BHE is in the select mode, DQ[15:8] are affected.
When the device is in standby mode, address inputs, and data inputs/outputs are internally isolated from any external
influence.
3.
4.
5.
6.
When WE is active, the OE input is internally disabled and has no effect on the I/Os.
The device will consume active power in this mode whenever addresses are changed.
VIN = VCCQ or 0V; all device balls must be static (unswitched) in order to achieve minimum standby current.
DPD is enabled when Refresh Configuration Register bit RCR[4] is “0”; otherwise, PAR is enabled.
Elite Semiconductor Memory Technology Inc.
Publication Date : Dec. 2010
Revision: 1.0
18/21
ESMT
M24L16161ZA
PACKING DIMENSIONS
48-BALL PSRAM (6 x 8 mm)
Symbol
Dimension in mm
Min
Norm
Max
A
1.00
A1
0.21
A2
0.66
Φb
0.30
D
5.90
6.00
6.10
E
7.90
8.00
8.10
D1
3.75
E1
5.25
e
0.75
Controlling dimension : Millimeter.
Elite Semiconductor Memory Technology Inc.
Dimension in inch
Min
Norm
Max
0.039
0.008
0.026
0.012
0.232
0.236
0.240
0.311
0.315
0.319
0.148
0.207
0.030
Publication Date : Dec. 2010
Revision: 1.0
19/21
ESMT
M24L16161ZA
Revision History
Revision
Date
0.1
2010.02.03
0.2
2010.04.28
0.3
2010.11.03
1.0
2010.12.13
Elite Semiconductor Memory Technology Inc.
Description
Original
1. Modify title and product ID
2. Add package description into ball configuration
3. Correct the specification of IPAR
1. Modify the specification of ISB and IPAR
2. Update the specification of tASKEW and tASKEWP
Delete Preliminary
Publication Date : Dec. 2010
Revision: 1.0
20/21
ESMT
M24L16161ZA
Important Notice
All rights reserved.
No part of this document may be reproduced or duplicated in any form or by any means
without the prior permission of ESMT.
The contents contained in this document are believed to be accurate at the time of
publication. ESMT assumes no responsibility for any error in this document, and reserves
the right to change the products or specification in this document without notice.
The information contained herein is presented only as a guide or examples for the
application of our products. No responsibility is assumed by ESMT for any infringement of
patents, copyrights, or other intellectual property rights of third parties which may result
from its use. No license, either express , implied or otherwise, is granted under any
patents, copyrights or other intellectual property rights of ESMT or others.
Any semiconductor devices may have inherently a certain rate of failure. To minimize
risks associated with customer's application, adequate design and operating safeguards
against injury, damage, or loss from such failure, should be provided by the customer
when making application designs.
ESMT's products are not authorized for use in critical applications such as, but not limited
to, life support devices or system, where failure or abnormal operation may directly affect
human lives or cause physical injury or property damage. If products described here are
to be used for such kinds of application, purchaser must do its own quality assurance
testing appropriate to such applications.
Elite Semiconductor Memory Technology Inc.
Publication Date : Dec. 2010
Revision: 1.0
21/21