M66258FP
8192 × 8-Bit Line Memory
REJ03F0252-0200
Rev.2.00
Sep 14, 2007
Description
The M66258FP is high speed line memory that uses high performance silicon gate CMOS process technology and
adopts the FIFO (First In First Out) structure consisting of 8192 words × 8 bits.
The M66258FP, performing reading and writing operations at different cycles independently and asynchronously, is
optimal for buffer memory to be used between equipment of different data processing speeds.
Features
•
•
•
•
•
•
•
•
Memory configuration:
8192 words × 8 bits configuration
High speed cycle:
20 ns (Min)
High speed access:
16 ns (Max)
Output hold:
3 ns (Min)
Reading and writing operations can be completely carried out independently and asynchronously
Variable length delay bit
Input/output:
TTL direct connection allowable
Output:
3 states
Application
Digital copying machine, laser beam printer, high speed facsimile, etc.
WCK 17
Write
clock input
13 14 15 16 21 22 23 24
1 2 3 4 9 10 11 12
Input buffer
Output buffer
VCC 18
REJ03F0252-0200 Rev.2.00 Sep 14, 2007
Page 1 of 13
Memory array
8192 × 8 bits
Read control circuit
Write
reset input
Data outputs
Q0 to Q7
Read address counter
WRES 19
Data inputs
D0 to D7
Write address counter
WE 20
Write
enable input
Write control circuit
Block Diagram
5 RE
Read
enable input
6 RRES
Read
reset input
8 RCK
Read
clock input
7 GND
M66258FP
Pin Arrangement
M66258FP
Data output
Read enable input
Read reset input
Read clock input
Data output
Q0
Q1
Q2
Q3
RE
RRES
GND
RCK
Q4
Q5
Q6
Q7
1
24 D0
2
23 D1
3
22 D2
4
21 D3
5
20 WE
6
7
19 WRES Write reset input
18 VCC
8
17 WCK
9
16 D4
10
15 D5
11
14 D6
12
13 D7
(Top view)
Outline: 24P2U-A
REJ03F0252-0200 Rev.2.00 Sep 14, 2007
Page 2 of 13
Data input
Write enable input
Write clock input
Data input
M66258FP
Absolute Maximum Ratings
(Ta = 0 to 70°C, unless otherwise noted)
Item
Supply voltage
Symbol
VCC
Input voltage
Output voltage
VI
VO
Power dissipation
Storage temperature
Pd
Tstg
Ratings
−0.5 to +6.0
Unit
V
−0.5 to VCC + 0.5
−0.5 to VCC + 0.5
V
V
825
−65 to 150
mW
°C
Conditions
Value based on the GND pin
Ta = 25°C
Recommended Operating Conditions
Supply voltage
Item
Symbol
VCC
Supply voltage
Operating temperature
GND
Topr
Min
4.5
Typ
5.0
Max
5.5
Unit
V
0
0 to 70
V
°C
Electrical Characteristics
(Ta = 0 to 70°C, VCC = 5 V ± 10%, GND = 0 V, unless otherwise noted)
Item
High-level input voltage
Symbol
VIH
Min
2.0
Typ
Max
Unit
V
Low-level input voltage
High-level output voltage
Test Conditions
VIL
VOH
VCC − 0.8
0.8
V
V
Low-level output voltage
High-level input current
VOL
IIH
0.55
1.0
V
µA
IOL = 4 mA
VI = VCC
WE, WRES, WCK,
RE, RRES, RCK,
D0 to D7
Low-level input current
IIL
−1.0
µA
VI = GND
Off-state high-level output current
IOZH
5.0
µA
VO = VCC
Off-state low-level output current
Average supply current during
operation
IOZL
ICC
−5.0
150
µA
mA
Input capacitance
CI
10
pF
VO = GND
VI = VCC, GND, Output open
tWCK, tRCK = 20 ns
f = 1 MHz
Off-time output capacitance
CO
15
pF
f = 1 MHz
IOH = −4 mA
WE, WRES, WCK,
RE, RRES, RCK,
D0 to D7
Function
When write enable input WE is set to "L", the contents of data inputs D0 to D7 are read in synchronization with a rising
edge of write clock input WCK to perform writing operation. When this is the case, the write address counter is also
incremented simultaneously.
When WE is set to "H", the writing operation is inhibited and the write address counter stops.
When write reset input WRES is set to "L", the write address counter is initialized.
When read enable input RE is set to "L", the contents of memory are output to data outputs Q0 to Q7 in synchronization
with a rising edge of read clock input RCK to perform reading operation. When this is the case, the read address
counter is incremented simultaneously.
When RE is set to "H", the reading operation is inhibited and the read address counter stops. The outputs are placed in
a high impedance state.
When read reset input RRES is set to "L", the read address counter is initialized.
REJ03F0252-0200 Rev.2.00 Sep 14, 2007
Page 3 of 13
M66258FP
Switching Characteristics
(Ta = 0 to 70°C, VCC = 5 V ± 10%, GND = 0 V, unless otherwise noted)
Item
Symbol
Access time
tAC
Min
Typ
Max
16
Unit
ns
Output hold time
Output enable time
tOH
tOEN
3
3
16
ns
ns
Output disable time
tODIS
3
16
ns
Timing Requirements
(Ta = 0 to 70°C, VCC = 5 V ± 10%, GND = 0 V, unless otherwise noted)
Min
Typ
Max
Unit
Write clock (WCK) cycle
Write clock (WCK) "H" pulse width
Item
tWCK
tWCKH
Symbol
20
8
ns
ns
Write clock (WCK) "L" pulse width
Read clock (RCK) cycle
tWCKL
tRCK
8
20
ns
ns
Read clock (RCK) "H" pulse width
Read clock (RCK) "L" pulse width
tRCKH
tRCKL
8
8
ns
ns
Input data setup time for WCK
Input data hold time for WCK
tDS
tDH
4
3
ns
ns
Reset setup time for WCK/RCK
Reset hold time for WCK/RCK
tRESS
tRESH
4
3
ns
ns
Reset non-selection setup time for WCK/RCK
Reset non-selection hold time for WCK/RCK
tNRESS
tNRESH
4
3
ns
ns
WE setup time for WCK
WE hold time for WCK
tWES
tWEH
4
3
ns
ns
WE non-selection setup time for WCK
WE non-selection hold time for WCK
tNWES
tNWEH
4
3
ns
ns
RE setup time for RCK
RE hold time for RCK
tRES
tREH
4
3
ns
ns
RE non-selection setup time for RCK
RE non-selection hold time for RCK
tNRES
tNREH
4
3
ns
ns
Input pulse up/down time
Data hold time*
tr, tf
tH
20
20
ns
ms
Notes: Perform reset operation after turning on power supply.
* For 1 line access, the following conditions must be satisfied:
WE high-level period ≤ 20 ms − 8192 • tWCK − WRES low-level period
RE high-level period ≤ 20 ms − 8192 • tRCK − RRES low-level period
REJ03F0252-0200 Rev.2.00 Sep 14, 2007
Page 4 of 13
M66258FP
Switching Characteristics Measurement Circuit
VCC
RL = 1 kΩ
Qn
SW1
CL = 30 pF: tAC, tOH
Qn
SW2
CL = 5 pF: tOEN, tODIS
RL = 1 kΩ
Input pulse level:
0 to 3 V
Input pulse up/down time: 3 ns
Judging voltage Input:
1.3 V
Output: 1.3 V (However, tODIS (LZ) is judged with 10% of the output amplitude, while tODIS (HZ) is
judged with 90% of the output amplitude)
Load capacitance CL includes the floating capacity of connected lines and input capacitance of probe.
Item
SW1
SW2
tODIS (LZ)
tODIS (HZ)
Close
Open
Open
Close
tOEN (ZL)
tOEN (ZH)
Close
Open
Open
Close
tODIS and tOEN Measurement Condition
3V
RCK
1.3 V
1.3 V
GND
3V
RE
GND
tODIS (HZ)
tOEN (ZH)
VOH
90%
1.3 V
Qn
tODIS (LZ)
Qn
1.3 V
10%
REJ03F0252-0200 Rev.2.00 Sep 14, 2007
Page 5 of 13
tOEN (ZL)
VOL
M66258FP
Operation Timing
Write Cycle
n cycle
n + 1 cycle
n + 2 cycle
Disable cycle
n + 3 cycle
n + 4 cycle
WCK
tWCKH tWCKL tWEH tNWES
tWCK
tNWEH tWES
WE
tDS tDH
Dn
(n)
(n + 1)
(n + 2)
(n + 4)
(n + 3)
WRES = "H"
Write Reset Cycle
n − 1 cycle
n cycle
tWCK
tNRESH tRESS
Reset cycle
0 cycle
1 cycle
2 cycle
WCK
tRESH tNRESS
WRES
tDS tDH
Dn
(n − 1)
(n)
(0)
(1)
(2)
WE = "L"
REJ03F0252-0200 Rev.2.00 Sep 14, 2007
Page 6 of 13
M66258FP
Matters that Needs Attention when WCK Stops
n cycle
n + 1 cycle
n cycle
Disable cycle
WCK
tWCK
tNWES
WE
Dn
tDS tDH
tDS tDH
(n)
(n)
Period for writing data (n)
into memory
Period for writing data (n)
into memory
WRES = "H"
Input data of n cycle is read at the rising edge after WCK of n cycle and writing operation starts in the WCK low-level
period of n + 1 cycle. The writing operation is complete at the falling edge after n + 1 cycle.
To stop reading write data at n cycle, enter WCK before the rising edge after n + 1 cycle.
When the cycle next to n cycle is a disable cycle, WCK for a cycle requires to be entered after the disable cycle as well.
REJ03F0252-0200 Rev.2.00 Sep 14, 2007
Page 7 of 13
M66258FP
Read Cycle
n cycle
n + 1 cycle
n + 2 cycle
tRCK
tRCKH tRCKL
tREH tNRES
Disable cycle
n + 3 cycle
n + 4 cycle
RCK
tNREH
tRES
tAC
RE
tODIS
Qn
(n)
(n + 1)
tOEN
HIGH-Z
(n + 2)
(n + 4)
(n + 3)
tOH
RRES = "H"
Read Reset Cycle
n − 1 cycle
n cycle
tRCK
tNRESH tRESS
Reset cycle
0 cycle
1 cycle
2 cycle
RCK
tRESH tNRESS
RRES
tAC
Qn
(n − 1)
(n)
(0)
(0)
(0)
(1)
tOH
RE = "L"
REJ03F0252-0200 Rev.2.00 Sep 14, 2007
Page 8 of 13
(2)
M66258FP
Variable Length Delay Bit
1 Line (8192 Bits) Delay
Input data can be written at the rising edge of WCK after write cycle and output data is read at the rising edge of RCK
before read cycle to easily make 1 line delay.
0 cycle
1 cycle
2 cycle
8190 cycle 8191 cycle
8192 cycle 8193 cycle 8194 cycle
(0')
(1')
(2')
WCK
RCK
tRESS tRESH
WRES
RRES
tDS tDH
Dn
(0)
tDS tDH
(1)
(2)
(8189)
(8190)
(8191)
(0')
(2')
(3')
(1)
(2)
(3)
tOH
tAC
8192 cycle
(1')
(0)
Qn
WE, RE = "L"
n-bit Delay Bit
(Reset at cycles according to the delay length)
0 cycle
1 cycle
n − 2 cycle n − 1 cycle
2 cycle
n cycle
(0')
n + 1 cycle n + 2 cycle n + 3 cycle
(1')
(2')
(3')
WCK
RCK
tRESS tRESH
tRESS tRESH
WRES
RRES
tDS tDH
Dn
(0)
tDS tDH
(1)
(2)
m cycle
Qn
(n − 3)
(n − 2)
(n − 1)
tAC
(0')
(1')
(2')
(3')
(1)
(2)
(3)
tOH
(0)
WE, RE = "L"
m≥3
REJ03F0252-0200 Rev.2.00 Sep 14, 2007
Page 9 of 13
M66258FP
n-bit Delay 2
(Slides input timings of WRES and RRES at cycles according to the delay length)
0 cycle
1 cycle
n − 2 cycle n − 1 cycle
2 cycle
n + 1 cycle n + 2 cycle n + 3 cycle
n cycle
WCK
RCK
tRESS tRESH
WRES
tRESS tRESH
RRES
tDS tDH
Dn
(0)
tDS tDH
(1)
(2)
(n − 2)
(n − 1)
(n)
(0)
Qn
(n + 2)
(n + 3)
(1)
(2)
(3)
tOH
tAC
m cycle
(n + 1)
WE, RE = "L"
n-bit Delay 3
(Slides address by disabling RE in the period according to the delay length)
0 cycle
1 cycle
n − 1 cycle
2 cycle
n cycle
n + 1 cycle n + 2 cycle n + 3 cycle
WCK
RCK
tRESS tRESH
WRES
RRES
tNREH tRES
RE
tDS tDH
Dn
(0)
tDS tDH
(1)
(2)
m cycle
(n − 2)
(n − 1)
(n)
tAC
(n + 1)
(n + 2)
(n + 3)
(1)
(2)
(3)
tOH
HIGH-Z
Qn
(0)
WE, RE = "L"
m≥3
REJ03F0252-0200 Rev.2.00 Sep 14, 2007
Page 10 of 13
M66258FP
Reading Shortest n-cycle Write Data "n"
(Reading side n − 1 cycle starts after the end of writing side n − 1 cycle)
When the reading side n − 1 cycle starts before the end of the writing side n + 1 cycle, output Qn of n cycle is made
invalid. In the following diagram, reading operation of n − 1 cycle is invalid.
n + 1 cycle
n cycle
n + 2 cycle
n + 3 cycle
WCK
(n)
Dn
(n +1)
n − 2 cycle
(n +2)
n − 1 cycle
(n +3)
n cycle
RCK
Invalid
Qn
(n)
Reading Longest n-cycle Write Data "n": 1 Line Delay
(When writing side n-cycle <2>* starts, reading side n cycle <1>* then starts)
Output Qn of n cycle <1>* can be read until the start of reading side n cycle <1> and the start of writing side n cycle
<2>* overlap each other.
n cycle <1>*
0 cycle <2>*
n cycle <2>*
WCK
Dn
(n − 1) <1>*
(n) <1>*
n cycle <0>*
(0) <2>*
0 cycle <1>*
(n − 1) <2>*
(n) <2>*
n cycle <1>*
RCK
Qn
(n − 1) <0>*
(n) <0>*
Note: <0>*, <1>* and <2>* indicate value of lines.
REJ03F0252-0200 Rev.2.00 Sep 14, 2007
Page 11 of 13
(0) <1>*
(n − 1) <1>*
(n) <1>*
M66258FP
Application Example
Sub Scan Resolution Compensation Circuit with Laplacian Filter
D0
to
D7
B
(n + 1) line
image data
Q0
to
Q7
Adder
N + K {2N − (A + B) }
N
n line image data
M66258
×2
Subtractor
2N − (A + B)
1 line
delay
M66258
Q0
to
Q7
A
(n + 1) line
image data
1 line
delay
Sub scan direction
×K
Adder
A+B
D0
to
D7
Compensated
image data
Main scan direction
A
(n − 1) line
X
n line
B
(n + 1) line
REJ03F0252-0200 Rev.2.00 Sep 14, 2007
Page 12 of 13
N' = N + K { (N − A) + (N − B) }
= N + K {2N − (A + B)}
K: Laplacian coefficient
M66258FP
Package Dimensions
24P2U-A
Plastic 24pin 375mil SSOP
EIAJ Package Code
SSOP24-P-375-0.80
Weight(g)
0.4
JEDEC Code
—
24
Lead Material
Cu Alloy
e
b2
E
HE
e1
I2
13
F
Recommended Mount Pad
Symbol
12
1
A
D
G
A2
e
b
L
L1
y
A1
c
z
Z1
Detail G
REJ03F0252-0200 Rev.2.00 Sep 14, 2007
Page 13 of 13
Detail F
A
A1
A2
b
c
D
E
e
HE
L
L1
z
Z1
y
b2
e1
I2
Dimension in Millimeters
Min
Nom
Max
—
2.65
—
0.2
0.1
0.3
—
2.3
—
0.3
0.35
0.45
0.3
0.23
0.25
10.2
10.3
10.4
7.4
7.5
7.6
0.8
—
—
10.0
10.3
10.6
0.9
0.5
0.7
1.4
—
—
—
—
0.75
—
—
0.9
0.1
—
—
—
8°
0°
—
—
0.5
9.53
—
—
1.27
—
—
Sales Strategic Planning Div.
Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100-0004, Japan
Notes:
1. This document is provided for reference purposes only so that Renesas customers may select the appropriate Renesas products for their use. Renesas neither makes
warranties or representations with respect to the accuracy or completeness of the information contained in this document nor grants any license to any intellectual property
rights or any other rights of Renesas or any third party with respect to the information in this document.
2. Renesas shall have no liability for damages or infringement of any intellectual property or other rights arising out of the use of any information in this document, including,
but not limited to, product data, diagrams, charts, programs, algorithms, and application circuit examples.
3. You should not use the products or the technology described in this document for the purpose of military applications such as the development of weapons of mass
destruction or for the purpose of any other military use. When exporting the products or technology described herein, you should follow the applicable export control laws
and regulations, and procedures required by such laws and regulations.
4. All information included in this document such as product data, diagrams, charts, programs, algorithms, and application circuit examples, is current as of the date this
document is issued. Such information, however, is subject to change without any prior notice. Before purchasing or using any Renesas products listed in this document,
please confirm the latest product information with a Renesas sales office. Also, please pay regular and careful attention to additional and different information to be
disclosed by Renesas such as that disclosed through our website. (http://www.renesas.com )
5. Renesas has used reasonable care in compiling the information included in this document, but Renesas assumes no liability whatsoever for any damages incurred as a
result of errors or omissions in the information included in this document.
6. When using or otherwise relying on the information in this document, you should evaluate the information in light of the total system before deciding about the applicability
of such information to the intended application. Renesas makes no representations, warranties or guaranties regarding the suitability of its products for any particular
application and specifically disclaims any liability arising out of the application and use of the information in this document or Renesas products.
7. With the exception of products specified by Renesas as suitable for automobile applications, Renesas products are not designed, manufactured or tested for applications
or otherwise in systems the failure or malfunction of which may cause a direct threat to human life or create a risk of human injury or which require especially high quality
and reliability such as safety systems, or equipment or systems for transportation and traffic, healthcare, combustion control, aerospace and aeronautics, nuclear power, or
undersea communication transmission. If you are considering the use of our products for such purposes, please contact a Renesas sales office beforehand. Renesas shall
have no liability for damages arising out of the uses set forth above.
8. Notwithstanding the preceding paragraph, you should not use Renesas products for the purposes listed below:
(1) artificial life support devices or systems
(2) surgical implantations
(3) healthcare intervention (e.g., excision, administration of medication, etc.)
(4) any other purposes that pose a direct threat to human life
Renesas shall have no liability for damages arising out of the uses set forth in the above and purchasers who elect to use Renesas products in any of the foregoing
applications shall indemnify and hold harmless Renesas Technology Corp., its affiliated companies and their officers, directors, and employees against any and all
damages arising out of such applications.
9. You should use the products described herein within the range specified by Renesas, especially with respect to the maximum rating, operating supply voltage range,
movement power voltage range, heat radiation characteristics, installation and other product characteristics. Renesas shall have no liability for malfunctions or damages
arising out of the use of Renesas products beyond such specified ranges.
10. Although Renesas endeavors to improve the quality and reliability of its products, IC products have specific characteristics such as the occurrence of failure at a certain
rate and malfunctions under certain use conditions. Please be sure to implement safety measures to guard against the possibility of physical injury, and injury or damage
caused by fire in the event of the failure of a Renesas product, such as safety design for hardware and software including but not limited to redundancy, fire control and
malfunction prevention, appropriate treatment for aging degradation or any other applicable measures. Among others, since the evaluation of microcomputer software
alone is very difficult, please evaluate the safety of the final products or system manufactured by you.
11. In case Renesas products listed in this document are detached from the products to which the Renesas products are attached or affixed, the risk of accident such as
swallowing by infants and small children is very high. You should implement safety measures so that Renesas products may not be easily detached from your products.
Renesas shall have no liability for damages arising out of such detachment.
12. This document may not be reproduced or duplicated, in any form, in whole or in part, without prior written approval from Renesas.
13. Please contact a Renesas sales office if you have any questions regarding the information contained in this document, Renesas semiconductor products, or if you have
any other inquiries.
http://www.renesas.com
RENESAS SALES OFFICES
Refer to "http://www.renesas.com/en/network" for the latest and detailed information.
Renesas Technology America, Inc.
450 Holger Way, San Jose, CA 95134-1368, U.S.A
Tel: <1> (408) 382-7500, Fax: <1> (408) 382-7501
Renesas Technology Europe Limited
Dukes Meadow, Millboard Road, Bourne End, Buckinghamshire, SL8 5FH, U.K.
Tel: <44> (1628) 585-100, Fax: <44> (1628) 585-900
Renesas Technology (Shanghai) Co., Ltd.
Unit 204, 205, AZIACenter, No.1233 Lujiazui Ring Rd, Pudong District, Shanghai, China 200120
Tel: <86> (21) 5877-1818, Fax: <86> (21) 6887-7898
Renesas Technology Hong Kong Ltd.
7th Floor, North Tower, World Finance Centre, Harbour City, 1 Canton Road, Tsimshatsui, Kowloon, Hong Kong
Tel: <852> 2265-6688, Fax: <852> 2730-6071
Renesas Technology Taiwan Co., Ltd.
10th Floor, No.99, Fushing North Road, Taipei, Taiwan
Tel: <886> (2) 2715-2888, Fax: <886> (2) 2713-2999
Renesas Technology Singapore Pte. Ltd.
1 Harbour Front Avenue, #06-10, Keppel Bay Tower, Singapore 098632
Tel: <65> 6213-0200, Fax: <65> 6278-8001
Renesas Technology Korea Co., Ltd.
Kukje Center Bldg. 18th Fl., 191, 2-ka, Hangang-ro, Yongsan-ku, Seoul 140-702, Korea
Tel: <82> (2) 796-3115, Fax: <82> (2) 796-2145
Renesas Technology Malaysia Sdn. Bhd
Unit 906, Block B, Menara Amcorp, Amcorp Trade Centre, No.18, Jalan Persiaran Barat, 46050 Petaling Jaya, Selangor Darul Ehsan, Malaysia
Tel: <603> 7955-9390, Fax: <603> 7955-9510
© 2007. Renesas Technology Corp., All rights reserved. Printed in Japan.
Colophon .7.0