MITSUBISHI <DIGITAL ASSP> M66258FP 8192 x 8-BIT LINE MEMORY DESCRIPTION The M66258FP is high speed line memory that uses high performance silicon gate CMOS process technology and adopts the FIFO (First In First Out) structure consisting of 8192 words x 8 bits. The M66258FP, performing reading and writing operations at different cycles independently and asynchronously, is optimal for buffer memory to be used between equipment of different data processing speeds. PIN CONFIGURATION (TOP VIEW) Q0 1 24 D0 2 23 D1 3 22 D2 FEATURES • • • • • Memory configuration 8192 words x 8 bits configuration High speed cycle 20 ns (Min.) High speed access 16 ns (Max.) Output hold 3 ns (Min.) Reading and writing operations can be completely carried out independently and asynchronously. • Variable length delay bit • Input/output TTL direct connection allowable • Output 3 states Q3 READ ENABLE RE INPUT READ RESET RRES INPUT 4 21 D3 GND 7 RCK 8 Q4 9 16 D4 Q5 10 15 D5 Q6 11 14 D6 Q7 12 13 D7 READ CLOCK INPUT DATA OUTPUT APPLICATION • Digital copying machine, laser beam printer, high speed facsimile, etc. 5 6 M66258FP Q1 Q2 DATA OUTPUT DATA INPUT WRITE ENABLE INPUT 19 WRES WRITE RESET INPUT 20 WE 18 VCC 17 WCK WRITE CLOCK INPUT DATA INPUT Outline 24P2U-A(SSOP) FUNCTIONAL DESCRIPTION When write enable input WE is set to "L", the contents of data inputs D0 to D7 are read in synchronization with a rising edge of write lock input WCK to perform writing operation. When this is the case,the write address counter is also incremented simultaneously. When WE is set to "H", the writing operation is inhibited and the write address counter stops. When write reset input WRES is set to "L", the write address counter is initialized. When read enable input RE is set to "L", the contents of memory are output to data outputs Q0 to Q7 in synchronization with a rising edge of read clock input RCK to perform reading operation. When this is the case, the read address counter is incremented simultaneously. When RE is set to "H", the reading operation is inhibited and the read address counter stops. The outputs are placed in a high impedance state. When read reset input RRES is set to "L", the read address counter is initialized. 1 2 WE 20 Write clock input VCC 18 WCK 17 Write reset input WRES 19 Write enable input BLOCK DIAGRAM 13 14 15 21 Input buffer 16 Data inputs D0 to D7 22 24 1 2 Memory array 8192 x 8 bits 23 3 9 Output buffer 4 Data outputs Q0 to Q7 10 11 12 Read enable input 7 GND 8 RCK Read clock input 6 RRES Read reset input 5 RE MITSUBISHI <DIGITAL ASSP> M66258FP 8192 x 8-BIT LINE MEMORY Read control circuit Read address counter Write address counter Write control circuit MITSUBISHI <DIGITAL ASSP> M66258FP 8192 x 8-BIT LINE MEMORY ABSOLUTE MAXIMUM RATINGS (Ta=0 – 70 °C unless otherwise noted) Symbol Vcc VI VO Pd Tstg Parameter Supply voltage Input voltage Output voltage Power dispersion Storage temperature Conditions Value based on the GND pin Ta=25 °C Ratings Unit -0.5 – +6.0 -0.5 – VCC+0.5 -0.5 – VCC+0.5 825 -65 – 150 V V V mW °C RECOMMENDED OPERATING CONDITIONS Symbol Vcc GND Topr Parameter Supply voltage Supply voltage Operating temperature Min. 4.5 Limits Typ. 5.0 0 0 – 70 Max. 5.5 Unit V V °C ELECTRICAL CHARACTERISTICS (Ta=0 – 70 °C, Vcc=5V±10%, GND=0V unless otherwise noted) Symbol VIH VIL VOH VOL Parameter High-level input voltage Low-level input voltage High-level output voltage Low-level output voltage Conditions Min. 2.0 Limits Typ. Max. 0.55 V V V V 1.0 µA -1.0 µA 5.0 -5.0 µA µA 150 mA 10 15 pF pF 0.8 IOH = -4mA IOL = 4mA VCC-0.8 IIH High-level input current VI = VCC WE, WRES, WCK, RE, RRES, RCK, D0 – D7 IIL Low-level input current VI = GND WE, WRES, WCK, RE, RRES, RCK, D0 – D7 IOZH IOZL Off-state high-level output current Off-state low-level output current VO = VCC VO = GND ICC Average supply current during operation CI CO Input capacitance Off-time output capacitance VI = VCC, GND, output open tWCK, tRCK = 20ns f = 1MHz f = 1MHz Unit 3 MITSUBISHI <DIGITAL ASSP> M66258FP 8192 x 8-BIT LINE MEMORY SWITCHING CHARACTERISTICS (Ta=0 – 70 °C, Vcc=5V±10%, GND=0V unless otherwise noted) Symbol tAC tOH tOEN tODIS Parameter Access time Output hold time Output enable time Output disable time Min. Limits Typ. 3 3 3 Max. 16 16 16 Unit ns ns ns ns TIMING REQUIREMENTS (Ta=0 – 70 °C, Vcc=5V±10%, GND=0V unless otherwise noted) Symbol tWCK tWCKH tWCKL tRCK tRCKH tRCKL tDS tDH tRESS tRESH tNRESS tNRESH tWES tWEH tNWES tNWEH tRES tREH tNRES tNREH t r, t f tH Parameter Write clock (WCK) cycle Write clock (WCK) "H" pulse width Write clock (WCK) "L" pulse width Read clock (RCK) cycle Read clock (RCK) "H" pulse width Read clock (RCK) "L" pulse width Input data set up time for WCK Input data hold time for WCK Reset set up time for WCK/RCK Reset hold time for WCK/RCK Reset non-selection set up time for WCK/RCK Reset non-selection hold time for WCK/RCK WE set up time for WCK WE hold time for WCK WE non-selection set up time for WCK WE non-selection hold time for WCK RE set up time for RCK RE hold time for RCK RE non-selection set up time for RCK RE non-selection hold time for RCK Input pulse up/down time Data hold time (Note 1) Note 1: For 1 line access, the following conditions must be satisfied: WE high-level period ≤ 20 ms - 8192 • tWCK - WRES low-level period RE high-level period ≤ 20 ms - 8192 • tRCK - RRES low-level period 2: Perform reset operation after turning on power supply. 4 Min. 20 8 8 20 8 8 4 3 4 3 4 3 4 3 4 3 4 3 4 3 Limits Typ. Max. 20 20 Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ms MITSUBISHI <DIGITAL ASSP> M66258FP 8192 x 8-BIT LINE MEMORY SWITCHING CHARACTERISTICS MEASUREMENT CIRCUIT VCC RL=1KΩ SW1 Qn Qn SW2 CL = 30pF : tAC, tOH CL = 5pF : tOEN, tODIS RL=1KΩ Input pulse level Input pulse up/down time Judging voltage Input Output : 0 – 3V : 3 ns : 1.3V : 1.3V(However, tODIS(LZ) is judged with 10% of the output amplitude, while tODIS(HZ) is judged with 90% of the output amplitude.) Load capacitance CL includes the floating capacity of connected lines and input capacitance of probe. Item SW1 SW2 tODIS(LZ) Close Open tODIS(HZ) Open Close tOEN(ZL) Close Open tOEN(ZH) Open Close tODIS and tOEN measurement condition 3V RCK 1.3V 1.3V GND 3V RE GND tOEN(ZH) tODIS(HZ) VOH 90% Qn 1.3V tOEN(ZL) tODIS(LZ) Qn 1.3V 10% VOL 5 MITSUBISHI <DIGITAL ASSP> M66258FP 8192 x 8-BIT LINE MEMORY OPERATION TIMING • Write cycle n cycle n+1 cycle n+2 cycle Disable cycle n+3 cycle n+4 cycle WCK tWCK tWCKH tWCKL tWEH tNWES tNWEH tWES WE tDS tDH (n) Dn (n+1) (n+2) (n+3) (n+4) WRES = "H" • Write reset cycle n-1 cycle n cycle Reset cycle 0 cycle 1 cycle 2 cycle WCK tWCK tNRESH tRESS tRESH tNRESS WRES tDS tDH Dn (n-1) (n) (0) (1) WE = "L" 6 (2) MITSUBISHI <DIGITAL ASSP> M66258FP 8192 x 8-BIT LINE MEMORY • Matters that needs attetion when WCK stops n+1 cycle n cycle n cycle Disable cycle WCK tWCK tNWES WE Dn tDS tDH tDS tDH (n) (n) Period for writing data (n) into memory Period for writing data (n) into memory WRES = "H" Input data of n cycle is read at the rising edge after WCK of n cycle and writing operation starts in the WCK low-level period of n+1 cycle. The writing operation is complete at the falling edge after n+1 cycle. To stop reading write data at n cycle, enter WCK before the rising edge after n+1 cycle. When the cycle next to n cycle is a disable cycle, WCK for a cycle requires to be entered after the disable cycle as well. 7 MITSUBISHI <DIGITAL ASSP> M66258FP 8192 x 8-BIT LINE MEMORY • Read cycle n cycle n+1 cycle n+2 cycle Disable cycle n+3 cycle n+4 cycle RCK tRCKH tRCK tRCKL tREH tNREH tNRES tRES tAC RE tOEN tODIS (n) Qn (n+1) (n+2) HIGH-Z (n+3) (n+4) tOH RRES = "H" • Read reset cycle n-1 cycle n cycle Reset cycle tRCK tNRESH tRESS 0 cycle 1 cycle 2 cycle RCK tRESH tNRESS RRES tAC Qn (n-1) (n) (0) (0) (0) (1) tOH RE = "L" 8 (2) MITSUBISHI <DIGITAL ASSP> M66258FP 8192 x 8-BIT LINE MEMORY VARIABLE LENGTH DELAY BIT • 1 line (8192 bits) delay Input data can be written at the rising edge of WCK after write cycle and output data is read at the rising edge of RCK before read cycle to easily make 1 line delay. 1 cycle 0 cycle 2 cycle 8190 cycle 8191 cycle 8192 cycle 8193 cycle 8194 cycle (0') (1') (2') WCK RCK tRESS tRESH WRES RRES tDS tDH tDS tDH (0) Dn (1) (2) (8189) (8190) (8191) 8192 cycle (0') tAC (1') (2') (1) (2) (3') tOH (0) Qn (3) WE, RE = "L" • n-bit delay bit (Reset at cycles according to the delay length) 0 cycle 1 cycle n-2 cycle 2 cycle n-1 cycle n cycle (0') n+1 cycle (1') n+3 cycle (3') n+2 cycle (2') WCK RCK tRESS tRESH tRESS tRESH WRES RRES tDS tDH Dn (0) tDS tDH (1) (2) m cycle Qn (n-3) (n-2) (0') (n-1) tAC (1') (2') (1) (2) (3') tOH (0) (3) WE, RE = "L" m≥3 9 MITSUBISHI <DIGITAL ASSP> M66258FP 8192 x 8-BIT LINE MEMORY • n-bit delay 2 (Slides input timings of WRES and RRES at cycles according to the delay length.) 0 cycle 1 cycle 2 cycle n-2 cycle n-1 cycle n cycle n+1 cycle n+2 cycle n+3 cycle WCK RCK tRESS tRESH WRES tRESS tRESH RRES tDS tDH Dn tDS tDH (0) (1) (2) (n-2) (n-1) m cycle (n) tAC Qn (n+1) (n+2) (n+3) (1) (2) (3) tOH (0) WE, RE = "L" • n-bit delay 3 (Slides address by disabling RE in the period according to the delay length.) 0 cycle 1 cycle 2 cycle n-1 cycle n cycle n+1 cycle n+2 cycle n+3 cycle WCK RCK tRESS tRESH WRES RRES tNREH tRES RE tDS tDH tDS tDH Dn (0) (1) (2) m cycle Qn HIGH-Z (n-2) (n-1) (n) tAC (n+1) (n+2) (n+3) (1) (2) (3) tOH (0) WE, RE = "L" m≥3 10 MITSUBISHI <DIGITAL ASSP> M66258FP 8192 x 8-BIT LINE MEMORY • Reading shortest n-cycle write data "n" (Reading side n-1 cycle starts after the end of writing side n-1 cycle.) When the reading side n-1 cycle starts before the end of the writing side n+1 cycle, output Qn of n cycle is made invalid. In the following diagram, reading operation of n-1 cycle is invalid. n cycle n+1 cycle n+2 cycle n+3 cycle WCK Dn (n) (n+1) n-2 cycle (n+2) n-1 cycle (n+3) n cycle RCK Qn (n) invalid • Reading longest n-cycle write data "n": 1 line delay (When writing side n-cycle <2>* starts, reading side n cycle <1>* then starts.) Output Qn of n cycle <1>* can be read until the start of reading side n cycle <1> and the start of writing side n cycle <2>* overlap each other. n cycle <1>* n cycle <2>* 0 cycle <2>* WCK Dn (n-1)<1>* (n)<1>* n cycle <0>* (0)<2>* (n-1)<2>* 0 cycle <1>* (n)<2>* n cycle <1>* RCK Qn (n-1)<0>* (n)<0>* (0)<1>* (n-1)<1>* (n)<1>* <0>*, <1>* and <2>* indicate value of lines. 11 MITSUBISHI <DIGITAL ASSP> M66258FP 8192 x 8-BIT LINE MEMORY APPLICATION EXAMPLE Sub Scan Resolution Compensation Circuit with Laplacean Filter – D7 Q7 X2 Q0 – B (n+1) line image data D0 XK 2N-(A+B) Subtracter Adder 1 line delay M66258 – – D7 Q7 1 line delay A (n+1) line image data A+B Q0 Adder D0 Sub scan direction Main scan direction (n-1) line A X B n line (n+1) line N'=N+K { (N-A) + (N-B) } =N+K { (2N - (A+B) } K: Laplacean coefficient 12 N+K {2N-(A+B)} N n line image data M66258 Compensated image data