HD74LS74A Dual D-type Positive Edge-triggered Flip-Flops (with Preset and Clear) REJ03D0415–0300 Rev.3.00 Jul.22.2005 Features • Ordering Information Package Code (Previous Code) PRDP0014AB-B (DP-14AV) Part Name Package Type HD74LS74AP DILP-14 pin HD74LS74AFPEL SOP-14 pin (JEITA) HD74LS74ARPEL SOP-14 pin (JEDEC) PRSP0014DF-B (FP-14DAV) PRSP0014DE-A (FP-14DNV) Package Abbreviation Taping Abbreviation (Quantity) P — FP EL (2,000 pcs/reel) RP EL (2,500 pcs/reel) Note: Please consult the sales office for the above package availability. Pin Arrangement 1CLR 1 1D 2 1CK 3 1PR 4 1Q 5 D 1Q 6 CLR Q GND 7 CK D PR CLR Q Q CK PR Q (Top view) Rev.3.00, Jul.22.2005, page 1 of 7 14 VCC 13 2CLR 12 2D 11 2CK 10 2PR 9 2Q 8 2Q HD74LS74A Function Table Input Output Preset L Clear H Clock X D X Q H Q L H L L L X X X X L H* H H* H H H H ↑ ↑ H L H L L H H H L X Q0 Q0 H; high level, L; low level, X; irrelevant, ↑; transition from low to high level, Q0; level of Q before the indicated steady-state input conditions were established. Q0; complement of Q0 or level of Q before the indicated steady-state input conditions were established. *;This configuration is nonstable, that is, it will not persist when preset and clear inputs return to their inactive (high) level. Absolute Maximum Ratings Item Supply voltage Symbol VCC Ratings 7 Unit V VIN PT 7 400 V mW Tstg –65 to +150 °C Input voltage Power dissipation Storage temperature Note: Voltage value, unless otherwise noted, are with respect to network ground terminal. Recommended Operating Conditions Item Supply voltage Output current Operating temperature Clock frequency Symbol VCC Min 4.75 Typ 5.00 Max 5.25 Unit V IOH IOL — — — — –400 8 µA mA Topr fclock –20 0 25 — 75 25 °C MHz Pulse width Clock High Clear Preset tw tw 25 25 — — — — ns Setup time “H” Data “L” Data tsu tsu 20↑ 20↑ — — — — ns th 5↑ — — ns Hold time Note: ↑; The arrow indicates the rising edge. Rev.3.00, Jul.22.2005, page 2 of 7 HD74LS74A Electrical Characteristics (Ta = –20 to +75 °C) Item Input voltage Symbol VIH min. 2.0 typ.* — max. — Unit V VIL — — 0.8 V VOH 2.7 — — V VCC = 4.75 V, VIH = 2 V, VIL = 0.8 V, IOH = –400 µA VOL — — — — 0.5 0.4 V IOL = 8 mA IOL = 4 mA — — — — 20 40 — — — — 40 20 µA VCC = 5.25 V, VI = 2.7 V — — — — –0.4 –0.8 — — — — –0.8 –0.4 mA VCC = 5.25 V, VI = 0.4 V — — — — 0.1 0.2 — — — — 0.2 0.1 mA VCC = 5.25 V, VI = 7 V IOS –20 — –100 mA VCC = 5.25 V ICC** — 4 8 mA VCC = 5.25 V Output voltage D Clear Preset Clock Input current D Clear Preset Clock D Clear Preset Clock Short-circuit output current Supply current IIH IIL II Condition VCC = 4.75 V, VIL = 0.8 V, VIH = 2 V Input clamp voltage VIR — — –1.5 V VCC = 4.75 V, IIN = –18 mA Notes: * VCC = 5 V, Ta = 25°C ** With all output open, ICC is measured with the Q and Q outputs high in turn. At the time of measurement, the clock input is grounded. Switching Characteristics (VCC = 5 V, Ta = 25°C) Item Maximum clock frequency Propagation delay time Symbol fmax Inputs Outputs min. 25 typ. 33 max. Unit MHz tPLH tPHL Clear, Clock or Preset Q, Q — — 13 25 25 40 ns ns Condition CL = 15 pF, RL = 2 kΩ Timing Definition tw 3V 1.3 V 1.3 V 1.3 V Clock tsu th tsu 0V th 3V 1.3 V 1.3 V 1.3 V Data 0V "H" Data Rev.3.00, Jul.22.2005, page 3 of 7 "L" Data HD74LS74A Testing Method Test Circuit 1. ƒmax, tPLH, tPHL (Clock→Q, Q) 4.5V VCC Output Q Input RL PR P.G. Zout = 50Ω D Q Input CL Output Q P.G. Zout = 50Ω Notes: Load circuit 1 CK CLR Q Same as Load Circuit 1. 1. Test is put into the each flip-flop. 2. CL includes probe and jig capacitance. 3. All diodes are 1S2074(H). 2. tPHL, tPLH (Clear or Preset→ Q, Q) VCC Input Output Q P.G. Zout = 50Ω RL Load circuit 1 PR D Q CL Output Q Input CK CLR Q P.G. Zout = 50Ω Notes: 1. Test is put into the each flip-flop. 2. CL includes probe and jig capacitance. 3. All diodes are 1S2074(H). Rev.3.00, Jul.22.2005, page 4 of 7 Same as Load Circuit 1. HD74LS74A Waveforms 1 tTLH tTHL tw(L) 90% 90% 1.3 V 1.3 V Clock 3V 1.3 V 10% 10% 0V tw(H) 3V D 0V tPLH tPHL VOH 1.3 V Q 1.3 V tPHL VOL tPLH Q VOH 1.3 V 1.3 V VOL Note: Clock input pulse; tTLH ≤ 15 ns, tTHL ≤ 6 ns, PRR = 1 MHz, duty cycle = 50% and for fmax, tTLH = tTHL ≤ 2.5 ns Waveforms 2 tTHL Clear tTLH 90% 1.3V 10% 3V 90% 1.3V 10% tw (clear) ≥ 25ns 0V tTHL tTLH 90% 1.3V 10% Preset 90% 1.3V 10% tw (preset) ≥ 25ns tPLH tPHL 1.3V Q 3V 0V VOH 1.3V tPLH VOL VOH Q Note: 1.3V 1.3V tPHL Crear and presel input pulse; tTLH ≤ 15 ns, tTHL ≤ 6 ns, PRR = 1 MHz, Rev.3.00, Jul.22.2005, page 5 of 7 VOL HD74LS74A Package Dimensions JEITA Package Code P-DIP14-6.3x19.2-2.54 RENESAS Code PRDP0014AB-B Previous Code DP-14AV MASS[Typ.] 0.97g D 8 E 14 1 7 b3 Z A1 A Reference Symbol Nom e1 7.62 D 19.2 E 6.3 L θ A1 0.51 bp 0.40 e1 0.48 c 0.19 θ 0° JEITA Package Code P-SOP14-5.5x10.06-1.27 RENESAS Code PRSP0014DF-B *1 Previous Code FP-14DAV D 0.56 e 2.29 0.31 2.54 2.79 15° 2.39 L 2.54 MASS[Typ.] 0.23g NOTE) 1. DIMENSIONS"*1 (Nom)"AND"*2" DO NOT INCLUDE MOLD FLASH. 2. DIMENSION"*3"DOES NOT INCLUDE TRIM OFFSET. F 14 7.4 0.25 Z ( Ni/Pd/Au plating ) 20.32 1.30 b3 c Max 5.06 A bp e Dimension in Millimeters Min 8 c HE *2 E bp Index mark Reference Symbol Terminal cross section ( Ni/Pd/Au plating ) 1 Z *3 Nom Max D 10.06 10.5 E 5.50 A2 7 e A1 bp Dimension in Millimeters Min x M 0.00 0.10 0.20 0.34 0.40 0.46 0.15 0.20 0.25 7.80 8.00 2.20 A L1 bp b1 c A c A1 θ y L Detail F 1 θ 0° HE 7.50 1.27 e x 0.12 y 0.15 Z 1.42 0.50 L L Rev.3.00, Jul.22.2005, page 6 of 7 8° 1 0.70 1.15 0.90 HD74LS74A JEITA Package Code P-SOP14-3.95x8.65-1.27 RENESAS Code PRSP0014DE-A *1 MASS[Typ.] 0.13g Previous Code FP-14DNV NOTE) 1. DIMENSIONS"*1 (Nom)"AND"*2" DO NOT INCLUDE MOLD FLASH. 2. DIMENSION"*3"DOES NOT INCLUDE TRIM OFFSET. F D 14 8 c *2 Index mark HE E bp Reference Symbol Terminal cross section ( Ni/Pd/Au plating ) Dimension in Millimeters Min Nom Max D 8.65 9.05 E 3.95 A2 A1 7 1 Z e *3 bp 0.10 0.14 A x M bp L1 0.25 1.75 0.34 0.40 0.46 0.15 0.20 0.25 6.10 6.20 b1 c A c1 A1 θ L y Detail F θ 0° HE 5.80 1.27 e x 0.25 y 0.15 0.635 Z L L Rev.3.00, Jul.22.2005, page 7 of 7 8° 0.40 1 0.60 1.08 1.27 Sales Strategic Planning Div. Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100-0004, Japan Keep safety first in your circuit designs! 1. Renesas Technology Corp. puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble may occur with them. Trouble with semiconductors may lead to personal injury, fire or property damage. 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