IS61WV3216DBLL/DBLS IS64WV3216DBLL/DBLS 32K x 16 HIGH SPEED ASYNCHRONOUS CMOS STATIC RAM FEATURES APRIL 2015 DESCRIPTION HIGHSPEED:(IS61/64WV3216DBLL) • High-speed access time: 8, 10, 12, 20 ns • Low Active Power: 135 mW (typical) • Low Standby Power: 12 µW (typical) CMOS standby LOWPOWER:(IS61/64WV3216DBLS) • High-speed access time: 25, 35 ns • Low Active Power: 55 mW (typical) • Low Standby Power: 12 µW (typical) CMOS standby • Singlepowersupply —Vdd2.4Vto3.6V 32,768 words by 16 bits. It is fabricated using ISSI's highperformance CMOS technology.This highly reliable process coupled with innovative circuit design techniques, yields high-performance and low power consumption devices. When CE is HIGH (deselected), the device assumes a standby mode at which the power dissipation can be reduced down with CMOS input levels. • Fully static operation: no clock or refresh required • Three state outputs • Data control for upper and lower bytes • Industrial and Automotive temperature support • Lead-free available Easy memory expansion is provided by using Chip Enable and Output Enable inputs, CE and OE. The active LOW Write Enable (WE) controls both writing and reading of the memory. A data byte allows Upper Byte (UB) and Lower Byte (LB) access. TheIS61WV3216DBLxandIS64WV3216DBLxare packagedintheJEDECstandard44-pinTSOPTypeII and48-pinMiniBGA(6mmx8mm). FUNCTIONAL BLOCK DIAGRAM A0-A14 DECODER 32K x 16 MEMORY ARRAY I/O DATA CIRCUIT COLUMN I/O VDD GND I/O0-I/O7 Lower Byte I/O8-I/O15 Upper Byte CE OE WE UB LB CONTROL CIRCUIT Integrated Silicon Solution, Inc. does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can reasonably be expected to cause failure of the life support system or to significantly affect its safety or effectiveness. Products are not authorized for use in such applications unless Integrated Silicon Solution, Inc. receives written assurance to its satisfaction, that: a.) the risk of injury or damage has been minimized; b.) the user assume all such risks; and c.) potential liability of Integrated Silicon Solution, Inc is adequately protected under the circumstances Integrated Silicon Solution, Inc. — www.issi.com Rev. B 04/08/2015 1 IS61WV3216DBLL/DBLS IS64WV3216DBLL/DBLS TRUTH TABLE Mode Not Selected Output Disabled Read Write WE X H X H H H L L L CE H L L L L L L L L OE X H X L L L X X X LB X X H L H L L H L I/O PIN UB I/O0-I/O7 I/O8-I/O15 X High-Z High-Z X High-Z High-Z H High-Z High-Z H Dout High-Z L High-Z Dout LDoutDout H Din High-Z L High-Z Din LDinDin Vdd Current Isb1, Isb2 Icc Icc Icc PIN CONFIGURATIONS 44-Pin TSOP-II NC A14 A13 A12 A11 CE I/O0 I/O1 I/O2 I/O3 VDD GND I/O4 I/O5 I/O6 I/O7 WE A10 A9 A8 A7 NC 2 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 PIN DESCRIPTIONS 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 A0 A1 A2 OE UB LB I/O15 I/O14 I/O13 I/O12 GND VDD I/O11 I/O10 I/O9 I/O8 NC A3 A4 A5 A6 NC A0-A14 I/O0-I/O15 CE OE WE LB UB NC Vdd GND Address Inputs Data Inputs/Outputs Chip Enable Input Output Enable Input Write Enable Input Lower-byte Control (I/O0-I/O7) Upper-byte Control (I/O8-I/O15) No Connection Power Ground Integrated Silicon Solution, Inc. — www.issi.com Rev. B 04/08/2015 IS61WV3216DBLL/DBLS IS64WV3216DBLL/DBLS PIN CONFIGURATIONS 48-Pin mini BGA (6mm x 8mm) 1 2 3 4 5 6 A LB OE A0 A1 A2 NC B I/O8 UB A3 A4 CE I/O0 C I/O9 I/O10 A5 A6 I/O1 I/O2 D GND I/O11 NC A7 I/O3 VDD E VDD I/O12 NC NC I/O4 GND F I/O14 I/O13 A14 NC I/O5 I/O6 G I/O15 NC A12 A13 WE I/O7 H NC A8 A9 A10 A11 NC PIN DESCRIPTIONS A0-A14 I/O0-I/O15 CE OE WE LB UB NC Vdd GND Address Inputs Data Inputs/Outputs Chip Enable Input Output Enable Input Write Enable Input Lower-byte Control (I/O0-I/O7) Upper-byte Control (I/O8-I/O15) No Connection Power Ground Integrated Silicon Solution, Inc. — www.issi.com Rev. B 04/08/2015 3 IS61WV3216DBLL/DBLS IS64WV3216DBLL/DBLS DC ELECTRICAL CHARACTERISTICS (Over Operating Range) Vdd = 3.3V + 5% Symbol Voh Vol Vih Vil Ili Ilo Parameter Output HIGH Voltage Output LOW Voltage Input HIGH Voltage Input LOW Voltage(1) Input Leakage Output Leakage Test Conditions Vdd = Min., Ioh = –4.0 mA Vdd = Min., Iol = 8.0 mA GND ≤ Vin ≤ Vdd GND ≤ Vout ≤ Vdd, Outputs Disabled Min. 2.4 — 2 –0.3 –1 –1 Max. — 0.4 Vdd + 0.3 0.8 1 1 Unit V V V V µA µA Max. — 0.4 Vdd + 0.3 0.8 1 1 Unit V V V V µA µA Note: 1. Vil (min.) = –0.3V DC; Vil (min.) = –2.0V AC (pulse width < 10 ns). Not 100% tested. Vih (max.) = Vdd + 0.3V DC; Vih (max.) = Vdd + 2.0V AC (pulse width < 10 ns). Not 100% tested. DC ELECTRICAL CHARACTERISTICS (Over Operating Range) Vdd = 2.4V-3.6V Symbol Voh Vol Vih Vil Ili Ilo Parameter Output HIGH Voltage Output LOW Voltage Input HIGH Voltage Input LOW Voltage(1) Input Leakage Output Leakage Test Conditions Vdd = Min., Ioh = –1.0 mA Vdd = Min., Iol = 1.0 mA GND ≤ Vin ≤ Vdd GND ≤ Vout ≤ Vdd, Outputs Disabled Min. 1.8 — 2.0 –0.3 –1 –1 Note: 1. Vil (min.) = –0.3V DC; Vil (min.) = –2.0V AC (pulse width < 10 ns). Not 100% tested. Vih (max.) = Vdd + 0.3V DC; Vih (max.) = Vdd + 2.0V AC (pulse width < 10 ns). Not 100% tested. 4 Integrated Silicon Solution, Inc. — www.issi.com Rev. B 04/08/2015 IS61WV3216DBLL/DBLS IS64WV3216DBLL/DBLS AC TEST CONDITIONS Parameter Input Pulse Level Input Rise and Fall Times Input and Output Timing and Reference Level (VRef) Output Load R1 ( Ω ) R2 ( Ω ) Vtm (V) Unit (2.4V-3.6V) 0.4V to Vdd - 0.3V 1V/ ns VDD /2 See Figures 1 and 2 1909 1105 3.0V Unit (3.3V + 5%) 0.4V to Vdd - 0.3V 1V/ ns VDD + 0.05 2 See Figures 1 and 2 317 351 3.3V AC TEST LOADS R1 ZO = 50Ω VTM 50Ω VDD/2 OUTPUT 30 pF Including jig and scope Figure 1. Integrated Silicon Solution, Inc. — www.issi.com Rev. B 04/08/2015 OUTPUT 5 pF Including jig and scope R2 Figure 2. 5 IS61WV3216DBLL/DBLS IS64WV3216DBLL/DBLS ABSOLUTE MAXIMUM RATINGS(1) Symbol Vterm Vdd Tstg Pt Parameter Terminal Voltage with Respect to GND Vdd Relates to GND Storage Temperature Power Dissipation Value –0.5 to Vdd + 0.5 –0.3 to 4.0 –65 to +150 1.0 Unit V V °C W Notes: 1. Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. CAPACITANCE(1,2) Symbol Cin CI/O Parameter Input Capacitance Input/Output Capacitance Conditions Vin = 0V Vout = 0V Max. 6 8 Unit pF pF Notes: 1. Tested initially and after any design or process changes that may affect these parameters. 2. Test conditions: Ta = 25°C, f = 1 MHz, Vdd = 3.3V. 6 Integrated Silicon Solution, Inc. — www.issi.com Rev. B 04/08/2015 IS61WV3216DBLL/DBLS IS64WV3216DBLL/DBLS HIGH SPEED (IS61/64WV3216DBLL) OPERATING RANGE OPERATING RANGE (Vdd) (IS61WV3216DBLL)(1) Range Ambient Temperature Commercial 0°C to +70°C Industrial –40°C to +85°C Vdd (8 ns)1 3.3V + 5% 3.3V + 5% Vdd (10 ns)1 2.4V-3.6V 2.4V-3.6V Note: 1. When operated in the range of 2.4V-3.6V, the device meets 10ns. When operated in the range of 3.3V + 5%, the device meets 8ns. OPERATING RANGE (Vdd) (IS64WV3216DBLL) Range Ambient Temperature Automotive –40°C to +125°C Vdd (10 ns) 2.4V-3.6V POWER SUPPLY CHARACTERISTICS(1) (Over Operating Range) Symbol Parameter Test Conditions Icc Vdd Dynamic Operating Vdd = Max., Com. Supply Current Iout = 0 mA, f = fmax Ind. CE = Vil Auto.(3) Vin ≥ Vdd – 0.3V, or typ.(2) Vin ≤ 0.4V Isb2 CMOS Standby Vdd = Max., Com. Current (CMOS Inputs) CE ≥ Vdd – 0.2V, Ind. Vin ≥ Vdd – 0.2V, or Auto. Vin ≤ 0.2V, f = 0 typ.(2) -8 Min. Max. — 65 — 70 — — 45 -10 Min. Max. — 50 — 55 — 65 45 -12 Min. Max. — 45 — 50 — 55 45 -20 Min. Max. — 40 — 45 — 50 — 40 — 55 — — 4 — 40 — 55 — 90 4 — 40 — 55 — 90 4 — 40 — 55 — 90 Unit mA µA Note: 1. At f = fmax, address and data inputs are cycling at the maximum frequency, f = 0 means no input lines change. 2. Typical values are measured at Vdd = 3.0V, Ta = 25oC and not 100% tested. 3. For Automotive grade at 15ns, typ. Icc = 38mA, not 100% tested. Integrated Silicon Solution, Inc. — www.issi.com Rev. B 04/08/2015 7 IS61WV3216DBLL/DBLS IS64WV3216DBLL/DBLS LOW POWER (IS61/64WV3216DBLS) OPERATING RANGE OPERATING RANGE (Vdd) (IS61WV3216DBLS) Range Ambient Temperature Commercial 0°C to +70°C Industrial –40°C to +85°C Vdd (35 ns) 2.4V-3.6V 2.4V-3.6V OPERATING RANGE (Vdd) (IS64WV3216DBLS) Range Ambient Temperature Automotive –40°C to +125°C Vdd (35 ns) 2.4V-3.6V POWER SUPPLY CHARACTERISTICS(1) (Over Operating Range) Symbol Parameter Icc Vdd Dynamic Operating Supply Current Isb2 CMOS Standby Current (CMOS Inputs) -25 Test Conditions Min. Max. Vdd = Max., Com. — 20 Iout = 0 mA, f = fmax Ind. — 25 CE = Vil Auto. — 40 Vin ≥ Vdd – 0.3V, or typ.(2) 18 Vin ≤ 0.4V Vdd = Max., Com. — 40 CE ≥ Vdd – 0.2V, Ind. — 50 Vin ≥ Vdd – 0.2V, or Auto. — 75 Vin ≤ 0.2V, f = 0 typ.(2) 4 -35 Min. Max. — 20 — 25 — 35 — — — 40 50 75 Unit mA µA Note: 1. At f = fmax, address and data inputs are cycling at the maximum frequency, f = 0 means no input lines change. 2. Typical values are measured at Vdd = 3.0V, Ta = 25oC and not 100% tested. 8 Integrated Silicon Solution, Inc. — www.issi.com Rev. B 04/08/2015 IS61WV3216DBLL/DBLS IS64WV3216DBLL/DBLS READ CYCLE SWITCHING CHARACTERISTICS for IS61/64WV3216DBLL(1) (OverOperatingRange) Symbol trc taa toha tace tdoe thzoe(2) tlzoe(2) thzce(2 tlzce(2) tba thzb(2) tlzb(2) tpu tpd Parameter Read Cycle Time Address Access Time Output Hold Time CE Access Time OE Access Time OE to High-Z Output OE to Low-Z Output CE to High-Z Output CE to Low-Z Output LB, UB Access Time LB, UB to High-Z Output LB, UB to Low-Z Output Power Up Time Power Down Time -8 Min. Max. 8 — — 8 2.0 — — 8 — 5.5 — 3 0 — 0 3 3 — — 5.5 0 5.5 0 — 0 — — 8 -10 Min. Max. 10 — — 10 2.0 — — 10 — 6.5 — 4 0 — 0 4 3 — — 6.5 0 6.5 0 — 0 — — 10 -12 Min. Max. 12 — — 12 3 — — 12 — 6.5 — 6 0 — 0 6 3 — — 6.5 0 6.5 0 — 0 — — 10 Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns Notes: 1. Test conditions and output loading conditions are specified in the AC Test Conditions and ACTest Loads (Figure 1) 2. Tested with the load in Figure 2. Transition is measured ±500 mV from steady-state voltage. Integrated Silicon Solution, Inc. — www.issi.com Rev. B 04/08/2015 9 IS61WV3216DBLL/DBLS IS64WV3216DBLL/DBLS READ CYCLE SWITCHING CHARACTERISTICS for IS61/64WV3216DBLS(1) (OverOperatingRange) Symbol trc taa toha tace tdoe thzoe(2) tlzoe(2) thzce(2 tlzce(2) Parameter Read Cycle Time Address Access Time Output Hold Time CE Access Time OE Access Time OE to High-Z Output OE to Low-Z Output CE to High-Z Output CE to Low-Z Output tba thzb tlzb LB, UB Access Time LB, UB to High-Z Output LB, UB to Low-Z Output -20 ns -25 ns Min. Max. Min. Max. 20 — 25 — — 20 — 25 2.5 — 6 — — 20 — 25 — 8 — 12 0 8 0 8 0 — 0 — 0 8 0 8 3 — 10 — — 8 0 8 0 — — 0 0 25 8 — -35 ns Min.Max. 35 — — 35 8 — — 35 — 15 0 10 0 — 0 10 10 — — 0 0 35 10 — Unit ns ns ns ns ns ns ns ns ns ns ns ns Notes: 1. Test conditions and output loading conditions are specified in the AC Test Conditions and ACTest Loads (Figure 1) 2. TestedwiththeloadinFigure2.Transitionismeasured±500mVfromsteady-statevoltage.Not100%tested. 3. Not 100% tested. 10 Integrated Silicon Solution, Inc. — www.issi.com Rev. B 04/08/2015 IS61WV3216DBLL/DBLS IS64WV3216DBLL/DBLS AC WAVEFORMS READ CYCLE NO. 1(1,2) (Address Controlled) (CE = OE = Vil, UB and/or LB = Vil) t RC ADDRESS t OHA DOUT t AA t OHA DATA VALID PREVIOUS DATA VALID READ1.eps READ CYCLE NO. 2(1,3) tRC ADDRESS tAA tOHA OE tHZOE tDOE tLZOE CE tACE tLZCE tHZCE LB, UB DOUT VDD Supply Current HIGH-Z tBA tLZB tHZB tRC DATA VALID tPU 50% tPD 50% ICC ISB UB_CEDR2.eps Notes: 1. WE is HIGH for a Read Cycle. 2. The device is continuously selected. OE, CE, UB and/or LB = Vil. 3. Address is valid prior to or coincident with CE LOW transition. Integrated Silicon Solution, Inc. — www.issi.com Rev. B 04/08/2015 11 IS61WV3216DBLL/DBLS IS64WV3216DBLL/DBLS WRITE CYCLE SWITCHING CHARACTERISTICS for IS61/64WV3216DBLL(1,3) (OverOperatingRange) Symbol twc tsce taw tha tsa tpwb tpwe1 tpwe2 tsd thd thzwe(2) tlzwe(2) Parameter Write Cycle Time CE to Write End Address Setup Time to Write End Address Hold from Write End Address Setup Time LB, UB Valid to End of Write WE Pulse Width WE Pulse Width (OE = LOW) Data Setup to Write End Data Hold from Write End WE LOW to High-Z Output WE HIGH to Low-Z Output -8 Min. Max. 8 — 6.5 — 6.5 — 0 0 6.5 6.5 8.0 5 0 — 2 — — — — — — — 3.5 — -10 Min. Max. 10 — 8 — 8 — 0 0 8 8 10 6 0 — 2 — — — — — — — 5 — -12 Min. Max. 12 — 9 — 9 — 0 0 9 9 11 9 0 — 3 — — — — — — — 6 — Unit ns ns ns ns ns ns ns ns ns ns ns ns Notes: 1. Test conditions and output loading conditions are specified in the AC Test Conditions and ACTest Loads (Figure 1) 2. Tested with the load in Figure 2. Transition is measured ±500 mV from steady-state voltage. Not 100% tested. 3. The internal write time is defined by the overlap of CE LOW and UB or LB, and WE LOW. All signals must be in valid states to initiate a Write, but any one can go inactive to terminate the Write. The Data Input Setup and Hold timing are referenced to the rising or falling edge of the signal that terminates the write. Shaded area product in development 12 Integrated Silicon Solution, Inc. — www.issi.com Rev. B 04/08/2015 IS61WV3216DBLL/DBLS IS64WV3216DBLL/DBLS WRITE CYCLE SWITCHING CHARACTERISTICS for IS61/64WV3216DBLS(1,2) (OverOperatingRange) -20 ns Symbol Parameter Min. Max. twc Write Cycle Time 20 — tsce CE to Write End 12 — taw Address Setup Time 12 — to Write End tha Address Hold from Write End 0 — tsa Address Setup Time 0 — tpwb LB, UB Valid to End of Write 12 — tpwe1 WE Pulse Width (OE = HIGH) 12 — tpwe2 WE Pulse Width (OE = LOW) 17 — tsd Data Setup to Write End 9 — thd Data Hold from Write End 0 — (3) thzwe WE LOW to High-Z Output — 9 tlzwe(3) WE HIGH to Low-Z Output 3 — -25 ns Min. Max. 25 — 18 — 15 — 0 0 18 18 20 12 0 — 5 — — — — — — — 12 — -35 ns Min.Max. 35 — 25 — 25 — 0 0 30 30 30 15 0 — 5 Unit ns ns ns — — — — — — — 20 — ns ns ns ns ns ns ns ns ns Notes: 1. Test conditionsandoutput loading conditions are specified in the AC Test Conditions and ACTest Loads (Figure 1) 2. TestedwiththeloadinFigure2.Transitionismeasured±500mVfromsteady-statevoltage.Not100%tested. 3. The internal write time is defined by the overlap of CE LOW and UB or LB, and WE LOW. All signals must be in valid states to initiate a Write, but any one can go inactive to terminate the Write. The Data Input Setup and Hold timing are referenced to the rising or falling edge of the signal that terminates the write. Integrated Silicon Solution, Inc. — www.issi.com Rev. B 04/08/2015 13 IS61WV3216DBLL/DBLS IS64WV3216DBLL/DBLS AC WAVEFORMS WRITE CYCLE NO. 1 (CE Controlled, OE is HIGH or LOW) (1 ) t WC VALID ADDRESS ADDRESS t SA t SCE t HA CE t AW t PWE1 t PWE2 WE t PWB UB, LB t HZWE DOUT t LZWE HIGH-Z DATA UNDEFINED t SD t HD DATAIN VALID DIN UB_CEWR1.eps Notes: 1. WRITE is an internally generated signal asserted during an overlap of the LOW states on the CE and WE inputs and at least one of the LB and UB inputs being in the LOW state. 2. WRITE = (CE) [ (LB) = (UB) ] (WE). WRITE CYCLE NO. 2 (WE Controlled. OE is HIGH During Write Cycle) (1,2) t WC ADDRESS VALID ADDRESS t HA OE CE LOW t AW t PWE1 WE t SA t PWB UB, LB t HZWE DOUT DATA UNDEFINED t LZWE HIGH-Z t SD DIN t HD DATAIN VALID UB_CEWR2.eps 14 Integrated Silicon Solution, Inc. — www.issi.com Rev. B 04/08/2015 IS61WV3216DBLL/DBLS IS64WV3216DBLL/DBLS AC WAVEFORMS WRITE CYCLE NO. 3 (WE Controlled. OE is LOW During Write Cycle) (1) t WC ADDRESS VALID ADDRESS OE LOW CE LOW t HA t AW t PWE2 WE t SA t PWB UB, LB t HZWE DOUT t LZWE HIGH-Z DATA UNDEFINED t SD t HD DATAIN VALID DIN UB_CEWR3.eps WRITE CYCLE NO. 4 (LB, UB Controlled, Back-to-Back Write) (1,3) t WC ADDRESS t WC ADDRESS 1 ADDRESS 2 OE t SA CE LOW t HA t SA WE UB, LB t HA t PWB t PWB WORD 1 WORD 2 t HZWE DOUT t LZWE HIGH-Z DATA UNDEFINED t HD t SD DIN DATAIN VALID t HD t SD DATAIN VALID UB_CEWR4.eps Notes: 1. The internal Write time is defined by the overlap of CE = LOW, UB and/or LB = LOW, and WE = LOW. All signals must be in valid states to initiate a Write, but any can be deasserted to terminate the Write. The t sa, t ha, t sd, and t hd timing is referenced to the rising or falling edge of the signal that terminates the Write. 2. Tested with OE HIGH for a minimum of 4 ns before WE = LOW to place the I/O in a HIGH-Z state. 3. WE may be held LOW across many address cycles and the LB, UB pins can be used to control the Write function. Integrated Silicon Solution, Inc. — www.issi.com Rev. B 04/08/2015 15 IS61WV3216DBLL/DBLS IS64WV3216DBLL/DBLS HIGH SPEED (IS61WV3216DBLL) DATA RETENTION SWITCHING CHARACTERISTICS (2.4V-3.6V) Symbol Vdr Idr Parameter Vdd for Data Retention Data Retention Current Test Condition See Data Retention Waveform Vdd = 2.0V, CE ≥ Vdd – 0.2V tsdr trdr Data Retention Setup Time See Data Retention Waveform Recovery Time See Data Retention Waveform Options Com. Ind. Auto. Min. 2.0 — — Typ.(1) — 4 — 0 — — trc Max. 3.6 40 55 90 — — Unit V µA ns ns Note 1: Typical values are measured at Vdd = 3.0V, Ta = 25 C and not 100% tested. o DATA RETENTION WAVEFORM (CE Controlled) tSDR Data Retention Mode tRDR VDD VDR CE GND 16 CE ≥ VDD - 0.2V Integrated Silicon Solution, Inc. — www.issi.com Rev. B 04/08/2015 IS61WV3216DBLL/DBLS IS64WV3216DBLL/DBLS LOW POWER (IS61WV3216DBLS) DATA RETENTION SWITCHING CHARACTERISTICS (2.4V-3.6V) Symbol Vdr Idr Parameter Vdd for Data Retention Data Retention Current Test Condition See Data Retention Waveform Vdd = 2.0V, CE ≥ Vdd – 0.2V tsdr trdr Data Retention Setup Time See Data Retention Waveform Recovery Time See Data Retention Waveform Options Com. Ind. Auto. Min. 2.0 — — Typ.(1) — 4 — 0 — — trc Max. 3.6 40 50 75 — — Unit V µA ns ns Note 1: Typical values are measured at Vdd = 3.0V, Ta = 25 C and not 100% tested. o DATA RETENTION WAVEFORM (CE Controlled) tSDR Data Retention Mode tRDR VDD VDR CE GND Integrated Silicon Solution, Inc. — www.issi.com Rev. B 04/08/2015 CE ≥ VDD - 0.2V 17 IS61WV3216DBLL/DBLS IS64WV3216DBLL/DBLS ORDERING INFORMATION (HIGH SPEED) Industrial Range: -40°C to +85°C Voltage Range: 2.4V to 3.6V Speed (ns) 8 10 Order Part No. IS61WV3216DBLL-8BI IS61WV3216DBLL-8BLI IS61WV3216DBLL-8TI IS61WV3216DBLL-8TLI IS61WV3216DBLL-10BI IS61WV3216DBLL-10BLI IS61WV3216DBLL-10TI IS61WV3216DBLL-10TLI Package 48 mini BGA (6mm x 8mm) 48 mini BGA (6mm x 8mm), Lead-free TSOP (Type II) TSOP (Type II), Lead-free 48 mini BGA (6mm x 8mm) 48 mini BGA (6mm x 8mm), Lead-free TSOP (Type II) TSOP (Type II), Lead-free Automotive Range: -40°C to +125°C Voltage Range: 2.4V to 3.6V Speed (ns) 10 Order Part No. IS64WV3216DBLL-10BA3 IS64WV3216DBLL-10BLA3 IS64WV3216DBLL-10CTA3 IS64WV3216DBLL-10CTLA3 Package 48 mini BGA (6mm x 8mm) 48 mini BGA (6mm x 8mm), Lead-free TSOP (Type II), Copper Leadframe TSOP (Type II), Lead-free, Copper Leadframe ORDERING INFORMATION (LOW POWER - IN EVALUATION) Industrial Range: -40°C to +85°C Voltage Range: 2.4V to 3.6V Speed (ns) 35 18 Order Part No. Package IS61WV3216DBLS-35TLI TSOP (Type II), Lead-free Integrated Silicon Solution, Inc. — www.issi.com Rev. B 04/08/2015 Integrated Silicon Solution, Inc. — www.issi.com Rev. B 04/08/2015 Θ Package Outline 06/04/2008 3. DIMENSION b DOES NOT INCLUDE DAMBAR PROTRUSION/INTRUSION. 2. DIMENSION D AND E1 DO NOT INCLUDE MOLD PROTRUSION. 1. CONTROLLING DIMENSION : MM NOTE : Θ IS61WV3216DBLL/DBLS IS64WV3216DBLL/DBLS 1 2 3 4 5 6 7 8 9 10 11 12 19 20 08/12/2008 Package Outline 1. CONTROLLING DIMENSION : MM . 2. Reference document : JEDEC MO-207 NOTE : IS61WV3216DBLL/DBLS IS64WV3216DBLL/DBLS Integrated Silicon Solution, Inc. — www.issi.com Rev. B 04/08/2015