ISSI IS63WV1288DALL

IS63WV1288DALL/DALS
IS63WV1288DBLL/DBLS
IS64WV1288DBLL/DBLS
128K x 8 HIGH-SPEED CMOS STATIC RAM
FEATURES
HIGH SPEED: (IS63/64WV1288DALL/DBLL)
• High-speed access time: 8, 10, 12, 20 ns
• Low Active Power: 135 mW (typical)
• Low Standby Power: 12 µW (typical)
CMOS standby
LOW POWER: (IS63/64WV1288DALS/DBLS)
• High-speed access time: 25, 35 ns
• Low Active Power: 55 mW (typical)
• Low Standby Power: 12 µW (typical)
CMOS standby
• Single power supply
— Vdd 1.65V to 2.2V (IS63WV1288DAxx)
— Vdd 2.4V to 3.6V (IS63/64WV1288DBxx)
• Multiple center power and ground pins for
greater noise immunity
• Easy memory expansion with CE and OE options
• CE power-down
• Fully static operation: no clock or refresh required
• TTL compatible inputs and outputs
• Lead-free available
DECEMBER 2011
DESCRIPTION
The ISSI IS63/64WV1288Dxxx is a very high-speed,
low power, 131,072-word by 8-bit CMOS static RAM.
The IS63/64WV1288DBLL is fabricated using ISSI's
high-performance CMOS technology. This highly reliable
process coupled with innovative circuit design techniques, yields higher performance and low power
consumption devices.
When CE is HIGH (deselected), the device assumes a
standby mode at which the power dissipation can be reduced down to 25 µW (typical) with CMOS input levels.
The IS63/64WV1288DBLL operates from a single Vdd
power supply. The IS63/64WV1288Dxxx is available in
32-pin TSOP (Type II), 32-pin sTSOP (Type I), 48-Ball
miniBGA (6mm x 8mm), 32-pin SOJ (400-mil) and 32pin SOJ (300-mil) packages.
FUNCTIONAL BLOCK DIAGRAM
A0-A16
DECODER
128K X 8
MEMORY ARRAY
VDD
GND
I/O
DATA
CIRCUIT
I/O0-I/O7
CE
OE
COLUMN I/O
CONTROL
CIRCUIT
WE
Copyright © 2011 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without notice. ISSI
assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the latest version of this device
specification before relying on any published information and before placing orders for products.
Integrated Silicon Solution, Inc. does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can reasonably be expected to cause failure of the life support system or to significantly affect its safety or effectiveness. Products are not authorized for use in such applications unless Integrated Silicon
Solution, Inc. receives written assurance to its satisfaction, that:
a.) the risk of injury or damage has been minimized;
b.) the user assume all such risks; and
c.) potential liability of Integrated Silicon Solution, Inc is adequately protected under the circumstances
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 Rev. B
12/15/2011
1
IS63WV1288DALL/DALS
IS63WV1288DBLL/DBLS
IS64WV1288DBLL/DBLS
PIN CONFIGURATION
PIN CONFIGURATION
32-Pin SOJ
32-Pin TSOP (Type II) (T)
32-Pin sTSOP (Type I) (H)
A0
1
32
A16
A1
2
31
A15
A2
3
30
A14
A3
4
29
A13
CE
5
28
OE
I/O0
6
27
I/O7
I/O1
7
26
I/O6
VDD
8
25
GND
GND
9
24
VDD
I/O2
10
23
I/O5
I/O3
11
22
I/O4
WE
12
21
A12
A4
13
20
A11
A5
14
19
A10
A6
15
18
A9
A7
16
17
A8
PIN DESCRIPTIONS
A0-A16 CE OE WE I/O0-I/O7
Vdd
GND
2
Address Inputs
Chip Enable Input
Output Enable Input
Write Enable Input
Bidirectional Ports
Power
Ground
A0
A1
A2
A3
CE
I/O0
I/O1
VDD
GND
I/O2
I/O3
WE
A4
A5
A6
A7
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
A16
A15
A14
A13
OE
I/O7
I/O6
GND
VDD
I/O5
I/O4
A12
A11
A10
A9
A8
PIN CONFIGURATION
48-mini BGA (B) (6 mm x 8 mm)
1
2
3
4
5
6
A
NC
OE
A2
A6
A7
NC
B
I/O0
NC
A1
A5
CE
I/O7
C
I/O1
NC
A0
A4
NC
I/O6
D
GND
NC
NC
A3
NC
VDD
E
VDD
NC
NC
NC
NC
GND
F
I/O2
NC
A14
A11
I/O4
I/O5
G
I/O3
NC
A15
A12
WE
A8
H
NC
A10
A16
A13
A9
NC
Integrated Silicon Solution, Inc. — www.issi.com
Rev. B
12/15/2011
IS63WV1288DALL/DALS
IS63WV1288DBLL/DBLS
IS64WV1288DBLL/DBLS
TRUTH TABLE
Mode
Not Selected
(Power-down)
Output Disabled
Read
Write
WE
X
CE
H
OE
X
I/O Operation
High-Z
Vdd Current
Isb1, Isb2
H
H
L
L
L
L
H
L
X
High-Z
Dout
Din
Icc1, Icc2
Icc1, Icc2
Icc1, Icc2
ABSOLUTE MAXIMUM RATINGS(1)
Symbol
Vterm
Tstg
Pt
Vdd
Parameter
Terminal Voltage with Respect to GND
Storage Temperature
Power Dissipation
Vdd Related to GND
Value
–0.5 to Vdd+0.5
–65 to +150
1.5
-0.2 to +3.9
Unit
V
°C
W
V
Note:
1. Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the
device. This is a stress rating only and functional operation of the device at these or any other conditions above
those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum
rating conditions for extended periods may affect reliability.
Integrated Silicon Solution, Inc. — www.issi.com Rev. B
12/15/2011
3
IS63WV1288DALL/DALS
IS63WV1288DBLL/DBLS
IS64WV1288DBLL/DBLS
AC TEST CONDITIONS
Parameter
Unit
Unit
(2.4V-3.6V)
(3.3V + 5%)
Input Pulse Level
0.4V to Vdd - 0.3V
0.4V to Vdd - 0.3V
Input Rise and Fall Times
1V/ ns
1V/ ns
Input and Output Timing
VDD /2
VDD + 0.05
and Reference Level (VRef) 2
Output Load
See Figures 1 and 2
See Figures 1 and 2
R1 ( Ω )
1909
317
R2 ( Ω )
1105
351
Vtm (V)
3.0V
3.3V
Unit
(1.65V-2.2V)
0.4V to Vdd - 0.3V
1V/ ns
0.9V
See Figures 1 and 2
13500
10800
1.8V
AC TEST LOADS
R1
ZO = 50Ω
50Ω
VDD/2
OUTPUT
30 pF
Including
jig and
scope
Figure 1.
4
VTM
OUTPUT
5 pF
Including
jig and
scope
R2
Figure 2.
Integrated Silicon Solution, Inc. — www.issi.com
Rev. B
12/15/2011
IS63WV1288DALL/DALS
IS63WV1288DBLL/DBLS
IS64WV1288DBLL/DBLS
DC ELECTRICAL CHARACTERISTICS (Over Operating Range)
Vdd = 3.3V + 5%
Symbol
Voh
Vol
Vih
Vil
Ili
Ilo
Parameter
Output HIGH Voltage
Output LOW Voltage
Input HIGH Voltage
Input LOW Voltage(1)
Input Leakage
Output Leakage
Test Conditions
Vdd = Min., Ioh = –4.0 mA
Vdd = Min., Iol = 8.0 mA
GND ≤ Vin ≤ Vdd
GND ≤ Vout ≤ Vdd, Outputs Disabled
Min.
2.4
—
2
–0.3
–1
–1
Max.
—
0.4
Vdd + 0.3
0.8
1
1
Unit
V
V
V
V
µA
µA
Min.
1.8
—
2.0
–0.3
–1
–1
Max.
—
0.4
Vdd + 0.3
0.8
1
1
Unit
V
V
V
V
µA
µA
Note:
1. Vil (min.) = –0.3V DC; Vil (min.) = –2.0V AC (pulse width < 10 ns). Not 100% tested.
Vih (max.) = Vdd + 0.3V DC; Vih (max.) = Vdd + 2.0V AC (pulse width < 10 ns). Not 100% tested.
DC ELECTRICAL CHARACTERISTICS (Over Operating Range)
Vdd = 2.4V-3.6V
Symbol
Voh
Vol
Vih
Vil
Ili
Ilo
Parameter
Output HIGH Voltage
Output LOW Voltage
Input HIGH Voltage
Input LOW Voltage(1)
Input Leakage
Output Leakage
Test Conditions
Vdd = Min., Ioh = –1.0 mA
Vdd = Min., Iol = 1.0 mA
GND ≤ Vin ≤ Vdd
GND ≤ Vout ≤ Vdd, Outputs Disabled
Note:
1. Vil (min.) = –0.3V DC; Vil (min.) = –2.0V AC (pulse width < 10 ns). Not 100% tested.
Vih (max.) = Vdd + 0.3V DC; Vih (max.) = Vdd + 2.0V AC (pulse width < 10 ns). Not 100% tested.
DC ELECTRICAL CHARACTERISTICS (Over Operating Range)
Vdd = 1.65V-2.2V
Symbol
Voh
Vol
Vih
Vil(1)
Ili
Ilo
Parameter
Output HIGH Voltage
Output LOW Voltage
Input HIGH Voltage
Input LOW Voltage
Input Leakage
Output Leakage
Test Conditions
Vdd
Ioh = -0.1 mA
1.65-2.2V
Iol = 0.1 mA
1.65-2.2V
1.65-2.2V
1.65-2.2V
GND ≤ Vin ≤ Vdd
GND ≤ Vout ≤ Vdd, Outputs Disabled
Min.
1.4
—
1.4
–0.2
–1
–1
Max.
—
0.2
Vdd + 0.2
0.4
1
1
Unit
V
V
V
V
µA
µA
Note:
1. Vil (min.) = –0.3V DC; Vil (min.) = –2.0V AC (pulse width < 10 ns). Not 100% tested.
Vih (max.) = Vdd + 0.3V DC; Vih (max.) = Vdd + 2.0V AC (pulse width < 10 ns). Not 100% tested.
Integrated Silicon Solution, Inc. — www.issi.com Rev. B
12/15/2011
5
IS63WV1288DALL/DALS
IS63WV1288DBLL/DBLS
IS64WV1288DBLL/DBLS
HIGH SPEED (IS63WV1288DALL/DBLL)
OPERATING RANGE (Vdd) (IS63WV1288DALL)
Range
Ambient Temperature
Commercial
0°C to +70°C
Industrial
–40°C to +85°C
Automotive
–40°C to +125°C
Vdd
1.65V-2.2V
1.65V-2.2V
1.65V-2.2V
Speed
20ns
20ns
20ns
OPERATING RANGE (Vdd) (IS63WV1288DBLL)(1)
Range
Ambient Temperature
Commercial
0°C to +70°C
Industrial
–40°C to +85°C
Vdd (8 ns)1
3.3V + 5%
3.3V + 5%
Vdd (10 ns)1
2.4V-3.6V
2.4V-3.6V
Note:
1. When operated in the range of 2.4V-3.6V, the device meets 10ns. When operated in the range of 3.3V + 5%,
the device meets 8ns.
OPERATING RANGE (Vdd) (IS64WV1288DBLL)(2)
Range
Ambient Temperature
Automotive
–40°C to +125°C
Vdd (8 ns)2
3.3V + 5%
Vdd (10 ns)2
2.4V-3.6V
Note:
2. When operated in the range of 2.4V-3.6V, the device meets 10ns. When operated in the range of 3.3V + 5%,
the device meets 8ns.
POWER SUPPLY CHARACTERISTICS(1) (Over Operating Range)
Symbol Parameter
Test Conditions
Icc
Vdd Dynamic Operating Vdd = Max., Com.
Supply Current
Iout = 0 mA, f = fmax Ind.
CE = Vil
Auto.(3)
Vin ≥ Vdd – 0.3V, or typ.(2)
Vin ≤ 0.4V
Isb2
CMOS Standby
Vdd = Max., Com.
Current (CMOS Inputs) CE ≥ Vdd – 0.2V,
Ind.
Vin ≥ Vdd – 0.2V, or Auto.
Vin ≤ 0.2V, f = 0 typ.(2)
-8
-10
Min. Max.
Min. Max.
— 65
— 50
— 70
— 55
— —
— 65
45 —
—
— 40
—
55
—
—
— 4
40
55
90
-12
Min. Max.
— 45
— 50
— 55
45 -20
Min. Max.
— 40
— 45
— 50
— 40
— 55
— 90
4
— 40
— 55
— 90
Unit
mA
µA
Note:
1. At f = fmax, address and data inputs are cycling at the maximum frequency, f = 0 means no input lines change.
2. Typical values are measured at Vdd = 3.0V, Ta = 25oC and not 100% tested.
3. For Automotive grade at 15ns, typ. Icc = 38mA, not 100% tested.
6
Integrated Silicon Solution, Inc. — www.issi.com
Rev. B
12/15/2011
IS63WV1288DALL/DALS
IS63WV1288DBLL/DBLS
IS64WV1288DBLL/DBLS
LOW POWER (IS63WV1288DALS/DBLS)
OPERATING RANGE (Vdd) (IS63WV1288DALS)
Range
Ambient Temperature
Commercial
0°C to +70°C
Industrial
–40°C to +85°C
Automotive
–40°C to +125°C
Vdd
1.65V-2.2V
1.65V-2.2V
1.65V-2.2V
Speed
45ns
45ns
55ns
OPERATING RANGE (Vdd) (IS63WV1288DBLS)
Range
Ambient Temperature
Commercial
0°C to +70°C
Industrial
–40°C to +85°C
Vdd (35 ns)
2.4V-3.6V
2.4V-3.6V
OPERATING RANGE (Vdd) (IS64WV1288DBLS)
Range
Ambient Temperature
Automotive
–40°C to +125°C
Vdd (35 ns)
2.4V-3.6V
POWER SUPPLY CHARACTERISTICS(1) (Over Operating Range)
-25
Symbol Parameter
Test Conditions
Min. Max.
Icc
Vdd Dynamic Operating
Vdd = Max., Com.
— 15
Supply Current
Iout = 0 mA, f = fmax
Ind.
— 20
CE = Vil
Auto.
— 30
Vin ≥ Vdd – 0.3V, or
typ.(2) 18 Vin ≤ 0.4V
Isb2
CMOS Standby
Vdd = Max., Com.
— 40
Current (CMOS Inputs)
CE ≥ Vdd – 0.2V,
Ind.
— 50
Vin ≥ Vdd – 0.2V, or
Auto.
— 75
Vin ≤ 0.2V, f = 0
typ.(2) 4
-35
Min. Max.
— 15
— 20
— 30
— 40
— 50
— 75
-45
Min. Max.
— 12
— 18
— 25
— 40
— 50
— 75
Unit
mA
µA
Note:
1. At f = fmax, address and data inputs are cycling at the maximum frequency, f = 0 means no input lines change.
2. Typical values are measured at Vdd = 3.0V, Ta = 25oC and not 100% tested.
Integrated Silicon Solution, Inc. — www.issi.com Rev. B
12/15/2011
7
IS63WV1288DALL/DALS
IS63WV1288DBLL/DBLS
IS64WV1288DBLL/DBLS
READ CYCLE SWITCHING CHARACTERISTICS(1) (Over Operating Range)
Symbol
Parameter
trc
Read Cycle Time
taa
Address Access Time
toha
Output Hold Time
tace
CE Access Time
tdoe
OE Access Time
(2)
tlzoe OE to Low-Z Output
thzoe(2)
OE to High-Z Output
(2)
tlzce CE to Low-Z Output
(2)
thzce CE to High-Z Output
tpu
CE to Power Up Time
tpd
CE to Power Down Time
-8 ns
Min.
Max.
8
—
—
8
2
—
—
8
—
4
0
—
0
4
3
—
0
4
0
—
—
8
-10 ns
Min.
Max.
10
—
—
10
2
—
—
10
—
5
0
—
0
5
3
—
0
5
0
—
—
10
-12 ns
Min.
Max.
12
—
—
12
2
—
—
12
—
6
0
—
0
6
3
—
0
6
0
—
—
12
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Notes:
1. Test conditions assume signal transition times of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V loading specified in Figure 1.
2. Tested with the loading specified in Figure 2. Transition is measured ±500 mV from steady-state voltage. Not 100% tested.
READ CYCLE SWITCHING CHARACTERISTICS(1) (Over Operating Range)
-20 ns -25 ns -35 ns -45 ns
Symbol Parameter Min.Max.
Min. Max.
Min.Max.
Min. Max.
trc
Read Cycle Time
20 —
25 —
35 —
45 —
taa
Address Access Time — 20
— 25
— 35
— 45
toha
Output Hold Time
2.5 —
6 —
8 —
10 —
tace
CE Access Time
— 20
— 25
— 35
— 45
tdoe
OE Access Time
— 8
— 12
— 15
— 20
(2)
thzoe OE to High-Z Output
0 8
0 8
0 10
0 15
tlzoe(2)
OE to Low-Z Output
0 —
0 —
0 —
0 —
thzce tlzce(2)
(2
CE to High-Z Output
CE to Low-Z Output
0 8
3 —
0 8
10 —
0 10
10 —
0
10
15
—
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
Notes:
1. Test conditions assume signal transition times of 1.5 ns or less, timing reference levels of 1.25V, input pulse levels of 0.4V to
Vdd-0.3V and output loading specified in Figure 1a.
2. Tested with the load in Figure 1b. Transition is measured ±500 mV from steady-state voltage. Not 100% tested.
3. Not 100% tested.
8
Integrated Silicon Solution, Inc. — www.issi.com
Rev. B
12/15/2011
IS63WV1288DALL/DALS
IS63WV1288DBLL/DBLS
IS64WV1288DBLL/DBLS
AC WAVEFORMS
READ CYCLE NO. 1(1,2)
t RC
ADDRESS
t AA
t OHA
DOUT
t OHA
DATA VALID
PREVIOUS DATA VALID
READ1.eps
READ CYCLE NO. 2(1,3)
t RC
ADDRESS
t AA
t OHA
OE
t HZOE
t DOE
t LZOE
CE
t LZCE
DOUT
t ACE
HIGH-Z
t HZCE
DATA VALID
CE_RD2.eps
Notes:
1. WE is HIGH for a Read Cycle.
2. The device is continuously selected. OE, CE = Vil.
3. Address is valid prior to or coincident with CE LOW transitions.
Integrated Silicon Solution, Inc. — www.issi.com Rev. B
12/15/2011
9
IS63WV1288DALL/DALS
IS63WV1288DBLL/DBLS
IS64WV1288DBLL/DBLS
WRITE CYCLE SWITCHING CHARACTERISTICS(1,3) (Over Operating Range)
Symbol
Parameter
twc
Write Cycle Time
tsce
CE to Write End
taw
Address Setup Time to Write End
tha
Address Hold from
Write End
tsa
Address Setup Time
(1)
tpwe1 WE Pulse Width (OE High)
(2)
tpwe2 WE Pulse Width (OE Low)
tsd
Data Setup to Write End
thd
Data Hold from Write End
thzwe(2)
WE LOW to High-Z Output
(2)
tlzwe WE HIGH to Low-Z Output
-8 ns
Min. Max.
8
—
7
—
8
—
-10 ns
Min. Max.
10
—
7
—
8
—
-12 ns
Min. Max.
12
—
8
—
8
—
Unit
ns
ns
ns
0
—
0
—
0
—
ns
0
7
8
5
0
—
3
—
—
—
—
—
4
—
0
7
10
5
0
—
3
—
—
—
—
—
5
—
0
8
12
6
0
—
3
—
—
—
—
—
6
—
ns
ns
ns
ns
­ns
ns
ns
Notes:
1. Test conditions assume signal transition times of 3ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V and
output loading specified in Figure 1.
2. Tested with the load in Figure 2. Transition is measured ±500 mV from steady-state voltage. Not 100% tested.
3. The internal write time is defined by the overlap of CE LOW and WE LOW. All signals must be in valid states to initiate a Write,
but any one can go inactive to terminate the Write. The Data Input Setup and Hold timing are referenced to the rising or falling
edge of the signal that terminates the Write.
WRITE CYCLE SWITCHING CHARACTERISTICS(1,2) (Over Operating Range)
Symbol Parameter
twc
Write Cycle Time
tsce
CE to Write End
taw
Address Setup Time to Write End
tha
Address Hold from Write End tsa
Address Setup Time
tpwe1
WE Pulse Width (OE = HIGH) tpwe2
WE Pulse Width (OE = LOW) tsd
Data Setup to Write End
thd
Data Hold from Write End
(3)
thzwe WE LOW to High-Z Output
(3)
tlzwe WE HIGH to Low-Z Output
-20 ns-25 ns-35 ns
Min. Max.
Min. Max.
Min.Max.
20 —
25 —
35 —
12 —
18 —
25 —
12 —
15 —
25 —
0
0
12
17
9
0
—
3
—
—
—
—
—
—
9
—
0
0
18
20
12
0
—
5
—
—
—
—
—
—
12
—
0
0
30
30
15
­0
—
5
—
—
—
—
—
—
20
—
-45ns
Min. Max.
45 —
35 —
35 —
0
0
35
35
20
0
—
5
—
—
—
—
—
—
20
—
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Notes:
1. Test conditions for IS61WV6416LL assume signal transition times of 1.5ns or less, timing reference levels of 1.25V, input pulse
levels of 0.4V to Vdd-0.3V and output loading specified in Figure 1a.
2. Tested with the load in Figure 1b. Transition is measured ±500 mV from steady-state voltage. Not 100% tested.
3. The internal write time is defined by the overlap of CE LOW and UB or LB, and WE LOW. All signals must be in valid states to
initiate a Write, but any one can go inactive to terminate the Write. The Data Input Setup and Hold timing are referenced to the
rising or falling edge of the signal that terminates the write.
10
Integrated Silicon Solution, Inc. — www.issi.com
Rev. B
12/15/2011
IS63WV1288DALL/DALS
IS63WV1288DBLL/DBLS
IS64WV1288DBLL/DBLS
AC WAVEFORMS
WRITE CYCLE NO. 1(1,2 (CE Controlled, OE = HIGH or LOW)
t WC
VALID ADDRESS
ADDRESS
t SA
t SCE
t HA
CE
t AW
t PWE1
t PWE2
WE
t HZWE
DOUT
DATA UNDEFINED
t LZWE
HIGH-Z
t SD
DIN
t HD
DATAIN VALID
CE_WR1.eps
Integrated Silicon Solution, Inc. — www.issi.com Rev. B
12/15/2011
11
IS63WV1288DALL/DALS
IS63WV1288DBLL/DBLS
IS64WV1288DBLL/DBLS
AC WAVEFORMS
WRITE CYCLE NO. 2(1) (WE Controlled, OE = HIGH during Write Cycle)
t WC
ADDRESS
VALID ADDRESS
t HA
OE
CE
LOW
t AW
t PWE1
WE
t SA
DOUT
t HZWE
t LZWE
HIGH-Z
DATA UNDEFINED
t SD
t HD
DATAIN VALID
DIN
CE_WR2.eps
WRITE CYCLE NO. 3 (WE Controlled: OE is LOW During Write Cycle)
t WC
ADDRESS
VALID ADDRESS
OE
LOW
CE
LOW
t HA
t AW
t PWE2
WE
tSA
DOUT
DATA UNDEFINED
t HZWE
t LZWE
HIGH-Z
t SD
DIN
t HD
DATAIN VALID
CE_WR3.eps
Notes:
1. The internal write time is defined by the overlap of CE LOW and WE LOW. All signals must be in valid states to initiate a Write,
but any one can go inactive to terminate the Write. The Data Input Setup and Hold timing are referenced to the rising or falling
edge of the signal that terminates the Write.
2. I/O will assume the High-Z state if OE > Vih.
12
Integrated Silicon Solution, Inc. — www.issi.com
Rev. B
12/15/2011
IS63WV1288DALL/DALS
IS63WV1288DBLL/DBLS
IS64WV1288DBLL/DBLS
HIGH SPEED (IS63/4WV1288DALL/DBLL)
DATA RETENTION SWITCHING CHARACTERISTICS (2.4V-3.6V)
Symbol
Parameter
Test Condition
Vdr
Vdd for Data Retention
See Data Retention Waveform
Idr
Data Retention Current
Vdd = 2.0V, CE ≥ Vdd – 0.2V
tsdr
Data Retention Setup Time See Data Retention Waveform
trdr
Recovery Time
See Data Retention Waveform
Note 1: Typical values are measured at Vdd = 3.0V, Ta = 25 C and not 100% tested.
Options
Com.
Ind.
Auto.
Min.
2.0
—
—
0
trc
Typ.(1)
—
4
—
—
—
Max.
3.6
40
55
90
—
—
Unit
V
µA
Min.
1.2
—
—
—
0
trc
Typ.(1)
—
4
—
—
—
—
Max.
3.6
40
55
90
—
—
Unit
V
µA
ns
ns
o
DATA RETENTION SWITCHING CHARACTERISTICS (1.65V-2.2V)
Symbol
Parameter
Test Condition
Vdr
Vdd for Data Retention
See Data Retention Waveform
Idr
Data Retention Current
Vdd = 1.2V, CE ≥ Vdd – 0.2V
tsdr
Data Retention Setup Time See Data Retention Waveform
trdr
Recovery Time
See Data Retention Waveform
Note 1: Typical values are measured at Vdd = 1.8V, Ta = 25 C and not 100% tested.
Options
Com.
Ind.
Auto.
ns
ns
o
DATA RETENTION WAVEFORM (CE Controlled)
tSDR
Data Retention Mode
tRDR
VDD
VDR
CE
GND
Integrated Silicon Solution, Inc. — www.issi.com Rev. B
12/15/2011
CE ≥ VDD - 0.2V
13
IS63WV1288DALL/DALS
IS63WV1288DBLL/DBLS
IS64WV1288DBLL/DBLS
LOW POWER (IS63/4WV1288DALS/DBLS)
DATA RETENTION SWITCHING CHARACTERISTICS (2.4V-3.6V)
Symbol
Parameter
Test Condition
Vdr
Vdd for Data Retention
See Data Retention Waveform
Idr
Data Retention Current
Vdd = 2.0V, CE ≥ Vdd – 0.2V
tsdr
Data Retention Setup Time See Data Retention Waveform
trdr
Recovery Time
See Data Retention Waveform
Note 1: Typical values are measured at Vdd = 3.0V, Ta = 25 C and not 100% tested.
Options
Com.
Ind.
Auto.
Min.
2.0
—
—
0
trc
Typ.(1)
—
4
—
—
—
Max.
3.6
40
50
75
—
—
Unit
V
µA
Min.
1.2
—
—
—
0
trc
Typ.(1)
—
4
—
—
—
—
Max.
3.6
40
50
75
—
—
Unit
V
µA
ns
ns
o
DATA RETENTION SWITCHING CHARACTERISTICS (1.65V-2.2V)
Symbol
Parameter
Test Condition
Vdr
Vdd for Data Retention
See Data Retention Waveform
Idr
Data Retention Current
Vdd = 1.2V, CE ≥ Vdd – 0.2V
tsdr
Data Retention Setup Time See Data Retention Waveform
trdr
Recovery Time
See Data Retention Waveform
Note 1: Typical values are measured at Vdd = 1.8V, Ta = 25 C and not 100% tested.
Options
Com.
Ind.
Auto.
ns
ns
o
DATA RETENTION WAVEFORM (CE Controlled)
tSDR
Data Retention Mode
tRDR
VDD
VDR
CE
GND
14
CE ≥ VDD - 0.2V
Integrated Silicon Solution, Inc. — www.issi.com
Rev. B
12/15/2011
IS63WV1288DALL/DALS
IS63WV1288DBLL/DBLS
IS64WV1288DBLL/DBLS
ORDERING INFORMATION
Industrial Range: –40°C to +85°C
peed (ns)
S
8
10
Order Part No.
IS63WV1288DBLL-8TI
IS63WV1288DBLL-8TLI
IS63WV1288DBLL-8HI
IS63WV1288DBLL-8HLI
IS63WV1288DBLL-8JI
IS63WV1288DBLL-8JLI
IS63WV1288DBLL-10TI
IS63WV1288DBLL-10TLI
IS63WV1288DBLL-10HI
IS63WV1288DBLL-10HLI
IS63WV1288DBLL-10JI
IS63WV1288DBLL-10JLI
IS63WV1288DBLL-10KLI
Package
32-pin TSOP (Type II)
32-pin TSOP (Type II), Lead-free
sTSOP (Type I) (8mm x13.4mm)
sTSOP (Type I) (8mm x13.4mm), Lead-free
32-pin SOJ (300-mil)
32-pin SOJ (300-mil), Lead-free
32-pin TSOP (Type II)
32-pin TSOP (Type II), Lead-free
sTSOP (Type I) (8mm x13.4mm)
sTSOP (Type I) (8mm x13.4mm), Lead-free
32-pin SOJ (300-mil)
32-pin SOJ (300-mil), Lead-free 32-pin SOJ (400-mil), Lead-free
Automotive Range (A3): –40°C to +125°C
peed (ns)
S
10(8*)
Order Part No.
IS64WV1288DBLL-10TA3
IS64WV1288DBLL-10TLA3
IS64WV1288DBLL-10HA3
IS64WV1288DBLL-10HLA3
Package
32-pin TSOP (Type II)
32-pin TSOP (Type II), Lead-free
sTSOP (Type I) (8mm x13.4mm)
sTSOP (Type I) (8mm x13.4mm), Lead-free
Note:
1. Speed = 8ns for Vdd = 3.3V + 5%. Speed = 10ns for Vdd = 2.4V-3.6V.
Integrated Silicon Solution, Inc. — www.issi.com Rev. B
12/15/2011
15
IS63WV1288DALL/DALS
IS63WV1288DBLL/DBLS
IS64WV1288DBLL/DBLS
16
Integrated Silicon Solution, Inc. — www.issi.com
Rev. B
12/15/2011
Integrated Silicon Solution, Inc. — www.issi.com Rev. B
12/15/2011
SEATING PLANE
3. Dimension b2 does not include dambar protrusion/intrusion.
4. Formed leads shall be planar with respect to one another within 0.1mm
at the seating plane after final test.
5. Reference document : JEDEC SPEC MS-027.
2. Dimension D and E1 do not include mold protrusion .
1. Controlling dimension : mm
NOTE :
12/19/2007
IS63WV1288DALL/DALS
IS63WV1288DBLL/DBLS
IS64WV1288DBLL/DBLS
17
IS63WV1288DALL/DALS
IS63WV1288DBLL/DBLS
IS64WV1288DBLL/DBLS
18
Integrated Silicon Solution, Inc. — www.issi.com
Rev. B
12/15/2011
IS63WV1288DALL/DALS
IS63WV1288DBLL/DBLS
IS64WV1288DBLL/DBLS
Integrated Silicon Solution, Inc. — www.issi.com Rev. B
12/15/2011
19
20
08/12/2008
Package Outline
1. CONTROLLING DIMENSION : MM .
2. Reference document : JEDEC MO-207
NOTE :
IS63WV1288DALL/DALS
IS63WV1288DBLL/DBLS
IS64WV1288DBLL/DBLS
Integrated Silicon Solution, Inc. — www.issi.com
Rev. B
12/15/2011