SD210DE/214DE N-CHANNEL LATERAL DMOS SWITCH PRODUCT SUMMARY PART NUMBER V(BR)DS Min (V) V(GS)th Max (V) rDS(on) Max (Ω) Crss Max (pF) tON Max (ns) SD210DE 30 1.5 45 @ VGS=10V 0.5 2 SD214DE 20 1.5 45 @ VGS=10V 0.5 2 Features Benefits Applications • Ultra-High Speed Switching—tON: 1ns • Ultra-Low Reverse Capacitance: 0.2pF • Low Guaranteed rDS @5V • Low Turn-On Threshold Voltage • N-Channel Enhancement Mode • High-Speed System Performance • Low Insertion Loss at High Frequencies • Low Transfer Signal Loss • Simple Driver Requirement • Single Supply Operation • Fast Analog Switch • Fast Sample-and-Holds • Pixel-Rate Switching • DAC Deglitchers • High-Speed Driver Description The SD210DE/214DE are enhancement-mode MOSFETs designed for high speed low-glitch switching in audio, video and high-frequency applications. The SD214DE is normally used for a ±10-V analog switching. These MOSFETs utilize lateral construction to achieve low capacitance and ultra-fast switching speeds. These MOSFETs do not have a gate protection Zener diode which results in lower gate leakage and ± voltage capability from gate to substrate. A poly-silicon gate is featured for manufacturing reliability. For similar products see: quad array—SD5000/5400 series, and Zener protected—SD211DE/SST211 series. TOP VIEW TO-206AF (TO-72) S D Linear Integrated Systems 1 4 2 3 • Body Substrate (Case) G 4042 Clipper Court • Fremont, CA 94538 • Tel: 510 490-9160 • Fax: 510 353-0261 1/31/2011 Rev#A5 ECN# SD210DE_214DE Absolute Maximum Ratings (TA = 25°C unless otherwise noted) Gate-Drain, Gate-Source Voltage Gate-Substrate Voltage Drain-Source Voltage Source-Drain Voltage Drain-Substrate Voltage . . . . . . . . . . . . . . . . . . . . . . . . ± 40V . . . . . . . . . . . . . . . . . . . . .± 30V (SD210DE) . . . . . . . . . . . . . . . 30V (SD214DE) . . . . . . . . . . . . . . . 20V (SD210DE) . . . . . . . . . . . . . . . 10V (SD214DE) . . . . . . . . . . . . . . . 20V (SD210DE) . . . . . . . . . . . . . . . 30V (SD214DE) . . . . . . . . . . . . . . . 25V Source-Substrate Voltage Drain Current Lead Temperature (1/16” from ease for 10 seconds) Storage Temperature Operating Junction Temperature Power Dissipation* (SD210DE) . . . . . . . . . . . . . . . 15V (SD210DE) . . . . . . . . . . . . . . . 25V . . . . . . . . . . . . . . . . . . . . . . . .50mA . . . . . . . . . . . . . . . . . . . . . . . 300°C . . . . . . . . . . . . . . . . . -65 to 150°C . . . . . . . . . . . . . . . . . -55 to 125°C . . . . . . . . . . . . . . . . . . . . . . .300mW Note: * Derate 3mW/°C above 25°C Specificationsa PARAMETER SYMBOL b TEST CONDITIONS b TYP c LIMITS SD210DE SD214DE Min Max Min Max UNIT Static Drain - Source Breakdown Voltage V(BR)DS VGS = VBS = 0V, ID = 10 µA VGS = VBS = -5V, ID = 10 nA 35 30 30 10 20 V(BR)SD VGD = VBD = -5V, IS = 10 nA 22 10 20 35 15 25 35 15 25 Source - Drain Breakdown Voltage Drain - Substrate Breakdown Voltage V(BR)DBO Source - Substrate Breakdown Voltage V(BR)SBO Drain – Source Leakage IDS(off) Source - Drain Leakage ISD(off) Gate Leakage IGBS Threshold Voltage Drain – Source On-Resistance VGS(th) rDS(on) VGB = 0V, ID= 10 nA Source Open VGB = 0V, Is = 10 µA Drain Open VDS = 10V VGS = VBS = -5V VDS = 20V VSD = 10V VGD = VBD = -5V VSD = 20V VDB = VSB = 0V, VGB = ±4 0V VDS = VGS, ID = 1 µA , VSB = 0V VGS = 5V VSB = 0V ID = 1mA Linear Integrated Systems V 0.4 0.9 0.5 0.8 10 0.001 0.1 0.8 10 10 10 0.5 1.5 0.1 0.1 1.5 58 70 70 VGS = 10V 38 45 45 VGS = 15V 30 VGS = 20V 26 VGS = 25V 24 • nA V Ω 4042 Clipper Court • Fremont, CA 94538 • Tel: 510 490-9160 • Fax: 510 353-0261 1/31/2011 Rev#A5 ECN# SD210DE_214DE Specificationsa PARAMETER SYMBOL b TEST CONDITIONS b TYP c LIMITS SD210DE Min Max SD214DE Min Max UNIT Dynamic Forward Transconductance Gate Node Capacitance Drain Node Capacitance Source Node Capacitance Reverse Transfer Capacitance gfs gos 11 0.9 VDS = 10V, VSB = 0V, ID = 20mA, f = 1kHz C(GS+GD+GB) C(GD+DB) C(GS+SB) VDS = 10V, f = 1MHz VGS = VBS = -15V Crss 10 10 mS 2.5 3.5 3.5 1.1 1.5 1.5 3.7 5.5 5.5 0.2 0.5 0.5 0.5 0.6 2 6 1 1 1 1 pF Switching Turn-On Time Turn-Off Time tD(on) tr tD (off) tf VSB = 0V, VIN0 to 5V, RG = 25Ω VDD = 5V, RL = 680Ω ns Notes: a. TA= 25°C unless otherwise noted. b. B is the body (substrate) and V(BR) is breakdown voltage. c. Typical values are for DESIGN AID ONLY, not guaranteed nor subject to production testing. Linear Integrated Systems • 4042 Clipper Court • Fremont, CA 94538 • Tel: 510 490-9160 • Fax: 510 353-0261 1/31/2011 Rev#A5 ECN# SD210DE_214DE