SD-SST211/213/215 N-CHANNEL LATERAL DMOS SWITCH ZENER PROTECTED PRODUCT SUMMARY PART NUMBER V(BR)DS Min (V) V(GS)th Max (V) rDS(on) Max (Ω) C rss Max (pF) SD211DE 30 1.5 45 @ VGS=10V 0.5 2 SD213DE 10 1.5 45 @ VGS=10V 0.5 2 SD215DE 20 1.5 45 @ VGS=10V 0.5 2 SST211 30 1.5 50 @ VGS=10V 0.5 2 SST213 10 1.5 50 @ VGS=10V 0.5 2 SST215 20 1.5 50 @ VGS=10V 0.5 2 Features • Ultra-High Speed Switching—ION: 1ns • Ultra-Low Reverse Capacitance: 0.2pF • Low Guaranteed rDS @5V • Low Turn-On Threshold Voltage • N-Channel Enhancement Mode tON Max (ns) Benefits Applications • High-Speed System Performance • Low Insertion Loss at High Frequencies • Low Transfer Signal Loss • Simple Driver Requirement • Single Supply Operation • Fast Analog Switch • Fast Sample-and-Holds • Pixel-Rate Switching • DAC Deglitchers • High-Speed Driver Description The SD211DE/SST211 series consists of enhancement-mode MOSFETs designed for high speed low-glitch switching in audio, video and high-frequency applications. The SD211 may be used for a ±5-V analog switching or as a high speed driver of the SD214. The SD214 is normally used for ±10-V analog switching. These MOSFETs utilize lateral construction to achieve low capacitance and ultra-fast switching speeds. An integrated ZENER diode provides ESD protection. These devices feature a poly-silicon gate for manufacturing reliability. For similar products see: quad array—SD5000/5400 series, nonZener protection—SD210DE/214DE. TO-206AF (TO-72) Linear Integrated Systems • 4042 Clipper Court • Fremont, CA 94538 • Tel: 510 490-9160 • Fax: 510 353-0261 Doc 20114 06/19/13 Rev#A8 ECN# SD-SST211/213/215 Absolute Maximum Ratings (TA = 25°C unless otherwise noted) Gate Drain, Gate Source Voltage Gate-Substrate Voltage a Drain-Source Voltage Voltage (SD211DE/SST211) . . . . . . .-30/25V (SD213DE/SST213). . . . . . . -15/25V (SD215DE/SST215). . . . . . . -25/30V (SD211DE/SST211) . . . . . . .-0.3/25V (SD213DE/SST213) . . . . . . .-0.3/25V (SD215DE/SST215) . . . . . . .-0.3/30V (SD211DE/SST211) . . . . . . . .30V (SD213DE/SST213) . . . . . . . .10V (SD215DE/SST215) . . . . . . . .20V (SD211DE/SST211) . . . . . . . .10V (SD213DE/SST213) . . . . . . . .10V (SD215DE/SST215) . . . . . . . .20V Drain-Substrate Voltage Source-Substrate Voltage Drain Current Lead Temperature (1/16” from ease for 10 seconds) Storage Temperature Operating Junction Temperature Power Dissipation (SD211DE/SST211) . . . . . . . .30V (SD213DE/SST213) . . . . . . . .15V (SD215DE/SST215) . . . . . . . .25V (SD211DE/SST211) . . . . . . . .15V (SD213DE/SST213) . . . . . . . .15V (SD215DE/SST215) . . . . . . . .25V . . . . . . . . . . . . . . . . . . . . . . . .50mA . . . . . . . . . . . . . . . . . . . . . . . 300°C . . . . . . . . . . . . . . . . . -65 to 150°C . . . . . . . . . . . . . . . . . -55 to 125°C . . . . . . . . . . . . . . . . . . . . . . .300mW Notes: a. Derate 3mW/°C above 25°C Specificationsa PARAMETER SYMBOL b TEST CONDITIONS b TYP b LIMITS 211 Series 213 Series 215 Series Min Max Min Max Min Max UNIT Static V(BR)DS VGS = VBS = 0V, ID = 10 µA VGS = VBS = -5V, ID = 10 nA 35 30 30 10 10 20 V(BR)SD VGS = VBD = -5V, IS = 10 nA 22 10 10 20 35 15 15 25 35 15 15 25 Drain - Source Breakdown Voltage Source - Drain Breakdown Voltage Drain - Substrate Breakdown Voltage V(BR)DBO Source - Substrate Breakdown Voltage V(BR)SBO Drain – Source Leakage IDS(off) Source - Drain Leakage ISD(off) Gate Leakage IGBS Threshold Voltage Drain – Source On-Resistance VGS(th) rDS(on) VGB = 0V, ID= 10 nA Source Open VGB = 0V, Is = 10 µA Drain Open VDS = 10V VGS = VBS = -5V VDS = 20V VSD = 10V VGD = VBD = -5V VSD = 20V VDB = VSB = 0V, VGB = 30V VDS = VGS, ID = 1 µA , VSB = 0V VGS = 5V (SD Series) VGS = 5V (SST Series) VGS = 10V VSB = 0V (SD Series) ID = 1mA VGS = 10V (SST Series) VGS = 15V VGS = 20V VGS = 25V Linear Integrated Systems • V 0.4 0.9 0.5 10 10 10 10 0.01 0.8 10 100 0.5 1.5 nA 10 100 100 0.1 1.5 0.1 1.5 58 70 70 70 60 75 75 75 38 45 45 45 40 50 50 50 V Ω 30 26 24 4042 Clipper Court • Fremont, CA 94538 • Tel: 510 490-9160 • Fax: 510 353-0261 Doc 20114 06/19/13 Rev#A8 ECN# SD-SST211/213/215 Specificationsa PARAMETER SYMBOL b TEST CONDITIONS b TYP c LIMITS 211 Series Min Max 213 Series Min Max 215 Series 10 9 10 9 10 9 UNIT Dynamic gfs Forward Transconductance Gate Node Capacitance Drain Node Capacitance Source Node Capacitance Reverse Transfer Capacitance gos VDS = 10V, VSB = 0V, , ID = 20mA, f = 1kHz SD Series SST Series 11 10.5 All 0.9 C(GS+GD+GB) C(GD+DB) C(GS+SB) VDS = 10V, f = 1MHz VGS = VBS = 15V Crss SD Series mS 2.5 3.5 3.5 3.5 1.1 1.5 1.5 1.5 3.7 5.5 5.5 5.5 SST Series 4.2 SD Series 0.2 0.5 0.5 0.5 0.5 0.6 2 6 1 1 1 1 1 1 pF Switching Turn-On Time Turn-Off Time tD(on) tr tD (off) tf SD Series Only VSB = 0V, VIN 0 to 5V, RG = 25Ω VDD = 5V, RL = 680Ω ns Notes: a. TA = 25°C unless otherwise notes. b. B is the body (substrate) and V(BR) is breakdown voltage. c. Typical values are for DESIGN AID ONLY, not guaranteed nor subject to production testing. Linear Integrated Systems (LIS) is a 25-year-old, third-generation precision semiconductor company providing high-quality discrete components. Expertise brought to LIS is based on processes and products developed at Amelco, Union Carbide, Intersil and Micro Power Systems by company President John H. Hall. Hall, a protégé of Silicon Valley legend Dr. Jean Hoerni, was the director of IC Development at Union Carbide, co-founder and vice president of R&D at Intersil, and founder/president of Micro Power Systems. Linear Integrated Systems • 4042 Clipper Court • Fremont, CA 94538 • Tel: 510 490-9160 • Fax: 510 353-0261 Doc 20114 06/19/13 Rev#A8 ECN# SD-SST211/213/215