MX69V28F64

MX69V28F64
Read-While-Write, Multiplexed, Burst Mode,
Flash Memory
MX69V28F64
P/N:PM1751
REV. 1.3, JUL. 22, 2013
1
MX69V28F64
128M-BIT [8M x 16-bit] CMOS 1.8 Volt-only
1. FEATURES
Characteristics
Program/Erase Cycles
Burst Length
• Burst Mode - Continuous linear
Data Retention
• 100,000 cycles typical
• 20 years
• Linear burst length - 8/16 word with wrap around
Sector Architecture
• Multi-bank Architecture (8 banks)
• Read while write operation
• Four 16 Kword sectors on top/ bottom of address
range
• 127 sectors are 64 KWord sectors
Hardware Features
Power Supply Operations
Hardware Sector Protection
• All sectors locked when ACC = VIL
• Supports multiplexing data and address for reduced
I/O count.
• A15–A0 multiplexed as Q15–Q0 Sector Architecture
• 1.8V for read, program and erase operations (1.70V
to 1.95V)
• Deep power down mode
Package
• 56-Ball Thin FBGA (Fine-Pitch Ball Grid Array)
• REACH SVHC Free and RoHS Compliant
Performance
Handshaking Feature
• Allows system to determine the read operation
High Performance
of burst data with minimum possible latency by
monitoring RDY.
• 30us - Word programming time
• 7.5us - Effective word programming time utilizing a
32 word Write Buffer at VCC level
• 2.5us - Effective word programming time of utilizing
a 32 word Write Buffer at ACC level
Sector Erase Time
• 500ms for 16 Kword sectors
• 1000ms for 64 Kword sectors
Read Access Time
• Burst access time: 7ns (at industrial temperature
range)
• Asynchronous random access time: 80ns
• Synchronous random access time: 75ns
Secure Silicon Sector Region
• 128 words for the factory & customer secure silicon
sector
Power Dissipation
• Typical values: 8 bits switching,
CL = 10 pF at 108 MHz, CIN excluded
• 20mA for Continuous burst read mode
• 30mA for Program/Erase Operations (max.)
• 30uA for Standby mode
P/N:PM1751
REV. 1.3, JUL. 22, 2013
2
MX69V28F64
2. Product Selection Guide
MX69V28F64BBXJW
128Mb
108MHz
108MHz
Boot Sector
Type
7.7x6.2x1.2 56-TFBGA
Bottom
MX69V28F64BBXLW
128Mb
108MHz
108MHz
7.7x6.2x1.05 56-TFBGA
Bottom
MX69V28F64MBXLW
128Mb
108MHz
108MHz
7.7x6.2x1.05 56-TFBGA
Bottom
Device
Flash Density Flash Speed
P/N:PM1751
pSRAM
Package Type
REV. 1.3, JUL. 22, 2013
3
MX69V28F64
3. BLOCK DIAGRAM
R-LB #
R-CRE
R-UB#
R-CE #
OE#
WE#
AVD #
CLK
LB#
CRE
UB#
CE #
pSRAM
WAIT
AD15-AD0
Amax-A16
F- CE #
F-ACC
F-WP#
F-RST#
OE#
WE#
AVD #
CLK
max- A16
CE#
ACC
WP#
RST#
OE#
WE#
AVD #
V
RDY
RDY/WAIT
AD15-AD0
AD15-AD0
CLK
Amax- A16
P/N:PM1751
REV. 1.3, JUL. 22, 2013
4
MX69V28F64
4. PIN CONFIGURATIONS
56-Ball, VFBGA with pSRAM
Legend
A1
A14
NC
NC
C3
C4
C7
C8
C11
C12
NC
NC
R- LB#
R- UB#
NC
NC
D3
D4
D5
D6
D7
D8
D9
D10
D11
D12
F-RDY/
R-WAIT
A21
VSS
CLK
VCC
WE#
F-ACC
A19
A17
A22
E9
E3
E4
E5
E6
E7
E8
E10
E11
E12
VI/O
A16
A20
AVD#
NC
F-RST#
F-WP#
A18
F-CE#
VSSQ
F3
F4
F5
F6
F7
F8
F9
F10
F11
F12
VSS
A/Q7
A/Q6
A/Q13
A/Q12
A/Q3
A/Q2
A/Q9
A/Q8
OE#
G3
G4
G5
G6
G7
G8
G9
G10
G11
G12
A/Q15
A/Q14
VSSQ
A/Q5
A/Q4
A/Q11
A/Q10
VI/O
A/Q1
A/Q0
H3
H4
H7
H8
H11
H12
NC
NC
R-CE#
NC
NC
R-CRE
No Connect
(Distance between
outer NC balls
is 2x pitch)
Flash/RAM
Shared Only
Flash Only
RAM Only
K1
K14
NC
NC
Notes:
1. Flash & pSRAM shared the address pins, which varies by density of pSRAM.
MCP
Shared AQ Pins
Flash-only Addresses
Shared Addresses
MX69V28F64
AQ15-AQ0
A22
A21~A16
P/N:PM1751
REV. 1.3, JUL. 22, 2013
5
MX69V28F64
5. PIN DESCRIPTION
SYMBOL
Amax-A16
A/Q15~A/Q0
OE#
WE#
VCC
VI/O
VSS
VSSQ
NC
RDY
CLK
AVD#
F-RBST#
F-WP#
F-ACC
R-CE#
F-CE#
R-CRE
R-UB#
R-LB#
DESCRIPTION
Address Inputs for 128Mb
Multiplexed Data Inputs/Outputs
Output Enable
Write Enable
Device Power Supply (1.70V~1.95V)
Input/Output Power Supply (1.70V~1.95V)
Device Ground
Input/Output Ground
No Connection
Ready status of the Burst Mode
Refer to configuration register table
Clock
Address Valid Data input.
Hardware Reset Pin, Active Low
H/W Write Protect
Programming Acceleration Input
Chip-enable
Chip-enable
Control Register Enable
Upper Byte Latch
Lower Byte Latch
Flash
V
V
V
V
V
V
V
V
V
V
RAM
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
Note: F- : For Flash
R- : For pSRAM
P/N:PM1751
REV. 1.3, JUL. 22, 2013
6
MX69V28F64
6. PART NAME DESCRIPTION
MX 69V
28
F 64
T
T XJ W
TEMPERATURE RANGE:
W: Wireless (-25° C to 85° C)
PACKAGE:
XJ: TFBGA with 56-ball (7.7x6.2x1.2mm)
XL: TFBGA with 56-ball (7.7x6.2x1.05mm)
Top/ Bottom boot
pSRAM Vendor
pSRAM DENSITY :
64: 64Mb
REVISION:
F
Flash DENSITY :
28: 128Mb
DEVICE:
69V : Multi-Chip Product (MCP)
1.8Volt Read-While-Write AD-Mux Burst Mode Flash Memory and RAM
P/N:PM1751
REV. 1.3, JUL. 22, 2013
7
MX69V28F64
7. PACKAGE INFORMATION
P/N:PM1751
REV. 1.3, JUL. 22, 2013
8
MX69V28F64
P/N:PM1751
REV. 1.3, JUL. 22, 2013
9
MX69V28F64
8. REVISION HISTORY
Revision No. Description
1.0
1. Removed "Advanced Information"
2. Modified word programming time, continuous burst read mode and standby mode
3. Added MX69V28F32BBXJW in Product Selection Guide
P3
1.1
1. Added MX69V28F64BBXLW in Product Selection Guide
2. Added 56-TFBGA (7.7x6.2x1.05mm) package information
P3
P7,9
NOV/27/2012
1.2
1. Modified PIN CONFIGURATIONS (from K3 to K1)
2. Added MX69V28F64MBXLW in Product Selection Guide
P5
P3
APR/25/2013
1.3
1. Removed MX69V28F32
All
JUL/22/2013
P/N:PM1751
Page
P1,2
P2
Date
JUL/30/2012
REV. 1.3, JUL. 22, 2013
10
MX69V28F64
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household applications only, and not for use in any applications which may, directly or indirectly, cause death,
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Copyright© Macronix International Co., Ltd. 2011~2013. All rights reserved, including the trademarks and
tradename thereof, such as Macronix, MXIC, MXIC Logo, MX Logo, Integrated Solutions Provider, NBit, Nbit,
NBiit, Macronix NBit, eLiteFlash, HybridNVM, HybridFlash, XtraROM, Phines, KH Logo, BE-SONOS, KSMC,
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For the contact and order information, please visit Macronix’s Web site at: http://www.macronix.com
MACRONIX INTERNATIONAL CO., LTD. reserves the right to change product and specifications without notice.
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