MX69N-E - Macronix

MX69N-E
MX69N MCPs
Multiplexed, 1.8V Burst-mode
64 Megabit
(Data Sheet)
Key Features
• Wireless Grade (Temperature = -25°C to 85°C)
• Combine MX29NS-E with pSRAM
• 56-ball TFBGA Package (6.2x7.7mm)
P/N:PM1648
REV. 1.4, MAR. 20, 2015
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MX69N-E
MCP FEATURES
• Operating Temperature Range
• Power supply voltage of 1.7V to 1.95V
- Wireless, -25°C to +85°C
• Burst Read: 108 MHz
• Package - MCP BGA: 0.5mm ball pitch
- 6.2 x 7.7mm, 56 ball
Product Description
This MX69N-E product series combine MX29NS-E with pSRAM in a Multi-Chip package. For detailed
specifications, please refer to the individual datasheet.
P/N:PM1648
REV. 1.4, MAR. 20, 2015
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MX69N-E
Product Selection Guide
Device
Flash Density
Flash Speed
pSRAM Speed
Package Type
MX69N64E32AXJW
64Mb
108MHz
108MHz
6.2x7.7 56-TFBGA
P/N:PM1648
REV. 1.4, MAR. 20, 2015
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MX69N-E
BLOCK DIAGRAM
F-RST#
RST#
F-ACC
F-WP#
F- CE #
OE#
WE#
AVD #
CLK
ACC
WP#
CE#
OE#
WE#
AVD #
CLK
Amax- A16
NS
RDY
AD15-AD0
RDY/ WAIT
AD15-AD0
Amax- A16
R-CE #
OE#
WE#
AVD #
CLK
CE #
R-CRE
R-UB#
R-LB #
CRE
UB#
LB#
pSRAM
WAIT
AD15-AD0
Amax-A16
P/N:PM1648
REV. 1.4, MAR. 20, 2015
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MX69N-E
PIN CONFIGURATIONS
pSRAM Based Pinout, 56-Ball, VFBGA
(Top View, Balls Facing Down)
Legend
A1
A14
NC
NC
C3
C4
C7
C8
C11
C12
NC
NC
R- LB#
R- UB#
NC
NC
D3
D4
D5
D6
D7
D8
D9
D10
D11
D12
F-RDY/
R-WAIT
A21
VSS
CLK
VCC
WE#
F-ACC
A19
A17
NC
E3
E4
E5
E6
E7
E8
E9
E10
E11
E12
VI/O
A16
A20
AVD#
NC
F-RST#
F-WP#
A18
F-CE#
VSSQ
F3
F4
F5
F6
F7
F8
F9
F10
F11
F12
VSS
A/Q7
A/Q6
A/Q13
A/Q12
A/Q3
A/Q2
A/Q9
A/Q8
OE#
G3
G4
G5
G6
G7
G8
G9
G10
G11
G12
A/Q15
A/Q14
VSSQ
A/Q5
A/Q4
A/Q11
A/Q10
VI/O
A/Q1
A/Q0
H3
H4
H7
H8
H11
H12
NC
NC
R-CE#
NC
NC
R-CRE
No Connect
(Distance between
outer NC balls
is 2x pitch)
Flash/RAM
Shared Only
Flash Only
RAM Only
K1
K14
NC
NC
Notes
1. Addresses are shared between Flash and RAM depending on the density of the pSRAM.
MCP
Flash-only Addresses
Shared Addresses
Shared AQ Pins
MX69N64E32
A21
A20~A16
AQ15-AQ0
P/N:PM1648
REV. 1.4, MAR. 20, 2015
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MX69N-E
PIN DESCRIPTION
SYMBOL
Amax-A16
A/Q15~A/Q0
OE#
WE#
VCC
VI/O
VSS
VSSQ
NC
RDY
CLK
AVD#
F-RBST#
F-WP#
F-ACC
R-CE#
F-CE#
R-CRE
R-UB#
R-LB#
DESCRIPTION
Address Inputs
Multiplexed Data Inputs/Outputs
Output Enable Input
Write Enable Input
Device Power Supply (1.70V~1.95V)
Input/Output Power Supply (1.70V~1.95V)
Device Ground
Input/Output Ground
No Connection
Ready output, the status of the Burst Read
Refer to configuration register table
Clock
Address Valid Data input.
Hardware Reset Pin, Active Low
Hardware Write Protect
Programming Acceleration Input
Chip-enable input for pSRAM.
Chip-enable input for Flash. Asynchronous relative to CLK for Burst Mode.
Control Register Enable (pSRAM).
Upper Byte Control (pSRAM).
Lower Byte Control (pSRAM).
P/N:PM1648
Flash
V
V
V
V
V
V
V
V
V
V
RAM
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
REV. 1.4, MAR. 20, 2015
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MX69N-E
PART NAME DESCRIPTION
MX
69N
64
E 32
A XJ
W
TEMPERATURE RANGE:
W: Wireless (-25° C to 85° C)
PACKAGE:
XJ: TFBGA with 56-ball (6.2x7.7mm)
pSRAM Vendor
pSRAM DENSITY :
32: 32Mb
REVISION:
E
Flash DENSITY :
64: 64Mb
DEVICE:
69N : Multi-Chip Product (MCP)
1.8Volt AD-Mux Burst Mode Flash Memory and RAM
P/N:PM1648
REV. 1.4, MAR. 20, 2015
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MX69N-E
PACKAGE INFORMATION
P/N:PM1648
REV. 1.4, MAR. 20, 2015
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MX69N-E
REVISION HISTORY
Revision No. Description
0.01
1. Added MX69N28E64AXJW & MX69N28E64FXJW
2. Modified table-PIN DESCRIPTION
Page
P3,5,7
P6
Date
JAN/18/2011
1.0
1. Removed Advanced Information
P2
MAY/30/2011
1.1
1. Modified Product Selection Guide
P3
MAY/10/2012
1.2
1. Removed 128Mb
All
JUL/22/2013
1.3
1. Modified Pin Configuration
P5
JUL/04/2014
1.4
1. Removed MX69N64E32BXJW
2. Updated speed from 104MHz to 108MHz
P3
P2,3
MAR/20/2015
P/N:PM1648
REV. 1.4, MAR. 20, 2015
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MX69N-E
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