M62301SP/FP 10 to 12-bit 4-ch Integrating A/D Converter REJ03D0861-0300 Rev.3.00 Mar 25, 2008 Description M62301 semiconductor integrated circuit forms an integrating A/D converter, being connected to a microcomputer unit. By using selection signals and counter clock signals from the unit, a 10 to 12-bit A/D converter can be created at a low cost. The integration time and resolution can be set at the users option by changing external parameters. In addition, the built-in circuit offset, delay time and temperature fluctuation are adjustable, enabling a wide range of applications. M62301 has a 3 input decoder circuit, high-precision reference voltage (1.22 V) generator, current supply and comparator for integration, and voltage-monitoring reset circuit for a 5 V power supply. It is also equipped with girdling to prevent current leak from integration capacitor. Features • Separate power supplies for analog section and digital section. • Low power dissipation: 2 mA (Typ) (1 mA for A/D conversion and the other 1 mA for reset) • Linear error: ±0.02% (Typ) • Conversion time: 526 µs/ch (Typ) • Built-in system reset: 4.45 V (Typ) Application High-precision control systems such as temperature control and speed control Block Diagram Constant current control Analog Analog Digital Digital VCC GND GND VDD 12 11 10 20 14 A1 A2 A2 18 + − 0.49 V A3 A3 17 + − A4 A4 16 Logic control A1 19 5 INT 1 VCC for RESET 6 RESET 0.36 V VREF Reference 15 input GND 150 µs Discharge + − Decoder + − Reference 13 voltage VREF 1.22 V 7 8 9 2 3 4 Guard Integrating Guard C0 C1 C2 ring 1 capacitor ring 2 REJ03D0861-0300 Rev.3.00 Mar 25, 2008 Page 1 of 11 Delay circuit M62301SP/FP Pin Arrangement M62301SP/FP VCC for RESET 1 20 Digital GND C0 2 19 A1 C1 3 18 A2 C2 4 17 A3 INT 5 16 A4 RESET 6 15 Reference input Guard ring 1 7 14 Digital VDD Integrating capacitor 8 13 Reference voltage Guard ring 2 9 12 Constant current control Analog GND 10 11 Analog VCC (Top view) Outline: PRDP0020BA-A (20P4B) PRSP0020DA-A (20P2N-A) Absolute Maximum Ratings (Ta = 25°C, unless otherwise noted) Item Analog section supply voltage Digital section supply voltage Digital input voltage Analog input voltage INT output current Reset output current INT output withstand voltage Reset output withstand voltage Reset supply voltage Power dissipation Thermal derating Operating temperature Storage temperature REJ03D0861-0300 Rev.3.00 Mar 25, 2008 Page 2 of 11 Symbol VCC VDD VID VIA IOINT IORE VINT VRESET VRE Pd Kθ Topr Tstg Ratings 15 8 –0.3 to VDD + 0.3 –0.3 to VDD + 0.3 6 6 15 15 6 990 (P) / 660 (FP) 9.9 (P) / 6.6 (FP) –20 to +75 –40 to +125 Unit V V V V mA mA V V V mW mW/°C °C °C M62301SP/FP Recommended Operating Conditions (Ta = 25°C, unless otherwise noted) Min Limits Typ Analog section supply voltage Digital section supply voltage Analog input voltage range (Il = 50 µA) VCC VDD VIA 4.5 4.5 0 8.0 5.0 — Reference input voltage (Il = 50 µA) VIR 1 — Integration capacity Resistance to determine charge current Output current CI RI IO 300 6 — — — — Item Note: Symbol Max Unit 12.0 5.5 V V V No more than (VCC – 2.5 V) 1 and VDD* No more than (VCC – 2.5 V) 1 and VDD* 22000 60 4 V pF kΩ mA 1. Maximum analog input voltage is less than the difference between VCC – 2.5 V as well as VDD. VREF Charging current II = R1 Electrical Characteristics (VCC = 5.0 V, VDD = 5.0 V, Ta = 25°C, unless otherwise noted) Reset Section A/D Converter Item Symbol Min Limits Typ — 0 1.0 — Max Unit 2.0 2.5 2.2 1.27 mA V µA %/FSR %/FSR µs Supply current Analog input voltage range ICC VIA Reference input voltage VREF 1.17 1.22 Permissible current inflow at reference voltage IREF+ — — Conversion error Linear error Conversion time IREF– EC EL TT — — — 0.05 0.02 526 50 –10 0.1 0.09 — Discharge time Tdi — 3 17 µs Analog input current Digital input "H" level Digital input "L" level INT output "L" level INT output leak current Detection voltage IB VIH VIL VLINT IOHINT VDET — 3.5 — — — 4.30 –0.35 — — 0.1 — 4.45 –3.5 — 0.8 0.4 1 4.60 µA V V V µA V Hysteresis voltage Delay time Reset output "L" level Reset output leak current Supply current Limit operating voltage ∆VDET TDE VLRE IOHRE IRE VOPL 30 75 — — — — — 50 150 0.1 — 1.0 0.75 0.6 80 300 0.4 1 2.0 1.0 0.8 mV µs V µA mA V V Test Conditions Il = 100 µA Il = 200 µA IREF = ±5 µA CREF = 4700 pF Rl = 24 kΩ*1 Rl = 24 kΩ*2 VIA = 2.5 V, Cl = 0.01 µF Rl = 24 kΩ V(8) = 3 V → 0.3 V Cl = 4700 pF IOL = 1 mA V(5) = 15 V IOL = 1 mA V(6) = 15 V VRE = 5 V RL = 2.2 kΩ, VLRE ≤ 0.4 V RL = 100 kΩ, VLRE ≤ 0.4 V Notes: 1. Conversion error; Deviation from the line that links the "0" scale point (mode 0) and reference scale point (mode 3. VFSR = 2.5 V). Associated with all channels. 2. Linear error; Deviation from the line that links the 0 V input point and 2.5 V input point on a given channel. REJ03D0861-0300 Rev.3.00 Mar 25, 2008 Page 3 of 11 M62301SP/FP Operating Description (1) Decoder Based on digital inputs to C0, C1, C2, the analog switch is set to on, and the input of "0" scale (GND input), input of reference scale (reference voltage input), input to A1-A4, or discharge from integration capacitor (CI) is performed. None of these operations is performed when the "mode 8" input is given: Mode 1 2 3 4 5 6 7 8 C0 C1 C2 0 0 0 Discharge 1 0 0 GND 0 1 0 1 1 0 A1 0 0 1 A2 1 0 1 A3 0 1 1 A4 1 1 1 — 3 1 VREF (2) A/D conversion Decoder selection mode 1 2 1 4 to 7 1 VIN + 0.49 V V (8) VREF + 0.49 V 0.49 V 0.36 V TGND TIN TREF Multiplexer first selects VGND, obtaining minimum pulse TGND. It then selects VREF, obtaining reference pulse TREF. Input is selected next, obtaining input pulse TIN. VIN is obtained by deducting TGND, as the offset, from TREF and TIN. VIN = VREF • TIN − TG TREF − TG By measuring voltage at the maximum input for approximately 500 µs under the counter clock of 8 MHz, resolution of approximately 12 bits can be obtained; 500 µs 125 ns ≈ 212 Note: To ensure discharge from capacitor CI, the decoder input as in the above diagram should stay in mode 1 at least for the period calculated above: Tdi = (CI × VIAmax + 0.49 1 mA ) It is not necessary to measure TGND, and TREF for each channel. REJ03D0861-0300 Rev.3.00 Mar 25, 2008 Page 4 of 11 M62301SP/FP (3) Constant current control Integrating current II can be obtained based on the reference voltage (1.22 V) by the built-in high-precision generator and resistance RI. II = 1.22 RI (A) .................... (1) Integration time TI can be calculated as follows; TI = (VIN + 0.49) CI II .................. (2) However, parameters such as built-in comparator offset voltage, analog switch offset, voltage leak current and delay time are not counted. II VREF 12 8 13 1.22 V RI CI 50 mA 4.45 V Reset supply voltage VRE 0.8 V t RESET output Output unsettled TDE TDE t When voltage applied to pin VRE becomes less than 4.45 V, the RESET output status becomes "L". If voltage increases over 4.50 V, the RESET status becomes "H" within 150 µs. REJ03D0861-0300 Rev.3.00 Mar 25, 2008 Page 5 of 11 M62301SP/FP Application Suggestion 1. 4-channel 11-bit A/D converter system 5V To microcomputer 5 V power supply 10 k 10 k 20 2 19 3 18 4 To counter 5 To RESET CINT 680 pF 6 7 M62301SP/FP To microcomputer control pin 1 16 15 14 8 50 µA 9 12 11 CI 4700 pF Note: CREF 4700 pF 13 10 Charge current II = Input analog voltage 17 II = 50 µA RI 1.22 V 24 kΩ 24 k ≈ 50 µA CREF: To stabilize reference voltage, be sure to connect capacitance of approximately 4700 pF. CINT: We suggest that this capacitance be connected to prevent malfunction due to noise. Use CI that leaks as slight current as possible. To prevent leak to the circuit board, we recommend providing guard ring (7), (9). Resolution depends on the number of microcomputer counter clock pulses that are generated while the INT output status is "high" at the maximum input voltage 2.5 V (VCC – 2.5 V). When the microcomputer counter clock frequency is 8 MHz, the resolution can be calculated by using the constant calculated above, as follows; 4700 pF × (2.5 + 0.13) 50 µA 1 8M ≈ 211 Therefore, the resolution of this system is approximately 11 bits. REJ03D0861-0300 Rev.3.00 Mar 25, 2008 Page 6 of 11 M62301SP/FP 2. 4-channel 12-bit A/D converter system Separate power supplies to analog section and digital section, analog input voltage range mode wider up to VDD, external reference voltage for integration. 8V To microcomputer 5 V power supply 10 k 10 k 20 2 A1 19 3 A2 18 4 To counter To RESET 5 CINT 680 pF 6 7 8 50 µA CI 6800 pF Note: M62301SP/FP To microcomputer control pin 1 Input analog voltage A3 17 A4 16 2.5 V 15 VDD 14 13 9 12 10 11 CREF 4700 pF To microcomputer 5 V power supply II = 50 µA RI 24 k CREF: To stabilize reference voltage, be sure to connect capacitance of approximately 4700 pF. CINT: We suggest that this capacitance be connected to prevent malfunction due to noise. Use CI that leaks as slight current as possible. To prevent leak to the circuit board, we recommend providing guard ring (7), (9). Because separate power supplies are provided for the analog are digital sections, the M62301 has two supply voltage VCC and VDD, enabling a wide analog input voltage range VIA. The upper limit of the range is required to be no more than the difference between VCC – 2.5 V as well as VDD, therefore, the analog input voltage range in this application is 0 V to 5 V. When the counter clock frequency is 8 MHz, resolution is; 6800 pF × 1 8M (5 + 0.13) 50 µA ≈ 212 An A/D converter system with resolution of approximately 12 bits can be formed. REJ03D0861-0300 Rev.3.00 Mar 25, 2008 Page 7 of 11 M62301SP/FP Recommended operational settings according to clock frequency, resolution, and time required for discharge (decoder mode 1) Counter Clock 8 MHz Resolution 10-bit 11-bit 12-bit 16 MHz 10-bit 11-bit 12-bit Note: 1. Discharge time Change Current Il (µA) 50 100 50 100 50 100 50 100 50 100 50 100 Tdi = ( CI × (VIAmax + 0.49) 1 mA Resistance to Determine Constant Current Rl (kΩ) 24 12 24 12 24 12 24 12 24 12 24 12 ) The values in this table apply when VIAmax is 5 V. REJ03D0861-0300 Rev.3.00 Mar 25, 2008 Page 8 of 11 Integration Capacitance Cl 1400 pF 2800 pF 2800 pF 5600 pF 5600 pF 12000 pF 700 pF 1400 pF 1400 pF 2800 pF 2800 pF 5600 pF Discharge Time Tdi (µs) 7.7 15.4 15.4 30.7 30.7 65.9 3.9 7.7 7.7 15.4 15.4 30.7 M62301SP/FP Typical Characteristics Analog Part Supply Current vs. Supply Voltage Thermal Derating 2.0 Analog Supply Current ICC (mA) Power Dissipation Pd (mW) 1000 800 600 400 200 0 0 0 25 50 75 100 125 0 5 10 Ambient Temperature Ta (°C) Analog Supply Voltage VCC (V) Standard Voltage vs. Ambient Temperature Linear Error 0.05 Linear Error EL (%/FSR) 1.24 Standard Voltage VREF (V) 1.0 1.23 1.22 1.21 1.20 1.19 −20 0.04 0.03 RI = 24 kΩ 0.02 RI = 12 kΩ 0.01 0 0 20 40 60 80 0 (OSR) Ambient Temperature Ta (°C) INT Output "L" Level vs. Output Current 1.0 2.0 Analog Input Range VIA (V) 2.5 (FSR) INT Output vs. Ambient Temperature INT Output "L" Level VLINT (mV) INT Output "L" Level VLINT (V) 1.0 0.9 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0 0.01 0.1 1 INT Output Current IO INT (mA) REJ03D0861-0300 Rev.3.00 Mar 25, 2008 Page 9 of 11 10 200 100 0 −20 0 20 40 60 Ambient Temperature Ta (°C) 80 M62301SP/FP Reset Supply Current vs. Supply Voltage Detection Voltage vs. Ambient Temperature 4.7 1.8 Detection Voltage VDET (V) Reset Supply Current IRE (mA) 2.0 1.6 1.4 1.2 1.0 0.8 0.6 0.4 0.2 0 0 1 2 3 4 5 6 7 8 4.4 4.3 0 20 40 60 80 Reset Voltage VCC VRE (V) Ambient Temperature Ta (°C) Reset Output "L" Level vs. Output Current Delay Time vs. Ambient Temperature 250 0.9 0.8 Delay Time TDE (µs) Reset Output "L" Level VREF (V) 4.5 4.2 −20 9 10 1.0 0.7 0.6 0.5 0.4 0.3 0.2 200 150 100 50 0.1 0 0.01 0.1 1 10 Reset Output Current IORE (mA) Limit Reset Voltage 2.0 1.8 Output Voltage VOUT (V) 4.6 1.6 1.4 1.2 1.0 0.8 RL = 2.2 kΩ 0.6 RL = 100 kΩ 0.4 0.2 0 0 0.6 1.0 Reset Voltage VCC VRE (V) REJ03D0861-0300 Rev.3.00 Mar 25, 2008 Page 10 of 11 2.0 0 −20 0 20 40 60 Ambient Temperature Ta (°C) 80 M62301SP/FP Package Dimensions RENESAS Code PRDP0020BA-A Previous Code 20P4B MASS[Typ.] 1.0g 11 1 10 c *1 E 20 e1 JEITA Package Code P-SDIP20-6.3x19-1.78 NOTE) 1. DIMENSIONS "*1" AND "*2" DO NOT INCLUDE MOLD FLASH. 2. DIMENSION "*3" DOES NOT INCLUDE TRIM OFFSET. *2 A A2 D Reference Dimension in Millimeters Symbol L A1 e1 D E A A1 A2 bp b3 c *3 b 3 e bp SEATING PLANE e L JEITA Package Code P-SOP20-5.3x12.6-1.27 RENESAS Code PRSP0020DA-A Previous Code 20P2N-A Min Nom Max 7.32 7.62 7.92 18.8 19.0 19.2 6.15 6.3 6.45 4.5 0.51 3.3 0.38 0.48 0.58 0.9 1.0 1.3 0.22 0.27 0.34 0° 15° 1.528 1.778 2.028 3.0 MASS[Typ.] 0.3g 20 E *1 HE 11 F 1 NOTE) 1. DIMENSIONS "*1" AND "*2" DO NOT INCLUDE MOLD FLASH. 2. DIMENSION "*3" DOES NOT INCLUDE TRIM OFFSET. 10 c Index mark *2 A2 D A1 L A Reference Symbol *3 e bp y Detail F D E A2 A1 A bp c HE e y L REJ03D0861-0300 Rev.3.00 Mar 25, 2008 Page 11 of 11 Dimension in Millimeters Min Nom Max 12.5 12.6 12.7 5.2 5.3 5.4 1.8 0.1 0.2 0 2.1 0.35 0.4 0.5 0.18 0.2 0.25 0° 8° 7.5 7.8 8.1 1.12 1.27 1.42 0.1 0.4 0.6 0.8 Sales Strategic Planning Div. Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100-0004, Japan Notes: 1. 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