M62384FP 8-Bit, 4-Channel, 3 to 5 V D-A Converter (Buffered) REJ03F0077-0200 Rev.2.00 Mar 25, 2008 Description The M62384 is a CMOS-structure semiconductor integrated circuit incorporating four 8-bit D-A converter channels with output buffer op-amps. Serial data transfer type input can easily be used through a combination of three lines: DI, CLK, and LD. Outputs incorporate buffer op-amps that have a drive capacity of 1 mA or above for both sink and source, and can operate over the entire voltage range from almost ground to VCC (0 to 5 V), making peripheral elements unnecessary and enabling configuration of a system with few component parts. Support of power supply voltages of 3 V to 5 V enables the M62384 to be used in a wide range of applications. Features • 12-bit serial data input (3-line type: SDI, SCK, SLD) • Serial data transfer clock frequency: 10 MHz (max.) • Output buffer op-amps Operable over entire voltage range from almost ground to VCC • Power-on reset and external reset functions • Chip select function Up to 4 chips connectable on the same bus • Supported power supply voltage: 3 V to 5 V (2.7 V to 5.5 V) Application Signal gain setting and automatic adjustment in CTV and display monitors, conversion from digital data to analog data in consumer and industrial products Pin Connection Diagram M62384FP GND 1 16 CS1 Ao1 2 15 CS0 Ao2 3 14 RST VCC 4 13 VDD Vref 5 12 SCK Ao3 6 11 SDI Ao4 7 10 SLD GND 8 9 VSS (Top view) Outline: PRSP0016DE-A (16P2N-A) This product is currently under development, and specifications and other details may be modified at a future date. REJ03F0077-0200 Rev.2.00 Mar 25, 2008 Page 1 of 7 M62384FP Block Diagram SDI 11 12-bit shift register SCK 12 VDD 13 VSS 9 Vref 8 Power-on reset RST 14 5 10 SLD Channel decoder 16 CS1 15 CS0 8-bit latch 8-bit latch 8-bit latch 8-bit latch 8-bit D-A 8-bit D-A 8-bit D-A 8-bit D-A 1 GND VCC 4 2 3 6 7 Ao1 Ao2 Ao3 Ao4 Pin Functions Pin No. Symbol Function 1, 8 GND Analog GND: analog circuit GND (D-A converter lower reference voltage) 2 3 6 7 4 Ao1 Ao2 Ao3 Ao4 Vcc D-A converter output pins (ch1 to ch4): full-swing buffer output Output voltage: Ao (00)h = 0V, Ao (FF)h = 255/256 × VREF 5 9 10 Vref Vss SLD D-A converter upper reference voltage input pin Digital GND Serial load signal input pin (Schmitt trigger input: with input hysteresis) When SLD is high, data is loaded from shift register into 8-bit latch corresponding to address. 11 SDI Serial data input pin (TTL input in case of 5 V power supply) Inputs serial data with a 12-bit data length (MSB-first). 12 SCK Serial clock signal input pin (Schmitt trigger input: with input hysteresis) At rising edge, data is read into shift register one bit at a time. 13 VDD Digital power supply pin (3 V to 5 V) When power supply rises, D-A output is reset (0 V output: power-on reset). 14 RST Forced reset pin (TTL input in case of 5 V power supply) L: D-A output (AO1 to 4) = Fixed setting of 0 V H: Reset release (power-on reset operation) 15 16 CS0 CS1 Chip select pins (TTL input in case of 5 V power supply) Access possible only when chip select data (D11, D10) and pin (CS1, CS0) logic match. Analog power supply (3 V to 5 V) Must rise simultaneously with VDD or after VDD rise. REJ03F0077-0200 Rev.2.00 Mar 25, 2008 Page 2 of 7 M62384FP Absolute Maximum Ratings (Unless specified otherwise, Ta = 25ºC) Item Symbol Power supply voltage VCC,VDD Digital input voltage Reference voltage input voltage D-A output voltage Permissible loss Operating ambient temperature Storage temperature VDIN Vref VAO Pd Topr Tstg Rated Value Unit –0.3 to 7.0 V –0.3 to Vcc+0.3 (≤ 7.0) –0.3 to Vcc+0.3 (≤ 7.0) –0.3 to Vcc+0.3 (≤ 7.0) 300 –20 to +75 –40 to +125 V V V mW °C °C Conditions DC voltage (“H” level) Recommended Operating Conditions (Unless specified otherwise, VCC = VDD = 5 V ±10%, Vref = 2 V to VCC, VSS = GND = 0 V, fsck = 5 MHz, VDINH = VDD, VDINL = VSS, Ta = 20ºC to 75ºC) Specification Values Item Symbol Analog power supply voltage Digital power supply voltage Reference voltage VCC VDD Vref Serial clock frequency “H” level digital input voltage “L” level digital input voltage Clock “H” pulse width Clock “L” pulse width Clock rise time Clock fall time Data setup time Data hold time Load setup time Load hold time Load “H” pulse width Reset “L” pulse width Load setup time after reset release fsck VDINH VDINL tsckH tsckL tsckR tsckF tDCH tCHD tCHL tLDC tLDH tRSTL tRCHL Min. Typ. 2.7 2.7 2.0 0.5VDD VSS 30 30 Max. Unit 5.5 5.5 5.5 V V V 10 VDD 0.2VDD MHz V V ns ns ns ns ns ns ns ns ns ns ns 200 200 10 20 40 20 20 50 50 Test Conditions VCC = VDD VCC = VDD Vref ≤ VCC VCC = VDD ≥ 2.7V VCC = VDD ≥ 2.7V Timing Chart t SCKR t SCKH t SCKF SCK t SCKL SDI t LDC t DCH t CHD t LDH t CHL SLD t LDD t RCHL AO RST t RSTL REJ03F0077-0200 Rev.2.00 Mar 25, 2008 Page 3 of 7 M62384FP Electrical Characteristics (Unless specified otherwise, VCC = VDD = 5 V ±10%, Vref = 2 V to VCC, VSS = GND = 0 V, fsck = 5 MHz, VDINH = VDD, VDINL = VSS, Ta = 20ºC to 75ºC) (1) Digital block Specification Values Item Symbol Digital block circuit current Input leakage current Input threshold voltage Input hysteresis voltage IDD IDINLK VDINT ∆VDINT Min. Typ. Max. Unit −1.0 0.2VDD 0 1.0 1.0 0.5VDD mA µA V mV 100 Test Conditions VDIN = VSS to VDD (2) Analog block Specification Values Item Symbol Min. Analog block circuit current Reference voltage input current ICC Iref Differential nonlinearity error Nonlinearity error Zero scale error Full-scale error Output current Settling time SDL SNL SZERO SFULL IAO tLDD −1.0 −1.5 −2.0 −2.0 ±0.5 Power-on reset voltage VPR 0.8 Typ. Max. Unit 0.8 0.5 2.0 1.0 mA mA No load 1.0 1.5 2.0 2.0 VCC = VDD = 2.7V to 5.5V IA0: With no load 5 10 LSB LSB LSB LSB mA µS 1.5 2.5 V Test Conditions All channels: Maximum current conditions VOA = 0.1V to VCC − 0.1V VOA = 0.5↔4.5V, IOA = 0.1mA, Co = 50pF output absorbed within ±0.5 LSB VCC = 0 V → 5 V, V0A = 0 V setting voltage (reference values) Digital Data Format MSB(First) D11 LSB D10 D8 D9 D7 D6 D5 Chip select data Address data D4 D3 D2 D1 D0 DAC data (1) Chip select data D11 D10 CS1 CS0 0 0 L L 0 1 1 1 0 1 L H H H L H Data is transferred only when logic of D11 and D10 matches CS pin setting (CS1, CS0). (2) Address data D8 D9 0 0 1 1 0 1 0 1 Channel Selection AO1 selected AO2 selected AO3 selected AO4 selected REJ03F0077-0200 Rev.2.00 Mar 25, 2008 Page 4 of 7 M62384FP DAC Data D7 D6 D5 D4 D3 D2 D1 D0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 1 0 1 (0/256)×Vref (1/256)×Vref (2/256)×Vref (3/256)×Vref 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 1 (254/256)×Vref (255/256)×Vref ⋅⋅ ⋅ ⋅⋅ ⋅ ⋅⋅ ⋅ ⋅⋅ ⋅ ⋅⋅ ⋅ ⋅⋅ ⋅ ⋅⋅ ⋅ ⋅⋅ ⋅ D-A output ⋅⋅ ⋅ Data Timing Chart SDI D11 D10 D9 D8 D2 D1 D0 SCK SLD Ao When SLD is high, data captured in the shift register is loaded into the 8-bit latch corresponding to the address. Therefore, SCK should be held high or low when SLD is high. REJ03F0077-0200 Rev.2.00 Mar 25, 2008 Page 5 of 7 M62384FP Sample Application Circuit SDI SCK MCU SLD RST RST SLD SCK SDI VCC VDD VCC Ao1 VDD Vref Chip select setting (connected to either VDD or GND) Vref CS0 Ao3 CS1 GND GND Ao2 Ao4 VSS M62384FP REJ03F0077-0200 Rev.2.00 Mar 25, 2008 Page 6 of 7 M62384FP Package Dimensions JEITA Package Code P-SOP16-5.3x10.1-1.27 RENESAS Code PRSP0016DE-A Previous Code 16P2N-A E 9 *1 HE 16 MASS[Typ.] 0.2g F NOTE) 1. DIMENSIONS "*1" AND "*2" DO NOT INCLUDE MOLD FLASH. 2. DIMENSION "*3" DOES NOT INCLUDE TRIM OFFSET. 1 8 Index mark A2 A1 c Reference Dimension in Millimeters Symbol D L A *2 e y *3 bp Detail F D E A2 A1 A bp c HE e y L REJ03F0077-0200 Rev.2.00 Mar 25, 2008 Page 7 of 7 Min Nom Max 10.0 10.1 10.2 5.2 5.3 5.4 1.8 0.1 0.2 0 2.1 0.35 0.4 0.5 0.18 0.2 0.25 0° 8° 7.5 7.8 8.1 1.12 1.27 1.42 0.1 0.4 0.6 0.8 Sales Strategic Planning Div. Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100-0004, Japan Notes: 1. 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