M62376GP 8-bit 12ch D/A Converter IC Built-in 12-bit I/O Expander REJ03D0881-0300 Rev.3.00 Mar 25, 2008 Description The M62376GP is a semiconductor IC that adopts a CMOS structure having 12 channels of 8-bit D/A converter and 12bit I/O expander. The IC has achieved a wide operation range of 2.7 to 5.5 V in power voltage. Data is easily available via 3-wire combination system serial input of SI, CLK and EN. The IC also provides an SO pin enabling cascade connection. It provides 8 pins that share D/A converter and I/O ports that can be arbitrarily switched with serial input data. Features • • • • Supply voltage: 2.7 to 5.5 V Adopts 4 special ports for each of DAC and I/O and 8 ports that share DAC output and I/O Each port can be set by serial data for input/output status Built-in power-on reset where D/A output is set to "L" in the initial status and I/O goes to high-impedance when power is turned on • Small package of 0.65 mm pitch and 24 pin Application Adjustment/control of industrial or home-use electronic equipment, such as VCR camera, VCR set, TV, and CRT display. Block Diagram RESET VDD VCC GND 23 13 14 24 SI 20 EN 22 CLK 19 Shift register 21 SO S15 S14 S13 S12 S11 S10 S9 S8 S7 S6 S5 S4 S3 S2 S1 S0 Clock control circuit Decoder 8-bit latch ...... 8-bit latch 8-bit latch ............ 8-bit latch 8-bit D/A converter ...... 8-bit D/A converter 8-bit D/A converter ............ 8-bit D/A converter − + ...... − + − + ............ A4 A1 Amp. Hi-Z 8-bit latch I/O select 12-bit latch (12) − + A5 A12 ............ ............ Output data 8-bit latch 1 A1 ...... 4 A4 5 D11/A5 REJ03D0881-0300 Rev.3.00 Mar 25, 2008 Page 1 of 10 ............ 12 D4/A12 Output data 4-bit latch 15 D3 ............ 18 D0 M62376GP Pin Arrangement M62376GP A1 1 24 GND A2 2 23 RESET A3 3 22 EN A4 4 21 SO D11/A5 5 20 SI D10/A6 6 19 CLK D9/A7 7 18 D0 D8/A8 8 17 D1 D7/A9 9 16 D2 D6/A10 10 15 D3 D5/A11 11 14 VCC D4/A12 12 13 VDD (Top view) Outline: PLSP0024JA-A (24P2E-A) Pin Description Pin No. 20 21 19 Pin Name SI SO CLK Function Serial data input pin. Enters serial data of 16-bit in length. Outputs data from 16-bit shift register that reads serial data or parallel data. 22 EN 1 2 3 4 5 6 7 8 9 10 A1 A2 A3 A4 D11/A5 D10/A6 D9/A7 D8/A8 D7/A9 D6/A10 Entry of low level into the EN pin starts to read data. Putting 16-bit data at high level after input loads the input data to a specified register. Special output pin for 8-bit D/A converter (DAC) 11 12 18 17 16 15 14 24 13 D5/A11 D4/A12 D0 D1 D2 D3 VCC GND VDD 23 RESET Shift clock input pin. At the rise of shift clock, input signal from the SI pin is entered into the 16-bit shift register. Pin that shares I/O and DAC output. Settings can be selected with serial data. D4 to D11 are connected to the VDD power supply. Digital input output pin. Digital block power supply pin. GND pin Power supply pin in analog block and reference voltage input pin on the upper side of D/A converter RESET pin REJ03D0881-0300 Rev.3.00 Mar 25, 2008 Page 2 of 10 M62376GP Block Diagram for Explanation of Terminals EN 22 CLK 19 VCC GND 13 14 24 [1110] Clock control circuit EN CLK SI 20 RESET 23 VDD Di11 Di10 Di9 Di8 Di7 Di6 Di5 Di4 Di3 Di2 Di1 Di0 Shift register S15 S14 S13 S12 S11 S10 S9 S8 21 SO S7 S6 S5 S4 S3 Power ON RESET S2 S1 S0 Level shift EN Level shift EN Decoder (12) Decoder (4) ......... [0000] 8-bit latch ... 8-bit latch 8-bit latch ............ 8-bit latch 8-bit latch 8-bit D/A converter 8-bit D/A converter ............ 8-bit D/A converter Level shift (11010000) (A5-A12 Hi-Z) [1111] 8-bit D/A converter − + ... ... − + A1 A4 − + ............ A5 (8) 12-bit latch (8) − + A12 (12) Level shift [1101] Latch (4) Latch (8) 1 A1 ...... 4 A4 5 D11/A5 ............ 12 D4/A12 15 D3 16 D2 17 D1 18 D0 Absolute Maximum Ratings Item Digital supply voltage Symbol VCC VDD Ratings –0.3 to +7.0 –0.3 to +7.0 Unit V V Analog supply (D/A converter upper reference voltage) Input voltage Output voltage Input voltage Output voltage Power dissipation Operating temperature Storage temperature VIN Vout VIN Vout Pd Topr Tstg –0.3 to VCC + 0.3 –0.3 to VCC + 0.3 –0.3 to VDD + 0.3 –0.3 to VDD + 0.3 200 –20 to +85 –40 to +125 V V V V mW °C °C REJ03D0881-0300 Rev.3.00 Mar 25, 2008 Page 3 of 10 Conditions VCC supply side pin VCC supply side pin VDD supply side pin VDD supply side pin M62376GP Electrical Characteristics <Recommended Operating Condition> Item Digital supply voltage Symbol VCC VDD Ratings 2.7 to 5.5 2.7 to 5.5 Unit V V Analog supply (D/A converter upper reference voltage) Input pin voltage (VCC part) Output pin voltage (VCC part) Input pin voltage (VDD part) Output pin voltage (VDD part) VIN VOUT VIN VOUT 0 to VCC 0 to VCC 0 to VDD 0 to VDD V V V V Conditions VDD ≥ VCC EN, SI, D0 to D3 SO, D0 to D3 RESET, D4/A12 to D11/A5 A1 to A4, D4/A12 to D11/A5 <Digital Part (VCC) > (VCC = 2.7 to 5.5 V, Ta = –20 to +85°C, unless otherwise noted.) Item Symbol Min Limits Typ Max Unit Conditions Supply voltage VCC 2.7 3.0 5.5 V Supply current ICC — 0.2 2.5 mA CLK = 1 MHz operation, VCC = 3 V, IAO = 0 µA Input leak current Input low voltage Input high voltage Output low voltage Output high voltage IILK VIL VIH VOL VOH VT+ — — — — — — 10 0.2 VCC — 0.4 — 0.5 VCC µA V V V V V VIN = 0 to VCC Forward threshold voltage (EN, CLK) –10 — 0.5 VCC — VCC – 0.4 — Backward threshold voltage (EN, CLK) VT– 0.2 VCC — — V IOL = 2.5 mA IOH = –400 µA <Digital Part (VDD) > (VDD = 2.7 to 5.5 V, Ta = –20 to +85°C, unless otherwise noted.) Item Supply voltage Input leak current Input low voltage Input high voltage Output low voltage Output high voltage Note: Symbol VDD IILK VIL VIH VOL VOH Min Limits Typ Max Unit 2.7 –10 — 0.5 VDD — VDD – 0.4 3.0 — — — — — 5.5 10 0.2 VDD — 0.4 — V µA V V V V For circuit current of VDD, see the analog block. REJ03D0881-0300 Rev.3.00 Mar 25, 2008 Page 4 of 10 Conditions VIN = 0 to VDD IOL = 2.5 mA IOH = –400 µA M62376GP <Analog Part> (VDD (VrefU) = 2.7 to 5.5 V, Ta = –20 to +85°C, unless otherwise noted.) Min Limits Typ Max Unit Dissipation current IDD — 1.5 3.5 mA VrefU = 3 V input data condition: When maximum current of R-2R rudder is supplied D/A converter upper reference voltage range VDD (VrefU) 2.7 — 5.5 V In the setup range of reference voltage, all values are not taken with output. Values to be taken depend on the item of buffer amplifier output voltage range. Buffer amplifier output voltage range VAO 0.1 0.2 — — VDD – 0.1 VDD – 0.2 V V Buffer amplifier output drive range IAO –0.3 — 1 mA Differential nonlinearity error Nonlinearity error Zero code error Full scale error Output capacitive load SDL –1.0 — 1.0 LSB SL SZERO SFULL CO –1.5 –2 –2 — — — — — — 5 1.5 2 2 10 — LSB LSB LSB µF Ω Item Buffer amplifier output impedance Symbol RO Conditions IAO = ±100 µA IAO = +500 µA –200 µA Upper saturation voltage = 0.4 V Lower saturation voltage = 0.4 V VDD = 2.700 V (VrefU) Without load (IAO = +0 µA) AC Characteristics (VCC, VDD = 2.7 to 5.5 V, Ta = –20 to +85°C, unless otherwise noted.) Item Symbol Min Limits Typ Max Unit Conditions Clock low pulse width Clock high pulse width Clock rise time Clock fall time Data setup time Data hold time Clock (EN) setup time EN setup time EN high hold time tCKL tCKH tCR tCF tDCH tCHD tCLH tCHL tENH 200 200 — — 30 60 100 200 200 — — — — — — — — — — — 200 200 — — — — — ns ns ns ns ns ns ns ns ns Serial data output delay time tSO Parallel data output delay time D/A output setting time tDO — — 200 400 350 600 ns ns CL = 100 pF CL = 100 pF tLDD — — 100 µs CL ≤ 100 pF, VAO: 0.1 ↔ 2.6 V Until output takes ±2 LSB of the final value. Input DUT Output CL REJ03D0881-0300 Rev.3.00 Mar 25, 2008 Page 5 of 10 M62376GP Timing Chart tENH EN tCLH tCR tCKH tCF tCHL CLK tCKL SI tDCH tDCH tCHD tCHD D0 to D11 input D0 to D11 output tSO tDO SO output tLDD A0 to A11 output REJ03D0881-0300 Rev.3.00 Mar 25, 2008 Page 6 of 10 M62376GP Data Structure Serial data MSB LSB S15 S14 S13 S12 S11 S10 S9 S8 S7 S6 S5 S4 S3 Data for DAC and I/O expander S2 S1 Address data Address Data S3 0 0 0 0 0 0 0 0 1 1 S2 0 0 0 0 1 1 1 1 0 0 S1 0 0 1 1 0 0 1 1 0 0 S0 0 1 0 1 0 1 0 1 0 1 1 1 1 1 1 1 0 0 1 1 1 1 1 1 0 0 1 1 0 1 0 1 0 1 Setup (a) A1 selection A2 selection A3 selection A4 selection A5 selection A6 selection A7 selection A8 selection A9 selection A10 selection A11 selection A12 selection I/O expander (serial → parallel conversion) I/O expander (parallel → serial conversion) I/O expander status setup • I/O expander (serial → parallel conversion) Outputs data on S4 to S15 to pins D0 to D11. S3 1 S2 1 S1 0 S0 1 • I/O expander (parallel → serial conversion) Writes data on D0 to D11 pins into S4 to S15. When next data communication is provided, outputs data sequentially from SO pin at the rise of the shift clock (CLK). S3 1 S2 1 S1 1 S0 0 S1 1 S0 1 • I/O expander status setup register Sets input/output pin of I/O expanders. Data: "0" = Input mode (Hi-Z status), "1" = Output mode S3 1 S2 1 Data S15 S14 S13 S12 S11 S10 S9 S8 S7 S6 S5 S4 Pin D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 REJ03D0881-0300 Rev.3.00 Mar 25, 2008 Page 7 of 10 S0 M62376GP DAC Data S15 0 0 0 : 1 1 X S14 0 0 0 : 1 1 X Note: S13 0 0 0 : 1 1 X S12 0 0 0 : 1 1 X S11 0 0 0 : 1 1 X S10 0 0 0 : 1 1 X S9 0 0 1 : 1 1 X S8 0 1 0 : 0 1 X S7 X X X : X X X S6 X X X : X X X S4* 0 0 0 : 0 0 1 S5 X X X : X X X Analog output voltage (Reference voltage on the lower side = 0.0 V fixed) (VDD / 256) × 1 [V] (1 LSB) (VDD / 256) × 2 [V] (2 LSB) (VDD / 256) × 3 [V] (3 LSB) : (VDD / 256) × 255 [V] (255 LSB) VDD [V] (256 LSB) High-impedance (I/O expander selected) X: Don’t care Only A5 to A12 outputs are available for DAC output by S4 and Hi-Z conversion. (a) Command to set DAC output to High-impedance (DACHiZ command) S15 S14 S13 S12 S11 S10 S9 S8 S7 S6 S5 S4 S3 S2 S1 S0 X X X X X X X X 1 1 0 1 0 0 0 0 Analog output voltage Sets D/A output of A5 to A12 to High-impedance. (b) Initial status just after power is turned on: Low level output from A1 to A4 (set to 00h) D4/A12 to D11/A5: DAC output of high-impedance (Hi-Z), I/O of input mode (Hi-Z) D0 to D3: input mode (Hi-Z) (c) The DACHiZ command is effective only for DAC settings (A5 to A12), but not for the I/O ports (D0 to D11) Note: To change the status of pins D4/A12 to D11/A5, switch both analog and digital after setup of high-impedance. Timing Chart (Model) EN ..... CLK ..... SI S0 ..... n-1 ..... S15 S0 S1 S2 S3 ..... n-1 n n n Parallel input (→Serial output) D0 to D11 ..... (Serial input→) Parallel output D0 to D11 ..... SO A1 to A12 H-Z S15 S0 ..... n-3 n-2 ..... REJ03D0881-0300 Rev.3.00 Mar 25, 2008 Page 8 of 10 S15 n-2 H-Z S15 S0 S1 S2 n-2 n-1 n-1 n-1 S3 ..... n-1 ..... S12 S13 S14 S15 n n n n S12 S13 S14 S15 n-1 n-1 n-1 H-Z M62376GP Application Example VDD VCC 13 VDD 14 VCC 1 A1 DAC output Adjustment pins for analog IC Shared pins for DAC and I/O DAC output 2 A2 RESET 23 3 A3 EN 22 4 A4 SO 21 5 D11/A5 SI 20 6 D10/A6 CLK 19 (*) MCU 7 D9/A7 Adjustment pins for analog IC I/O Logic IC comparator 8 D8/A8 D0 18 9 D7/A9 D1 17 10 D6/A10 D2 16 11 D5/A11 D3 15 I/O Logic IC comparator 12 D4/A12 GND 24 Note: The RESET pin is directly connected with the power pin to use power-on reset. However, when forced reset is done from outside, the capacitance (0.1 to 10 µF) should be connected between RESET pin and ground to remove noise due to installation of line, etc. Precaution for Use This IC has two power supply pins and a ground pin. Superimposition of these pins with ripple and spike noise may cause reduction of conversion accuracy and occurrence of malfunction. Be sure to insert a capacitor between each power supply and the GND pin to stabilize D/A converting operation. The output buffer amplifier of this IC has strong characteristics against capacitive load. Accordingly, when the capacitance (10 µF Max) is connected between output and ground to remove jitter and noise due to installation of output line, no problem may occur in operation of DAC. However, notice that the removal results in lengthening the settling time. This IC also provides power-on reset function. To assure the resetting operation, power supply should be turned on in the order of timing shown in the diagram below. Order: 1. VCC → 2. VDD VDD Voltage VCC Time t Figure 1 Order for Power-on REJ03D0881-0300 Rev.3.00 Mar 25, 2008 Page 9 of 10 M62376GP Package Dimensions JEITA Package Code P-LSSOP24-5.6x7.8-0.65 RENESAS Code PLSP0024JA-A Previous Code 24P2E-A 13 24 E HE MASS[Typ.] 0.1g *1 NOTE) 1. DIMENSIONS "*1" AND "*2" DO NOT INCLUDE MOLD FLASH. 2. DIMENSION "*3" DOES NOT INCLUDE TRIM OFFSET. F A2 1 A1 12 Index mark c Reference Symbol *2 A L D Detail F *3 bp e D E A2 A A1 bp c y HE e y L REJ03D0881-0300 Rev.3.00 Mar 25, 2008 Page 10 of 10 Dimension in Millimeters Min 7.7 5.5 Nom Max 7.8 7.9 5.6 5.7 1.15 1.45 0 0.1 0.2 0.17 0.22 0.32 0.13 0.15 0.2 0° 10° 7.4 7.6 7.8 0.53 0.65 0.77 0.10 0.3 0.5 0.7 Sales Strategic Planning Div. Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100-0004, Japan Notes: 1. This document is provided for reference purposes only so that Renesas customers may select the appropriate Renesas products for their use. Renesas neither makes warranties or representations with respect to the accuracy or completeness of the information contained in this document nor grants any license to any intellectual property rights or any other rights of Renesas or any third party with respect to the information in this document. 2. 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