M62023L/P/FP System Reset IC with Switch for 3V Memory Back-up REJ03D0528-0200 Rev.2.00 Jun 15, 2007 General Description The M62023L/P/FP is a system reset IC that controls the memory backup function of an SRAM and an embedded RAM of a microcontroller. The IC outputs reset signals (RES/RES) to a microcontroller at power-down and power failure. It also shifts the power supply to RAMs from main to backup, outputs a signal (CS) that invokes standby mode, and alters RAMs to backup circuit mode. Features • • • • • • Built-in switch for selection between main power supply and backup power supply to RAMs Small difference between input and output voltages (IOUT = 80mA, VIN=3V): 0.15V typ. Detection voltage (power supply monitor voltage): 2.57V typ. Chip select signal output (CS) Two channels of reset outputs (RES/RES) Power on reset circuit. Application Power supply control systems for memory of microcontroller systems in electronic equipment such as OA equipment, industrial equipment, and home-use electronic appliances and SRAM boards with built-in backup function that require switching between external power supply and battery. Block Diagram SW VIN 3 1 VOUT 2 VBAT 8 CS 4 Ct D1 R1 Com Reset Circuit R2 1.24V RES 7 RES 5 Delay Circuit 6 GND REJ03D0528-0200 Rev.2.00 Jun 15, 2007 Page 1 of 12 M62023L/P/FP Pin Arrangement M62023P M62023FP M62023L 8 CS VOUT 1 8 CS 7 RES VBAT 2 7 RES 6 GND VIN 3 6 GND 5 RES Ct 4 5 RES (Top view) 4 Ct 3 VIN Outline: PRDP0008AA-A (8P4) [P] PRSP0008DE-C [FP] (recommend) PRSP0008DA-A (8P2S-A) [FP] (not recommend for new design) 2 VBAT 1 VOUT (Top view) Outline: PRSS0008AA-A (8P5) [L] Pin Description Pin No. Symbol Name 1 VOUT Power supply output 2 VBAT Backup power supply input VIN and VBAT are controlled by means of an internal switch and output through VOUT. The pin is capable of outputting up to 100mA. Use it as VDD of CMOS RAM and the like. Backup power supply is connected to this pin. If a lithium battery is used, insert a resistor in series for safety purposes. 3 4 VIN Ct Power supply input Delay capacitor connection pin +3V input pin. Connect to a logic power supply. A delay capacitor is connected to this pin. By connecting a capacitor, it is possible to delay each output. 5 RES Positive reset output 6 GND Ground Connect to the positive reset input of a microcontroller. The pin is capable of flowing 1mA sink current. Reference for all signals. 7 RES Negative reset output 8 CS Chip select output REJ03D0528-0200 Rev.2.00 Jun 15, 2007 Page 2 of 12 Function Connect to the negative reset input of a microcontroller. The pin is capable of flowing 1mA sink current. Connect to the Chip Select of RAM. The CS output is at low level in normal state thereby letting RAM be active. Under failure or backup condition, the CS output is set to high level, then RAM enters standby state disabling read/write function. The pin is capable of flowing a 1mA sink current. M62023L/P/FP Absolute Maximum Ratings (Ta = 25°C, unless otherwise noted.) Item Symbol Ratings Unit Input voltage VIN 7 V Output current IOUT 100 mA Power dissipation Pd 800 (L) / 625 (P) / 440 (FP) mW Thermal derating Conditions Kθ 8 (L) / 6.25 (P) / 4.4 (FP) mW/°C Operating temperature Topr –20 to +75 °C Storage temperature Tstg –40 to +125 °C Ta ≥ 25°C Electrical Characteristics (Ta = 25°C, unless otherwise noted.) Sysbol Min Typ Max Unit Detection voltage Item VS 2.44 2.57 2.70 V Hysteresis voltage Circuit current ∆VS 50 — 100 1.5 200 3.0 mV mA — — 6.5 0.1 10 0.2 VOH(Ct) — 2.0 0.15 2.4 0.3 — V VIN = 3V * VOL(Ct) VOH(RES) — 1.5 0.02 2.0 0.1 — V V VIN = 2V * 1 VIN = 2V * — 0.02 — — 0.04 0.2 V VIN = 3V * VIN = 3V, Isink = 1mA VOH(RES) 2.5 3.0 — V VIN = 3V * VOL(RES) — — 0.02 0.04 — 0.2 V VIN = 2V * VIN = 2V, Isink = 1mA VOH(CS) 1.3 2.40 1.6 2.47 — — V VIN = 2V * 2 VIN = 0V, VBAT = 3V * VOL(CS) — — 0.07 0.08 — 0.3 V VIN = 3V * VIN = 3V, Isink = 1mA IR — — — — ±0.5 ±0.5 µA 0.54 0.6 V Difference between input and output voltage Ct output voltage (high level) Ct output voltage (low level) RES output voltage (high level) RES output voltage (low level) RES output voltage (high level) RES output voltage (low level) CS output voltage (high level) CS output voltage (low level) Backup Di leak current ICC VDROP VOL(RES) V Test Conditions VIN (At change from H→L) ∆VS = VSH – VSL IOUT = 0mA VIN = 2V VIN = 3V IOUT = 50mA VIN = 3V IOUT = 80mA 1 1 1 1 1 2 1 VBAT = 3V VIN = 3V VIN = 0V IF = 10µA Backup Di forward direction voltage Delay time VF — tpd 10 27 55 ms VIN = 0V→3V, Ct = 4.7µF Response time td — 5.0 25.0 µs VIN = 3V→2V VOPL (RES) — 0.65 — V * RES limit voltage of operation 3 Notes: 1. Regarding conditions to measure VOH and VOL, voltage values are generated by internal resistance only and no external resistor is used. 2. These values are produced inserting an external resistor, RCS = 1MΩ, between the CS pin and GND. 3. With no external resistor (10kΩ internal resistance only). REJ03D0528-0200 Rev.2.00 Jun 15, 2007 Page 3 of 12 M62023L/P/FP Application Example M62023 +3.0V (Main Power Supply) VIN VOUT SW 1 3 D1 CIN*1 R1 VBAT Com Reset Circuit VDD 2 R2 MCU or CPU 8 1.24V RES 7 5 RES REJ03D0528-0200 Rev.2.00 Jun 15, 2007 Page 4 of 12 Delay Circuit 4 Battery 3V CS CMOS RAM Ct Ct GND 6 COUT*1 VDD M62023L/P/FP Configuration <Power supply detector> The internal reference voltage Vref is compared by means of a comparator with resistor divided voltage VR (resistordivided voltage produced by R1 and R2 from VIN). If the input voltage is 3V, VR is set to 1.24V or higher, so the comparator output is at low level and the Ct output (Q1 collector output) is set to high level. If the input voltage drops to below 2.57V in an abnormal condition, VR becomes below 1.24V, so the comparator output goes from low to high level and the Ct output, from high to low. The input voltage at this point is called VSL. Next, when the input voltage, restored from abnormal state, has a rise, the comparator output goes from high to low level and the Ct output, from low to high. Ct output VO (Ct) (V) The comparator used for detection has 100mV hysteresis (∆Vs), so that malfunctioning is prevented in case that the input voltage slowly drops or VR nearly equals Vref. 3.0 ∆Vs 2.0 VSL 1.0 0 VSH 2.4 2.5 2.6 2.7 2.8 2.9 Input voltage VIN (V) <Delay Circuit> Connecting an external capacitor to the Ct pin lets RES, RES, CS, and VOUT be delayed due to RC transient phenomenon (electric charge). Delay time is determined as follows. Delay time (tpd) = Ct×R3×In [VOH(Ct)-VOL(Ct)] [VOH(Ct)-INV1(VTH)] 3 Note: Ct is an external capacitance. Taking into consideration the time taken by the oscillator of microcomputer to be stable, connect a 4.7µF capacitor to the Ct pin. (As the response time of detection can be slowed due to internal structure depending on the rising rate of power supply, avoid connecting a too large capacitance.) tpd VOH (Ct) INV1 (Vth) VOL (Ct) Delayed output waveforms of Ct REJ03D0528-0200 Rev.2.00 Jun 15, 2007 Page 5 of 12 M62023L/P/FP <Schmitt trigger circuit> Since waveforms show a gentle rise due to the RC delay circuit, INV1, INV2, and R6 constitute a Schmitt trigger circuit to produce hysteresis so as to prevent each output from chattering. Internal Circuit Ct VIN RES RES 4 3 5 7 Q4 VR R1 25.6kΩ R3 22kΩ Com R4 0Ω Q1 R5 10kΩ R8 10kΩ R7 10kΩ R6 47kΩ Q2 Vref 1.24V R11 10kΩ INV1 INV2 INV3 INV4 INV5 INV6 INV7 INV8 REJ03D0528-0200 Rev.2.00 Jun 15, 2007 Page 6 of 12 INV9 R9 5kΩ VOUT 2 VBAT 8 CS 6 GND D1 R10 800Ω Q3 R2 24kΩ 1 R10 22kΩ Q5 M62023L/P/FP Timing Chart tpd tpd 3V VSH VSL VIN ∆Vs 0V V1 VOUT V2 V3 V2 V3 CS VOL(CS) 3V VIN(VSL) RES VOL(RES) VOH(RES) VIN(VSL) RES VOL(RES) V1=VIN-VDROP V2=VIN-VEB(SW Tr.) V3=VBAT-VF Input voltage In normal operation Output pin Input voltage: 3V In failure (instantaneous drop) Restoration from failure (instantaneous drop) In backup state Input voltage: 3V→2V Each output varies if the input voltage drops to VSL or under Input voltage: 2V→3V If the input voltage goes higher than VSL by 100mV, each output varies after delay produced by the delay circuit. Input voltage: 0V VBAT-VF VOUT With SW Tr. set to ON, a voltage (VIN-VDROP) is output. SW Tr. is turned OFF. A voltage (VIN-VEB) is output by the diode between E and B of SW Tr. SW Tr. is turned ON after delay and a voltage (VIN-VDROP) is output. RES The output level is VOL (RES) with a logic low. As the state shifts from a logic low to logic high, the output level becomes approximately equal to the input voltage. A logic high is maintained, and then shifts to a logic low. RES The output level is VOH(RES) with a logic high. As the state shifts from a logic high to logic low, the output level becomes VOL(RES) A logic low is maintained, and then shifts to a logic high. CS The output level is VOL(CS) with a logic low. As the state shifts from a logic low to logic high, the output level becomes the voltage VIN-VEB. A logic high is maintained, and then shifts to a logic low. REJ03D0528-0200 Rev.2.00 Jun 15, 2007 Page 7 of 12 Backup voltage: 3V The output is a logic high and the output level is VBAT-VF M62023L/P/FP Typical Characteristics Thermal Derating (Maximum Rating) Power dissipation P d (mW) 1000 M62023L 800 M62023P 600 M62023FP 400 200 0 0 25 125 100 75 Ambient temperature Ta (°C) 50 Hysteresis Voltage vs . Ambient Temperature 2.64 140 2.63 130 2.62 120 2.61 110 2.60 100 v Detection voltage Vs (V) Detection Voltage vs . Ambient Temperature 2.59 90 2.58 80 2.57 70 2.56 -20 0 60 20 40 60 80 100 -20 0 20 40 60 80 100 Ambient temperature Ta (°C) Ambient temperature Ta (°C) 9 Circuit Current vs. Ambient Temperature 4.0 Circuit Current vs. Ambient Temperature VIN = 2V VIN = 3V Circuit current Icc (mA) Circuit current Icc (mA) 10 Tj = 25°C 8 7 6 5 4 3.5 3.0 2.5 2.0 1.5 1.0 0.5 3 2 -20 0 20 40 60 80 100 Ambient temperature Ta (°C) REJ03D0528-0200 Rev.2.00 Jun 15, 2007 Page 8 of 12 0 -20 0 20 40 60 80 100 Ambient temperature Ta (°C) M62023L/P/FP Output Current vs. Difference Between Input and Output Voltages Difference Between Input and Output Voltages vs. Ambient Temperature 400 VIN = 3V 350 80 Difference between input and output voltages VDROP (mV) Output current IOUT (mA) 100 60 40 20 0 0 50 100 150 200 250 300 250 IOUT=100mA 200 IOUT=80mA 150 IOUT=50mA 100 50 0 -20 c 140 120 d 100 80 f 60 40 20 0 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 Backup Di forward direction voltage VF (V) 160 0.8 0.7 0.6 60 50 40 30 20 10 0 -20 0 20 40 60 80 100 Ambient temperature Ta (°C) REJ03D0528-0200 Rev.2.00 Jun 15, 2007 Page 9 of 12 RES "L" output voltage VOL (RES) (mV) RES "L" output voltage VOL (RES) (mV) 70 IF=100µA 0.5 IF=10µA 0.4 0.3 IF=1µA 0.2 0.1 0 RES "L" Output Voltage vs . Ambient Temperature VIN=3V Isink =1mA 20 40 60 80 100 Backup Di Forward Direction Voltage vs. Ambint Temperature Backup Di forward direction voltage VF (V) 80 0 Ambient temperature Ta (°C) Difference between input and output voltages VDROP (mV) Backup Di Forward Direction Current vs. Voltage VIN = 3V 80 70 -20 0 20 40 60 80 100 Ambient temperature Ta (°C) RES "L" Output Voltage vs. Ambient Temperature VIN=2V Isink =1mA 60 50 40 30 20 10 0 -20 0 20 40 60 80 100 Ambient temperature Ta (°C) CS "L" Output Voltage vs. Ambint Temperature CS "H" output voltage VOH (CS) (mV) CS "L" output voltage VOL (CS) (mV) M62023L/P/FP 160 VIN=3V Isink =1mA 140 120 100 80 60 40 20 VIN=2V RCS=1MΩ 3.6 3.4 3.2 3.0 2.8 2.6 -20 0 20 40 60 80 100 Ambint temperature Ta (°C) -20 0 20 40 60 80 100 Ambient temperature Ta (°C) Delay Time vs. External Capacitance Connected to The Ct Pin 7 5 40 VIN=0V 3V 35 Delay time tpd (ms) 3 Delay time tpd (ms) 3.8 2.4 0 1000 4.0 CS "H" Output Voltage vs. Ambient Temperature 2 100 7 5 3 2 10 7 5 30 Delay Time vs. Ambient Temperature VIN=0V 3V Ct=4.7µA 25 20 15 10 3 5 2 1 0.1 2 3 5 7 1 2 3 5 7 10 2 3 5 7 External capacitance connected to the Ct pin Ct (µF) REJ03D0528-0200 Rev.2.00 Jun 15, 2007 Page 10 of 12 100 0 -20 0 20 40 60 80 100 Ambient temperature Ta (°C) M62023L/P/FP Package Dimensions JEITA Package Code P-SIP8-6.4x19-2.54 RENESAS Code PRSS0008AA-A Previous Code 8P5 2.8 ±0.2 ±0.2 2.54 0.5 ±0.1 0.85 3.0 Min 1.2 Min 8.3 Max 6.4 19.0 MASS[Typ.] 0.73g +0.3 -0.1 1.2 ±0.1 1.2 +0.1 -0.3 RENESAS Code PRDP0008AA-A 5 1 4 MASS[Typ.] 0.5g c *1 E 8 Previous Code 8P4 +0.07 -0.05 e1 JEITA Package Code P-DIP8-6.3x8.84-2.54 0.27 NOTE) 1. DIMENSIONS "*1" AND "*2" DO NOT INCLUDE MOLD FLASH. 2. DIMENSION "*3" DOES NOT INCLUDE TRIM OFFSET. *2 L A1 A A2 D SEATING PLANE *3 b 3 *3 b 2 bp e Reference Symbol e1 D E A A1 A2 bp b2 b3 c e L REJ03D0528-0200 Rev.2.00 Jun 15, 2007 Page 11 of 12 Dimension in Millimeters Min Nom Max 7.32 7.62 7.92 8.7 8.9 9.1 6.15 6.3 6.45 4.5 0.51 3.3 0.4 0.5 0.6 0.9 1.0 1.3 1.4 1.5 1.8 0.22 0.27 0.34 15° 0° 2.29 2.54 2.79 3.0 M62023L/P/FP JEITA Package Code P-SOP8-4.4x4.85-1.27 RENESAS Code PRSP0008DE-C *1 Previous Code — MASS[Typ.] 0.1g F D 8 NOTE) 1. DIMENSIONS"*1 (Nom)"AND"*2" DO NOT INCLUDE MOLD FLASH. 2. DIMENSION"*3"DOES NOT INCLUDE TRIM OFFSET. 5 c *2 E HE bp Index mark Terminal cross section ( Ni/Pd/Au plating ) Reference Symbol 4 1 *3 e Z bp x M A A2 L1 A1 θ L y Detail F JEITA Package Code P-SOP8-4.4x5-1.27 RENESAS Code PRSP0008DA-A Min Nom Max 4.65 4.85 5.05 4.2 4.4 4.6 1.85 0.00 0.1 0.20 2.03 0.34 0.4 0.46 0.15 0.20 0.25 0° 8° 5.7 6.2 6.5 1.12 1.27 1.42 0.12 0.10 0.75 0.25 0.45 0.65 0.90 MASS[Typ.] 0.07g E 5 *1 HE 8 Previous Code 8P2S-A D E A2 A1 A bp b1 c c1 θ HE e x y Z L L1 Dimension in Millimeters F 1 NOTE) 1. DIMENSIONS "*1" AND "*2" DO NOT INCLUDE MOLD FLASH. 2. DIMENSION "*3" DOES NOT INCLUDE TRIM OFFSET. 4 Index mark c A2 *2 A1 D L A Reference Symbol *3 e bp y D E A2 A1 A bp c Detail F HE e y L REJ03D0528-0200 Rev.2.00 Jun 15, 2007 Page 12 of 12 Dimension in Millimeters Min Nom Max 4.8 5.0 5.2 4.2 4.4 4.6 1.5 0.05 1.9 0.35 0.4 0.5 0.13 0.15 0.2 0° 10° 5.9 6.2 6.5 1.12 1.27 1.42 0.1 0.2 0.4 0.6 Sales Strategic Planning Div. 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