HD74LVC74 Dual D-type Flip Flops with Preset and Clear REJ03D0347–0400Z (Previous ADE-205-066C (Z)) Rev.4.00 Jul. 22, 2004 Description The HD74LVC74 has independent data, preset, clear, and clock inputs Q and Q outputs in a 14 pin package. The logic level present at the data input is transferred to the output during the positive going transition of the clock pulse. Preset and clear are independent of the clock and accomplished by a low level at the appropriate input. Low voltage and highspeed operation is suitable at the battery drive product (note type personal computer) and low power consumption extends the life of a battery for long time operation. Features • • • • • • VCC = 2.0 V to 5.5 V All inputs VIH (Max.) = 5.5 V (@VCC = 0 V to 5.5 V) Typical VOL ground bounce < 0.8 V (@VCC = 3.3 V, Ta = 25°C) Typical VOH undershoot > 2.0 V (@VCC = 3.3 V, Ta = 25°C) High output current ±24 mA (@VCC = 3.0 V to 5.5 V) Ordering Information Part Name Package Type Package Code HD74LVC74FPEL HD74LVC74TELL SOP–14 pin (JEITA) TSSOP–14 pin FP–14DAV TTP–14DV Package Abbreviation FP T Taping Abbreviation (Quantity) EL (2,000 pcs/reel) ELL (2,000 pcs/reel) Note: Please consult the sales office for the above package availability. Function Table Inputs Outputs PR CLR CK D Q Q L H L H H H H L L H H H X X X ↑ ↑ L X X X H L X H L H *1 H L Q0 L H H *1 L H Q0 H H H H H ↓ X X Q0 Q0 Q0 Q0 H: L: X: ↓: ↑: Q0 : Note: High level Low level Immaterial High to Low transition Low to high transition Level to Q before the indicated steady input conditions was established. 1. Q and Q will remain high as long as preset and clear are low, but Q and Q are unpredictable, if preset and clear go high simultaneously. Rev.4.00 Jul. 22, 2004 page 1 of 6 HD74LVC74 Pin Arrangement 1CLR 14 VCC 1 CK 1D 2 D 13 2CLR PR CLR 1CK 3 Q Q 1PR 4 12 2D 11 2CK D 1Q 5 CK 10 2PR CLR PR 1Q 6 Q 9 2Q Q GND 7 8 2Q (Top view) Absolute Maximum Ratings Item Symbol Ratings Unit Supply voltage Input diode current Input voltage Output diode current VCC IIK VI IOK V mA V mA Output voltage Output current VCC, GND current / pin Storage temperature VO IO ICC or IGND Tstg –0.5 to 6.0 –50 –0.5 to 6.0 –50 50 –0.5 to VCC +0.5 ±50 100 –65 to +150 Conditions VI = –0.5 V VO = –0.5 V VO = VCC +0.5 V V mA mA °C Note: The absolute maximum ratings are values, which must not individually be exceeded, and furthermore, no two of which may be realized at the same time. Recommended Operating Conditions Item Symbol Ratings Unit Conditions Supply voltage VCC V Input / output voltage VI VO 1.5 to 5.5 2.0 to 5.5 0 to 5.5 Data retention At operation PR, CLR, CK, D Q, Q Operating temperature Output current Ta IOH IOL Input rise / fall time *1 tr, tf 0 to VCC –40 to 85 –12 –24 *2 12 24 *2 10 V °C mA mA ns/V Notes: 1. This item guarantees maximum limit when one input switches. Waveform: Refer to test circuit of switching characteristics. 2. Duty cycle ≤ 50% Rev.4.00 Jul. 22, 2004 page 2 of 6 VCC = 2.7 V VCC = 3.0 V to 5.5 V VCC = 2.7 V VCC = 3.0 V to 5.5 V HD74LVC74 Electrical Characteristics Ta = –40 to 85°C Item Symbol VCC (V) Min Max Unit Input voltage VIH 2.7 to 3.6 4.5 to 5.5 2.7 to 3.6 4.5 to 5.5 2.7 to 5.5 2.7 3.0 3.0 4.5 2.7 to 5.5 2.7 3.0 4.5 0 to 5.5 5.5 3.0 to 3.6 2.0 VCC×0.7 — — VCC –0.2 2.2 2.4 2.0 3.8 — — — — — — — — — 0.8 VCC×0.3 — — — — — 0.2 0.4 0.55 0.55 ±5.0 20 500 V VIL Output voltage VOH VOL Input current Quiescent supply current IIN ICC ∆ICC Rev.4.00 Jul. 22, 2004 page 3 of 6 Test Conditions V V IOH = –100 µA IOH = –12 mA IOH = –24 mA V IOL = 100 µA IOL = 12 mA IOL = 24 mA µA µA µA VIN = 5.5 V or GND VIN = VCC or GND VIN = one input at (VCC –0.6)V, other inputs at VCC or GND HD74LVC74 Switching Characteristics Ta = –40 to 85°C From (Input) To (Output) ns CLK Q, Q ns PR or CLR Q, Q Item Symbol VCC (V) Min Typ Max Unit Maximum clock frequency fmax tPLH tPHL 150.0 150.0 150.0 — 1.5 — — 1.5 — 4.0 3.0 3.0 2.0 2.0 2.0 4.0 4.0 4.0 6.0 5.0 4.0 3.0 2.0 2.0 — — — — — 6.0 5.0 4.0 6.5 5.0 4.0 — — — — — — — — — — — — — — — 3.0 15.0 — — — 9.0 8.0 6.5 9.0 8.0 6.5 — — — — — — — — — — — — — — — — — MHz Propagation delay time 2.7 3.3±0.3 5.0±0.5 2.7 3.3±0.3 5.0±0.5 2.7 3.3±0.3 5.0±0.5 2.7 3.3±0.3 5.0±0.5 2.7 3.3±0.3 5.0±0.5 2.7 3.3±0.3 5.0±0.5 2.7 3.3±0.3 5.0±0.5 2.7 3.3±0.3 5.0±0.5 2.7 2.7 tPLH tPHL Setup time tsu Hold time th Pulse width tw Recovery time trec Input capacitance Output capacitance CIN CO ns ns ns CK PR or CLR ns pF pF Test Circuit VCC Pulse Generator Zout = 50 Ω Input Pulse Generator Zout = 50 Ω Notes: See Function Table Input PR D CL = 50 pF CK CLR 1. CL includes probe and jig capacitance. 2. Test is put into the each flip flops. Rev.4.00 Jul. 22, 2004 page 4 of 6 Output Q Q 450 Ω 50 Ω Scope Output Q Q CL = 50 pF 450 Ω 50 Ω Scope HD74LVC74 Waveforms tf Input CLR tr 90 % Vref 10 % VIH 90 % Vref 10 % GND tw tf tr VIH 90 % Vref Input PR t rec Input CK t w (H) tf tr 90 % Vref 10 % 90 % Vref 10 % t s (H) Input D 90 % Vref 10 % tr t w (L) 90 % Vref 10 % 10 % tw GND t rec VIH Vref Vref Vref Vref GND t h (H) t s (L) t h (L) VIH 90 % Vref 10 % Vref Vref GND tf t PHL t PLH Vref Vref t PHL t PLH VOH Output Q Vref Vref VOL t PLH t PHL t PLH t PHL VOH Output Q Vref Vref Vref Vref VOL Symbol VIH Vref Notes: VCC = 2.7 V, 3.3±0.3 V VCC = 5.0±0.5 V 2.7 V VCC 1.5 V 1. tr = 2.5 ns, tf = 2.5 ns 2. Clock pulse input waveform : PRR = 10 MHz, duty cycle 50% 3. Data input waveform : PRR = 5 MHz, duty cycle 50% Rev.4.00 Jul. 22, 2004 page 5 of 6 50%VCC HD74LVC74 Package Dimensions As of January, 2003 Unit: mm 10.06 10.5 Max 8 5.5 14 1 2.20 Max *0.20 ± 0.05 7 1.42 Max *0.40 ± 0.06 1.15 0˚ – 8˚ 0.10 ± 0.10 1.27 0.20 7.80 +– 0.30 0.70 ± 0.20 0.15 0.12 M Package Code JEDEC JEITA Mass (reference value) *Ni/Pd/Au plating FP-14DAV — Conforms 0.23 g As of January, 2003 Unit: mm 4.40 5.00 5.30 Max 14 8 1 7 0.65 1.0 *0.20 ± 0.05 0.13 M 6.40 ± 0.20 *Ni/Pd/Au plating Rev.4.00 Jul. 22, 2004 page 6 of 6 0.07 +0.03 –0.04 0.10 *0.15 ± 0.05 1.10 Max 0.83 Max 0˚ – 8˚ 0.50 ± 0.10 Package Code JEDEC JEITA Mass (reference value) TTP-14DV — — 0.05 g Sales Strategic Planning Div. Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100-0004, Japan Keep safety first in your circuit designs! 1. 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