Powering the Next Generation of AMD Opteron™ Processors Presented by George Schuellein – IR David Bates - AMD ©2007. Advanced Micro Devices, Inc. All rights reserved. AMD, the AMD Arrow logo, AMD Opteron, and combinations thereof, are trademarks of Advanced Micro Devices. Other names are for informational purposes only and may be trademarks of their respective owners. November 2007 1 The Data Center Challenge Data Centers consumed 1.2% of total US electricity in 20051 This number grows at 4x the rate of server spending2 HP plans to reduce energy in servers by 20% by 20101 • Target to raise MIPS / W by 10x in 3 years (double every yr)1 Reference: 1. Business Week, March 2007, 2. IDC WW Server Power & Cooling Expense Report, 9/06 November 2007 2 Data Center Value Drivers MIPS / W (Efficiency) Efficiency savings add up quickly MIPS / Ft^2 (density) A watt saved in power MIPS / $ consumption saves at least a watt in cooling . Total cost of ownership A watt saved in power Reliability / Up-time consumption saves a dollar in data center costs Serviceability (remote control) Energy Efficient CPUs Modularity / Scalability and Voltage Regulators Configurability increase MIPS / Watt Reference: IBM & HP Websites November 2007 3 Next-generation AMD Opteron™ Processors “Barcelona” is the first x86 CPU to integrate four processing cores on a single silicon die New Dual Dynamic Power Management (DDPM), provides an independent power supply to the cores and to the memory controller, allowing the cores and memory controller to operate at different voltages, determined by usage Significant performance and MIPS-per-watt improvements Backwards compatible with existing AMD Opteron™ processor-based platforms November 2007 4 New “Barcelona” Power Management Techniques Dynamic adjustment of individual core frequencies Processor cores can reduce their voltage level even while the onchip memory controller runs at full speed. Service external memory requests independent from core p-state transitions Increased p-state opportunities lead to additional power savings “Clock gating” enables automatic shut-down of areas of logic not being utilized November 2007 5 AMD Opteron™ Processor Power Architecture Current generation processors Single power plane (VDD) for Core and on-chip Northbridge 6 bit PVI (parallel voltage identification) used by the processor to program output voltage 0.375V to 1.55V range 25mV LSB for 1.55V to 0.8V 12.5mV LSB for 0.8V to 0.375V Voltage regulator starts upon receiving an Enable signal IVDDMAX = 90.4 Amps DC Tolerance +/-50mV AC Tolerance (<5us) +/-100mV November 2007 6 AMD Opteron™ Processor Power Architecture “Barcelona” processor 2 independent power planes VDD supplies the Core VDDNB supplies the Northbridge 7 bit SVI (serial VID interface) 0.5 to 1.55V Range 12.5mV LSB Voltage regulator reads a 2 bit parallel boot VID from the SVI inputs upon Enable, then starts Voltage regulator responds to SVI commands after receiving a PWROK signal indicating all system rails are within regulation IVDDMAX = 95 Amps, IVDDNBMAX = 20 Amps DC Tolerance +/-50mV AC Tolerance (<5us) +/-100mV November 2007 7 AMD SVI (Serial VID Interface) What is SVI? SVI is a two wire (clock and data) bus that connects a single master (processor) to one or more slaves (voltage regulators) Based on fast-mode I2C/SMBus interface Programs voltage regulator output voltage Voltage regulators do not transmit data to processor Why SVI? Replaces the ever-growing parallel VID interface Allows independent VDD power rails Lower pin count/smaller package sizes for voltage regulator suppliers Specification owned and developed by AMD Increased flexibility for AMD and its technology partners Allows for quick enhancements for future processors November 2007 8 SMBus Send Byte Protocol 8 bit words Processor starts send byte by pulling SVD low Address for VDD or VDDNB next 7 clocks Voltage regulator sends ACK bit Processor sends VID byte Voltage regulator sends acknowledge bit (ACK) and moves output voltage to the new value November 2007 9 0.5 to 1.55V SVI Commands VDD VDDNB Data 1 1 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 Clock Address = 1100011 = Set VID on both Output 1 and Output 2 Write = 0, ACK = 0, Data = 0000000 = 1.55V, ACK = 0 November 2007 10 PVI/SVI Hybrid Voltage Regulator Allows a motherboard to accept either PVI or SVI processors Includes six I/Os for PVI 2 of 6 I/Os are clock and data inputs in SVI mode Reads VID1 upon Enable VID1 = 1 = SVI mode VID1 = 0 = PVI mode VDDNB voltage regulator remains off in PVI mode with it’s output in a high impedance state November 2007 11 The Power Design Triangle New Technology can improve all 3 goals and minimize the power triangle! November 2007 With a given Technology; Must make tradeoffs between the 3 goals 2 of 3 goals can be optimized; 3rd suffers Focus on 1 goal; 2nd & 3rd suffer 12 Goal Oriented Design Approach Low Cost/Size 750kHz Fsw “Value” MOSFETs VDD Output 4 Phase 120nH Inductors 34 x 22uF MLCC output caps VDDNB Output 1 Phase 150nH Inductor 1 x 220uF SP + 10 x 22uF MLCC Output Caps Heat sink November 2007 High Efficiency 300kHz Fsw “Performance” MOSFETs VDD Output 5 Phase 220nH Inductors 5 x 330uF SP + 10 x 1206 22uF + 20 x 0805 22uF + 8 x 0402 0.1uF MLCC Output Caps VDDNB Output 1 Phase 220nH Inductor 1 x 330uF SP + 10 x 1206 22uF + 10 x 0805 22uF MLCC Caps No heat sink 13 PVI/SVI Voltage Regulator Down 3.5 inch 1.2 inch Top Bottom 1.2 inch 2.5 inch November 2007 14 Load Line (droop) on VDD Reduces Output Capacitors 1.06 1.04 1.02 1 0.98 VDD VDDMAX 0.96 VDDMIN 0.94 0.92 1.06 0.9 98 84 70 56 42 28 14 0 1.04 1.02 1 VDDNB VDDNBMAX 0.98 VDDNBMIN 0.96 0.94 0.92 November 2007 18 .7 16 .0 13 .3 10 .7 8. 0 5. 3 2. 7 0. 0 0.9 15 Test Data for Low Cost/Size Design November 2007 16 VDD & VDDNB Efficiency Total VDD & VDDNB Efficiency vs % of Full Load Current @ VID = 1.2V, 25C, 400LFM 87 86 85 Efficiency % 84 83 82 81 80 79 78 77 76 10 20 30 40 50 60 70 80 90 100 % of VDD + VDDNB Full Load November 2007 17 VDD + VDDNB Power Loss Power Loss (watts) Power Loss vs % of VDD + VDDNB Full Load Current @ VID = 1.2V, 25C, 400LFM 26 24 22 20 18 16 14 12 10 8 6 4 2 0 0 10 20 30 40 50 60 70 80 90 100 % VDD + VDDNB Load Current VDD + VDDNB Loss VDD Loss VDDNB Loss 8.3 Watts / inch2 November 2007 18 VDD Thermals (with heat sink) Temperature versus % of VDD + VDDNB Full Load Current @ VID = 1.2V, 25C, 400LFM 65 60 Temperature (oC 55 50 45 40 35 30 25 0 10 20 30 40 50 60 70 80 90 100 % VDD + VDDNB Full Load Current November 2007 Heat Sink VDD Inductor VDDNB Inductor VDDNB PCB under inductor VDD PCB under Heatsink 19 Bode Plots @ VID = 1.1V, No Load VDD BW = 180kHz VDDNB BW = 125kHz November 2007 20 VDD 50-100A & VDDNB 8 – 20A Load Transient November 2007 21 Test Data High Efficiency Design November 2007 22 VDD Efficiency Efficiency vs Load Current @ VID = 1.2V, 25C, 400LFM 91 90 89 Efficiency % 88 87 86 85 84 83 82 15 20 25 30 35 40 45 50 55 60 65 70 75 80 85 90 95 Output Current (Am ps) November 2007 23 VDD Power Loss Power Loss vs Load Current @ VID = 1.2V, 25C, 400LFM 14 13 12 11 Watts 10 9 8 7 6 5 4 3 0 5 10 15 20 25 30 35 40 45 50 55 60 65 70 75 80 85 90 95 Output Current (Am ps) 5.6 Watts / inch2 November 2007 24 VDD Thermals (no heat sink) Temperatures vs Load Current @ VID = 1.2V, 25C, 400LFM 70 High Side FET 65 Low Side FET Degrees C 60 Driver IC 55 Inductor 50 Control IC 45 40 35 30 0 5 10 15 20 25 30 35 40 45 50 55 60 65 70 75 80 85 90 95 Output Current (Am ps) November 2007 25 SVI Voltage Regulator Module AMD defined standard VRM Dimensions, connector, and output capacitors specified by AMD Up to 6 Phase VDD 1 Phase VDDNB 4.74 inch 2 inch November 2007 26 Design Approach Spacious form factor allows 500kHz switching frequency, 5 + 1 phases, and “value” MOSFETs without heat sink Conservative design – large amount of bulk capacitance results in low control loop BW (Fsw/7) VDD Output 5 Phase 120nH 7 x 10mm ferrite bead inductors 9 x 470uF SP + 10 x 22uF Output Caps VDDNB Output 1 Phase 220nH 7 x 10mm ferrite bead inductor 9 x 470uF SP + 10 x 22uF Output Caps November 2007 27 VDD Efficiency November 2007 28 VDD Power Loss 2.9Watts / in2 – No cooling from motherboard November 2007 29 Thermal Image VID=1.1V, 25ºC, 500LFM, IVDD=95A, IVDDNB=20A, No Heat Sink November 2007 30 Summary AMD’s “Barcelona” brings new power requirements Separate supplies for CPU Core and memory Serial VID Control of VR Output Voltage “Barcelona” compatible components have been developed to provide Computing OEMs with a range of solutions for the “Power Design Triangle” November 2007 31