IRDC3899

IRDC3899-P1V05
SupIRBuck
TM
USER GUIDE FOR IR3899 EVALUATION BOARD
1.05Vout
DESCRIPTION
The IR3899 is a synchronous buck
converter, providing a compact, high
performance and flexible solution in a small
4mm X 5 mm Power QFN package.
Key features offered by the IR3899 include
internal Digital Soft Start/Soft Stop, precision
0.5Vreference voltage, Power Good,
thermal protection, programmable switching
frequency, Enable input, input under-voltage
lockout for proper start-up, enhanced line/
load regulation with feed forward, external
frequency synchronization with smooth
clocking, internal LDO and pre-bias startup.
Output over-current protection function is
implemented by sensing the voltage developed
across the on-resistance of the synchronous
Mosfet for optimum cost and performance and
the current limit is thermally compensated.
This user guide contains the schematic and bill
of materials for the IR3899 evaluation board.
The guide describes operation and use of the
evaluation board itself. Detailed application
information for IR3899 is available in the
IR3899 data sheet.
BOARD FEATURES
• Vin = +12V (+ 13.2V Max)
•Vout = +1.05V @ 0- 8A
• Fs=500kHz
• L= 1.2uH
• Cin= 4x10uF (ceramic 1206) + 1X330uF (electrolytic)
• Cout=4x22uF (ceramic 0805) + 1x470uF (SP-Cap, Polymer Aluminum)
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IRDC3899-P1V05
CONNECTIONS and OPERATING INSTRUCTIONS
A well regulated +12V input supply should be connected to VIN+ and VIN-. A maximum of 8A load should be
connected to VOUT+ and VOUT-. The inputs and output connections of the board are listed in Table I.
IR3899 has only one input supply and internal LDO generates Vcc from Vin. If operation with external Vcc
is required, then R15 can be removed and external Vcc can be applied between Vcc+ and Vcc- pins. Vin pin
and Vcc/LDO_Out pins should be shorted together for external Vcc operation.
The output can track voltage at the Vp pin. For this purpose, Vref pin is to be connected to ground (use zero
ohm resistor for R21). The value of R14 and R28 can be selected to provide the desired tracking ratio
between output voltage and the tracking input.
Table I. Connections
Connection
Signal Name
VIN+
Vin (+12V)
VIN-
Ground of Vin
Vout+
Vout(+1.05V)
Vout-
Ground for Vout
Vcc+
Vcc/ LDO_Out Pin
Vcc-
Ground for Vcc input
Enable
Enable
PGood
Power Good Signal
AGnd
Analog ground
LAYOUT
The PCB is a 4-layer board (2.23”x2”) using FR4 material. All layers use 2 Oz. copper. The PCB
thickness is 0.062”. The IR3899 and other major power components are mounted on the top side of the
board.
Power supply decoupling capacitors, the bootstrap capacitor and feedback components are located
close to IR3899. The feedback resistors are connected to the output at the point of regulation and are
located close to the SupIRBuck IC. To improve efficiency, the circuit board is designed to minimize the
length of the on-board power ground current path.
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IRDC3899-P1V05
Connection Diagram
Vin
Gnd
Gnd
Vout
Enable
VDDQ
Top View
Vref
Sync
S-Ctrl
AGnd
PGood Vsns Vcc+ Vcc-
Bottom View
Fig. 1: Connection Diagram of IR3899 Evaluation Boards
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IRDC3899-P1V05
Fig. 2: Board Layout-Top Layer
Single point connection
between AGnd and PGnd
Fig. 3: Board Layout-Bottom Layer
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IRDC3899-P1V05
Fig. 4: Board Layout-Mid Layer 1
Fig. 5: Board Layout-Mid Layer 2
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Vcc-
PGood
N/S
C10
N/A
49.9K
R17
Vcc+
R28
VCC
R14
0 ohm
Agnd VDDQ
R1
SYNC
15K
39pF
C11
R9
47.5K
1
2.2nF
C26
1nF
C12
S_Ctrl
R13
0 ohm
C23
2.2uF
VCC
S_Ctrl
Vp
Rt_Sy nc
AGnd
COMP
C32
1.0uF
IR3899
R7
R4
R3
9.09K
10K
R2
806ohm
N/A
PGnd
SW
PVin
C8
Vsns
PGND
N38703
C7
0.1uF
0.1uF
C24
N/S
R29
VCC
R15
9.09K
N/S
A
20 ohm
R6
R12
B
10K
R11
1.2uH
L1
0 ohm
C25
2200pF
11
12
13
0 ohm
R10
49.9K
R18
N/S
N/S
N/S
C28
0 ohm
R50
+ C35
+ C36
470uF
N/S
C29
C30
Fig. 6: Schematic of the IR3899 evaluation board
6
16
5
4
3
1
FB
N/S
7.5K
U1
C37
R19
2
VREF
1
15
Enable
R21
N/S
1
Boot
1
1
1
9
Vin
PGood
7
Vcc/LDO_OUT
10
14
Vsns
8
GND
17
VREF
1
1
1
1
1
Enable
1
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N/S
C27
N/S
C20
N/S
C19
C5
10uF
C6
10uF
C4
22uF
C18
10uF
C3
22uF
C17
10uF
22uF
C16
22uF
C15
1
1
Vout+
Vin-
Vin+
1
1
C14
0.1uFVout-
Vout
C1 +
N/S 330uF/25V
C2
Vin
IRDC3899-P1V05
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IRDC3899-P1V05
Bill of Materials
Item
Qty
Part Reference
Value
Description
Manufacturer
Part Number
1
1
C1
330uF
SMD Electrolytic F size 25V 20%
Panasonic
EEV-FK1E331P
2
4
C2 C3 C4 C5
10uF
1206, 25V, X5R, 20%
TDK
C3216X5R1E106M
3
3
C7 C14 C24
0.1uF
0603, 25V, X7R, 10%
Murata
GRM188R71E104KA01B
4
1
C12
1nF
0603,50V,X7R
Murata
GRM188R71H102KA01B
5
1
C8
2200pF
0603,50V,X7R
Murata
GRM188R71H222KA01B
6
1
C11
39pF
0603, 50V, NP0, 5%
Murata
GRM1885C1H390JA01D
7
4
C15 C16 C17 C18
22uF
0805, 6.3V, X5R, 20%
TDK
C2012X5R0J226M
8
1
C35
470uF
SP Cap, LX size, 2.5V, 20%
TDK
EEFLX0E471R4
9
1
C23
2.2uF
0603, 16V, X5R, 20%
TDK
C1608X5R1C225M
10
1
C26
2.2nF
0603, 25V, X7R, 10%
Murata
GRM188R71E222KA01J
11
1
C32
1.0uF
0603, 25V, X5R, 10%
Murata
GRM188R61E105KA12D
12
1
L1
1.2uH
SMD 1.8mΩ
Wurth Electronic
744325120
13
1
R1
15K
Thick Film, 0603,1/10W,1%
Panasonic
ERJ-3EKF1502V
14
2
R2 R11
10K
Thick Film, 0603,1/10W,1%
Panasonic
ERJ-3EKF1002V
15
2
R3 R12
9.09K
Thick Film, 0603,1/10W,1%
Panasonic
ERJ-3EKF9091V
16
1
R4
1k
Thick Film, 0603,1/10W,1%
Panasonic
ERJ-3EKF1001V
17
1
R6
20
Thick Film, 0603,1/10W,1%
Panasonic
ERJ-3EKF20R0V
18
1
R9
47.5K
Thick Film, 0603,1/10W,1%
Panasonic
ERJ-3EKF4752V
19
5
R10 R13 R14 R15 R50
0
Thick Film, 0603,1/10W
Panasonic
ERJ-3GEY0R00V
20
2
R17 R18
49.9K
Thick Film, 0603,1/10W,1%
Panasonic
ERJ-3EKF4992V
21
1
R19
7.5K
Thick Film, 0603,1/10W,1%
Panasonic
ERJ-3EKF7501V
22
1
U1
IR3899
PQFN 4x5mm
IR
IR3899MPBF
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IRDC3899-P1V05
TYPICAL OPERATING WAVEFORMS
Vin=12.0V, Vo=1.05V, Io=0-8A, Room Temperature, no airflow
Fig. 7: Start up at 8A Load
Ch1:Vin, Ch2:Vo, Ch3:PGood Ch4:Enable
Fig. 9: Start up with 0.9V Pre Bias , 0A
Load, Ch2:Vo
Fig. 11: Inductor node at 8A load
Ch3:LX
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Fig. 8: Start up at 8A Load,
Ch1:Vin, Ch2:Vo, Ch3:Vcc, Ch4:PGood
Fig. 10: Output Voltage Ripple, 8A load
Ch2: Vout ,
Fig. 12: Short circuit (Hiccup) Recovery
Ch2:Vout , Ch4:Iout
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IRDC3899-P1V05
TYPICAL OPERATING WAVEFORMS
Vin=12.0V, Vo=1.05V, Io=0-8A, Room Temperature, no air flow
Fig. 13: Transient Response, 2A to 6A step
Ch2:Vout
Ch4-Iout
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IRDC3899-P1V05
TYPICAL OPERATING WAVEFORMS
Vin=12.0V, Vo=1.05V, Io=0-8A, Room Temperature, no air flow
Fig. 14: Bode Plot at 8A load shows a bandwidth of 62.7KHz and phase margin of 51 degrees
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IRDC3899-P1V05
TYPICAL OPERATING WAVEFORMS
Vin=12.0V, Vo=1.05V, Io=0-8A, Room Temperature, no air flow
Fig (15) Soft start and soft stop using S_Ctrl pin
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IRDC3899-P1V05
Efficiency [%]
TYPICAL OPERATING WAVEFORMS
Vin=12.0V, Vo=1.05V, Io=0-8A, Room Temperature, no air flow
90
88
86
84
82
80
78
76
74
72
70
68
0.8
1.6
2.4
3.2
4
4.8
Io [A]
5.6
6.4
7.2
8
Fig.16: Efficiency versus load current
1.5
Power Loss [W]
1.3
1.0
0.8
0.5
0.3
0.0
0
1
2
3
4
Io [A]
5
6
7
8
Fig.17: Power loss versus load current
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IRDC3899-P1V05
THERMAL IMAGES
Vin=12.0V, Vo=1.05V, Io=0-8A, Room Temperature, No Air flow
Fig. 18: Thermal Image of the board at 8A load
Test point 1 is IR3899
Test point 2 is inductor
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IRDC3899-P1V05
PCB METAL AND COMPONENT PLACEMENT
Evaluations have shown that the best overall performance is achieved using the substrate/PCB layout
as shown in following figures. PQFN devices should be placed to an accuracy of 0.050mm on both X
and Y axes. Self-centering behavior is highly dependent on solders and processes, and experiments
should be run to confirm the limits of self-centering on specific processes. For further information, please
refer to “SupIRBuck™ Multi-Chip Module (MCM) Power Quad Flat No-Lead (PQFN) Board Mounting
Application Note.” (AN1132)
Figure 19: PCB Metal Pad Spacing (all dimensions in mm)
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IRDC3899-P1V05
SOLDER RESIST
IR recommends that the larger Power or Land Area pads are Solder Mask Defined (SMD.)
This allows the underlying Copper traces to be as large as possible, which helps in terms of current
carrying capability and device cooling capability. When using SMD pads, the underlying copper
traces should be at least 0.05mm larger (on each edge) than the Solder Mask window,
in order to accommodate any layer to layer misalignment. (i.e. 0.1mm in X & Y.)
However, for the smaller Signal type leads around the edge of the device, IR recommends that
these are Non Solder Mask Defined or Copper Defined. When using NSMD pads,
the Solder Resist Window should be larger than the Copper Pad by at least 0.025mm on
each edge, (i.e. 0.05mm in X&Y,) in order to accommodate any layer to
layer misalignment. Ensure that the solder resist in-between the smaller signal lead areas are at
least 0.15mm wide, due to the high x/y aspect ratio of the solder mask strip.
Figure 20: Solder resist
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IRDC3899-P1V05
STENCIL DESIGN
Stencils for PQFN can be used with thicknesses of 0.100-0.250mm (0.004-0.010"). Stencils thinner than
0.100mm are unsuitable because they deposit insufficient solder paste to make good solder joints with the
ground pad; high reductions sometimes create similar problems. Stencils in the range of 0.125mm-0.200mm
(0.005-0.008"), with suitable reductions, give the best results. Evaluations have shown that the best overall
performance is achieved using the stencil design shown in following figure. This design is for
a stencil thickness of 0.127mm (0.005").The reduction should be adjusted for stencils of other thicknesses.
Figure 21: Stencil Pad Spacing (all dimensions in mm)
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IRDC3899-P1V05
PACKAGE INFORMATION
Figure 22: Package Dimensions
IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, USA Tel: (310) 252-7105
TAC Fax: (310) 252-7903
This product has been designed and qualified for the Industrial market
Visit us at www.irf.com for sales contact information
Data and specifications subject to change without notice. 12/11
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