IRDC3897-P1V05 SupIRBuck TM USER GUIDE FOR IR3897 EVALUATION BOARD 1.05Vout DESCRIPTION The IR3897 is a synchronous buck converter, providing a compact, high performance and flexible solution in a small 4mm X 5 mm Power QFN package. Key features offered by the IR3897 include internal Digital Soft Start/Soft Stop, precision 0.5Vreference voltage, Power Good, thermal protection, programmable switching frequency, Enable input, input under-voltage lockout for proper start-up, enhanced line/ load regulation with feed forward, external frequency synchronization with smooth clocking, internal LDO and pre-bias startup. Output over-current protection function is implemented by sensing the voltage developed across the on-resistance of the synchronous rectifier MOSFET for optimum cost and performance and the current limit is thermally compensated. This user guide contains the schematic and bill of materials for the IR3897 evaluation board. The guide describes operation and use of the evaluation board itself. Detailed application information for IR3897 is available in the IR3897 data sheet. BOARD FEATURES • Vin = +1.5V (+ 1.65V Max) • Vcc = +5V • Vout = +1.05V @ 0- 4A • Fs= 400kHz • L= 0.47uH • Cin= 2x10uF (ceramic 1206) + 1x330uF (electrolytic) • Cout=4x22uF (ceramic 0805) 9/26/2012 1 IRDC3897-P1V05 CONNECTIONS and OPERATING INSTRUCTIONS A well regulated +1.5V input supply should be connected to VIN+ and VIN-. A maximum of 4A load should be connected to VOUT+ and VOUT-. The inputs and output connections of the board are listed in Table I. IR3897 has only one input supply and internal LDO generates Vcc from Vin. If operation with external Vcc is required, then R15 can be removed and external Vcc can be applied between Vcc+ and Vcc- pins. Vin pin and Vcc/LDOout pins should be shorted together for external Vcc operation. The output can track voltage at the Vp pin. For this purpose, Vref pin is to be connected to ground (use zero ohm resistor for R21). The value of R14 and R28 can be selected to provide the desired tracking ratio between output voltage and the tracking input. Table I. Connections Connection Signal Name VIN+ Vin (+1.5V) VIN- Ground of Vin Vout+ Vout(+1.05V) Vout- Ground for Vout Vcc+ Vcc/ LDO_out Pin (+5V) Vcc- Ground for Vcc input Enable Enable P_Good Power Good Signal AGnd Analog ground LAYOUT The PCB is a 4-layer board (2.23”x2”) using FR4 material. All layers use 2 Oz. copper. The PCB thickness is 0.062”. The IR3897 and other major power components are mounted on the top side of the board. Power supply decoupling capacitors, the bootstrap capacitor and feedback components are located close to IR3897. The feedback resistors are connected to the output at the point of regulation and are located close to the SupIRBuck IC. To improve efficiency, the circuit board is designed to minimize the length of the on-board power ground current path. 9/26/2012 2 IRDC3897-P1V05 Connection Diagram Vin Gnd Gnd Vout Enable VDDQ Top View Vref Sync S-Ctrl AGnd PGood Vsns Vcc+ Vcc- Bottom View Fig. 1: Connection Diagram of IR3899/98/97 Evaluation Boards 9/26/2012 3 IRDC3897-P1V05 Fig. 2: Board Layout-Top Layer Single point connection between AGnd and PGnd Fig. 3: Board Layout-Bottom Layer 9/26/2012 4 IRDC3897-P1V05 Fig. 4: Board Layout-Mid Layer 1 Fig. 5: Board Layout-Mid Layer 2 9/26/2012 5 PGood C10 N/A 49.9K R17 VCC SYNC 3.57k 60.4k R9 0.1nF C12 1 10nF 16 5 4 3 1 R13 0 ohm Enable C32 1.0uF IR3897 R7 R4 N38703 R3 3.01k R2 3.32K Vsns PGND C8 11 12 C7 0.1uF 0.1uF C24 0 ohm R29 VCC L1 3.01k N/S A 20 ohm R6 R12 B 3.32K R11 0.47uH N/S R15 C25 100 ohm 2200pF N/A PGnd SW PVin 13 0 ohm R10 0 ohm R18 N/S N/S 0 ohm R50 IR3897 + C35 N/S C29 C30 C20 N/S C27 N/S N/S C19 22uF C18 C17 22uF 22uF C16 1 1 1 1 1 1 Vout+ Vout+ Vin- Vin- Vin+ Vin+ 1 Vout- 1 C14 0.1uFVout- 4mmx5mm Power QFN package, Max Io=4A + C36 N/S 22uF C15 Vout C1 + N/S 330uF/25V C2 22uF, 0805, 6.3V, X5R, 20% N/S C28 C3 N/S Input ceramic: 1206 C4 10uF C5 10uF C6 N/S SPM6530T-R47M170 from TDK Fig. 6: Schematic of the IR3897 evaluation board C23 2.2uF VCC S_Ctrl Vp Rt_Sy nc AGnd COMP FB N/S N/S U1 C37 R19 S_Ctrl 6 VREF C26 120pF C11 R21 N/S R1 Agnd Agnd Agnd Agnd Agnd Agnd 1 2 VREF 1 15 Enable 1 1 1 Vcc+ 1 Vcc- 1 1 Boot 1 N/S 1 1 9 Vin PGood 7 Vcc/LDO_OUT 10 14 Vsns 8 GND 17 R28 1 1 R14 0 ohm 1 1 Agnd VDDQ 1 1 9/26/2012 1 Vin IRDC3897-P1V05 6 IRDC3897-P1V05 Bill of Materials Item Qty Part Reference Value Description Manufacturer Part Number 1 1 C1 330uF SMD Electrolytic F size 25V 20% Panasonic EEV-FK1E331P 2 2 C4 C5 10uF 1206, 16V, X5R, 20% TDK C3216X5R1C106M 3 3 C7 C14 C24 0.1uF 0603, 25V, X7R, 10% Murata GRM188R71E104KA01D 4 1 C12 0.1nF 0603, 50V, 5% Murata GRM1885C1H101JA01D 5 1 C8 2.2nF 0603,50V,X7R Murata GRM188R71H222KA01D 6 1 C11 120pF 0603, 50V, NP0, 5% Murata GRM1885C1H121JA01D 7 4 C15 C16 C17 C18 22uF 0805, 6.3V, X5R, 20% TDK C2012X5R0J226M 8 1 C23 2.2uF 0603, 16V, X5R, 20% TDK C1608X5R1C225M 9 1 C26 10nF 0603, 25V, X7R, 5% TDK C1608C0G1E103J 10 1 C32 1.0uF 0603, 25V, X5R, 10% Murata GRM188R61E105KA12D 11 1 L1 0.47uH TDK SPM6530T-R47M170 12 1 R1 3.57k Thick Film, 0603,1/10W,1% Panasonic ERJ-3EKF3571V 13 2 R2, R11 3.32k Thick Film, 0603,1/10W,1% Panasonic ERJ-3EKF3321V 14 2 R3,R12 3.01k Thick Film, 0603,1/10W,1% Panasonic ERJ-3EKF3011V 15 1 R4 100 Thick Film, 0603,1/10W,1% Panasonic ERJ-3GEYJ101V 16 1 R6 20 Thick Film, 0603,1/10W,1% Panasonic ERJ-3EKF20R0V 17 1 R9 60.4k Thick Film, 0603,1/10W,1% panasonic ERJ-3EKF6042V 18 6 R10 R13 R14 R18 R29 R50 0 Thick Film, 0603,1/10W Panasonic ERJ-3GEY0R00V 19 2 R17 49.9k Thick Film, 0603,1/10W,1% Panasonic ERJ-3EKF4992V 20 1 U1 IR3897 PQFN 4x5mm IR IR3897MTRPBF 9/26/2012 0.47uH, Isat. 15.3A, 3.3m ohm 7 IRDC3897-P1V05 TYPICAL OPERATING WAVEFORMS Vin=1.5V, Vcc= 5V, Vo=1.05V, Io=0-4A , Room Temperature, no air flow Fig. 7: Bode Plot at 4A load shows a bandwidth of 81.35kHz and phase margin of 71.74 degree 9/26/2012 8 IRDC3897-P1V05 TYPICAL OPERATING WAVEFORMS Vin=1.5V, Vcc= 5V, Vo=1.05V, Io=0-4A , Room Temperature, no air flow Fig.8: Efficiency versus load current Fig.9: Power loss versus load current 9/26/2012 9 IRDC3897-P1V05 PCB METAL AND COMPONENT PLACEMENT Evaluations have shown that the best overall performance is achieved using the substrate/PCB layout as shown in following figures. PQFN devices should be placed to an accuracy of 0.050mm on both X and Y axes. Self-centering behavior is highly dependent on solders and processes, and experiments should be run to confirm the limits of self-centering on specific processes. For further information, please refer to “SupIRBuck™ Multi-Chip Module (MCM) Power Quad Flat No-Lead (PQFN) Board Mounting Application Note.” (AN1132) Fig. 10: PCB Metal Pad Spacing (all dimensions in mm) 9/26/2012 10 IRDC3897-P1V05 SOLDER RESIST IR recommends that the larger Power or Land Area pads are Solder Mask Defined (SMD.) This allows the underlying Copper traces to be as large as possible, which helps in terms of current carrying capability and device cooling capability. When using SMD pads, the underlying copper traces should be at least 0.05mm larger (on each edge) than the Solder Mask window, in order to accommodate any layer to layer misalignment. (i.e. 0.1mm in X & Y.) However, for the smaller Signal type leads around the edge of the device, IR recommends that these are Non Solder Mask Defined or Copper Defined. When using NSMD pads, the Solder Resist Window should be larger than the Copper Pad by at least 0.025mm on each edge, (i.e. 0.05mm in X&Y,) in order to accommodate any layer to layer misalignment. Ensure that the solder resist in-between the smaller signal lead areas are at least 0.15mm wide, due to the high x/y aspect ratio of the solder mask strip. Fig. 11: Solder resist 9/26/2012 11 IRDC3897-P1V05 STENCIL DESIGN Stencils for PQFN can be used with thicknesses of 0.100-0.250mm (0.004-0.010"). Stencils thinner than 0.100mm are unsuitable because they deposit insufficient solder paste to make good solder joints with the ground pad; high reductions sometimes create similar problems. Stencils in the range of 0.125mm-0.200mm (0.005-0.008"), with suitable reductions, give the best results. Evaluations have shown that the best overall performance is achieved using the stencil design shown in following figure. This design is for a stencil thickness of 0.127mm (0.005").The reduction should be adjusted for stencils of other thicknesses. Fig. 12: Stencil Pad Spacing (all dimensions in mm) 9/26/2012 12 IRDC3897-P1V05 PACKAGE INFORMATION Fig. 13: Package Dimensions IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, USA Tel: (310) 252-7105 TAC Fax: (310) 252-7903 This product has been designed and qualified for the Industrial market Visit us at www.irf.com for sales contact information Data and specifications subject to change without notice. 06/11 9/26/2012 13