HT16C23/HT16C23G RAM Mapping 56×4 / 52×8 LCD Driver

HT16C23/HT16C23G
RAM Mapping 56×4 / 52×8
LCD Driver Controller
Features
Applications
• Operating voltage: 2.4 ~ 5.5V
• Electronic meter
• Internal 32kHz RC oscillator
• Water meter
• Bias: 1/3 or 1/4; Duty:1/4 or 1/8
• Gas meter
• Internal LCD bias generation with voltage-follower
buffers
• Heat energy meter
• I2C-bus interface
• Games
• Household appliance
• Two Selectable LCD frame frequencies: 80Hz or
160Hz
• Telephone
• Consumer electronics
• Up to 52 x 8 bits RAM for display data storage
• Display patterns:
––56 x 4 patterns: 56 segments and 4 commons
––52 x 8 patterns: 52 segments and 8 commons
General Description
The HT16C23/HT16C23G device is a memory
mapping and multi-function LCD controller driver.
The Display segments of the device are 224 patterns
(56 segments and 4commons) or 416 patterns (52
segments and 8commons). The software configuration
feature of the HT16C23/HT16C23G device makes it
suitable for multiple LCD applications including LCD
modules and display subsystems. The HT16C23/
HT16C23G device communicates with most
microprocessors / microcontrollers via a two-line
bidirectional I2C-bus.
• Versatile blinking modes
• R/W address auto increment
• Internal 16-step voltage adjustment to adjust LCD
operating voltage
• Low power consumption
• Provides VLCD pin to adjust LCD operating voltage
• Manufactured in silicon gate CMOS process
• Package Type: 48LQFP, 64LQFP, Chip and
Goldbump chip.
Block Diagram
Power_on reset
VSS
COM0
SDA
SCL
Internal RC
Oscillator
Timing
generator
I2C
Controller
Column
/Segment
driver
output
Display RAM
52*8bits
8
COM3
COM4/SEG0
COM7/SEG3
VDD
VCCA2
VLCD
－
OP4
Internal
voltage
adjustment
SEG4
＋
R
－
OP3
＋
R
Segment
driver
output
－
OP2
＋
R
－
OP1
＋
LCD
Voltage
Selector
SEG55
R
LCD bias generator
Rev. 1.20
1
January 27, 2015
SEG15
SEG14
SEG13
SEG12
SEG11
SEG10
SEG9
SEG8
SEG7
SEG6
SEG5
SEG4
SEG19
SEG18
SEG17
SEG16
SEG15
SEG14
SEG13
SEG12
SEG11
SEG10
SEG9
SEG8
COM2
SEG30
COM3
SEG29COM4/SEG0
SEG28COM5/SEG1
SEG27COM6/SEG2
SEG26COM7/SEG3
SEG25
SEG4
SEG24
SEG5
SEG6
SEG7
64 63 62 61 60 59 58 57 56 55 54 53
HT16C23
64 LQFP-A
17 18 19 20 21 22 23 24 25 26 27 28
SEG19
SEG18
SEG17
SEG16
SEG15
SEG14
SEG13
SEG12
SEG11
SEG10
SEG9
SEG8
HT16C23
64 LQFP-A
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
SEG39
SEG38
SEG37
SEG36
SEG35
SEG34
SEG33
SEG32
SEG31
SEG30
SEG29
SEG28
SEG27
SEG26
SEG25
SEG24
SEG23
SEG22
SEG21
SEG20
SEG19
SEG18
SEG17
SEG16
SEG15
SEG14
SEG13
SEG12
SEG11
SEG10
SEG9
SEG8
SEG15
SEG14
SEG13
SEG12
SEG11
SEG10
SEG9
SEG8
SEG7
SEG6
SEG7
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
Note: 1. Application at VDD ≤ VLCD or VLCD ≤ VDD.
2. When the 48-pin LQFP package is selected, this device does not support LCD 1/4 duty.
3. The VCCA2 pad is internally connected with the VLCD pad.
Rev. 1.20
2
SEG44
COM1
SEG31
SEG45
COM0
SEG32
SEG46
SEG33
SEG47
VSS
SEG48
SCL
SEG34
SEG49
SDA
SEG35
SEG50
SEG36
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
SEG51
VDD
SEG52
SEG37
SEG53
SEG38
SEG40
SEG6
SEG41
SEG5
SEG42
SEG4
SEG43
COM7/SEG3
SEG44
COM6/SEG2
SEG45
COM5/SEG1
SEG46
COM4/SEG0
SEG47
COM3
SEG48
COM2
SEG49
COM1
SEG50
COM0
SEG51
SEG27
SEG26
SEG25
SEG24
SEG23
SEG22
SEG21
SEG20
SEG19
SEG18
SEG17
SEG16
SEG52
SCL
SEG53
VLCD
46 45 44 43 42 41 40 39 38 37
36
35
34
33
32
31
HT16C23
30
48 LQFP-A
29
28
27
26
25
1516 17 18 19 20 2122 23 24
VSS
SDA
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
SEG54
SEG28
SEG29
SEG30
SEG31
SEG32
SEG33
SEG34
SEG35
SEG36
VDD
VLCD
SEG39
SEG54
SEG40
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
48
1
47
2
46
3
45
4
44
5
43
6
48 47 46 45 44 43 42 41 40 39 38 37
SEG27
1
36
42
7 VDD
35
SEG26
2
41
HT16C23
8 SDA
SEG25
3
34
SCL
64 LQFP-A
40
9
4
33
SEG24
VSS
39
10
5
32
SEG23
COM0
38
11
31
6
HT16C23
SEG22
COM1
7
37
30
48 LQFP-A
SEG21
COM2
12
29
8
SEG20
COM3
36
13
28
9
SEG19
COM4
35
14
27
10
SEG18
COM5
34
15
11
26
SEG17
COM6
33
16
25
12
SEG16
COM7
17 18 19 20
22 2317
241825
28 23
2924
30 31 32
13 21
14 1516
1926
2027
2122
SEG23
SEG22
SEG21
SEG15
SEG14
SEG20
SEG13
SEG19
SEG12
SEG18
SEG11
SEG17
SEG10
SEG16
SEG9
SEG15
SEG8
SEG14
SEG7
SEG6
SEG13
SEG5
SEG12
SEG4
SEG11
SEG10
SEG9
SEG8
SEG15
SEG14
SEG13
SEG12
SEG11
SEG10
SEG9
SEG8
SEG7
SEG6
SEG7
SEG41
SEG6
SEG42
SEG5
SEG43
SEG4
SEG44
COM7/SEG3
SEG45
COM6/SEG2
SEG46
COM5/SEG1
SEG47
COM4/SEG0
SEG48
COM3
SEG49
COM2
SEG50
COM1
SEG51
COM0
HT16C23/HT16C23G
SEG28
SEG29
SEG30
SEG31
SEG32
SEG33
SEG34
SEG35
SEG36
SEG37
SEG38
VLCD
VSS
SEG27
SEG26
SEG25
SEG24
SEG23
SEG22
SEG21
SEG20
SEG19
SEG18
SEG17
SEG16
SEG52
SCL
SEG53
46 45 44 43 42 41 40 39 38 37
36
35
34
33
32
31
HT16C23
48 LQFP-A
30
29
28
27
26
25
1516 17 18 19 20 2122 23 24
SDA
SEG54
SEG28
SEG29
SEG30
SEG31
SEG32
SEG33
SEG34
SEG35
SEG36
VDD
SEG55
Pin Assignment
17 18 19 20 21 22 23 24 25 26 27 28
January 27, 2015
HT16C23/HT16C23G
Pad assignment for COB
SEG39
SEG40
SEG41
SEG42
SEG43
SEG44
SEG45
SEG46
SEG47
SEG48
SEG49
SEG50
SEG51
SEG52
SEG53
SEG54
SEG55
VLCD
VCCA2
1 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51
VDD
SDA
SCL
Option
VSS
COM0
COM1
COM2
COM3
COM4/SEG0
COM5/SEG1
COM6/SEG2
COM7/SEG3
SEG4
SEG5
SEG6
SEG7
50
49
48
47
46
45
44
43
42
2
3
4
5
6
7
8
10
11
12
13
14
15
16
17
18
19
(0, 0)
N.C.
9
41
40
39
38
37
36
SEG38
SEG37
SEG36
SEG35
SEG34
SEG33
SEG32
SEG31
SEG30
SEG29
SEG28
SEG27
SEG26
SEG25
SEG24
20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35
SEG23
SEG22
SEG21
SEG20
SEG19
SEG18
SEG17
SEG16
SEG15
SEG14
SEG13
SEG12
SEG11
SEG10
SEG9
SEG8
Chip size: 1843 x 2018μm2
Note: 1. The option (pad 5) must be bonded to VDD or floating.
2. The IC substrate should be connected to VSS in the PCB layout artwork.
3. VLCD (pad 68) and VCCA2 (pad 1) must be bonded together for the application at VDD ≤ VLCD or
VLCD ≤ VDD.
Internal voltage adjustment (IVA)
set command
VLCD
(pad 68)
SEG55
(pad 67)
Note
DE bit
VE bit
0
0
Input
Null
●●VLCD support internal bias voltage.
0
1
Input
Null
●●Internal Voltage Adjustment is null
●●VLCD support internal bias voltage
1
0
Input
Output
●●VLCD support internal bias voltage
1
1
Input
Output
●●VLCD support internal bias voltage
4. VDD (pad2) and VCCA2 (pad 1) must be bonded together for the application at VLCD ≤ VDD.
Internal voltage adjustment (IVA)
set command
VLCD
(pad 68)
SEG55
(pad 67)
Note
DE bit
VE bit
0
0
Input
Null
●●VLCD support internal bias voltage.
0
1
Output
Null
●●Detect the internal bias voltage
●●VDD support internal bias voltage
1
0
Floating
Output
●●VDD support internal bias voltage
1
1
Floating
Output
●●VDD support internal bias voltage
Rev. 1.20
3
January 27, 2015
HT16C23/HT16C23G
Pad Coordinates for COB
Unit: μm
No
Name
X
Y
No
Name
X
Y
1
VCCA2
-788.05
905.4
35
SEG23
780.15
-905.4
-582.35
2
VDD
-783.15
572.25
36
SEG24
817.45
3
SDA
-817.9
419.55
37
SEG25
817.45
-497.35
4
SCL
-817.9
334.55
38
SEG26
817.45
-412.35
5
OPTION
-817.9
249.55
39
SEG27
817.45
-327.35
6
VSS
-817.9
164.55
40
SEG28
817.45
-242.35
7
COM0
-817.9
79.55
41
SEG29
817.45
-157.35
8
COM1
-817.9
-5.45
42
SEG30
817.45
-72.35
9
N.C.
-484.014
-35.6
43
SEG31
817.45
12.65
10
COM2
-817.9
-90.45
44
SEG32
817.45
97.65
11
COM3
-817.9
-175.45
45
SEG33
817.45
182.65
12
COM4/SEG0
-817.9
-270.35
46
SEG34
817.45
267.65
13
COM5/SEG1
-817.9
-355.35
47
SEG35
817.45
352.65
14
COM6/SEG2
-817.9
-440.35
48
SEG36
817.45
437.65
15
COM7/SEG3
-817.9
-525.35
49
SEG37
817.45
522.65
16
SEG4
-817.9
-613.1
50
SEG38
817.45
607.65
17
SEG5
-817.9
-698.1
51
SEG39
741.95
905.4
18
SEG6
-817.9
-783.1
52
SEG40
656.95
905.4
19
SEG7
-817.9
-868.1
53
SEG41
571.95
905.4
20
SEG8
-494.85
-905.4
54
SEG42
486.95
905.4
21
SEG9
-409.85
-905.4
55
SEG43
401.95
905.4
22
SEG10
-324.85
-905.4
56
SEG44
316.95
905.4
23
SEG11
-239.85
-905.4
57
SEG45
231.95
905.4
24
SEG12
-154.85
-905.4
58
SEG46
146.95
905.4
25
SEG13
-69.85
-905.4
59
SEG47
61.95
905.4
26
SEG14
15.15
-905.4
60
SEG48
-23.05
905.4
27
SEG15
100.15
-905.4
61
SEG49
-108.05
905.4
28
SEG16
185.15
-905.4
62
SEG50
-193.05
905.4
29
SEG17
270.15
-905.4
63
SEG51
-278.05
905.4
30
SEG18
355.15
-905.4
64
SEG52
-363.05
905.4
31
SEG19
440.15
-905.4
65
SEG53
-448.05
905.4
32
SEG20
525.15
-905.4
66
SEG54
-533.05
905.4
33
SEG21
610.15
-905.4
67
SEG55
-618.05
905.4
34
SEG22
695.15
-905.4
68
VLCD
-703.05
905.4
Rev. 1.20
4
January 27, 2015
HT16C23/HT16C23G
Pad Assignment for Goldbump Chip
54 53 52
1 94 93
92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55
2
3
4
5
6
7
8
9
10
11
12
13
14
15
(0, 0)
16 17 18 19
20
21 22
23 24 25 26 27 28 29 30 31 32 33 34 35 36 37
51
50
49
48
47
46
45
44
43
42
41
40
39
38
Note:
• VLCD (pad 21) must be connected to VCCA2 (pad 22) in the PCB layout for the application at VDD ≤ VLCD or
VLCD ≤ VDD.
Internal voltage adjustment (IVA)
set command
VLCD
(pad 21)
SEG55
(pad 14)
Note
DE bit
VE bit
0
0
Input
Null
●●VLCD support internal bias voltage.
0
1
Input
Null
●●Internal Voltage Adjustment is null
●●VLCD support internal bias voltage
1
0
Input
Output
●●VLCD support internal bias voltage
1
1
Input
Output
●●VLCD support internal bias voltage
• VDD (pad 19) must be connected to VCCA2 (pad 22) in the PCB layout for the application at VLCD ≤ VDD.
Internal voltage adjustment (IVA)
set command
VLCD
(pad 21)
SEG55
(pad 14)
Note
DE bit
VE bit
0
0
Input
Null
●●VLCD support internal bias voltage.
0
1
Output
Null
●●Detect the internal bias voltage
●●VDD support internal bias voltage
1
0
Floating
Output
●●VDD support internal bias voltage
1
1
Floating
Output
●●VDD support internal bias voltage
Rev. 1.20
5
January 27, 2015
HT16C23/HT16C23G
Pad Dimensions for Goldbump Chip
Item
Size
Number
Chip size
－
Chip thickness
－
X
2806
1, 3~15, 38~50, 52~94
Pad pitch
16~37
1080
Unit
μm
508
μm
60
μm
87
Output pad
Bump size
Y
μm
5~14, 39~48
60
40
μm
54~93
40
60
μm
Input pad
17~22
67
67
μm
3, 4, 15, 38, 49, 50
60
40
μm
Dummy pad
1, 52, 53, 94
40
60
μm
16, 23~37
67
Bump height
All pad
67
18±3
μm
μm
Alignment mark Dimensions for Goldbump Chip
Item
Number
Size
Unit
(-1330, 362.5)
10 m
10 m
ALIGN_A
2
20 m
10 m
10 m
40 m
20 m
μm
40 m
(1310, 362.5)
10 m
10 m
ALIGN_B
51
Rev. 1.20
6
40 m
10 m
10 m
20 m
20 m
20 m
μm
20 m
January 27, 2015
HT16C23/HT16C23G
Pad Coordinates for Goldbump Chip
Unit: μm
No
Name
X
Y
No
Name
X
Y
1
DUMMY
-1290
444.5
48
SEG5
1308.5
151.25
3
DUMMY
-1308.5
271.25
49
DUMMY
1308.5
211.25
4
DUMMY
-1308.5
211.25
50
DUMMY
1308.5
271.25
5
SEG46
-1308.5
151.25
52
DUMMY
1290
444.5
6
SEG47
-1308.5
91.25
53
DUMMY
1230
444.5
7
SEG48
-1308.5
31.25
54
SEG6
1170
444.5
8
SEG49
-1308.5
-28.75
55
SEG7
1110
444.5
9
SEG50
-1308.5
-88.75
56
SEG8
1050
444.5
10
SEG51
-1308.5
-148.75
57
SEG9
990
444.5
11
SEG52
-1308.5
-208.75
58
SEG10
930
444.5
12
SEG53
-1308.5
-268.75
59
SEG11
870
444.5
13
SEG54
-1308.5
-328.75
60
SEG12
810
444.5
14
SEG55
-1308.5
-388.75
61
SEG13
750
444.5
15
DUMMY
-1308.5
-448.75
62
SEG14
690
444.5
16
DUMMY
-1007.85
-436.872
63
SEG15
630
444.5
17
SDA
-920.85
-436.872
64
SEG16
570
444.5
18
SCL
-833.85
-436.872
65
SEG17
510
444.5
19
VDD
-746.85
-436.872
66
SEG18
450
444.5
20
VSS
-594.45
-436.872
67
SEG19
390
444.5
21
VLCD
-507.45
-436.872
68
SEG20
330
444.5
22
VCCA2
-420.45
-436.872
69
SEG21
270
444.5
23
DUMMY
-234.45
-436.872
70
SEG22
210
444.5
24
DUMMY
-147.45
-436.872
71
SEG23
150
444.5
444.5
25
DUMMY
-60.45
-436.872
72
SEG24
90
26
DUMMY
26.55
-436.872
73
SEG25
30
444.5
27
DUMMY
113.55
-436.872
74
SEG26
-30
444.5
28
DUMMY
200.55
-436.872
75
SEG27
-90
444.5
29
DUMMY
287.55
-436.872
76
SEG28
-150
444.5
30
DUMMY
374.55
-436.872
77
SEG29
-210
444.5
31
DUMMY
461.55
-436.872
78
SEG30
-270
444.5
32
DUMMY
548.55
-436.872
79
SEG31
-330
444.5
444.5
33
DUMMY
635.55
-436.872
80
SEG32
-390
34
DUMMY
722.55
-436.872
81
SEG33
-450
444.5
35
DUMMY
809.55
-436.872
82
SEG34
-510
444.5
36
DUMMY
896.55
-436.872
83
SEG35
-570
444.5
37
DUMMY
983.55
-436.872
84
SEG36
-630
444.5
38
DUMMY
1308.5
-448.75
85
SEG37
-690
444.5
39
COM0
1308.5
-388.75
86
SEG38
-750
444.5
40
COM1
1308.5
-328.75
87
SEG39
-810
444.5
41
COM2
1308.5
-268.75
88
SEG40
-870
444.5
42
COM3
1308.5
-208.75
89
SEG41
-930
444.5
43
COM4/SEG0
1308.5
-148.75
90
SEG42
-990
444.5
44
COM5/SEG1
1308.5
-88.75
91
SEG43
-1050
444.5
45
COM6/SEG2
1308.5
-28.75
92
SEG44
-1110
444.5
46
COM7/SEG3
1308.5
31.25
93
SEG45
-1170
444.5
47
SEG4
1308.5
91.25
94
DUMMY
-1230
444.5
Rev. 1.20
7
January 27, 2015
HT16C23/HT16C23G
Alignment Mark Coordinates for Goldbump Chip
No
Name
X
Y
No
Name
X
Y
2
ALIGN_A
-1330
362.5
51
ALIGN_B
1310
362.5
Pad Description
Pad Name
Type
Description
SDA
I/O
SCL
I
VDD
—
Positive power supply.
VSS
—
Negative power supply, ground.
Serial Data Input/Output for I C interface
2
Serial Clock Input for I2C interface
VLCD
—
Power supply for LCD driver.
COM0~COM3
O
LCD Common outputs.
COM4/SEG0~
COM7/SEG3
O
LCD Common/Segment multiplexed driver outputs
SEG4~SEG55
O
LCD Segment outputs.
VCCA2
—
Power supply for LCD bias generator.
Approximate Internal Connections
COM0~COM7; SEG0~SEG55
SCL, SDA (for schmit Trigger type)
VDD
Vselect-on
Vselect-off
VSS
Rev. 1.20
8
January 27, 2015
HT16C23/HT16C23G
Absolute Maximum Ratings
Supply Voltage ........................................................................................................................VSS-0.3V to VSS+6.5V
Input Voltage ..........................................................................................................................VSS-0.3V to VDD+0.3V
Storage Temperature ......................................................................................................................... -55°C to 150°C
Operating Temperature ....................................................................................................................... -40°C to 85°C
Note: These are stress ratings only. Stresses exceeding the range specified under “Absolute Maximum Ratings”
may cause substantial damage to the device. Functional operation of this device at other conditions beyond
those listed in the specification is not implied and prolonged exposure to extreme conditions may affect device
reliability.
D.C. Characteristics
VSS = 0V; VDD =2.4V to 5.5V; Ta = -40 to +85°C. VCCA2 pad is connected to VDD Pad
Symbol
Parameter
Test Condition
VDD
Condition
Min.
Typ.
Max.
Unit
VDD
Operating Voltage
—
—
2.4
—
5.5
V
VLCD
Operating Voltage
—
—
2.4
—
5.5
V
3V
No load, VLCD=VDD, 1/3bias,
fLCD=80Hz, LCD display on,
Internal system oscillator on,
DA0~DA3 are set to ”0000”
—
25
40
μA
—
35
50
μA
No load, VLCD=VDD, 1/3bias
fLCD=80Hz, LCD display off,
Internal system oscillator on,
DA0~DA3 are set to ”0000”
—
2
5
μA
—
4
10
μA
—
—
1
μA
5V
No load, VLCD=VDD,
LCD display off,
Internal system oscillator off,
—
—
2
μA
IDD
Operating Current
5V
3V
IDD1
Operating Current
5V
3V
ISTB
Standby Current
VIH
Input high Voltage
—
SDA ,SCL
0.7VDD
—
VDD
V
VIL
Input low Voltage
—
SDA, SCL
0
—
0.3VDD
V
IIL
Input leakage current
—
VIN=VSS or VDD
-1
—
1
μA
IOL
Low level output current
3V
3
—
—
mA
5V
VOL=0.4V
SDA
6
—
—
mA
IOL1
LCD COM Sink Current
3V
VLCD=3V, VOL=0.3V
250
400
—
μA
5V
VLCD=5V, VOL=0.5V
500
800
—
μA
IOH1
LCD COM Source Current
3V
VLCD=3V, VOH=2.7V
-140
-230
—
μA
5V
VLCD=5V, VOH=4.5V
-300
-500
—
μA
IOL2
LCD SEG Sink Current
3V
VLCD=3V, VOL=0.3V
250
400
—
μA
5V
VLCD=5V, VOL=0.5V
500
800
—
μA
IOH2
LCD SEG Source Current
3V
VLCD=3V, VOH=2.7V
-140
-230
—
μA
5V
VLCD=5V, VOH=4.5V
-300
-500
—
μA
Rev. 1.20
9
January 27, 2015
HT16C23/HT16C23G
A.C. Characteristics
Symbol
VSS = 0V; VDD = 2.4 to 5.5V; Ta= -40 to +85°C. VCCA2 pad is connected to VDD Pad
Parameter
Test Condition
Condition
VDD
Min.
Typ.
Max.
Unit
fLCD1
LCD Frame Frequency
4V
1/4 duty, Ta =25°C
72
80
88
Hz
fLCD2
LCD Frame Frequency
4V
1/4 duty, Ta =25°C
144
160
176
Hz
fLCD3
LCD Frame Frequency
4V
1/4 duty,Ta=-40 to +85°C
52
80
124
Hz
fLCD4
LCD Frame Frequency
4V
1/4 duty, Ta=-40 to +85°C
104
160
248
Hz
tOFF
VDD OFF Times
—
VDD drop down to 0V
20
—
—
ms
tSR
VDD Slew Rate
—
0.05
—
—
V/ms
—
Note:
• If the conditions of Power on Reset timing are not satisfied during the power ON/OFF sequence, the internal
Power on Reset (POR) circuit will not operate normally.
• If the VDD voltage drops below the minimum voltage of operating voltage spec. during operating, the Power on
Reset timing conditions must also be satisfied. That is, the VDD voltage must drop to 0V and remain at 0V for
20ms (min.) before rising to the normal operating voltage.
A.C. Characteristics – I2C Interface
Symbol
fSCL
tBUF
tHD: STA
Parameter
Clock Frequency
Condition
VDD=2.4V to 5.5V VDD=3.0V to 5.5V
—
Bus Free Time
Time in which the bus
must be free before a new
transmission can start
Start Condition Hold Time
After this period, the first
clock pulse is generated
Unit
Min.
Max.
Min.
Max.
—
100
—
400
KHZ
4.7
—
1.3
—
μs
4
—
0.6
—
μs
tLOW
SCL Low Time
—
4.7
—
1.3
—
μs
tHIGH
SCL High Time
—
4
—
0.6
—
μs
4.7
—
0.6
—
μs
Only relevant for repeated
START condition
tSU: STA
Start Condition Setup Time
tHD: DAT
Data Hold Time
—
0
—
0
—
ns
tSU: DAT
Data Setup Time
—
250
—
100
—
ns
tR
SDA and SCL Rise Time
Note
—
1
—
0.3
μs
tF
SDA and SCL Fall Time
Note
—
0.3
—
0.3
μs
Stop Condition set-up Time
—
4
—
0.6
—
μs
tAA
Output Valid from Clock
—
—
3.5
—
0.9
μs
tSP
Input Filter Time Constant
(SDA and SCL Pins)
—
100
—
50
ns
tSU: STO
Noise suppression time
Note: These parameters are periodically sampled but not 100% tested.
Rev. 1.20
10
January 27, 2015
HT16C23/HT16C23G
Timing Diagrams
I2C Timing
SDA
tBUF
tSU:DAT
tf
tLOW
tHD:STA
tr
tSP
SCL
tHD:STA
S
tHD:DAT
tHIGH
tSU:STA
tAA
tSU:STO
Sr
P
S
SDA
OUT
Power On Reset Timing
Rev. 1.20
11
January 27, 2015
HT16C23/HT16C23G
Functional Description
• Detection switch for the VLCD pin is disabled.
Power-On Reset
• Blinking function is switched off
• Frame Frequency is set to 80Hz.
When the power is applied, the device is initialized
by an internal power-on reset circuit. The status of the
internal circuits after initialization is as follows:
Data transfers on the I2C-bus should be avoided for
1 ms following power-on to allow completion of the
reset action.
• All common / segment outputs are set to VDD when
VCCA2 pad is connected to VDD pad.
Display Memory – RAM Structure
The display RAM is static 52 x 8-bits RAM which
stores the LCD data. Logic “1” in the RAM bit-map
indicates the “on” state of the corresponding LCD
segment; similarly, logic 0 indicates the ‘off’ state.
• All common / segment outputs are set to VLCD
when VCCA2 pad is connected to VLCD pad.
• The drive mode 1/4 duty output and 1/3 bias is
selected for 64 pin LQFP package.
• The drive mode 1/8 duty output and 1/3 bias is
selected for 48 pin LQFP package.
The contents of the RAM data are directly mapped
to the LCD data. The first RAM column corresponds
to the segments operated with respect to COM0. In
multiplexed LCD applications the segment data of the
second, third and fourth column of the display RAM
are time-multiplexed with COM1, COM2 and COM3
respectively. The following is a mapping from the RAM
data to the LCD pattern:
• The System Oscillator and the LCD bias generator
are off state.
• LCD Display is off state.
• Internal voltage adjustment function is enabled.
• The Segment / VLCD shared pin is set as the
Segment pin.
Output
COM3
COM2
COM1
COM0
Output
COM3
COM2
COM1
COM0
address
SEG1
SEG0
00H
SEG3
SEG2
01H
SEG5
SEG4
02H
SEG7
SEG6
03H
SEG9
SEG8
04H
SEG11
SEG10
05H
SEG55
SEG54
D7
D6
D5
D4
1BH
D3
D2
D1
D0
Data
RAM Mapping of 56×4 Display Mode
Rev. 1.20
12
January 27, 2015
HT16C23/HT16C23G
Output
COM7/
SEG3
COM6/
SEG2
COM5/
SEG1
COM4/
SEG0
COM3
COM2
COM1
COM0
address
SEG4
00H
SEG5
01H
SEG6
02H
SEG7
03H
SEG8
04H
SEG9
05H
SEG55
33H
D7
D6
D5
D4
D3
D2
D1
D0
Data
RAM Mapping of 52×8 Display Mode
MSB
D7
LSB
D6
D5
D4
D3
D2
D1
D0
System Oscillator
LCD Bias Generator
The timing for the internal logic and the LCD drive
signals are generated by an internal oscillator. The
System Clock frequency (fSYS) determines the LCD
frame frequency. During initial system power on the
System Oscillator will be in the stop state.
The full-scale LCD voltage (VOP) is obtained from
(VLCD – VSS). The LCD voltage may be temperature
compensated externally through the Voltage supply to
the VLCD pin.
Rev. 1.20
Fractional LCD biasing voltages, known as 1/3 or 1/4
bias voltage, are obtained from an internal voltage
divider of four series resistors connected between
VLCD and VSS. The centre resistor can be switched
out of circuits to provide a 1/3bias voltage level
configuration.
13
January 27, 2015
HT16C23/HT16C23G
LCD Drive Mode Waveforms
• When the LCD drive mode is selected as 1/4 duty and 1/3 bias, the waveform and LCD display is shown as
follows:
tLCD
LCD segment
LCD segment
VLCD
VLCD
VLCD- Vop/3
VLCD- Vop/3
COM0
COM0 VLCD- 2Vop/3
VLCD- 2Vop/3
State1
State1
(on)
(on)
VSS
VSS
VLCD
VLCD
COM1
COM1
State2
State2
(off)
(off)
VLCD- Vop/3
VLCD- Vop/3
VLCD- 2Vop/3
VLCD- 2Vop/3
VSS
VSS
VLCD
VLCD
COM2
COM2
VLCD- Vop/3
VLCD- Vop/3
VLCD- 2Vop/3
VLCD- 2Vop/3
VSS
VSS
VLCD
VLCD
COM3
COM3
VLCD- Vop/3
VLCD- Vop/3
VLCD- 2Vop/3
VLCD- 2Vop/3
VSS
VSS
VLCD
VLCD
VLCD- Vop/3
VLCD- Vop/3
SEG n
SEG n VLCD- 2Vop/3
VLCD- 2Vop/3
VSS
VSS
VLCD
VLCD
VLCD- Vop/3
VLCD- Vop/3
SEG n+1
SEG n+1 VLCD- 2Vop/3
VLCD- 2Vop/3
VSS
VSS
VLCD
VLCD
VLCD- Vop/3
VLCD- Vop/3
SEG n+2
SEG n+2 VLCD- 2Vop/3
VLCD- 2Vop/3
VSS
VSS
VLCD
VLCD
VLCD- Vop/3
VLCD- Vop/3
SEG n+3
SEG n+3VLCD- 2Vop/3
VLCD- 2Vop/3
VSS
VSS
Note: tLCD=1/fLCD
Rev. 1.20
Waveforms for 1/4 duty drive mode with1/3 bias (VOP=VLCD-VSS)
14
January 27, 2015
HT16C23/HT16C23G
• When the LCD drive mode is selected as 1/8 duty and 1/4bias, the waveform and LCD display is shown as
follows:
tLCD
LCD segment
LCD segment
VLCD
VLCD
VLCD- Vop/4
VLCD- Vop/4
VLCD- 2Vop/4
COM0
VLCD- 2Vop/4
COM0
State1
State1
(on)
(on)
VLCD- 3Vop/4
VLCD- 3Vop/4
VSS
VSS
VLCD
VLCD
State2
State2
(off)
(off)
VLCD- Vop/4
VLCD- Vop/4
VLCD- 2Vop/4
COM1
VLCD- 2Vop/4
COM1
VLCD- 3Vop/4
VLCD- 3Vop/4
VSS
VSS
VLCD
VLCD
VLCD- Vop/4
VLCD- Vop/4
VLCD- 2Vop/4
COM2
VLCD- 2Vop/4
COM2
VLCD- 3Vop/4
VLCD- 3Vop/4
VSS
VSS
VLCD
VLCD
VLCD- Vop/4
VLCD- Vop/4
VLCD- 2Vop/4
COM3
VLCD- 2Vop/4
COM3
VLCD- 3Vop/4
VLCD- 3Vop/4
VSS
VSS
VLCD
VLCD
VLCD- Vop/4
VLCD- Vop/4
VLCD- 2Vop/4
COM4
VLCD- 2Vop/4
COM4
VLCD- 3Vop/4
VLCD- 3Vop/4
VSS
VSS
VLCD
VLCD
VLCD- Vop/4
VLCD- Vop/4
VLCD- 2Vop/4
COM5
VLCD- 2Vop/4
COM5
VLCD- 3Vop/4
VLCD- 3Vop/4
VSS
VSS
VLCD
VLCD
VLCD- Vop/4
VLCD- Vop/4
VLCD- 2Vop/4
COM6
VLCD- 2Vop/4
COM6
VLCD- 3Vop/4
VLCD- 3Vop/4
VSS
VSS
VLCD
VLCD
VLCD- Vop/4
VLCD- Vop/4
VLCD- 2Vop/4
COM7
VLCD- 2Vop/4
COM7
VLCD- 3Vop/4
VLCD- 3Vop/4
VSS
VSS
VLCD
VLCD
VLCD- Vop/4
VLCD- Vop/4
SEG n
SEG n
VLCD- 2Vop/4
VLCD- 2Vop/4
VLCD- 3Vop/4
VLCD- 3Vop/4
VSS
VSS
VLCD
VLCD
VLCD- Vop/4
VLCD- Vop/4
SEG n+1
VLCD- 2Vop/4
SEG n+1
VLCD- 2Vop/4
VLCD- 3Vop/4
VLCD- 3Vop/4
VSS
VSS
VLCD
VLCD
VLCD- Vop/4
VLCD- Vop/4
SEG n+2
VLCD- 2Vop/4
SEG n+2
VLCD- 2Vop/4
VLCD- 3Vop/4
VLCD- 3Vop/4
VSS
VSS
VLCD
VLCD
VLCD- Vop/4
VLCD- Vop/4
SEG n+3
VLCD- 2Vop/4
SEG n+3
VLCD- 2Vop/4
VLCD- 3Vop/4
VLCD- 3Vop/4
VSS
VSS
Note: tLCD=1/fLCD
Rev. 1.20
Waveforms for 1/8 duty drive mode with1/4 bias (VOP=VLCD-VSS)
15
January 27, 2015
HT16C23/HT16C23G
Segment Driver Outputs
Blinker Function
The LCD drive section includes 56 segment outputs
SEG0~SEG55 or 52 segment outputs SEG4~SEG55
which should be connected directly to the LCD
panel. The segment output signals are generated in
accordance with the multiplexed column signals and
with the data resident in the display latch. The unused
segment outputs should be left open-circuit when less
than 56 or 52 segment outputs are required.
The device contains versatile blinking capabilities.
The whole display can be blinked at frequencies
selected by the Blink command. The blinking
frequency is a subdivided ratio of the system
frequency. The ratio between the system oscillator
and blinking frequencies depends on the blinking
mode in which the device is operating, as shown in
the following table:
Column Driver Outputs
Blinking Mode
The LCD drive section includes 4 column outputs
COM0~COM3 or 8 column outputs COM0~COM7
which should be connected directly to the LCD
panel. The column output signals are generated in
accordance with the selected LCD drive mode. The
unused column outputs should be left open-circuit if
less than 4 or 8 column outputs are required.
0
0
Blink off
1
fSYS / 16384Hz
2
2
fSYS / 32768Hz
1
3
fSYS / 65536Hz
0.5
Frame Frequency
The HT16C23/HT16C23G device provides two frame
frequencies selected with Mode set command known
as 80Hz and 160Hz respectively.
Address Pointer
The addressing mechanism for the display RAM is
implemented using the address pointer. This allows
the loading of an individual display data byte, or a
series of display data bytes, into any location of the
display RAM. The sequence commences with the
initialization of the address pointer by the Address
pointer command.
Rev. 1.20
Operating Mode
Blinking
Ratio
Frequency (Hz)
16
January 27, 2015
HT16C23/HT16C23G
Internal VLCD Voltage Adjustment
• The internal VLCD adjustment contains four resistors in series and a 4-bit programmable analog switch which
can provide sixteen voltage adjustment options using the VLCD voltage adjustment command.
• The internal VLCD adjustment structure is shown in the diagram:
VDD pad
VCCA2 pad
VE bit
DE bit
VLCD pad
R
Internal voltage adjustment
R
R
R
LCD Bias
generator
• The relationship between the programmable 4-bit analog switch and the VLCD output voltage is shown in the
table:
1. When VCCA2 pad is connected to VDD pad
DA3~DA0
00H
Rev. 1.20
Bias
1/3
1/4
1.000*VDD
1.000*VDD
01H
0.944*VDD
0.957*VDD
02H
0.894*VDD
0.918*VDD
03H
0.849*VDD
0.882*VDD
04H
0.808*VDD
0.849*VDD
05H
0.771*VDD
0.818*VDD
06H
0.738*VDD
0.789*VDD
07H
0.707*VDD
0.763*VDD
08H
0.678*VDD
0.738*VDD
09H
0.652*VDD
0.714*VDD
0AH
0.628*VDD
0.692*VDD
0BH
0.605*VDD
0.672*VDD
0CH
0.584*VDD
0.652*VDD
0DH
0.565*VDD
0.634*VDD
0EH
0.547*VDD
0.616*VDD
0FH
0.529*VDD
0.600*VDD
17
Note
Default value
January 27, 2015
HT16C23/HT16C23G
2. When VCCA2 pad is connected to VLCD pad
Bias
1/3
1/4
1.000*VLCD
1.000* VLCD
01H
0.944* VLCD
0.957* VLCD
02H
0.894* VLCD
0.918* VLCD
03H
0.849* VLCD
0.882* VLCD
04H
0.808* VLCD
0.849* VLCD
05H
0.771* VLCD
0.818* VLCD
06H
0.738* VLCD
0.789* VLCD
07H
0.707* VLCD
0.763* VLCD
08H
0.678* VLCD
0.738* VLCD
09H
0.652* VLCD
0.714* VLCD
0AH
0.628* VLCD
0.692* VLCD
0BH
0.605* VLCD
0.672*VDD
0CH
0.584* VLCD
0.652* VLCD
0DH
0.565* VLCD
0.634* VLCD
0EH
0.547* VLCD
0.616* VLCD
0FH
0.529* VLCD
0.600* VLCD
DA3~DA0
00H
Note
Default value
I2C Serial Interface
The device supports I2C serial interface. The I2C bus is for bidirectional, two-line communication between
different ICs or modules. The two lines are a serial data line, SDA, and a serial clock line, SCL. Both lines are
connected to the positive supply via pull-up resistors with a typical value of 4.7KΩ. When the bus is free, both
lines are high. Devices connected to the bus must have open-drain or open-collector outputs to implement a wiredor function. Data transfer is initiated only when the bus is not busy.
Data Validity
The data on the SDA line must be stable during the high period of the serial clock. The high or low state of the
data line can only change when the clock signal on the SCL line is Low as shown in the diagram.
SDA
SCL
Data line stable,
Data valid
Rev. 1.20
Chang of data
allowed
18
January 27, 2015
HT16C23/HT16C23G
START and STOP Conditions
• A high to low transition on the SDA line while SCL is high defines a START condition.
• A low to high transition on the SDA line while SCL is high defines a STOP condition.
• START and STOP conditions are always generated by the master. The bus is considered to be busy after the
START condition. The bus is considered to be free again a certain time after the STOP condition.
• The bus stays busy if a repeated START (Sr) is generated instead of a STOP condition. In some respects, the
START(S) and repeated START (Sr) conditions are functionally identical.
SDA
SDA
SCL
SCL
S
P
START condition
STOP condition
Byte Format
Every byte put on the SDA line must be 8-bit long. The number of bytes that can be transmitted per transfer is
unrestricted. Each byte has to be followed by an acknowledge bit. Data is transferred with the most significant bit,
MSB, first.
P
SDA
Sr
SCL
S
or
Sr
1
2
7
9
8
1
2
3-8
P
or
Sr
9
ACK
ACK
Acknowledge
• Each bytes of eight bits is followed by one acknowledge bit. This acknowledge bit is a low level placed on the
bus by the receiver. The master generates an extra acknowledge related clock pulse.
• A slave receiver which is addressed must generate an acknowledge, ACK, after the reception of each byte.
• The device that acknowledges must pull down the SDA line during the acknowledge clock pulse so that it
remains stable low during the high period of this clock pulse.
• A master receiver must signal an end of data to the slave by generating a not-acknowledge, NACK, bit on the
last byte that has been clocked out of the slave. In this case, the master receiver must leave the data line high
during the 9th pulse to not acknowledge. The master will generate a STOP or repeated START condition.
Data Output
by Transmitter
not acknowledge
Data Outptu
by Receiver
acknowledge
SCL From
Master
S
1
2
START
condition
Rev. 1.20
7
8
9
clock pulse for
acknowledgement
19
January 27, 2015
HT16C23/HT16C23G
Slave Addressing
• The slave address byte is the first byte received following the START condition form the master device. The
first seven bits of the first byte make up the slave address. The eighth bit defines a read or write operation to be
performed. When the R/W bit is “1”, then a read operation is selected. A “0” selects a write operation.
• The HT16C23/HT16C23G address bits are “0111110”. When an address byte is sent, the device compares the
first seven bits after the START condition. If they match, the device outputs an acknowledge on the SDA line.
Slave Address
MSB
LSB
0
1
1
1
1
1
0
R/W
Write Operation
Byte Writes Operation
• Command Byte
A Command Byte write operation requires a START condition, a slave address with an R/W bit, a command byte,
a command setting byte and a STOP condition for a command byte write operation.
Command byte
Command setting
BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BIT0
BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BIT0
Slave Address
S
0
1
1
1
1
1
0
0
Write ACK
ACK
1st
P
ACK
2nd
Command Byte Write Operation
• Display RAM Single Data Byte
A display RAM data byte write operation requires a START condition, a slave address with an R/W bit, a
command byte, a valid Register Address byte, a Data byte and a STOP condition.
Slave Address
S
0
1
1
1
1
1
0
0
Write ACK
Command byte
Register Address byte
BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BIT0
BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BIT0
1st
ACK
2nd
Data byte
D7
ACK
D6
D5
D4
D3
D2
D1
P
D0
ACK
Display RAM Single Data Byte Write Operation
Rev. 1.20
20
January 27, 2015
HT16C23/HT16C23G
Display RAM Page Write Operation
After a START condition the slave address with the R/W bit is placed on the bus followed with a command
byte and the specified display RAM Register Address of which the contents are written to the internal address
pointer. The data to be written to the memory will be transmitted next and then the internal address pointer will be
incremented by 1 to indicate the next memory address location after the reception of an acknowledge clock pulse.
After the internal address point reaches the maximum memory address, which is 1BH for 1/4 duty drive mode or
33H for 1/8 duty drive mode, the address pointer will be reset to 00H.
Command byte
Register Address byte
BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BIT0
BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BIT0
1st
2nd
Slave Address
S
0
1
1
1
1
1
0
0
Write
Data byte
D7
D6
D5
D4
ACK
ACK
ACK
Data byte
D3
D2
D1
D0
D7
D6
D5
D4
D3
Data byte
D2
D1
D0
D7
D6
D5
2nd data
1st data
D4
D3
D2
D1
Nth data
ACK
ACK
P
D0
ACK
ACK
N Bytes Display RAM Data Write Operation
Display RAM Read Operation
• In this mode, the master reads the HT16C23/HT16C23G data after setting the slave address. Following the
R/W bit (=“0”) is an acknowledge bit, a command byte and the register address byte which is written to the
internal address pointer. After the start address of the Read Operation has been configured, another START
condition and the slave address transferred on the bus followed by the R/W bit (=“1”). Then the MSB of the
data which was addressed is transmitted first on the I2C bus. The address pointer is only incremented by 1 after
the reception of an acknowledge clock. That means that if the device is configured to transmit the data at the
address of AN+1, the master will read and acknowledge the transferred new data byte and the address pointer is
incremented to AN+2. After the internal address pointer reaches the maximum memory address, which is 1Bh for
1/4 duty drive mode or 33H for 1/8 duty drive mode, the address pointer will be reset to 00H.
• This cycle of reading consecutive addresses will continue until the master sends a STOP condition.
Command byte
Register Address byte
BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BIT0
BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BIT0
Slave Address
S
0
1
1
1
1
1
0
0
Write
Device Address
S
0
1
1
1
1
0
1
Read
Rev. 1.20
2nd
1st
D7
D6
D5
D4
D3
Data byte
D2
D1
D7
D0
D6
D5
D4
D3
Data byte
D2
D1
D0
D7
2nd data
1st data
ACK
ACK
ACK
ACK
Data byte
1
P
ACK
21
D6
D5
D4
D3
Nth data
ACK
D2
D1
D0
P
NACK
ACK
January 27, 2015
HT16C23/HT16C23G
Command Summary
Display Data Input Command
This command sends data from MCU to memory MAP of the HT16C23/HT16C23G device.
Byte
(MSB)
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
(LSB)
Bit0
Display Data
Input/output
Command
1st
1
0
0
0
0
0
0
0
Address pointer
2nd
X
X
A5
A4
A3
A2
A1
A0
Function
Note
R/W Def
W
Display data
start address of
memory map
W
00H
Note:
●●Power on status: the address is set to 00H.
●●If the programmed command is not defined, the function will not be affected.
●●For 1/4 duty drive mode after reaching the memory location 1BH, the pointer will reset to 00H.
●●For 1/8 duty drive mode after reaching the memory location 33H, the pointer will reset to 00H.
Drive Mode Command
Function
Driver mode
setting
command
Duty and Bias
setting
Byte
(MSB)
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
(LSB)
Bit0
1st
1
0
0
0
0
0
1
0
2nd
X
X
X
X
X
X
Duty
Bias
Note
R/W Def
W
No matter
what “Duty” bit
is set, 1/8 duty
drive mode is
only available
for 48 LQFP.
W
00H
Note:
Bit
Duty
Bias
0
1/4duty
1/3bias
1
1/4duty
1/4bias
1
0
1/8duty
1/3bias
1
1
1/8duty
1/4bias
Duty
Bias
0
0
●●Power on status: The drive mode 1/4 duty output and 1/3 bias is selected.
●●If the programmed command is not defined, the function will not be affected.
Rev. 1.20
22
January 27, 2015
HT16C23/HT16C23G
System Mode Command
This command controls the internal system oscillator on/off and display on/off.
Function
Byte
(MSB)
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
(LSB)
Bit0
System mode setting
command
1st
1
0
0
0
0
1
0
0
W
System oscillator and
Display on/off Setting
2nd
X
X
X
X
X
X
S
E
W
Note
R/W Def
00H
Note:
Bit
Internal System
oscillator
LCD Display
X
off
off
0
on
off
1
on
on
S
E
0
1
1
●●Power on status: Display off and disable the internal system oscillator.
●●If the programmed command is not defined, the function will not be affected.
Frame Frequency Command
This command selects the frame frequency.
Byte
(MSB)
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
(LSB)
Bit0
Frame frequency
command
1st
1
0
0
0
0
1
1
0
W
Frame frequency
setting
2nd
X
X
X
X
X
X
X
F
W
Function
Note
R/W Def
00H
Note:
Bit
F
Frame Frequency
0
80Hz
1
160Hz
●●Power on status: Frame frequency is set to 80Hz.
●●If the programmed command is not defined, the function will not be affected.
Rev. 1.20
23
January 27, 2015
HT16C23/HT16C23G
Blinking Frequency Command
This command defines the blinking frequency of the display modes.
Byte
(MSB)
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
(LSB)
Bit0
Blinking Frequency
command
1st
1
0
0
0
1
0
0
0
W
Blinking Frequency
setting
2nd
X
X
X
X
X
X
BK1
BK0
W
Function
Note
R/W Def
00H
Note:
Bit
Blinking Frequency
BK1
BK0
0
0
Blinking off
0
1
2Hz
1
0
1Hz
1
1
0.5Hz
●●Power on status: Blinking function is switched off.
●●If the programmed command is not defined, the function will not be affected.
Rev. 1.20
24
January 27, 2015
HT16C23/HT16C23G
Internal Voltage Adjustment (IVA) Setting Command
The internal voltage (VLCD) adjustment can provide sixteen kinds of regulator voltage adjustment options by
setting the LCD operating voltage adjustment command.
Function Byte Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
IVA
Command
IVA
Control
1st
2nd
1
X
0
X
0
DE
0
VE
1
0
1
Note
R/W
0
Def
W
●●The Segment/VLCD shared
pin can be programmed via
the “DE” bit.
●●The “VE” bit is used to enable
or disable the internal voltage
DA3 DA2 DA1 DA0
adjustment is supply voltage
to bias voltage.
●●The DA3~DA0 bits can be
used to adjust the VLCD output
voltage.
W
30H
Note:
Bit
DE
VE
0
0
1
1
0
1
0
1
Segment
55/ VLCD
shared pin
select
VLCD
VLCD
Segment 55
Segment 55
Internal
Voltage
Adjustment
Note
off
●●The bias voltage is supplied by the external VLCD pin when VCCA2 is
connected to VLCD.
●●The bias voltage is supplied by the external VLCD pin when VCCA2 is
connected to VDD.
●●If the VLCD pin is connected to the VDD pin, the internal voltage
follower (OP4) must be disabled by setting the DA3~DA0 bits as “0000”.
on
●●When VCCA2 is connected to VLCD, internal voltage adjustment can
not be used to adjust internal bias voltage. (Bias voltage is supplied by
the external VLCD pin)
●●When VCCA2 is connected to VDD, internal voltage adjustment can not
be used to adjust internal bias voltage when VLCD pin is supplies with
external voltage.(Recommend: can not be used)
●●When VCCA2 is connected to VDD, internal voltage adjustment can
be used to adjust internal bias voltage when VLCD pin is floating and
internal voltage adjustment is enable.(Bias voltage is supplied by the
internal voltage adjustment)
off
●●The bias voltage is supplied by the external VLCD pin when VCCA2 is
connected to VLCD.
●●The bias voltage is supplied by the external VDD power when VCCA2
is connected to VDD.
●●The internal voltage-follower (OP4) is disabled automatically and
DA3~DA0 don’t care.
on
●●When VCCA2 is connected to VLCD, internal voltage adjustment can
be used to adjust internal bias voltage when VLCD pin is supplies
with external voltage and internal voltage adjustment is enable. (Bias
voltage is supplied by the internal voltage adjustment)
●●When VCCA2 is connected to VDD, internal voltage adjustment can be
used to adjust internal bias voltage when internal voltage adjustment is
enable.(Bias voltage is supplied by the internal voltage adjustment)
●●Power on status: Enable the internal voltage Adjustment and the Segment/VLCD pin is set as the segment pin.
●●When the DA0~DA3 bits are set to “0000”, the internal voltage-follower (OP4) is disabled. When the DA0~DA3
bits are set to other values except “0000”, the internal voltage follower (OP4) is enabled.
●●If the programmed command is not defined, the function will not be affected.
Rev. 1.20
25
January 27, 2015
HT16C23/HT16C23G
Operation Flowchart
Access procedures are illustrated below by means of the flowcharts.
Initialization
Power On
Internal LCD bias and duty setting
Internal LCD frame frequency setting
Segment / VLCD shared pin setting
LCD blinking frequency setting
Next processing
Rev. 1.20
26
January 27, 2015
HT16C23/HT16C23G
Display Data Read/Write (Address Setting)
Start
Address setting
Display RAM data write
Display on and enable internal system clock
Next processing
Rev. 1.20
27
January 27, 2015
HT16C23/HT16C23G
Segment / VLCD Shared Pin and Internal Voltage Adjustment Setting
Start
Set as Segment pin
Internal voltage
adjustment
enable ?
yes
Segment / VLCD share
pin setting
The bias voltage is supplied by
Programmable Internal voltage
adjustment
no
The bias voltage is supplied by
internal VDD power
Rev. 1.20
Set as VLCD pin
The external MCU
can detect the
voltage of VLCD pin
yes
Internal voltage
adjustment
enable ?
no
One external resistor must be connected
between to VLCD pin and VDD pin to
determine the bias voltage
Next processing
28
January 27, 2015
HT16C23/HT16C23G
Application Circuits
64-pin Package
1/4 Duty
VLCD
0.1uF
VDD
0.1uF
VDD
4.7KΩ
VLCD
VDD
4.7KΩ
COM0~COM3
COM0~COM3
SCL
HOST
HT16C23
LCD panel
SDA
SEG0~SEG54
SEG0~SEG54
VSS
VSS
VSS
1/8 Duty
VLCD
0.1uF
VDD
0.1uF
VDD
4.7KΩ
VLCD
VDD
4.7KΩ
COM0~COM7
COM0~COM7
SCL
HOST
HT16C23
LCD panel
SDA
SEG4~SEG54
SEG0~SEG50
VSS
VSS
VSS
Rev. 1.20
29
January 27, 2015
HT16C23/HT16C23G
48-pin Package (The 48-pin Package Supports LCD 1/8 Duty only)
VLCD
0.1uF
VDD
0.1uF
VDD
4.7KΩ
VLCD
VDD
4.7KΩ
COM0~COM7
COM0~COM7
SCL
HOST
HT16C23
LCD panel
SDA
SEG4~SEG38
SEG0~SEG34
VSS
VSS
VSS
Rev. 1.20
30
January 27, 2015
HT16C23/HT16C23G
Package Information
Note that the package information provided here is for consultation purposes only. As this information may be
updated at regular intervals users are reminded to consult the Holtek website for the latest version of the package
information.
Additional supplementary information with regard to packaging is listed below. Click on the relevant section to be
transferred to the relevant website page.
• Further Package Information (include Outline Dimensions, Product Tape and Reel Specifications)
• Packing Meterials Information
• Carton information
Rev. 1.20
31
January 27, 2015
HT16C23/HT16C23G
48-pin LQFP (7mm×7mm) Outline Dimensions
Symbol
Dimensions in inch
Min.
Nom.
Max.
A
—
0.354 BSC
—
B
—
0.276 BSC
—
C
—
0.354 BSC
—
D
—
0.276 BSC
—
E
—
0.020 BSC
—
F
0.007
0.009
0.011
G
0.053
0.055
0.057
H
—
—
0.063
I
0.002
—
0.006
J
0.018
0.024
0.030
K
0.004
—
0.008
α
0°
―
7°
Symbol
Rev. 1.20
Dimensions in mm
Min.
Nom.
Max.
A
—
9.00 BSC
—
B
—
7.00 BSC
—
C
—
9.00 BSC
—
D
—
7.00 BSC
—
E
—
0.50 BSC
—
F
0.17
0.22
0.27
G
1.35
1.40
1.45
H
—
—
1.60
I
0.05
—
0.15
J
0.45
0.60
0.75
K
0.09
—
0.20
α
0°
―
7°
32
January 27, 2015
HT16C23/HT16C23G
64-pin LQFP (7mm×7mm) Outline Dimensions
Symbol
Min.
Nom.
Max.
A
—
0.354 BSC
—
B
—
0.276 BSC
—
C
—
0.354 BSC
—
D
—
0.276 BSC
—
E
—
0.016 BSC
—
F
0.005
0.007
0.009
G
0.053
0.055
0.057
H
—
—
0.063
I
0.002
—
0.006
J
0.018
0.024
0.030
K
0.004
—
0.008
α
0°
—
7°
Symbol
Rev. 1.20
Dimensions in inch
Dimensions in mm
Min.
Nom.
Max.
A
—
9.0 BSC
—
B
—
7.0 BSC
—
C
—
9.0 BSC
—
D
—
7.0 BSC
—
E
—
0.4 BSC
—
F
0.13
0.18
0.23
G
1.35
1.40
1.45
H
—
—
1.60
I
0.05
—
0.15
J
0.45
0.60
0.75
K
0.09
—
0.20
α
0°
—
7°
33
January 27, 2015
HT16C23/HT16C23G
Copyright© 2015 by HOLTEK SEMICONDUCTOR INC.
The information appearing in this Data Sheet is believed to be accurate at the time
of publication. However, Holtek assumes no responsibility arising from the use of
the specifications described. The applications mentioned herein are used solely
for the purpose of illustration and Holtek makes no warranty or representation that
such applications will be suitable without further modification, nor recommends
the use of its products for application that may present a risk to human life due to
malfunction or otherwise. Holtek's products are not authorized for use as critical
components in life support devices or systems. Holtek reserves the right to alter
its products without prior notification. For the most up-to-date information, please
visit our web site at http://www.holtek.com.tw.
Rev. 1.20
34
January 27, 2015