HT9B95 RAM Mapping 39×8 / 43×4 LCD Driver Feature Selection Table • Logic Operating Voltage: 2.4V~5.5V Part No. COM SEG • Integrated oscillator circuitry HT9B95A 8 35 8 39 4 43 8 39 4 43 • Bias: 1/3 or 1/4 HT9B95B • Internal LCD bias generation with voltage-follower buffers HT9B95G • External VLCD pin to supply LCD operating voltage Package 48TSSOP, 52LQFP 52LQFP COG • Support I2C-bus serial interface • Integrated voltage adjustment function for LCD driving voltage Applications • Leisure products • Up to 39×8 bits RAM for display data storage • Telephone display • Display patterns • Household appliance HT9B95A: 35×8 patterns - 35 segments and 8 commons ♦♦ HT9B95B: 39×8 patterns - 39 segments and 8 commons 43×4 patterns - 43 segments and 4 commons ♦♦ HT9B95G: 39×8 patterns - 39 segments and 8 commons 43×4 patterns - 43 segments and 4 commons ♦♦ • Consumer electronics General Description The HT9B95 is a memory mappling and multifunction LCD controller driver. The maximum display segments of the device are 312 patterns (39 segments and 8 commons) or 280 patterns (35 segments and 8 commons) display depending upon which device is selected. The software configuration feature of the HT9B95 device makes it suitable for multiple LCD applications including LCD modules and display subsystems. The HT9B95 device communicates with most microprocessors / microcontrollers via a two-wire bidirectional I2C-bus interface. • Support Power Save Mode for low power consumption • Package Type HT9B95A: 48-pin TSSOP, 52-pin LQFP HT9B95B: 52-pin LQFP ♦♦ HT9B95G: COG ♦♦ ♦♦ Rev. 1.00 1 May 28, 2015 HT9B95 Block Diagram Power ON Reset SCL SDA SEG0 SEG1 SEG2 I2C Controller Display RAM Internal Oscillator Timing Generator Segment driver output VDD SEG38 VLCD _ OP + _ OP Common /Segment driver output COM0/SEG39 COM1/SEG40 COM2/SEG41 COM3/SEG42 Common driver output COM4/COM0 COM5/COM1 COM6/COM2 COM7/COM3 + _ OP + LCD Voltage Selector _ OP + VSS LCD Bias Generator Rev. 1.00 2 May 28, 2015 HT9B95 Pin Assignment 47 3 46 4 45 5 44 6 43 7 42 8 41 9 40 10 39 11 38 12 37 13 36 14 35 15 34 16 33 17 32 18 31 19 30 20 29 21 28 22 27 23 26 24 25 HT9B95A 48 TSSOP-A SDA SCL SEG21 SEG22 SEG23 SEG24 SEG25 SEG26 SEG27 SEG28 SEG29 SEG30 SEG31 SEG32 SEG33 SEG34 COM0 COM1 COM2 COM3 COM4 COM5 COM6 COM7 SEG5 SEG4 SEG3 SEG2 SEG1 SEG0 COM7 COM6 COM5 COM4 COM3 COM2 COM1 39 38 37 36 35 34 33 32 31 30 29 28 27 26 40 25 41 24 42 23 43 22 44 21 45 HT9B95A 20 46 52 LQFP-A 47 19 18 48 17 49 16 50 51 15 14 52 1 2 3 4 5 6 7 8 9 10 11 12 13 SEG4 SEG3 SEG2 SEG1 SEG0 COM7/COM3 COM6/COM2 COM5/COM1 COM4/COM0 COM3/SEG42 COM2/SEG41 COM1/SEG40 COM0/SEG39 39 38 37 36 35 34 33 32 31 30 29 28 27 26 40 25 41 42 24 23 43 22 44 21 45 HT9B95B 20 46 52 LQFP-A 19 47 18 48 17 49 16 50 51 15 14 52 1 2 3 4 5 6 7 8 9 10 11 12 13 SEG18 SEG19 SEG20 VSS VLCD VDD SDA SCL SEG21 SEG22 SEG23 SEG24 SEG25 SEG17 SEG16 SEG15 SEG14 SEG13 SEG12 SEG11 SEG10 SEG9 SEG8 SEG7 SEG6 SEG5 48 2 NC NC SEG26 SEG27 SEG28 SEG29 SEG30 SEG31 SEG32 SEG33 SEG34 COM0 NC 1 SEG17 NC SEG16 SEG15 SEG14 SEG13 SEG12 SEG11 SEG10 SEG9 SEG8 SEG7 SEG6 VDD VLCD VSS SEG20 SEG19 SEG18 SEG17 SEG16 SEG15 SEG14 SEG13 SEG12 SEG11 SEG10 SEG9 SEG8 SEG7 SEG6 SEG5 SEG4 SEG3 SEG2 SEG1 SEG0 SEG18 SEG19 SEG20 VSS VLCD VDD SDA SCL SEG21 SEG22 SEG23 SEG24 SEG25 SEG26 SEG27 SEG28 SEG29 SEG30 SEG31 SEG32 SEG33 SEG34 SEG35 SEG36 SEG37 SEG38 Rev. 1.00 3 May 28, 2015 HT9B95 Pad Assignment for COG − HT9B95G 3 DUMMY 2 DUMMY COM7 / COM3 COM6 / COM2 COM5 / COM1 COM4 / COM0 DUMMY COM3 / SEG42 COM2 / SEG41 COM1 / SEG40 COM0 / SEG39 SEG38 SEG37 SEG36 SEG35 SEG34 SEG33 SEG32 SEG31 SEG30 SEG29 SEG28 SEG27 SEG26 SEG25 SEG24 SEG23 SEG22 SEG21 SEG20 SEG19 SEG18 SEG17 SEG16 SEG15 SEG14 SEG13 SEG12 SEG11 SEG10 SEG9 SEG8 SEG7 SEG6 SEG5 SEG4 SEG3 SEG2 SEG1 SEG0 DUMMY 1 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 DUMMY Y 26 DUMMY X DUMMY 4 DUMMY 5 24 DUMMY DUMMY 6 23 DUMMY DUMMY 7 22 DUMMY ALIGN_A 8 21 ALIGN_B (0,0) 15 16 17 18 VDD VLCD DUMMY VSS 19 20 DUMMY 14 DUMMY 13 SDA DUMMY 12 SCL DUMMY 11 TEST 10 DUMMY 9 25 DUMMY Pad Dimensions for COG Item Size Pad Number X Y Chip size ─ Chip thickness ─ 508 μm 1, 28~75 60 μm 2~7, 22~27 80 μm 9~20 >80 μm Pad pitch Bump size Bump height Rev. 1.00 3108 1132 Unit µm 1, 28~75 40 60 μm 2~7, 22~27 40 60 μm 9~20 67 67 μm All pad 18±3 4 μm May 28, 2015 HT9B95 Alignment Mark Dimensions for COG Item Number Size Unit ALIGN_A 8 μm ALIGN_B 21 μm Pad Coordinates for COG Unit: μm No. Name X Y No. Name X Y 1 DUMMY -1470.500 472.500 39 SEG36 762.700 472.500 2 DUMMY -1470.500 136.340 40 SEG35 702.700 472.500 3 DUMMY -1470.500 56.340 41 SEG34 642.700 472.500 4 DUMMY -1470.500 -23.660 42 SEG33 582.700 472.500 5 DUMMY -1470.500 -103.660 43 SEG32 522.700 472.500 6 DUMMY -1470.500 -183.660 44 SEG31 462.700 472.500 7 DUMMY -1470.500 -263.660 45 SEG30 402.700 472.500 8 ALIGN_A -1477.000 -330.000 46 SEG29 342.700 472.500 9 DUMMY -1457.000 -469.000 47 SEG28 282.700 472.500 10 DUMMY -923.150 -469.000 48 SEG27 222.700 472.500 11 DUMMY -552.600 -469.000 49 SEG26 162.700 472.500 12 TEST -187.900 -469.000 50 SEG25 102.700 472.500 13 SCL 4.100 -468.000 51 SEG24 42.700 472.500 14 SDA 89.100 -468.000 52 SEG23 -17.300 472.500 15 VDD 182.900 -468.000 53 SEG22 -77.300 472.500 16 VLCD 270.950 -469.000 54 SEG21 -137.300 472.500 17 DUMMY 406.900 -469.000 55 SEG20 -197.300 472.500 18 VSS 490.950 -469.000 56 SEG19 -257.300 472.500 19 DUMMY 963.600 -469.000 57 SEG18 -317.300 472.500 20 DUMMY 1457.000 -469.000 58 SEG17 -377.300 472.500 21 ALIGN_B 1458.000 -330.000 59 SEG16 -437.300 472.500 22 DUMMY 1470.500 -260.810 60 SEG15 -497.300 472.500 23 DUMMY 1470.500 -180.810 61 SEG14 -557.300 472.500 Rev. 1.00 5 May 28, 2015 HT9B95 No. Name X Y No. Name X Y 24 DUMMY 1470.500 -100.810 62 SEG13 -617.300 472.500 25 DUMMY 1470.500 -20.810 63 SEG12 -677.300 472.500 26 DUMMY 1470.500 59.190 64 SEG11 -737.300 472.500 27 DUMMY 1470.500 139.190 65 SEG10 -797.300 472.500 28 DUMMY 1470.500 472.500 66 SEG9 -857.300 472.500 29 COM7/COM3 1396.300 472.500 67 SEG8 -917.300 472.500 30 COM6/COM2 1336.300 472.500 68 SEG7 -977.300 472.500 31 COM5/COM1 1276.300 472.500 69 SEG6 -1037.300 472.500 32 COM4/COM0 1216.300 472.500 70 SEG5 -1097.300 472.500 33 COM3/SEG42 1147.700 472.500 71 SEG4 -1157.300 472.500 34 COM2/SEG41 1087.700 472.500 72 SEG3 -1217.300 472.500 35 COM1/SEG40 1027.700 472.500 73 SEG2 -1277.300 472.500 36 COM0/SEG39 967.700 472.500 74 SEG1 -1337.300 472.500 37 SEG38 882.700 472.500 75 SEG0 -1397.300 472.500 38 SEG37 822.700 472.500 Pin Description HT9B95A Pin Name Type Description SDA I/O Serial Data Input/Output pin Serial Data (SDA) Input/Output for 2-wire I2C interface is an NMOS open drain structure. SCL I Serial Clock Input pin Serial Data (SCL) is a clock input for 2-wire I2C interface. COM0~COM7 O LCD Common outputs. SEG0~SEG34 O LCD Segment outputs. VDD — Positive power supply. VSS — Negative power supply, ground. VLCD — LCD power supply pin HT9B95B/HT9B95G Pin Name Type Description SDA I/O Serial Data Input/Output pin Serial Data (SDA) Input/Output for 2-wire I2C interface is an NMOS open drain structure. SCL I Serial Clock Input pin Serial Data (SCL) is a clock input for 2-wire I2C interface. COM0/SEG39 ~ COM3/SEG42 O LCD common or segment outputs These pins are set to COM0 ~ COM3 when 1/8 duty is set These pins are set to SEG39 ~ SEG42 when 1/4 duty is set COM4/COM0 ~ COM7/COM3 O LCD Common outputs. These pins are set to COM4 ~ COM7 when 1/8 duty is set These pins are set to COM0 ~ COM3 when 1/4 duty is set SEG0~SEG38 O LCD Segment outputs. VDD — Positive power supply. VSS — Negative power supply, ground. VLCD — LCD power supply pin TEST — TEST pin in HT9B95G, keep floating. Only available in HT9B95G. DUMMY — Dummy pin, keep floating. Only available in HT9B95G. Rev. 1.00 6 May 28, 2015 HT9B95 Approximate Internal Connections SCL, SDA (for Schmitt trigger type) COM0/SEG39 ~ COM3/SEG42 COM4/COM0 ~ COM7/COM3 SEG0 ~ SEG38 VDD VLCD VSS VLCD VSS VSS Absolute Maximum Ratings Supply Voltage ����������������������������������������������������������������������������������������������������������������������������VSS-0.3V ~ VSS+6.5V Input Voltage ����������������������������������������������������������������������������������������������������������������������������� VSS-0.3V ~ VDD+0.3V Storage Temperature ���������������������������������������������������������������������������������������������������������������������������� -55°C ~ 150°C Operating Temperature �������������������������������������������������������������������������������������������������������������������������� -40°C ~ 85°C Note: These are stress ratings only. Stresses exceeding the range specified under "Absolute Maximum Ratings" may cause substantial damage to these devices. Functional operation of these devices at other conditions beyond those listed in the specification is not implied and prolonged exposure to extreme conditions may affect devices reliability. Timing Diagrams I2C Timing SDA tBUF tSU:DAT tf tLOW tHD:STA tr tSP SCL tHD:SDA S tHD:DAT tHIGH tSU:STA tAA tSU:STO Sr P S SDA OUT Rev. 1.00 7 May 28, 2015 HT9B95 Power On Reset Timing Note: 1. If the conditions of Reset timing are not satisfied in power ON/OFF sequence, the internal Power on Reset (POR) circuit will not operate normally. 2. If it is difficult to meet power on reset timing conditions, please execute software reset command after Power on. D.C. Characteristics Symbol Parameter VSS = 0V; VDD =2.4V to 5.5V; Ta = -40°C to +85°C Test condition VDD Condition Min. Typ. Max. Unit VDD Operating Voltage — — 2.4 — 5.5 V VLCD LCD Operating Voltage — — 2.5 — 5.5 V VIH Input High Voltage — SCL, SDA 0.7VDD — VDD V VIL Input Low Voltage — SCL, SDA 0 — 0.3VDD V IIL Input Leakage Current — VIN=VSS or VDD -1 — 1 μA IOL Low Level Output Current IDD ILCD ISTB IOL1 IOH1 Operating Current Operating Current Standby Current LCD Common Sink Current LCD Common Source Current 3.3V 5.0V VOL=0.4V for SDA pin VLCD=VDD, No load, Ta=25°C, 3.3V LCD display on, f =80Hz, LCD 1/4 bias, 1/8 duty, B type inversion, 5.0V Power save mode = Low Current2 mode VLCD=VDD, No load, Ta=25°C, 3.3V LCD display on, f =80Hz, LCD 1/4 bias, 1/8 duty, B type inversion, 5.0V Power save mode = Low Current2 mode VLCD=VDD, No load, Ta=25°C, 3.3V LCD display off, f =80Hz, LCD 1/4 bias, 1/8 duty, B type inversion, 5.0V Power save mode = Low Current2 mode — — IOL2 LCD Segment Sink Current — IOH2 LCD Segment Source Current — — — mA — — mA — 3 10 μA — 5 20 μA — 5 20 μA — 6 30 μA — — 1 μA — — 2 μA VLCD=3.3V, VOL=0.33V 250 400 — μA VLCD=5V, VOL=0.5V 500 800 — μA VLCD=3.3V, VOH=2.97V -140 -230 — μA VLCD=5V, VOH=4.5V -300 -500 — μA VLCD=3.3V, VOL=0.33V 250 400 — μA VLCD=5V, VOL=0.5V 500 800 — μA VLCD=3.3V, VOH=2.97V -140 -230 — μA VLCD=5V, VOH=4.5V -300 -500 — μA A.C. Characteristics Rev. 1.00 6 9 VSS = 0V; VDD =2.4V to 5.5V; Ta= -40°C to +85 °C 8 May 28, 2015 HT9B95 Symbol fLCD1 fLCD2 Parameter LCD Frame Frequency LCD Frame Frequency Test condition Min. Typ. Max. Ta=25°C, internal oscillator is used, LCD frame frequency = 80 Hz 72 80 88 Ta=25°C, internal oscillator is used, LCD frame frequency = 71 Hz 63.9 71 78.1 Ta=25°C, internal oscillator is used, LCD frame frequency = 64 Hz 57.6 64 70.4 Ta=25°C, internal oscillator is used, LCD frame frequency = 50Hz 45 50 55 Ta=-40 to 85°C, internal oscillator is used, LCD frame frequency = 80 Hz 56 80 104 Ta=-40 to 85°C, internal oscillator is used, 49.7 LCD frame frequency = 71 Hz 71 92.3 Ta=-40 to 85°C, internal oscillator is used, 44.8 LCD frame frequency = 64 Hz 64 83.2 Ta=-40 to 85°C, internal oscillator is used, 35.2 LCD frame frequency = 50Hz 50 65 condition VDD 3.3V 2.4~ 5.5V Unit Hz Hz VPOR VDD Start Voltage to ensure Poewr-on Reset — — — — 100 mV RRVDD VDD Rise Rate to ensure Power-on Reset — — 0.05 — — V/ms tPOR Minimum Time for VDD to remain at VPOR to ensure Power-on Reset — — 10 — — ms I2C Interface Characteristics Unless otherwise specified, VSS = 0 V; VDD = 2.4V to 5.5V; Ta=-40 to +85°C Symbol Parameter Condition Min. Max. Unit — — 400 kHZ fSCL Clock frequency tBUF bus free time Time in which the bus must be free before a new transmission can start 1.3 — μs tHD: STA Start condition hold time After this period, the first clock pulse is generated. 0.6 — μs tLOW SCL Low time — 1.3 — μs tHIGH SCL High time — 0.6 — μs tSU: STA Start condition setup time Only relevant for repeated START condition. 0.6 — μs tHD: DAT Data hold time — 0 — ns tSU: DAT Data setup time — 100 — ns tR SDA and SCL rise time Note — 0.3 μs tF SDA and SCL fall time Note — 0.3 μs tSU: STO Stop condition set-up time — 0.6 — μs tAA Output Valid from Clock — — 0.9 μs tSP Input Filter Time Constant (SDA and SCL Pins) Noise suppression time — 50 ns Note: These parameters are periodically sampled but not 100% tested. Rev. 1.00 9 May 28, 2015 HT9B95 Functional Description Power-On Reset Column Driver Outputs When the power is applied, the device is initialized by an internal power-on reset circuit. The status of the internal circuits after initialization is as follows: The LCD drive section includes up to 8 column outputs COM0~COM7 which should be connected directly to the LCD panel. The column output signals are generated in accordance with the selected LCD drive mode. The unused column outputs should be left open-circuit if less than 8 column outputs are required. • All common outputs are set to VSS. • All segment outputs are set to VSS. • LCD Driver Output Waveform: B-type inversion. • Internal oscillator is selected. Address Pointer • The 1/3 bias drive mode is selected. The addressing mechanism for the display RAM is implemented using the address pointer. This allows the loading of an individual display data byte, or a series of display data bytes, into any location of the display RAM. The sequence commences with the initialization of the address pointer by the Display Data Input command. • LCD bias generator is in an off state. • LCD Display and internal oscillator are in off states. • Power save mode is set to normal current. • Frame Frequency is set to 80Hz. • Blinking function is switched off Data transfers on the I2C-bus should be avoided for 1 ms following power-on to allow completion of the reset action. Display Memory – RAM Structure The display RAM is static 39x8 bits RAM which stores the LCD data. Logic “1” in the RAM bit-map indicates the “on” state of the corresponding LCD segment; similarly, logic 0 indicates the ‘off’ state. System Oscillator The timing for the internal logic and the LCD drive signals are generated by the internal oscillator. The System Clock frequency (fSYS) determines the LCD frame frequency. During initial system power on the System Oscillator will be in the stop state. The contents of the RAM data are directly mapped to the LCD data. The first RAM column corresponds to the segments operated with respect to COM0. In multiplexed LCD applications the segment data from 2nd to 7th column of the display RAM are timemultiplexed with COM1 to COM7 respectively. The following diagram is a data transfer format for I2C interface. Segment Driver Outputs The LCD drive section includes up to 43 segment outputs SEG0 ~ SEG42 which should be connected directly to the LCD panel. The segment output signals are generated in accordance with the multiplexed common signals and with the data resident in the display latch. The unused segment outputs should be left open-circuit. Rev. 1.00 MSB SDA Data Bit 7 LSB Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 LCD Display Output Data Transfer Format for I2C Bus 10 May 28, 2015 HT9B95 When the HT9B95A device is selected, the LCD RAM map is implemented as the following table shown. Address COM0 COM1 COM2 COM3 COM4 COM5 COM6 COM7 Output 00H SEG0 01H SEG1 02H SEG2 03H SEG3 : : : : : : : : : : : : : : : : : : : : 1FH SEG31 20H SEG32 21H SEG33 22H RAM Data SEG34 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 RAM Mapping of 35x8 Display Mode When the HT9B95B/HT9B95G device is selected with 1/8 duty, the LCD RAM map is implemented as the following table shown. Address COM0 COM1 COM2 COM3 COM4 COM5 COM6 COM7 Output 00H SEG0 01H SEG1 02H SEG2 03H SEG3 : : : : : : : : : : : : : : : : : : : : 23H SEG35 24H SEG36 25H SEG37 26H SEG38 RAM Data Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 RAM Mapping of 39x8 Display Mode When the HT9B95B/HT9B95G device is selected with 1/4 duty, the LCD RAM map is implemented as the following table shown. Address COM0 COM1 COM2 COM3 Output COM0 COM1 COM2 COM3 Output 00H SEG0 SEG1 01H SEG2 SEG3 02H SEG4 SEG5 03H SEG6 SEG7 : : : : : : : : : : : : : : : : : : : : : : 12H SEG36 SEG37 13H SEG38 SEG39 14H SEG40 15H SEG42 RAM Data Bit 7 Bit 6 Bit 5 Bit 4 SEG41 — — — — Bit 3 Bit 2 Bit 1 Bit 0 — RAM Mapping of 43x4 Display Mode Rev. 1.00 11 May 28, 2015 HT9B95 LCD Bias Generator The max voltage level of the LCD driving voltage named as V0 can be adjusted through the LVA command setting. The full-scale LCD voltage, VOP, is obtained from (V0-VSS). Fractional LCD biasing voltages, known as 1/3 or 1/4 bias voltage, are obtained from an internal voltage divider several of series resistors connected between VLCD and VSS. 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LCD Drive Mode Waveforms • When the LCD drive mode is selected as 1/4 duty and 1/3 bias, the waveform and LCD display is shown as follows: AAType Typeinversion inversion BBType Typeinversion inversion tLCD tLCD V0 V0 COM0 COM0 2Vop/3 2Vop/3 Vop/3 Vop/3 V0 V0 COM0 COM0 VSS VSS COM1 COM1 Vop/3 Vop/3 V0 V0 COM1 COM1 Vop/3 Vop/3 COM2 COM2 Vop/3 Vop/3 COM3 COM3 Vop/3 Vop/3 SEG n SEG n Vop/3 Vop/3 SEG n+1 SEG n+1 Vop/3 Vop/3 SEG n+2 SEG n+2 Vop/3 Vop/3 2Vop/3 2Vop/3 Vop/3 Vop/3 V0 V0 V0 V0 SEG n+3 SEG n+3 Vop/3 Vop/3 VSS VSS VSS VSS 2Vop/3 2Vop/3 2Vop/3 2Vop/3 V0 V0 V0 V0 SEG n+2 SEG n+2 Vop/3 Vop/3 VSS VSS VSS VSS 2Vop/3 2Vop/3 2Vop/3 2Vop/3 V0 V0 V0 V0 SEG n+1 SEG n+1 Vop/3 Vop/3 VSS VSS VSS VSS 2Vop/3 2Vop/3 2Vop/3 2Vop/3 V0 V0 V0 V0 SEG n SEG n Vop/3 Vop/3 VSS VSS VSS VSS 2Vop/3 2Vop/3 2Vop/3 2Vop/3 V0 V0 V0 V0 COM3 COM3 State2 State2 (off) (off) VSS VSS VSS VSS 2Vop/3 2Vop/3 Vop/3 Vop/3 State1 State1 (on) (on) V0 V0 V0 V0 COM2 COM2 2Vop/3 2Vop/3 VSS VSS VSS VSS 2Vop/3 2Vop/3 Vop/3 Vop/3 VSS VSS V0 V0 2Vop/3 2Vop/3 LCD LCDstatus status 2Vop/3 2Vop/3 SEG n+3 SEG n+3 2Vop/3 2Vop/3 Vop/3 Vop/3 VSS VSS VSS VSS Waveforms for 1/4 duty drive mode with 1/3 bias (VOP=V0-VSS) Note: tLCD=1/fLCD Rev. 1.00 12 May 28, 2015 HT9B95 • When the LCD drive mode is selected as 1/8 duty and 1/4 bias, the waveform and LCD display is shown as follows: COM0 V0 V0-VOP/4 V0-2VOP/4 V0-3VOP/4 VSS COM1 V0 V0-VOP/4 V0-2VOP/4 V0-3VOP/4 VSS COM2 V0 V0-VOP/4 V0-2VOP/4 V0-3VOP/4 VSS COM3 tLCD COM0 V0 V0-VOP/4 V0-2VOP/4 V0-3VOP/4 VSS COM1 V0 V0-VOP/4 V0-2VOP/4 V0-3VOP/4 VSS COM2 V0 V0-VOP/4 V0-2VOP/4 V0-3VOP/4 VSS V0 V0-VOP/4 V0-2VOP/4 V0-3VOP/4 VSS COM3 V0 V0-VOP/4 V0-2VOP/4 V0-3VOP/4 VSS COM4 V0 V0-VOP/4 V0-2VOP/4 V0-3VOP/4 VSS COM4 V0 V0-VOP/4 V0-2VOP/4 V0-3VOP/4 VSS COM5 V0 V0-VOP/4 V0-2VOP/4 V0-3VOP/4 VSS COM5 V0 V0-VOP/4 V0-2VOP/4 V0-3VOP/4 VSS COM6 V0 V0-VOP/4 V0-2VOP/4 V0-3VOP/4 VSS COM6 V0 V0-VOP/4 V0-2VOP/4 V0-3VOP/4 VSS COM7 V0 V0-VOP/4 V0-2VOP/4 V0-3VOP/4 VSS COM7 V0 V0-VOP/4 V0-2VOP/4 V0-3VOP/4 VSS SEGn V0 V0-VOP/4 V0-2VOP/4 V0-3VOP/4 VSS SEGn V0 V0-VOP/4 V0-2VOP/4 V0-3VOP/4 VSS SEGn+1 V0 V0-VOP/4 V0-2VOP/4 V0-3VOP/4 VSS SEGn+1 V0 V0-VOP/4 V0-2VOP/4 V0-3VOP/4 VSS SEGn+2 V0 V0-VOP/4 V0-2VOP/4 V0-3VOP/4 VSS SEGn+2 V0 V0-VOP/4 V0-2VOP/4 V0-3VOP/4 VSS SEGn+3 V0 V0-VOP/4 V0-2VOP/4 V0-3VOP/4 VSS SEGn+3 V0 V0-VOP/4 V0-2VOP/4 V0-3VOP/4 VSS tLCD LCD LCDstatus status State1 State1 (on) (on) State2 State2 (off) (off) Waveforms for 1/8 duty drive mode with1/4 bias (VOP= V0-VSS) Note: tLCD=1/fLCD Rev. 1.00 13 May 28, 2015 HT9B95 I2C Serial Interface I2C Operation 2 Acknowledge • Each bytes of eight bits is followed by one acknowledge bit. This Acknowledge bit is a low level placed on the bus by the receiver. The master generates an extra acknowledge related clock pulse. 2 The device supports I C serial interface. The I C bus is for bidirectional, two-line communication between different ICs or modules. The two lines are a serial data line, SDA, and a serial clock line, SCL. Both lines are connected to the positive supply via pull-up resistors with a typical value of 4.7kΩ. When the bus is free, both lines are high. Devices connected to the bus must have open-drain or open-collector outputs to implement a wired-or function. Data transfer is initiated only when the bus is not busy. • A slave receiver which is addressed must generate an Acknowledge, ACK, after the reception of each byte. • The device that acknowledges must pull down the SDA line during the acknowledge clock pulse so that it remains stable low during the high period of this clock pulse. Data Validity The data on the SDA line must be stable during the high period of the serial clock. The high or low state of the data line can only change when the clock signal on the SCL line is Low as shown in the diagram. • A master receiver must signal an end of data to the slave by generating a not-acknowledge, NACK, bit on the last byte that has been clocked out of the slave. In this case, the master receiver must leave the data line high during the 9th pulse to not acknowledge. The master will generate a STOP or repeated START condition. Data Output by Transmitter not acknowledge START and STOP Conditions • A high to low transition on the SDA line while SCL is high defines a START condition. Data Outptu by Receiver acknowledge SCL From Master • A low to high transition on the SDA line while SCL is high defines a STOP condition. SDA SCL S 8 9 clock pulse for acknowledgement • The HT9B95 device address bits are “0111110”. When an address byte is sent, the device compares the first seven bits after the START condition. If they match, the device outputs an Acknowledge on the SDA line. P START condition 7 Slave Addressing • The slave address byte is the first byte received following the START condition form the master device. The first seven bits of the first byte make up the slave address. The eighth bit defines a read or write operation to be performed. When the R/W bit is “1”, a read operation is selected. When the R/ W bit is “0”, a write operation is selected. • The bus stays busy if a repeated START (Sr) is generated instead of a STOP condition. In some respects, the START(S) and repeated START (Sr) conditions are functionally identical. SCL 2 START condition • START and STOP conditions are always generated by the master. The bus is considered to be busy after the START condition. The bus is considered to be free again a certain time after the STOP condition. SDA 1 S STOP condition Byte Format Every byte put on the SDA line must be 8-bit long. The number of bytes that can be transmitted per transfer is unrestricted. Each byte has to be followed by an acknowledge bit. Data is transferred with the most significant bit, MSB, first. Slave Address MSB 0 1 1 1 1 1 LSB 0 R/W P SDA Sr SCL S or Sr Rev. 1.00 1 2 7 8 9 ACK 1 2 3-8 9 ACK P or Sr 14 May 28, 2015 HT9B95 I2C Interface Write Operation Slave Address S Write Operation A Write operation requires a START condition, a slave address byte with a R/W bit, a command byte, a command byte or display RAM data byte and a STOP condition. Slave Address 1 1 1 1 Command byte 1 1 0 0 0 0 R/ W C Bit6 Bit5 ACK st 1 • Display RAM Single Data Byte A display RAM data byte write operation requires a START condition, a slave address with a R/W bit, a valid Register Address byte, a Data byte and a STOP condition. The start address can only be set from 00H to the maximum available address, 22H, 15H or 26H, depending upon which device is used with different duty configurations. It is recommended that the start address should not be greater than the maximum available address. Bit4 Bit3 Bit2 Command byte Bit1 Bit0 C bit ="1", the next byte is command ACK P Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 C bit ACK Command byte 1 1 • Compound Command Type A Compound Command write operation requires a START condition, a slave address with a R/W bit followed by multiple command bytes and finally a STOP condition for a compound command write operation. • Single Command Type A Single Command write operation requires a START condition, a slave address with a R/W bit, a command byte and a STOP condition for a single command write operation. 1 1 I2C Single Command Type Write Operation Once it enters display RAM data write mode, it can not be written any command. To write a command byte, it is necessary to generate a START condition again. 0 1 R/ W The MSB of the command byte is defined as “C” bit, the C bit is the command/data selection bit. When the C bit is set to “1”, the next byte is a command byte. When the C bit is set to “0”, the next byte is display RAM data. The data transfer format is shown in the accompanying diagram. S 0 C Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 P Bit0 ACK ACK 2 I C Command Type Write Operation Slave Address S 0 1 1 1 1 RAM Data byte RAM Address byte 1 0 0 R/ W C Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 C bit ="0", the next byte is display RAM data ACK ACK P Bit0 ACK I2C Display RAM Data Write Operation Slave Address S 0 1 1 1 1 Command byte 1 0 0 1 Bit6 C bit R/ W ACK Bit5 Bit4 Bit3 Bit2 Command byte Bit1 Bit0 1 Bit6 C bit 1st Command Bit5 Bit4 Bit3 Bit2 Command byte Bit1 Bit0 1 Bit6 C bit 2nd Command ACK Bit5 Bit4 Bit3 Bit2 Bit1 nth Command P Bit0 ACK ACK 2 I C Compound Command Type Write Operation Slave Address S 0 1 1 1 1 RAM Address byte 1 0 0 R/ W 0 ACK 0 A5 A4 A3 C bit A2 RAM Data byte A1 D7 A0 D6 ACK D5 D4 D3 D2 D1 P D0 ACK I2C Display RAM Single Data Byte Write Operation Rev. 1.00 15 May 28, 2015 HT9B95 • Display RAM Page Write Operation After a START condition the slave address with a R/W bit is placed on the bus followed with the specified display RAM Register Address of which the contents are written into the internal address pointer. The data to be written into the memory will be transmitted next. The internal address pointer will be incremented by 1 after a 8-bit data is shifted in. Then the acknowledge clock pulse will be received after an 8-bit data is shifted. After the internal address point reaches the maximum available address, 22H, 15H or 26H, the address pointer will be reset to 00H. It is strongly recommended to write the display RAM data from address 00H to maximum available address using the Display RAM Page Write Operation. Part No. Read Operation • Display RAM Read Operation The master reads the display RAM data after setting the slave address. Following the R/W bit (=”0”) is an acknowledge bit and the register address byte which is written to the internal address pointer. After the start address of the read operation has been configured, another START condition and the slave address transferred on the bus followed by the R/W bit (=”1”). Then the MSB of the data which was addressed is transmitted first on the I2C bus. The address pointer is only incremented by 1 after the reception of an acknowledge clock. After reaching the maximum available address, the address pointer will be reset to 00H. The C bit in the register address byte can be set to “1” or “0”. This read operation will continue until the master sends a STOP condition. The maximum available address is summarized in the above section. Duty Maximum Available Address HT9B95A 1/8 22H HT9B95B HT9B95G 1/4 15H 1/8 26H Display RAM Maximum Available Address RAM Address byte Slave Address S 0 1 1 1 1 1 0 0 0 0 A5 A4 C bit R/ W D7 D6 D5 D4 n th A2 A1 A0 Address n ACK Data byte A3 ACK Data byte D3 D2 D1 D0 D7 D6 D5 data D4 ( n+1) Data byte D3 th D2 D1 D0 D7 D6 D5 data D4 N ACK ACK th D3 D2 D1 P D0 data ACK ACK I2C Interface N Bytes Display RAM Data Write Operation Slave Address S 0 1 1 1 1 RAM Address byte 1 0 R/ W 0 Write 0 1 1 1 1 ACK 0 A5 A4 A3 A2 A1 1 0 R/ W 1 Read D7 ACK D6 D5 D4 D3 1st data P A0 C bit ACK Data byte Device Address S C Data byte D2 D1 D0 D7 ACK D6 D5 D4 D3 2nd data Data byte D2 D1 D0 D7 ACK D6 D5 D4 D3 Nth data D2 D1 D0 P NACK Display RAM Read Operation Rev. 1.00 16 May 28, 2015 HT9B95 • Command Register Read Operation The master reads the command register after setting the slave address. Following the R/W bit (=”0”) is an acknowledge bit and the register address byte which is written to the internal address pointer. After the start address of the read operation has been configured, another START condition and the slave address transferred on the bus followed by the R/W bit (=”1”). Then the MSB of the data which was addressed is transmitted first on the I2C bus. The C bit in the register address byte can be set to “1” or “0”. Slave Address 0 1 1 1 1 HT9B95A 23h 24h HT9B95B HT9B95G 27h 28h Command Register Address • Command Register 1 All command setting values are put together into two command registers with the register addresses of 23H and 24H or 27H and 28H when the Command Register Read Operation is executed. Each time the Command Register Read Operation is executed, only one command register can be read. To read all command registers, execute the Command Register Read Operation twice with the register address of 23H or 27H and 24H or 28H respectively. The two command registers contents are arranged in the following two registers and the detailed definition are described in the “Command Summary” section. S Bit 7 6 Name — DB 0 R/ W 0 Write ACK C 0 C bit A5 A4 A3 A2 A1 5 4 2 1 0 SR LV4 LV3 LV2 LV1 LV0 DB: Duty and Bias setting Bit 5 SR: Software Reset Operation Bit 4~0 LV4~LV0: LCD Voltage Adjustment setting • Command Register 2 Bit 7 6 5 4 Name FR1 FR0 PS1 PS0 3 2 W D 1 0 AP1 AP0 Bit 7~6 FR1~FR0: Frame Frequency setting Bit 5~4 PS1~PS0: Power Save Mode setting Bit 3 W: LCD Drive Waveform setting Bit 2 D: Display On/Off setting Bit 1~0 AP1~AP0: All pixels On/Off setting Device Address S P A0 3 Bit 6 Command Register Address 1 Command Command Register 1 Address Register 2 Address Part No. 0 1 1 1 1 Command Data byte 1 0 R/ W ACK 1 Read D7 ACK D6 D5 D4 D3 1st data D2 D1 D0 P NACK Command Register Read Operation Rev. 1.00 17 May 28, 2015 HT9B95 Command Summary The overall commands are summarized in this section. Note that the bit 7 denoted as “C” in the individual command here is the selection bit which is used to determine that the next byte is the display RAM data or command byte. C bit Description 0 Next byte is Display RAM data 1 Next byte is command (MSB) Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 (LSB) Bit0 Display RAM Address setting C 0 A5 A4 A3 A2 A1 A0 The display RAM address and command register setting. LCD driving Voltage Adjustment (LVA) C 1 0 LV4 LV3 LV2 LV1 LV0 Adjust the maximum voltage level of LCD driving voltage. Display control C 1 1 0 FR1 FR0 PS1 PS0 Frame frequency setting and power save mode setting Drive mode setting and software reset C 1 1 1 0 W SR D LCD drive waveform select, display ON/OFF setting and software reset All pixel control setting C 1 1 1 1 0 AP1 AP0 All pixel control setting Duty and Bias setting C 1 1 1 1 1 0 DB Duty and bias setting Command Function description Note: The “Duty and Bias setting” command is available in the HT9B95B and HT9B95G device. Display RAM Address Setting Command This command is used to define the accessed address of the display RAM or command register. Function (MSB) Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 (LSB) Bit0 Note Address Pointer C 0 A5 A4 A3 A2 A1 A0 Display RAM memory start address or Command register address. Note: • The display RAM address range is dependent upon the selected device with different duty setting. Part No. Duty Maximum Available Address HT9B95A 1/8 22H HT9B95B HT9B95G 1/4 15H 1/8 26H • The command register address is dependent upon the selected device. Part No. Command Register 1 Address Command Register 2 Address HT9B95A 23H 24H HT9B95B HT9B95G 27H 28H • Power on status: the address will be set to 00H • If the programmed command is not defined, the function will not be affected. Rev. 1.00 18 May 28, 2015 HT9B95 LCD Driving Voltage Adjustment Command – LVA This command is used to adjust the maximum voltage level of the LCD driving voltage, V0. Function (MSB) Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 (LSB) Bit0 Note LCD driving Voltage Adjustment (LVA) C 1 0 LV4 LV3 LV2 LV1 LV0 — Note: V0: The maximum voltage level of the LCD driving voltage. The relationship between V0 and LVA setting is summarized as the following table shown. LV4~LV0 Voltage ratio VLCD =5.5V VLCD =5V VLCD =3.5V VLCD =3V VLCD =2.5V 00000 VLCD V0=5.500V V0=5.000V V0=3.500V V0=3.000V V0=2.500V 00001 0.967 * VLCD V0=5.319V V0=4.835V V0=3.385V V0=2.901V V0=2.418V 00010 0.937 * VLCD V0=5.154V V0=4.685V V0=3.280V V0=2.811V V0=2.343V 00011 0.909 * VLCD V0=5.000V V0=4.545V V0=3.182V V0=2.727V V0=2.273V 00100 0.882 * VLCD V0=4.851V V0=4.410V V0=3.087V V0=2.646V V0=2.205V 00101 0.857 * VLCD V0=4.714V V0=4.285V V0=3.000V V0=2.571V V0=2.143V 00110 0.833 * VLCD V0=4.582V V0=4.165V V0=2.916V V0=2.499V V0=2.083V 00111 0.810 * VLCD V0=4.455V V0=4.050V V0=2.835V V0=2.430V V0=2.025V 01000 0.789 * VLCD V0=4.340V V0=3.945V V0=2.762V V0=2.367V V0=1.973V 01001 0.769 * VLCD V0=4.230V V0=3.845V V0=2.692V V0=2.307V V0=1.923V 01010 0.750 * VLCD V0=4.125V V0=3.750V V0=2.625V V0=2.250V V0=1.875V 01011 0.731 * VLCD V0=4.021V V0=3.655V V0=2.559V V0=2.193V V0=1.828V 01100 0.714 * VLCD V0=3.927V V0=3.570V V0=2.499V V0=2.142V V0=1.785V 01101 0.697 * VLCD V0=3.834V V0=3.485V V0=2.440V V0=2.091V V0=1.743V 01110 0.681 * VLCD V0=3.746V V0=3.405V V0=2.384V V0=2.043V V0=1.703V 01111 0.666 * VLCD V0=3.663V V0=3.330V V0=2.331V V0=1.998V V0=1.665V 10000 0.652 * VLCD V0=3.586V V0=3.260V V0=2.282V V0=1.956V V0=1.630V 10001 0.638 * VLCD V0=3.509V V0=3.190V V0=2.233V V0=1.914V V0=1.595V 10010 0.625 * VLCD V0=3.438V V0=3.125V V0=2.188V V0=1.875V V0=1.563V 10011 0.612 * VLCD V0=3.366V V0=3.060V V0=2.142V V0=1.836V V0=1.530V 10100 0.600 * VLCD V0=3.300V V0=3.000V V0=2.100V V0=1.800V V0=1.500V 10101 0.588 * VLCD V0=3.234V V0=2.940V V0=2.058V V0=1.764V V0=1.470V 10110 0.576 * VLCD V0=3.168V V0=2.880V V0=2.016V V0=1.728V V0=1.440V 10111 0.566 * VLCD V0=3.113V V0=2.830V V0=1.981V V0=1.698V V0=1.415V 11000 0.555 * VLCD V0=3.053V V0=2.775V V0=1.943V V0=1.665V V0=1.388V 11001 0.545 * VLCD V0=2.998V V0=2.725V V0=1.908V V0=1.635V V0=1.363V 11010 0.535 * VLCD V0=2.943V V0=2.675V V0=1.873V V0=1.605V V0=1.338V 11011 0.526 * VLCD V0=2.893V V0=2.630V V0=1.841V V0=1.578V V0=1.315V 11100 0.517 * VLCD V0=2.844V V0=2.585V V0=1.810V V0=1.551V V0=1.293V 11101 0.508 * VLCD V0=2.794V V0=2.540V V0=1.778V V0=1.524V V0=1.270V 11110 0.500 * VLCD V0=2.750V V0=2.500V V0=1.750V V0=1.500V V0=1.250V 11111 0.491 * VLCD V0=2.701V V0=2.455V V0=1.719V V0=1.473V V0=1.228V Prohibit setting • It is prohibited to set V0 voltage less than 2.5V and the condition “VLCD-V0>0.6V” must be met. If the voltage of (VLCD-V0) is equal to or less than 0.6V, the output voltage will be unstable. • Power on status: V0=VLCD. • If the programmed command is not defined, the function will not be affected. Rev. 1.00 19 May 28, 2015 HT9B95 Display Control Command This command is used to select the current mode according to the characteristics of the LCD panel for achieving high display quality and frame frequency. Function (MSB) Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 (LSB) Bit0 Note Display Control Setting C 1 1 0 FR1 FR0 PS1 PS0 — PS [1:0] Power Save Mode Current Consumption 00 Low Current2 Mode x 0.5 01 Low Current1 Mode x 0.67 10 Normal Current Mode x 1 (default) 11 High Current Mode x 1.8 FR [1:0] Frame Frequency @VDD=3.3V (Hz) 00 80 (default) 01 71 10 64 11 50 Note: • The setting of the frame frequency, LCD output waveform and current mode will influence the display image qualities. Please select a proper display setting suitable for the current consumption and display image quality with LCD panel. Mode Flicker Frame Frequency ○ LCD Driver Output Waveform ○ Image Quality/Contrast ○ Power Save Mode ○ • Power on status: Normal current mode and Frame frequency is set to 80Hz. • If the programmed command is not defined, the function will not be affected. Rev. 1.00 20 May 28, 2015 HT9B95 Drive Mode Setting and Software Reset Command This command is used to control the LCD display On/Off, drive waveform and software reset. Function (MSB) Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 (LSB) Bit0 Note Drive Mode setting and Software reset setting C 1 1 1 0 W SR D — W LCD drive output waveform 0 A type inversion 1 B type inversion (default) SR Software reset 0 No operation (default) 1 Software reset executed D Display On/Off 0 Display Off (default) 1 Display On Note: When the software reset is executed, the device is initialized by an internal power-on reset circuit. The status of the internal circuits after initialization is as follows: • All common and segment outputs are set to VSS. • Display RAM address pointer is set to 00H. • The maximum voltage level of the LCD driving voltage V0 is set to VLCD. • Frame Frequency is set to 80Hz. • Power save mode is set to normal current. • LCD Driver Output Waveform: B-type inversion. • LCD Display is in the off state. • LCD bias generator is off state. • All pixel control is set to normal display. If the programmed command is not defined, the function will not be affected. Rev. 1.00 21 May 28, 2015 HT9B95 All Pixels On/Off Setting Command This command controls that all pixels are switched on or off when the LCD normally displays. Function (MSB) Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 (LSB) Bit0 Note All Pixels Display setting C 1 1 1 1 0 AP1 AP0 — AP [1:0] Display output status 00 Normal Display (default) 01 All Pixels Off 10 All Pixels On 11 All Pixels Off Note: • This command is only available when the LCD normally displays. • The contents of the display RAM will not be affected in this duration. • Power on status: Normal display. • If the programmed command is not defined, the function will not be affected. Duty and Bias Setting Command This command controls the duty and bias setting and is available in the HT9B95B and HT9B95G device. Function (MSB) Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 (LSB) Bit0 Note Duty and bias setting C 1 1 1 1 1 0 DB — DB Duty and Bias setting 0 1/8 duty, 1/4 bias (default) 1 1/4 duty, 1/3 bias Note: • This command is available in the HT9B95B and HT9B95G device. • Power on status: 1/8 duty, 1/4 bias. • If the programmed command is not defined, the function will not be affected. Rev. 1.00 22 May 28, 2015 HT9B95 Operation Flow Chart Access procedures are illustrated below using flowcharts. Initialization Power On Software Reset Setting Duty and bias Setting LCD driving voltage adjustment LCD Current Mode Setting LCD Frame Frequency Setting LCD Output Waveform Setting Next processing Rev. 1.00 23 May 28, 2015 HT9B95 Display Data Write (Address Setting) Start Address setting Display data RAM write Display on Next processing Rev. 1.00 24 May 28, 2015 HT9B95 Display Quality or Operating Current (Power Save Mode) Setting Start Reduce operating current or enhance display quality. Display quality 1. Please select Frame rate from 80, 71, 64, 50Hz according to LCD panel characteristic. 2. A type inversion 3. High current mode Operating current 1. Operating current decreases in order of 80Hz à 71Hz à64Hz à 50Hz 2. B type inversion 3. Low Current 2 mode Screen Flicker? No 1. Please select Frame rate from 80, 71, 64, 50Hz according to LCD panel characteristic. 2. B type inversion 3. Low Current 2 mode YES 1. Operating current decreases in order of 80Hz à 71Hz à64Hz à 50Hz 2. B type inversion 3. Low Current 1 mode Screen Flicker? No 1. Please select Frame rate from 80, 71, 64, 50Hz according to LCD panel characteristic. 2. B type inversion 3. Low Current 1 mode YES 1. Operating current decreases in order of 80Hz à 71Hz à64Hz à 50Hz 2. B type inversion 3. Normal Current mode Screen Flicker? No 1. Please select Frame rate from 80, 71, 64, 50Hz according to LCD panel characteristic. 2. B type inversion 3. Normal Current mode YES 1. Operating current decreases in order of 80Hz à 71Hz à64Hz à 50Hz 2. B type inversion 3. High Current mode Rev. 1.00 25 May 28, 2015 HT9B95 Application Circuit HT9B95A – 1/8 Duty and 1/4 Bias VLCD VLCD VDD COM VDD 8 0.1uF 4.7kΩ 4.7kΩ HT9B95A VDD LCD panel SCL MCU SDA SEG VSS VSS 35 VSS HT9B95B/HT9B95G – 1/8 Duty and 1/4 Bias VLCD VLCD VDD COM VDD 8 0.1uF 4.7kΩ VDD MCU HT9B95B HT9B95G 4.7kΩ SCL SDA SEG VSS VSS Rev. 1.00 LCD panel 39 VSS 26 May 28, 2015 HT9B95 HT9B95B/HT9B95G – 1/4 Duty and 1/3 Bias VLCD VLCD VDD COM VDD 4 0.1uF 4.7kΩ VDD MCU 4.7kΩ HT9B95B HT9B95G SCL LCD panel SDA SEG VSS 43 VSS VSS Rev. 1.00 27 May 28, 2015 HT9B95 Package Information Note that the package information provided here is for consultation purposes only. As this information may be updated at regular intervals users are reminded to consult the Holtek website for the latest version of the package information. Additional supplementary information with regard to packaging is listed below. Click on the relevant section to be transferred to the relevant website page. • Further Package Information (include Outline Dimensions, Product Tape and Reel Specifications) • Packing Meterials Information • Carton information Rev. 1.00 28 May 28, 2015 HT9B95 48-pin TSSOP Outline Dimensions Symbol Dimensions in inch Min. Nom. Max. A — — 0.047 A1 0.002 — 0.006 A2 0.031 0.039 0.041 b 0.007 — 0.011 c 0.004 — 0.008 D 0.488 0.492 0.496 E — 0.319 BSC — E1 0.236 0.240 0.244 e — 0.020 BSC — 0.030 L 0.018 0.024 L1 — 0.039 BSC — y — 0.004 — θ 0° — 8° Symbol Rev. 1.00 Dimensions in mm Min. Nom. Max. A — — 1.20 A1 0.05 — 0.15 A2 0.80 1 1.05 b 0.17 — 0.27 c 0.09 — 0.20 D 12.40 12.50 12.60 E — 8.10 BSC — E1 6.00 6.10 6.20 e — 0.50 BSC — L 0.45 0.60 0.75 L1 — 1.0 BSC — y — 0.10 — θ 0° — 8° 29 May 28, 2015 HT9B95 52-pin LQFP (14mm×14mm) Outline Dimensions Symbol Dimensions in inch Min. Nom. Max. A 0.622 0.630 0.638 B 0.547 0.551 0.555 C 0.622 0.630 0.638 D 0.547 0.551 0.555 E — 0.039 BSC — F 0.015 — 0.019 G 0.053 0.055 0.057 H — — 0.063 I 0.002 — 0.008 J 0.018 — 0.030 K 0.005 — 0.007 α 0° — 7° Symbol Rev. 1.00 Dimensions in mm Min. Nom. Max. A 15.80 16.00 16.20 B 13.90 14.00 14.10 C 15.80 16.00 16.20 D 13.90 14.00 14.10 E — 1.00 BSC — F 0.39 — 0.48 G 1.35 1.40 1.45 H — — 1.60 I 0.05 — 0.20 J 0.45 — 0.75 K 0.13 — 0.18 α 0° — 7° 30 May 28, 2015 HT9B95 Copyright© 2015 by HOLTEK SEMICONDUCTOR INC. The information appearing in this Data Sheet is believed to be accurate at the time of publication. However, Holtek assumes no responsibility arising from the use of the specifications described. The applications mentioned herein are used solely for the purpose of illustration and Holtek makes no warranty or representation that such applications will be suitable without further modification, nor recommends the use of its products for application that may present a risk to human life due to malfunction or otherwise. Holtek's products are not authorized for use as critical components in life support devices or systems. Holtek reserves the right to alter its products without prior notification. For the most up-to-date information, please visit our web site at http://www.holtek.com.tw. Rev. 1.00 31 May 28, 2015