HT16C22/HT16C22G
RAM Mapping 44*4 LCD Controller Driver
Features
●
Operating voltage:2.4~5.5V
●
Internal 32kHz RC oscillator
●
Bias: 1/2 or 1/3; Duty: 1/4
●
Internal LCD bias generation with voltage-follower buffers
●
I2C-bus interface
●
Two Selectable LCD frame frequencies: 80Hz or 160Hz
●
44 x 4 bits RAM for display data storage
●
Max. 44 x 4 patterns, 44 segments and 4 commons
●
Versatile blinking modes
●
R/W address auto increment
●
Internal 16-step voltage adjustment to adjust LCD operating voltage
●
Low power consumption
●
Provides VLCD pin to adjust LCD operating voltage
●
Manufactured in silicon gate CMOS process
●
Package Type: 48LQFP, 52QFP, chip and COG.
Applications
●
Electronic meter
●
Water meter
●
Gas meter
●
Heat energy meter
●
Household appliance
●
Games
●
Telephone
●
Consumer electronics
General Description
The HT16C22/HT16C22G device is a memory mapping and multi-function LCD controller driver. The maximum
Display segments of the device are 176 patterns (44 segments and 4commons). The software configuration feature
of the HT16C22/HT16C22G makes it suitable for multiple LCD applications including LCD modules and display
subsystems. The HT16C22/HT16C22G device communicates with most microprocessors / microcontrollers via a
two-line bidirectional I2C-bus.
Rev. 1.20
1
May 10, 2011
HT16C22/HT16C22G
Block Diagram
VSS
Power_on reset
COM0
SDA
Internal RC
Oscillator
SCL
Timing
generator
I2C
Controller
Column
driver
output
Display RAM
44*4its
8
COM3
VDD
－
OP3
Internal
voltage
adjustment
VLCD
SEG0
＋
R
－
OP2
＋
R
LCD
Voltage
Selector
Segment
driver
output
－
OP1
＋
SEG43
R
Rev. 1.20
LCD bias generator
2
May 10, 2011
HT16C22/HT16C22G
Pin Assignment
S
S
S
S
S
S
S
S
S
S
S
S E G 3 9
E G
E G
E G
E G
E G
E G
E G
E G
E G
E G
E G
/ V
C
S
S
S
S
S
4 6
4 5
3 9
3 8
3 7
3 6
4
3 3
5
3 2
3 1
H T 1 6 C 2 2
4 8 L Q F P - A
7
3
8
3
4 0
3 4
1
2
4 1
4 2
3
6
1
4 3
3 5
2
0
4 4
2
L
0
4 7
4 8
1
A
2 8
2 9
3 0
3 1
3 2
3 3
3 4
3 5
3 6
3 7
*C
D
3 8
L C D
*C
C
V D
S D
S C
V S
O M
O M
O M
O M
E G
E G
E G
E G
3 0
2 9
9
2 8
1 0
2 7
1 1
2 6
1 2
2 5
1 3
1 4
1 6
1 5
1 8
1 7
2 0
1 9
2 1
2 2
2 3
2 4
S E G
S E G
S E G
S E G
S E G
S E G
S E G
S E G
S E G
S E G
S E G
S E G
2 7
2 6
2 5
2 4
2 3
2 2
2 1
2 0
1 9
1 8
1 7
1 6
S E G
S E G
S E G
S E G
S E G
S E G
S E G
S E G
S E G
S E G
S E G
S E G
1 5
1 4
1 3
1 2
1 1
1 0
9
8
7
6
5
4
Note: The *COM1 and *COM2 pins are not in sequential order.
S
S
S
S
S
S
S
S
S
S
S
S
S E G 4
E G
E G
E G
E G
E G
E G
E G
E G
E G
E G
E G
E G
3 /V
3 1
3 2
3 3
3 4
3 5
3 6
S
3 7
S
S
3 8
S
3 9
S
4 0
C
S
5 2 5 1 5 0 4 9 4 8 4 7 4 6 4 5 4 4 4 3 4 2 4 1 4 0
1
A
4 1
*C
D
4 2
L C D
*C
C
V D
S D
S C
V S
O M
O M
O M
O M
E G
E G
E G
E G
E G
3 9
3 8
3
3 7
L
2
3 6
5
3 5
2
6
3
8
1
1 0
3
1 2
3 4
3 3
3 2
3 1
3 0
2 9
2 8
2 7
0
4
H T 1 6 C 2 2
5 2 Q F P -A
1
7
0
9
2
1 1
4
1 3
1 4 1 5 1 6 1 7 1 8 1 9 2 0 2 1 2 2 2 3 2 4 2 5 2 6
S E G
S E G
S E G
S E G
S E G
S E G
S E G
S E G
S E G
S E G
S E G
S E G
S E G
3 0
2 9
2 8
2 7
2 6
2 5
2 4
2 3
2 2
2 1
2 0
1 9
1 8
S E
S E
S E
S E
S E
S E
S E
S E
S E
S E
S E
S E
S E
C 1
G 1
G 1
G 1
G 1
G 1
G 1
G 1
G 9
G 8
G 7
G 6
G 5
7
6
5
4
3
2
1
0
Note: The *COM1 and *COM2 pins are not in sequential order.
Rev. 1.20
3
May 10, 2011
HT16C22/HT16C22G
Pad Assignment for COB
S E G
S E G
S E G
S E G
S E G
S E G
S E G
S E G
S E G
S E G
S E G
S E G
S E G
V L
3 1
3 2
3 3
3 4
3 5
3 6
3 7
3 8
3 9
4 0
4 1
4 2
4 3
C D
1
5 6 5 5 5 4 5 3 5 2 5 1 5 0 4 9 4 8 4 7 4 6 4 5 4 4
4 3
4 2
4 1
O P T IO N 1
V D D
S D A
S C L
V S S
O P T IO
C O
*C O
*C O
C O
S E
S E
S E
S E
N 0
M 0
M 2
M 1
M 3
G 0
G 1
G 2
G 3
2
4 0
3
3 9
4
3 8
3 7
3 6
3 5
3 4
3 3
3 2
3 1
5
6
(0 , 0 )
7
8
9
2 4
1 0
1 1
1 2
1 3
1 4
1 5
N .C .
1 6 1 7 1 8 1 9 2 0 2 1 2 2
S E G 3 0
S E G 2 9
S E G 2 8
S E
S E
S E
S E
S E
S E
S E
S E
S E
S E
G 2
G 2
G 2
G 2
G 2
G 2
G 2
G 2
G 1
G 1
7
6
5
4
3
2
1
0
9
8
2 3 2 5 2 6 2 7 2 8 2 9 3 0
S E
S E
S E
S E
S E
S E
S E
S E
S E
S E
S E
S E
S E
S E
G 1
G 1
G 1
G 1
G 1
G 1
G 1
G 1
G 9
G 8
G 7
G 6
G 5
G 4
7
6
5
4
3
2
1
0
Chip size: 1673 x 1676 um2
Note: 1. The Option0 (Pad7) should be bonded to VDD or floating.
2. The Option1 (Pad2) should be bonded to VSS or floating.
3. The IC substrate should be connected to VSS in the PCB layout artwork
4. The *COM1 and *COM2 pins are not in sequential order.
Internal Voltage Adjustment
(IVA) Set Command
VLCD
(PAD1)
Segment43
(PAD56)
Note
DE bit
VE bit
0
0
Input
Null
The VLCD input voltage can be smaller than or
equal to VDD
0
1
Output
Null
The VLCD pin is an output pin of which the
voltage can be detected by the external MCU
host.
1
0
Null
Output
—
1
1
Null
Output
—
Rev. 1.20
4
May 10, 2011
HT16C22/HT16C22G
Pad Coordinates for COB
unit: μm
No
Pad Name
X
Y
No
Pad Name
X
Y
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
VLCD
Option1
VDD
SDA
SCL
VSS
Option0
COM0
*COM2
*COM1
COM3
SEG0
SEG1
SEG2
SEG3
SEG4
SEG5
SEG6
SEG7
SEG8
SEG9
SEG10
SEG11
N.C.
SEG12
SEG13
SEG14
SEG15
-695.6
-732.9
-732.9
-732.9
-732.9
-732.9
-732.9
-732.9
-732.9
-732.9
-732.9
-732.9
-732.9
-732.9
-732.9
-409.85
-324.85
-239.85
-154.85
-69.85
15.15
100.15
185.15
70.747
270.15
355.15
440.15
525.15
734.4
421.349
336.349
251.349
166.349
81.349
-3.801
-102.1
-187.1
-272.1
-357.1
-442.1
-527.1
-612.1
-697.1
-734.4
-734.4
-734.4
-734.4
-734.4
-734.4
-734.4
-734.4
-239.021
-734.4
-734.4
-734.4
-734.4
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
SEG16
SEG17
SEG18
SEG19
SEG20
SEG21
SEG22
SEG23
SEG24
SEG25
SEG26
SEG27
SEG28
SEG29
SEG30
SEG31
SEG32
SEG33
SEG34
SEG35
SEG36
SEG37
SEG38
SEG39
SEG40
SEG41
SEG42
SEG43
610.15
695.15
732.45
732.45
732.45
732.45
732.45
732.45
732.45
732.45
732.45
732.45
732.45
732.45
732.45
409.4
324.4
239.4
154.4
69.4
-15.6
-100.6
-185.6
-270.6
-355.6
-440.6
-525.6
-610.6
-734.4
-734.4
-411.35
-326.35
-241.35
-156.35
-71.35
13.65
98.65
183.65
268.65
353.65
527.1
612.1
697.1
734.4
734.4
734.4
734.4
734.4
734.4
734.4
734.4
734.4
734.4
734.4
734.4
734.4
Note: The *COM1 and *COM2 pins are not in sequential order.
Rev. 1.20
5
May 10, 2011
HT16C22/HT16C22G
Pad Assignment for COG
1 73 7271 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33
(0, 0)
2
3
4
5
6
7
32
31
30
29
28
27
8
26
9
10 11
12 13
14
15 16 17 18 19 20
21 22 23 24 25
Note:
Internal Voltage Adjustment
(IVA) Set Command
VLCD
(PAD14)
Segment43
(PAD5)
Note
DE bit
VE bit
0
0
Input
Null
The VLCD input voltage can be smaller than or
equal to VDD
0
1
Output
Null
The VLCD pin is an output pin of which the
voltage can be detected by the external MCU
host.
1
0
Null
Output
—
1
1
Null
Output
—
Pad Dimensions for COG
Item
Size
Number.
X
Y
Chip size
—
Chip thickness
—
508
μm
1~7, 27~73
60
μm
9~25
87
Pad pitch
Output pad
Bump size
Input pad
Dummy pad
Bump height
Rev. 1.20
2666
948
Unit
μm
μm
34~73
40
60
μm
2~5, 29~32
60
40
μm
10~14
67
67
μm
1, 33
40
60
μm
6~7, 27~28
60
40
μm
9, 15~25
67
67
μm
All pad
18±3
6
μm
May 10, 2011
HT16C22/HT16C22G
Alignment mark Dimensions for COG
Item
Number
Size
Unit
(-1237.5, 285)
10um
10um
ALIGN_A
20um
8
μm
10um
10um
40um
20um
(1237.5, -285)
10um
10um
ALIGN_B
μm
26
7
10um
10um
20um
Rev. 1.20
20um
20um
20um
May 10, 2011
HT16C22/HT16C22G
Pad Coordinates for COG
Unit: μm
No
Name
X
Y
No
Name
X
Y
1
DUMMY
-1230
379.5
39
SEG5
870
379.5
2
SEG40
-1238.5
86.25
40
SEG6
810
379.5
3
SEG41
-1238.5
26.25
41
SEG7
750
379.5
4
SEG42
-1238.5
-33.75
42
SEG8
690
379.5
5
SEG43
-1238.5
-93.75
43
SEG9
630
379.5
6
DUMMY
-1238.5
-153.75
44
SEG10
570
379.5
7
DUMMY
-1238.5
-213.75
45
SEG11
510
379.5
9
DUMMY
-1235
-370.4
46
SEG12
450
379.5
10
SDA
-933
-370.4
47
SEG13
390
379.5
11
SCL
-846
-370.4
48
SEG14
330
379.5
12
VDD
-575
-370.4
49
SEG15
270
379.5
13
VSS
-488
-370.4
50
SEG16
210
379.5
14
VLCD
-300
-370.4
51
SEG17
150
379.5
15
DUMMY
365
-370.4
52
SEG18
90
379.5
16
DUMMY
452
-370.4
53
SEG19
30
379.5
17
DUMMY
539
-370.4
54
SEG20
-30
379.5
18
DUMMY
626
-370.4
55
SEG21
-90
379.5
19
DUMMY
713
-370.4
56
SEG22
-150
379.5
20
DUMMY
800
-370.4
57
SEG23
-210
379.5
21
DUMMY
887
-370.4
58
SEG24
-270
379.5
22
DUMMY
974
-370.4
59
SEG25
-330
379.5
23
DUMMY
1061
-370.4
60
SEG26
-390
379.5
24
DUMMY
1148
-370.4
61
SEG27
-450
379.5
25
DUMMY
1235
-370.4
62
SEG28
-510
379.5
27
DUMMY
1238.5
-213.75
63
SEG29
-570
379.5
28
DUMMY
1238.5
-153.75
64
SEG30
-630
379.5
29
COM0
1238.5
-93.75
65
SEG31
-690
379.5
30
COM1
1238.5
-33.75
66
SEG32
-750
379.5
31
COM2
1238.5
26.25
67
SEG33
-810
379.5
32
COM3
1238.5
86.25
68
SEG34
-870
379.5
33
DUMMY
1230
379.5
69
SEG35
-930
379.5
34
SEG0
1170
379.5
70
SEG36
-990
379.5
35
SEG1
1110
379.5
71
SEG37
-1050
379.5
36
SEG2
1050
379.5
72
SEG38
-1110
379.5
37
SEG3
990
379.5
73
SEG39
-1170
379.5
38
SEG4
930
379.5
Alignment mark Coordinates for COG
No
Name
X
Y
No
Name
X
Y
8
ALIGN_A
-1237.5
-285
26
ALIGN_B
1237.5
-285
Rev. 1.20
8
May 10, 2011
HT16C22/HT16C22G
Pin Description
Pin Name
Type
SDA
I/O
SCL
I
Description
Serial Data Input/Output for I C interface
2
Serial Clock Input for I2C
VDD
―
Positive power supply.
VSS
―
Negative power supply , ground.
●
VLCD
―
●
●
One external resistor is connected between the VLCD pin and the VDD pin
to determine the bias voltage for package with a VLCD pin. Internal voltage
adjustment function is disabled.
Internal voltage adjustment function can be used to adjust the VLCD
voltage. If the VLCD pin is used as voltage detection pin, an external power
supply should not be applied to the VLCD pin.
An external MCU can detect the voltage of the VLCD pin and program the
internal voltage adjustment for packages with a VLCD pin.
COM0~COM3
O
LCD Common outputs.
SEG0~SEG43
O
LCD Segment outputs.
Approximate Internal Connections
C O M 0 ~ C O M 3 , S E G 0 ~ S E G 4 3
S C L , S D A
V D D
V s e le c t- o n
V s e le c t- o ff
G N D
Absolute Maximum Ratings
Supply Voltage
VSS−0.3V to VSS+6.5V
Input Voltage
VSS−0.3V to VDD+0.3V
Storage Temperature
−55°C to 150°C
Operating Temperature
−40°C to 85°C
Note : These are stress ratings only. Stresses exceeding the range specified under "Absolute Maximum Ratings"
may cause substantial damage to the device. Functional operation of this device at other conditions beyond
those listed in the specification is not implied and prolonged exposure to extreme conditions may affect
device reliability.
Rev. 1.20
9
May 10, 2011
HT16C22/HT16C22G
D.C. Characteristics
VSS = 0 V; VDD = 2.4 to 5.5 V; Ta =−40 to +85 °C
Symbol
Parameter
VDD
Test Conditions
Min.
Typ.
Max.
Unit
2.4
―
5.5
V
―
No load, VLCD=VDD, 1/3bias
fLCD=80Hz, LCD display on,
Internal system oscillator on,.
DA0~DA3 are set to "0000"
No load, VLCD=VDD, 1/3bias
fLCD=80Hz, LCD display off,
Internal system oscillator on,
DA0~DA3 are set to "0000"
―
―
VDD
V
―
18
27
μA
―
25
40
μA
―
2
5
μA
―
4
10
μA
―
―
―
―
1
2
μA
μA
0.7VDD
―
VDD
V
0
―
0.3VDD
V
-1
―
1
μA
VDD
Conditions
Operating Voltage
―
―
VLCD
Operating Voltage
―
IDD
Operating Current
3V
5V
3V
IDD1
Operating Current
5V
ISTB
Standby Current
3V
5V
No load, VLCD=VDD, LCD display
off, Internal system oscillator off,
VIH
Input Low Voltage
―
SDA , SCL
VIL
Input Low Voltage for
SDA and SCL pins
―
IIL
Input leakage current
―
IOL
Low level output current
IOL1
LCD Common Sink
Current
IOH1
LCD Common Source
Current
IOL2
LCD Segment Sink
Current
IOH2
LCD Segment Source
Current
3V
5V
―
VIN = VSS or VDD
VOL=0.4V on SDA pin
3
―
―
mA
6
―
―
mA
3V
VLCD=3V, VOL=0.3V
250
400
―
μA
5V
VLCD=5V, VOL=0.5V
500
800
―
μA
3V
VLCD=3V, VOH=2.7V
-140
-230
―
μA
5V
VLCD=5V, VOH=4.5V
-300
-500
―
μA
3V
VLCD=3V, VOL=0.3V
250
400
―
μA
5V
VLCD=5V, VOL=0.5V
500
800
―
μA
3V
VLCD=3V, VOH=2.7V
-140
-230
―
μA
5V
VLCD=5V, VOH=4.5V
-300
-500
―
μA
A.C. Characteristics
VSS = 0 V; VDD = 2.4 to 5.5 V; Ta =−40 to +85 °C
Symbol
Parameter
fLCD1
Test Conditions
Min.
Typ.
Max.
Unit
72
80
88
Hz
VDD
Conditions
LCD Frame Frequency
4V
1/4 duty, Ta =25 °C
fLCD2
LCD Frame Frequency
4V
1/4 duty, Ta = −40 to +85 °C
52
80
124
Hz
fLCD3
LCD Frame Frequency
4V
1/4 duty, Ta =25 °C
144
160
176
Hz
fLCD4
LCD Frame Frequency
4V
1/4 duty, Ta = −40 to +85 °C
104
160
248
Hz
tOFF
VDD OFF Times
―
VDD drop down to 0V
20
―
―
ms
tSR
VDD Slew Rate
―
―
0.05
―
―
V/ms
Note : ●
If the Power on Reset timing conditions are not satisfied during the power ON/OFF sequence, the internal
Power on Reset circuit will not operate normally.
●
If VDD drops below the minimum voltage of operating voltage spec. during operating, the Power on Reset
timing conditions must also be satisfied. That is, VDD must drop to 0V and remain at 0V for 20ms (min.)
before rising to its normal operating voltage.
Rev. 1.20
10
May 10, 2011
HT16C22/HT16C22G
A.C. Characteristics - I2C Interface
Symbol
Parameter
Clock frequency
fSCL
tBUF
tHD;STA
VDD=2.4V to 5.5V
Min.
Max.
Conditions
―
Time in which the bus must be
bus free time
free before a new transmission
can start
Start condition hold After this period, the first
time
clock pulse is generated
VDD=3.0V to 5.5V
Min.
Max.
Unit
―
100
―
400
kHZ
4.7
―
1.3
―
μs
4
―
0.6
―
μs
tLOW
SCL Low time
―
4.7
―
1.3
―
μs
tHIGH
SCL High time
―
4
―
0.6
―
μs
tSU;STA
Start condition setup Only relevant for repeated
time
START condition.
4.7
―
0.6
―
μs
tHD;DAT
Data hold time
―
0
―
0
―
ns
tSU;DAT
Data setup time
―
250
―
100
―
ns
tR
SDA and SCL rise time
Note*
―
1
―
0.3
μs
tF
SDA and SCL fall time
Note*
―
0.3
―
0.3
μs
tSU;STO
Stop condition set-up
time
―
4
―
0.6
―
μs
tAA
Output Valid from Clock
―
―
3.5
―
0.9
μs
tSP
Input Filter Time
Constant
(SDA and SCL Pins)
―
100
―
50
ns
Noise suppression time
Note : These parameters are periodically sampled but not 100% tested.
Timing Diagrams
●
I2C timing
Note : The write cycle time tWR is the time from a valid stop condition of a write sequence to the end of the valid start
condition of a sequential command.
●
Power On Reset timing
Rev. 1.20
11
May 10, 2011
HT16C22/HT16C22G
Functional Description
Power-ON Reset
When power is applied, the device is initialised by an internal power-on reset circuit. The status of the internal
circuits after initialisation is as follows:
●
All common outputs are set to VDD
●
All segment outputs are set to VDD
●
The drive mode 1/4 duty output and 1/3 bias is selected
●
The System Oscillator and the LCD bias generator is off state
●
LCD Display is off state
●
Internal voltage adjustment function is enabled
●
Detection switch for VLCD pin is disabled
●
Frame Frequency is set to 80Hz
●
Blinking function is switched off
Data transfers on the I2C-bus should be avoided for 1 ms following power-on to allow completion of the reset action.
Display Memory - RAM Structure
The display RAM is a static 44 x 4-bit RAM which stores LCD data. Logic “1” in the RAM bit-map indicates the “on”
state of the corresponding LCD segment; similarly logic 0 indicates the “off” state.
The contents of the RAM data are directly mapped to the LCD data. The first RAM column corresponds to the
44 segments operated with respect to COM0. In multiplexed LCD applications the segment data of the second,
third and fourth column of the display RAM are time-multiplexed with COM1, COM2 and COM3 respectively. The
following is a mapping from the RAM data to the LCD pattern:
Output
SEG1
SEG3
SEG5
SEG7
SEG9
SEG11
COM3
COM2
COM1
COM0
D7
D6
D5
D4
SEG43
Output
SEG0
SEG2
SEG4
SEG6
SEG8
SEG10
COM3
COM2
COM1
COM0
D3
D2
D1
D0
SEG42
address
0
1
2
3
4
5
21
Data
Display data transfer format for the I2C bus
MSB
LSB
D7 D6 D5 D4 D3 D2 D1 D0
System Oscillator
The timing for the internal logic and the LCD drive signals are generated by an internal oscillator. The System Clock
frequency (fSYS) determines the LCD frame frequency. During initial system power on the System Oscillator will be in
the stop state.
Rev. 1.20
12
May 10, 2011
HT16C22/HT16C22G
LCD Bias Generator
The full-scale LCD voltage (Vop) is obtained from VLCD – VSS. The LCD voltage may be temperature compensated
externally through the Voltage supply to the VLCD pin.
Fractional LCD biasing voltages are obtained from an internal voltage divider of three series resistors connected
between VLCD and VSS. The centre resistor can be switched out of the circuits to provide a 1/2 bias voltage level for
the 1/4 duty configuration.
LCD Drive Mode Waveforms
●
When two columns are provided in the LCD, the 1/4duty drive mode applies. The HT16C22/HT16C22G can use
1/2 or 1/3
bias types in output waveforms as shown as follows:
tLCD
LCD segment
LCD segment
VLCD
VLCD
COM0
COM0
(VLCD+VSS)/2
(VLCD+VSS)/2
State1
State1
(on)
(on)
VSS
VSS
VLCD
VLCD
COM1
COM1
State2
State2
(off)
(off)
(VLCD+VSS)/2
(VLCD+VSS)/2
VSS
VSS
VLCD
VLCD
COM2
COM2
(VLCD+VSS)/2
(VLCD+VSS)/2
VSS
VSS
VLCD
VLCD
COM3
COM3
(VLCD+VSS)/2
(VLCD+VSS)/2
VSS
VSS
VLCD
VLCD
SEG n
SEG n
(VLCD+VSS)/2
(VLCD+VSS)/2
VSS
VSS
VLCD
VLCD
SEG n+1
(VLCD+VSS)/2
SEG n+1
(VLCD+VSS)/2
VSS
VSS
VLCD
VLCD
SEG n+2
(VLCD+VSS)/2
SEG n+2
(VLCD+VSS)/2
VSS
VSS
VLCD
VLCD
SEG n+3
SEG n+3
(VLCD+VSS)/2
(VLCD+VSS)/2
VSS
VSS
Waveforms for 1/4 duty drive mode with1/2 bias (VOP=VLCD-VSS)
Rev. 1.20
13
May 10, 2011
HT16C22/HT16C22G
tLCD
LCD segment
LCD segment
VLCD
VLCD
VLCD- Vop/3
VLCD- Vop/3
COM0
COM0 VLCD- 2Vop/3
VLCD- 2Vop/3
State1
State1
(on)
(on)
VSS
VSS
VLCD
VLCD
COM1
COM1
State2
State2
(off)
(off)
VLCD- Vop/3
VLCD- Vop/3
VLCD- 2Vop/3
VLCD- 2Vop/3
VSS
VSS
VLCD
VLCD
COM2
COM2
VLCD- Vop/3
VLCD- Vop/3
VLCD- 2Vop/3
VLCD- 2Vop/3
VSS
VSS
VLCD
VLCD
COM3
COM3
VLCD- Vop/3
VLCD- Vop/3
VLCD- 2Vop/3
VLCD- 2Vop/3
VSS
VSS
VLCD
VLCD
VLCD- Vop/3
VLCD- Vop/3
SEG n
SEG n VLCD- 2Vop/3
VLCD- 2Vop/3
VSS
VSS
VLCD
VLCD
VLCD- Vop/3
VLCD- Vop/3
SEG n+1
SEG n+1 VLCD- 2Vop/3
VLCD- 2Vop/3
VSS
VSS
VLCD
VLCD
VLCD- Vop/3
VLCD- Vop/3
SEG n+2
SEG n+2 VLCD- 2Vop/3
VLCD- 2Vop/3
VSS
VSS
VLCD
VLCD
V - Vop/3
VLCD- Vop/3
SEG n+3
SEG n+3VLCD- 2Vop/3
VLCD- 2Vop/3
LCD
VSS
VSS
Waveforms for 1/4 duty drive mode with1/3 bias (VOP=VLCD-VSS)
Rev. 1.20
14
May 10, 2011
HT16C22/HT16C22G
Segment Driver Outputs
The LCD drive section includes 44 segment outputs SEG0 to SEG43 which should be connected directly to the
LCD panel. The segment output signals are generated in accordance with the multiplexed column signals and with
the data resident in the display latch. When less than 44 segment outputs are required the unused segment outputs
should be left open-circuit.
Column Driver Outputs
The LCD drive section includes four column outputs COM0 to COM3 which should be connected directly to the LCD
panel. The column output signals are generated in accordance with the selected LCD drive mode. When less than 4
column outputs are required the unused column outputs should be left open-circuit.
Address Pointer
The addressing mechanism for the display RAM is implemented using the address pointer. This allows the loading
of an individual display data byte, or a series of display data bytes, into any location of the display RAM. The
sequence commences with the initialisation of the address pointer by the Address pointer command.
Blinker Function
The device contains versatile blinking capabilities. The whole display can be blinked at frequency selected by the
Blink command. The blinking frequency is a subdivided ratio of the system frequency. The ratio between the system
oscillator and blinking frequency depends on the blinking mode in which the device is operating in, as shown in the
table:
Blinking Mode
0
1
2
3
Operating mode ratio
0
fSYS / 16384HZ
fSYS / 32768HZ
fSYS / 65536HZ
Blinking frequency (HZ)
Blink off
2
1
0.5
Frame Frequency
The HT16C22/HT16C22G provides two frame frequencies selected with the Mode set command; 80Hz and 160Hz.
VLCD Voltage Adjustment
●
The internal VLCD adjustment contains four resistors in series and a 4- bit programmable analog switch which
●
The VLCD adjustment structure is show in the diagram:
can provide sixteen voltage adjustment options using the VLCD voltage adjustment command.
VLCD pin
LCD Bias
generator
16R/15
Internal voltage adjustment
8R/15
4R/15
2R/15
VDD
R
DA3
DA2
DA1
DA0
R
R
Rev. 1.20
15
May 10, 2011
HT16C22/HT16C22G
●
The relationship between the programmable 4-bit analog switch and the VLCD output voltage is shown in the
table:
Bias
DA3~DA0
00H
01H
02H
03H
04H
05H
06H
07H
08H
09H
0AH
0BH
0CH
0DH
0EH
0FH
1/2
1/3
Note
1.000*VDD
0.9375*VDD
0.882*VDD
0.833*VDD
0.789*VDD
0.750*VDD
0.714*VDD
0.682*VDD
0.652*VDD
0.625*VDD
0.600*VDD
0.577*VDD
0.556*VDD
0.536*VDD
0.517*VDD
0.500*VDD
1.000*VDD
0.957*VDD
0.918*VDD
0.882*VDD
0.849*VDD
0.818*VDD
0.789*VDD
0.763*VDD
0.738*VDD
0.714*VDD
0.692*VDD
0.672*VDD
0.652*VDD
0.634*VDD
0.616*VDD
0.600*VDD
Default value
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
I2C Serial Interface
The device includes an I2C serial interface. The I2C bus is for bidirectional, two-line communication between different
ICs or modules. The two lines are a serial data line, SDA, and a serial clock line, SCL. Both lines are connected
to the positive supply via pull-up resistors with a typical value of 4.7KΩ. When the bus is free, both lines are high.
Devices connected to the bus must have open-drain or open-collector outputs to implement a wired-or function.
Data transfer is initiated only when the bus is not busy.
Data validity
The data on the SDA line must be stable during the high period of the serial clock. The high or low state of the data
line can only change when the clock signal on the SCL line is Low as shown in the diagram.
SDA
SCL
Data line stable,
Data valid
Chang of data
allowed
START and STOP conditions
●
A high to low transition on the SDA line while SCL is high defines a START condition
●
A low to high transition on the SDA line while SCL is high defines a STOP condition
●
START and STOP conditions are always generated by the master. The bus is considered to be busy after the
●
The bus stays busy if a repeated START (Sr) is generated instead of a STOP condition. In some respects, the
START condition. The bus is considered to be free again a certain time after the STOP condition.
START(S) and repeated START (Sr) conditions are functionally identical.
SDA
SDA
SCL
SCL
S
P
START condition
Rev. 1.20
STOP condition
16
May 10, 2011
HT16C22/HT16C22G
Byte format
Every byte placed on the SDA line must be 8-bits in length. The number of bytes that can be transmitted per transfer
is unrestricted. Each byte has to be followed by an acknowledge bit. Data is transferred with the most significant bit,
MSB, first.
P
SDA
Sr
SCL
S
or
Sr
1
2
7
8
9
1
2
3-8
ACK
9
ACK
P
or
Sr
Acknowledge
●
Each byte of eight bits is followed by one acknowledge bit. The acknowledge bit is a low level placed on the bus
by the receiver. The master generates an extra acknowledge related clock pulse.
●
A slave receiver which is addressed must generate an acknowledge bit, ACK, after the reception of each byte.
●
The device that acknowledges must pull down the SDA line during the acknowledge clock pulse so that it
●
A master receiver must signal an end of data to the slave by generating a not-acknowledge, NACK, bit on the
remains stable low during the high period of this clock pulse
last byte that has been clocked out of the slave. In this case, the master receiver must leave the data line high
during the 9th pulse to not acknowledge. The master will generate a STOP or repeated START condition.
DATA OUTPUT
BY TRANSMITER
not acknowledge
DATA OUTPUT
BY RECEIVER
acknowledge
SCL FROM
MASTER
1
2
7
8
9
S
START
condition
clk pulse for
acknowledgement
Slave Addressing
●
The slave address byte is the first byte received following the START condition form the master device. The
first seven bits of the first byte make up the slave address. The eighth bit defines a read or write operation to be
performed. When the R/W bit is “1”, a read operation is selected. A “0” selects a write operation.
●
The HT16C22/HT16C22G address bits are “0111111”. When an address byte is sent, the device compares the
first seven bits after the START condition. If they match, the device outputs an acknowledge on the SDA line.
MSB
LSB
0 1 1 1 1 1 1 1 R/W
Rev. 1.20
17
May 10, 2011
HT16C22/HT16C22G
Byte Write Operation
Byte Write Operation
A byte write operation requires a START condition, a slave address with an R/W bit, a valid Register Address, Data
and a STOP condition. After each of the three bytes, the device responds with an ACK.
Slave Address
S
0
1
1
1
1
Command byte
1
1
0
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
P
Bit0
Write ACK
ACK
Command Byte Received
Slave Address
S
0
1
1
1
1
Command / register Address byte
1
1
0
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2 Bit1
Data byte
Bit0
Write ACK
D7
D6
D5
D4
D3
D2
D1
P
D0
ACK
ACK
Single Data Byte Received
Note : If the byte following the slave address is a command code, the byte following the command code will be
ignored.
Page write operation
After a START condition the slave address with the R/W bit is placed on the bus followed with the Register Address
of which the contents are written to the internal address pointer. The data to be written to the memory will be
transmitted next and then the internal address pointer will be incremented by 1 to indicate the next memory address
location after the reception of an acknowledge clock. After the internal address point reaches the maximum memory
address, which is 15H, the address pointer will be reset to 00H.
N Data Bytes Received
Read Operation
● In this mode, the master reads the HT16C22/HT16C22G data after setting the slave address. Following the
R/W bit (=’0”) is an acknowledge bit and the Register Address (An) which is written to the internal address
pointer. After the start address of the Read Operation has been configured, another START condition and the
slave address are transferred on the bus followed by the R/W bit (=’1”). Then the MSB of the data which was
addressed is transmitted first on the I2C bus. The address pointer is only incremented by 1 after the reception
of an acknowledge clock. That means that if the device is configured to transmit the data at the address of
An+1, the master will read and acknowledge the transferred new data byte and the internal address pointer is
incremented to An+2. After the internal address pointer reaches the maximum memory address which is 15h,
the pointer will be reset to 00h.
●
This cycle of reading consecutive addresses will continue until the master sends a STOP condition.
Rev. 1.20
18
May 10, 2011
HT16C22/HT16C22G
Slave Address
S
0
1
1
1
1
Device Address
Command / register Address byte
1
1
0
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
S
P
Bit0
0
1
1
1
1
1
1
Read
Write
ACK
D6
D5
D4
D3
ACK
ACK
Data byte
Data byte
D7
D2
D1
1
D7
D0
D6
D5
D4
D3
Data byte
D2
D1
D0
D7
2nd data
1st data
D6
D5
D4
D3
nth data
ACK
ACK
D2
D1
D0
P
NACK
ACK
Reading N Data Bytes
Rev. 1.20
19
May 10, 2011
HT16C22/HT16C22G
Command Summary
●
LCD driver Mode set:
These commands set the frame frequency output and internal system oscillator on/off and display on/off and driver
mode set.
MSB
Function
Mode set
LSB
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
1
0
0
F
S
E
0
M0
Note
Def
80H
Note:
1. When “M0” is set to “0”:
The driver mode is set to 1/3bias.
2. When “M0” is set to “1”:
The driver mode is set to 1/2bias.
3. When “S” and “E” bits are set to {0, X}:
Display off and disable Internal System oscillator.
4. When “S” and “E” bits are set to {1, 0}:
Display off and enable Internal System oscillator.
5. When “S” and “E” bits are set to {1, 1}:
Display on and enable Internal System oscillator.
6. When “F” bits is set to “0”:
Frame Frequency=80Hz
7. When “F” bits is set to “1”:
Frame Frequency=160Hz
8. Power on status:
The drive mode 1/3 bias is selected
Display off and disable Internal System oscillator
Frame frequency is set to 80Hz
9. If programmed command data is not defined, the function will not be affected.
●
Display Data Input Setting:
This command sends data from MCU to memory MAP of HT16C22/HT16C22G.
MSB
Function
Address pointer
Bit7
0
LSB
Bit6
0
Bit5
0
Bit4
A4
Bit3
A3
Bit2
A2
Bit1
A1
Bit0
Note
Def
A0
Display data start
address of memory map
00H
Note:
1. Power on status: the address is set to 00H.
2. After reaching the memory location 15h, the pointer will reset to 00h.
3. If programmed command data is not defined, the function will not be affected.
Rev. 1.20
20
May 10, 2011
HT16C22/HT16C22G
●
Blinking setting command:
These commands set the blinking frequency of display modes.
MSB
LSB
Function
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
Blinking Frequency
1
1
0
0
0
0
BK1
BK0
Note
Def
C0H
Note:
1. When “BK1” and “BK0” bits are set to {0, 0}:
Blinking off
2. When “BK1” and “BK0” bits are set to {0, 1}:
Blinking Frequency= 2Hz
3. When “BK1” and “BK0” bits are set to {1, 0}:
Blinking Frequency= 1Hz
4. When “BK1” and “BK0” bits are set to {1, 1}:
Blinking Frequency= 0.5Hz
5. Power on status: Blinking is switched off.
6. If programmed command data is not defined, the function will not be affected.
Rev. 1.20
21
May 10, 2011
HT16C22/HT16C22G
●
Internal Voltage Adjustment (IVA) Setting command:
The internal voltage (VLCD) adjustment can provide sixteen kinds of regulator voltage adjustment options by setting
LCD operating voltage adjustment command code.
MSB
Function
Internal Voltage Adjust
control
Bit7
0
LSB
Bit6
1
Bit5
DE
Bit4
VE
Bit3
DA3
Bit2
DA2
Bit1
Bit0
Note
Def
DA1
The Segment/ VLCD
shared pin can be
programmed via the
“DE” bit
The “VE” bit is used
to enable or disable
DA0
the internal voltage
adjustment for bias
voltage.
DA3~DA0 can be used
to adjust the VLCD output
voltage.
70H
Note:
1. When “DE” and “VE” bits are set to {0, 0}:
The Segment/ VLCD shared pin is set as VLCD pin.
Disable internal voltage adjustment.
One external resister must be connected between VLCD pin and VDD pin to determine the bias voltage, and
internal voltage follower (OP3) must be enabled by setting DA3~DA0 as the value other than “0000”.
If VLCD pin is connected to VDD pin, the internal voltage follower (OP3) must be disabled by setting DA3~DA0 as
“0000”.
2. When “DE” and “VE” bits are set to {0,1}:
The Segment/ VLCD shared pin is set as VLCD pin.
Enable internal voltage adjustment.
The external MCU can detect the voltage of VLCD pin.
3. When “DE” and “VE” bits are set to {1,0}:
The Segment/ VLCD shared pin is set as Segment pin.
Disable internal voltage adjustment.
The bias voltage is supplied by internal VDD power.
The internal voltage-follower (OP3) is disabled automatically when DE & VE is set as “10”. DA3~DA0 don’t care.
4. When “DE” and “VE” bits are set to {1,1}:
The Segment/ VLCD shared pin is set as Segment pin.
Enable internal voltage adjustment.
5. When DA0~DA3 bits are set to “0000”, internal voltage-follower (OP3) is disabled. When DA0~DA3 bits are set
to other values, internal voltage follower (OP3) is enabled.
6. Power output status: Enable internal voltage adjustment and Segment/VLCD pin is set as the Segment pin.
7. If programmed command data is not defined, the function will not be affected.
Rev. 1.20
22
May 10, 2011
HT16C22/HT16C22G
HT16C22/HT16C22G Operation Flow Chart
Access procedures are illustrated below by means of flowcharts.
●
Initialization
Power On
Internal LCD bias setting
Internal LCD frame frequency setting
Segment / VLCD shared pin setting
LCD blinking frequency setting
Next processing
Rev. 1.20
23
May 10, 2011
HT16C22/HT16C22G
●
Display data read/write(address setting)
Start
Address setting
Display data RAM write
Display on and enable internal system clock
Next processing
Rev. 1.20
24
May 10, 2011
HT16C22/HT16C22G
●
Segment / VLCD share pin setting and internal voltage adjustment setting.
Start
Set as Segment pin.
Internal voltage
adjustment
enable ?
yes
Segment / VLCD share
pin setting
The bias voltage is supplied by
Programmable Internal voltage
adjustment
no
The bias voltage is supplied by
internal VDD power.
Rev. 1.20
Set as VLCD pin.
The external MCU
can detect the
voltage of VLCD pin.
yes
Internal voltage
adjustment
enable ?
no
One external resistor must be connected
between to VLCD pin and VDD pin to
determine the bias voltage
Next processing
25
May 10, 2011
HT16C22/HT16C22G
Application Circuit
●
Set as Segment pin
1. Disable internal voltage adjustment
2. The bias voltage is supplied by internal VDD power.
VDD
0.1uF
VDD
4.7KΩ
VDD
4.7KΩ
COM0~COM3
COM0~COM3
SCL
HT16C22
MCU
LCD panel
SDA
SEG0~SEGX
SEG0~SEGX
COM0~COM3
COM0~COM3
VSS
VSS
VSS
3. Enable internal voltage
4. The internal voltage adjustment for bias voltage
VDD
0.1uF
VDD
4.7KΩ
VDD
4.7KΩ
SCL
HT16C22
MCU
LCD panel
SDA
SEG0~SEGX
VSS
SEG0~SEGX
VSS
VSS
Rev. 1.20
26
May 10, 2011
HT16C22/HT16C22G
●
Set as VLCD pin
1. Disable internal voltage adjustment
2. One external resister must be connected between VLCD pin and VDD pin to determine the bias voltage
VDD
VR
0.1uF
VDD
4.7KΩ
VLCD
VDD
4.7KΩ
COM0~COM3
COM0~COM3
SCL
HT16C22
MCU
LCD panel
SDA
VSS
SEG0~SEGX
SEG0~SEGX
COM0~COM3
COM0~COM3
VSS
VSS
3. Enable internal voltage adjustment
4. The external MCU can detect the voltage of VLCD pin.
VDD
0.1uF
VDD
4.7KΩ
VDD
4.7KΩ
SCL
HT16C22
MCU
LCD panel
SDA
VLCD
SEG0~SEGX
SEG0~SEGX
VSS
VSS
VSS
Rev. 1.20
27
May 10, 2011
HT16C22/HT16C22G
Package Information
48-pin LQFP (7mmx7mm) Outline Dimensions
C
H
D
3 6
G
2 5
I
3 7
2 4
F
A
B
E
4 8
1 3
K
=
J
1
Symbol
A
Dimensions in inch
Min.
Nom.
Max.
0.350
―
0.358
B
0.272
―
0.280
C
0.350
―
0.358
D
0.272
―
0.280
E
―
0.020
―
F
―
0.008
―
G
0.053
―
0.057
H
―
―
0.063
I
―
0.004
―
J
0.018
―
0.030
K
0.004
―
0.008
α
0°
―
7°
Symbol
Rev. 1.20
1 2
Dimensions in mm
Min.
Nom.
Max.
A
8.90
―
9.10
B
6.90
―
7.10
C
8.90
―
9.10
D
6.90
―
7.10
E
―
0.50
―
F
―
0.20
―
G
1.35
―
1.45
H
―
―
1.60
I
―
0.10
―
J
0.45
―
0.75
K
0.10
―
0.20
α
0°
―
7°
28
May 10, 2011
HT16C22/HT16C22G
52-pin QFP (14mmx14mm) Outline Dimensions
C
H
D
3 9
G
2 7
I
2 6
4 0
F
A
B
E
1 4
5 2
K
J
1
Symbol
Dimensions in inch
Min.
Nom.
Max.
A
0.681
―
0.689
B
0.547
―
0.555
C
0.681
―
0.689
D
0.547
―
0.555
―
E
―
0.039
F
―
0.016
―
G
0.098
―
0.122
H
―
―
0.134
I
―
0.004
―
J
0.029
―
0.041
K
0.004
―
0.008
α
0°
―
7°
Symbol
Rev. 1.20
1 3
Dimensions in mm
Min.
Nom.
Max.
A
17.30
―
17.50
B
13.90
―
14.10
C
17.30
―
17.50
D
13.90
―
14.10
E
―
1.00
―
F
―
0.40
―
G
2.50
―
3.10
H
―
―
3.40
I
―
0.10
―
J
0.73
―
1.03
K
0.10
―
0.20
α
0°
―
7°
29
May 10, 2011
HT16C22/HT16C22G
Holtek Semiconductor Inc. (Headquarters)
No.3, Creation Rd. II, Science Park, Hsinchu, Taiwan
Tel: 886-3-563-1999
Fax: 886-3-563-1189
http://www.holtek.com.tw
Holtek Semiconductor Inc. (Taipei Sales Office)
4F-2, No. 3-2, YuanQu St., Nankang Software Park, Taipei 115, Taiwan
Tel: 886-2-2655-7070
Fax: 886-2-2655-7373
Fax: 886-2-2655-7383 (International sales hotline)
Holtek Semiconductor Inc. (Shenzhen Sales Office)
5F, Unit A, Productivity Building, No.5 Gaoxin M 2nd Road, Nanshan District, Shenzhen, China 518057
Tel: 86-755-8616-9908, 86-755-8616-9308
Fax: 86-755-8616-9722
Holtek Semiconductor (USA), Inc. (North America Sales Office)
46729 Fremont Blvd., Fremont, CA 94538, USA
Tel: 1-510-252-9880
Fax: 1-510-252-9885
http://www.holtek.com
Copyright© 2011 by HOLTEK SEMICONDUCTOR INC.
The information appearing in this Data Sheet is believed to be accurate at the time of publication. However,
Holtek assumes no responsibility arising from the use of the specifications described. The applications
mentioned herein are used solely for the purpose of illustration and Holtek makes no warranty or
representation that such applications will be suitable without further modification, nor recommends the use
of its products for application that may present a risk to human life due to malfunction or otherwise. Holtek's
products are not authorized for use as critical components in life support devices or systems. Holtek reserves
the right to alter its products without prior notification. For the most up-to-date information, please visit our
web site at http://www.holtek.com.tw.
Rev. 1.20
30
May 10, 2011