RENESAS RD74LVC74B

RD74LVC74B
Dual D-type Flip Flops with Preset and Clear
REJ03D0324–0100Z
Rev.1.00
Jun. 22, 2004
Description
The RD74LVC74B has independent data, preset, clear, and clock inputs Q and Q outputs in a 14 pin package. The
logic level present at the data input is transferred to the output during the positive going transition of the clock pulse.
Preset and clear are independent of the clock and accomplished by a low level at the appropriate input. Low voltage
and high-speed operation is suitable at the battery drive product (note type personal computer) and low power
consumption extends the life of a battery for long time operation.
Features
•
•
•
•
•
VCC = 1.65 V to 5.5 V
All inputs VIH (Max.) = 5.5 V (@VCC = 0 V to 5.5 V)
Typical VOL ground bounce < 0.8 V (@VCC = 3.3 V, Ta = 25°C)
Typical VOH undershoot > 2.0 V (@VCC = 3.3 V, Ta = 25°C)
High output current ±4 mA (@VCC = 1.65 V)
±8 mA (@VCC = 2.3 V)
±12 mA (@VCC = 2.7 V)
±24 mA (@VCC = 3.0 V to 5.5 V)
• Ordering Information
Part Name
Package Type
Package Code
Package
Abbreviation
Taping Abbreviation
(Quantity)
RD74LVC74BFPEL
SOP–14 pin (JEITA)
FP–14DAV
FP
EL (2,000 pcs / reel)
RD74LVC74BTELL
TSSOP–14 pin
TTP–14DV
T
ELL (2,000 pcs / reel)
Function Table
Inputs
PR
L
H
L
H
H
H
H
H
H:
L:
X:
↓:
↑:
Q0 :
Note:
CLR
H
L
L
H
H
H
H
H
Outputs
CK
X
X
X
↑
↑
L
H
↓
D
X
X
X
H
L
X
X
X
Q
Q
H
L
H*1
H
L
Q0
Q0
Q0
L
H
H*1
L
H
Q0
Q0
Q0
High level
Low level
Immaterial
High to Low transition
Low to high transition
Level to Q before the indicated steady input conditions were established.
1. Q and Q will remain high as long as preset and clear are low, but Q and Q are unpredictable, if preset and
clear go high simultaneously.
Rev.1.00 Jun. 22, 2004 page 1 of 8
RD74LVC74B
Pin Arrangement
14 VCC
1CLR 1
CK
1D 2
D
13 2CLR
PR CLR
1CK 3
Q
Q
1PR 4
12 2D
11 2CK
D
1Q 5
CK
CLR PR
1Q 6
Q
Q
GND 7
10 2PR
9 2Q
8 2Q
(Top view)
Absolute Maximum Ratings
Item
Symbol
Ratings
Unit
Supply voltage
VCC
–0.5 to 7.0
V
Input diode current
IIK
–50
mA
Input voltage
VI
–0.5 to 7.0
V
Output diode current
IOK
–50
mA
Output voltage
VO
–0.5 to VCC +0.5
V
Output current
IO
±50
mA
50
Conditions
VI = –0.5 V
VO = –0.5 V
VO = VCC +0.5 V
VCC, GND current / pin
ICC or IGND
100
mA
Storage temperature
Tstg
–65 to +150
°C
Note: The absolute maximum ratings are values, which must not individually be exceeded, and furthermore, no two of
which may be realized at the same time.
Rev.1.00 Jun. 22, 2004 page 2 of 8
RD74LVC74B
Recommended Operating Conditions
Item
Symbol
Ratings
1.5 to 5.5
Unit
Supply voltage
VCC
Input / output voltage
VI
0 to 5.5
VO
0 to VCC
Operating temperature
Ta
–40 to 85
°C
Output current
IOH
–4
mA
V
1.65 to 5.5
IOL
tr, tf
PR, CLR, CK, D
Q, Q
VCC = 1.65 V
–8
VCC = 2.3 V
–12
VCC = 2.7 V
–24
VCC = 3.0 V to 5.5 V
4
mA
VCC = 1.65 V
8
VCC = 2.3 V
12
VCC = 2.7 V
20
VCC = 3.0 V to 5.5 V
ns/V
10
Notes: 1. This item guarantees maximum limit when one input switches.
Waveform: Refer to test circuit of switching characteristics.
Rev.1.00 Jun. 22, 2004 page 3 of 8
Data retention
At operation
V
24
Input rise / fall time *1
Conditions
VCC = 1.65 V to 2.7 V
VCC = 3.0 V to 5.5 V
RD74LVC74B
Electrical Characteristics
Ta = –40 to 85°C
Item
Input voltage
Symbol
VIH
VIL
Output voltage
VOH
VOL
Input current
IIN
Quiescent supply current ICC
∆ICC
Rev.1.00 Jun. 22, 2004 page 4 of 8
VCC (V)
Min
Unit
Max
1.65 to 1.95
VCC×0.65 —
2.3 to 2.7
1.7
—
2.7 to 3.6
2.0
—
4.5 to 5.5
VCC×0.7
—
1.65 to 1.95
—
VCC×0.35 V
2.3 to 2.7
—
0.7
2.7 to 3.6
—
0.8
4.5 to 5.5
—
VCC×0.3
Test Conditions
V
V
1.65 to 5.5
VCC –0.2
—
1.65
1.2
—
IOH = –4 mA
IOH = –100 µA
2.3
1.7
—
IOH = –8 mA
2.7
2.2
—
IOH = –12 mA
3.0
2.4
—
3.0
2.2
—
4.5
3.8
—
1.65 to 5.5
—
0.2
1.65
—
0.45
IOL = 4 mA
2.3
—
0.7
IOL = 8 mA
2.7
—
0.4
IOL = 12 mA
3.0
—
0.55
IOL = 24 mA
4.5
—
0.55
0 to 5.5
—
±5.0
µA
VIN = 5.5 V or GND
2.7 to 3.6
—
±5.0
µA
VIN = 3.6 V to 5.5 V
2.7 to 5.5
—
5.0
2.7 to 3.6
—
500
IOH = –24 mA
V
IOL = 100 µA
VIN = VCC or GND
µA
VIN = one input at (VCC –0.6)V,
other inputs at VCC or GND
RD74LVC74B
Switching Characteristics
Item
Maximum clock frequency
Propagation delay time
Symbol
fmax
tPLH
tPHL
tPLH
tPHL
tPLH
tPHL
Setup time
tsu
tsu
Hold time
th
Pulse width
tw
Output skew between
pins*1
tOSLH
tOSHL
Input capacitance
CIN
Note:
VCC (V)
1.8±0.15
2.5±0.2
2.7
3.3±0.3
5.0±0.5
1.8±0.15
2.5±0.2
2.7
3.3±0.3
5.0±0.5
1.8±0.15
2.5±0.2
2.7
3.3±0.3
5.0±0.5
1.8±0.15
2.5±0.2
2.7
3.3±0.3
5.0±0.5
1.8±0.15
2.5±0.2
2.7
3.3±0.3
5.0±0.5
1.8±0.15
2.5±0.2
2.7
3.3±0.3
5.0±0.5
1.8±0.15
2.5±0.2
2.7
3.3±0.3
5.0±0.5
1.8±0.15
2.5±0.2
2.7
3.3±0.3
5.0±0.5
1.8±0.15
2.5±0.2
2.7
3.3±0.3
5.0±0.5
3.3
Ta = –40 to 85°C
Min
Typ
Max
—
—
83
—
—
83
—
—
150
—
—
150
—
—
150
1.0
—
13.4
1.0
—
7.1
1.0
—
6.0
1.0
—
5.2
1.0
—
4.1
1.0
—
14.4
1.0
—
7.7
1.0
—
6.0
1.0
—
5.2
1.0
—
4.4
1.0
—
12.9
1.0
—
7.0
1.0
—
6.0
1.0
—
5.4
1.0
—
4.1
3.6
—
—
2.3
—
—
3.4
—
—
3.0
—
—
3.0
—
—
2.7
—
—
1.9
—
—
2.2
—
—
2.0
—
—
2.0
—
—
1.0
—
—
1.0
—
—
1.0
—
—
0.0
—
—
0.0
—
—
4.1
—
—
3.3
—
—
3.3
—
—
3.3
—
—
3.3
—
—
—
—
—
—
—
—
—
—
—
—
—
1.0
—
—
1.0
—
4.0
—
1. This parameter is characterized but not tested.
tOSLH = |tPLHm – tPLHn|, tOSHL = |tPHLm – tPHLn|
Rev.1.00 Jun. 22, 2004 page 5 of 8
Unit
MHz
From (Input) To (Output)
ns
CK
Q
ns
CK
Q
ns
PR or CLR
Q, Q
ns
Data
ns
PR or CLR
ns
ns
ns
pF
CK, PR, CLR
RD74LVC74B
Operating Characteristics
Ta = 25°C
Item
Symbol
Power dissipation capacitance
CPD
VCC = (V)
Min
Typ
Max
1.8
—
34
—
2.5
—
34
—
3.3
—
36
—
5.0
—
40
—
Unit
pF
Test Conditions
f = 10 MHz
Test Circuit
VCC
Pulse Generator
Zout = 50 Ω
Input
Pulse Generator
Zout = 50 Ω
Notes:
See Function Table
Input
PR
D
CL
CK
CLR
1. CL includes probe and jig capacitance.
2. Test is put into the each flip flops.
Rev.1.00 Jun. 22, 2004 page 6 of 8
Output Q
Q
RL
Output Q
Q
CL
RL
RD74LVC74B
Waveforms
tr
tf
Input CLR
90 %
Vref
10 %
VIH
90 %
Vref
10 %
GND
tw
tf
tr
VIH
90 %
90 %
Vref
10 % 10 %
Vref
Input PR
t su
Input CK
t w (H)
tf
tr
90 %
Vref
10 %
90 %
Vref
10 %
t s (H)
Input D
90 %
Vref
10 %
tr
t w (L)
tw
GND
t SU
VIH
Vref
Vref
Vref
Vref
GND
t h (H)
t s (L)
t h (L)
VIH
90 %
Vref
10 %
Vref
Vref
GND
tf
t PHL
t PLH
Vref
Vref
t PHL
t PLH
VOH
Output Q
Vref
Vref
VOL
t PLH
t PHL
t PLH
t PHL
VOH
Output Q
Vref
Vref
Vref
Vref
VOL
INPUTS
Vcc (V)
VIH
Vcc = 1.8±0.15 V
Vcc
≤ 2 ns 1/2 Vcc 30 pF 1.0 kΩ
Vcc = 2.5±0.2 V
Vcc
≤ 2 ns 1/2 Vcc 30 pF 500 Ω
tr / tf
CL
RL
Vcc = 2.7 V
2.7 V ≤ 2.5 ns
1.5 V
50 pF 500 Ω
Vcc = 3.3±0.3 V
2.7 V ≤ 2.5 ns
1.5 V
50 pF 500 Ω
Vcc = 5.0±0.5 V
Vcc ≤ 2.5 ns 1/2 Vcc 50 pF 500 Ω
Notes: 1. Clock pulse Input waveform: PRR = 10 MHz, duty cycle 50%.
2. Data input waveform: PRR = 5 MHz, duty cycle 50%.
Rev.1.00 Jun. 22, 2004 page 7 of 8
Vref
RD74LVC74B
Package Dimensions
As of January, 2003
Unit: mm
10.06
10.5 Max
8
5.5
14
1
2.20 Max
*0.20 ± 0.05
7
1.42 Max
*0.40 ± 0.06
1.15
0˚ – 8˚
0.10 ± 0.10
1.27
0.20
7.80 +– 0.30
0.70 ± 0.20
0.15
0.12 M
Package Code
JEDEC
JEITA
Mass (reference value)
*Ni/Pd/Au plating
FP-14DAV
—
Conforms
0.23 g
As of January, 2003
Unit: mm
4.40
5.00
5.30 Max
14
8
1
7
0.65
1.0
*0.20 ± 0.05
0.13 M
6.40 ± 0.20
*Ni/Pd/Au plating
Rev.1.00 Jun. 22, 2004 page 8 of 8
0.07 +0.03
–0.04
0.10
*0.15 ± 0.05
1.10 Max
0.83 Max
0˚ – 8˚
0.50 ± 0.10
Package Code
JEDEC
JEITA
Mass (reference value)
TTP-14DV
—
—
0.05 g
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