400MHz Slew Enhanced VFAs EL5202, EL5203 Features The EL5202 and EL5203 are dual, high-speed VFAs based on a CFA architecture. This gives the typical high slew rate benefits of a CFA family along with the stability and ease of use associated with the VFA type architecture. With slew rates of 3500V/µs, these devices enable the use of voltage feedback amplifiers in a space where the only alternative has been current feedback amplifiers. This family also includes single, dual, and triple versions with 750MHz bandwidths; please see the EL5104 through EL5304 data sheet for details. • Operates off 3V, 5V, or ±5V supplies Both devices operate on single 5V or ±5V supplies from minimum supply current. The EL5202 also features an output enable function, which can be used to put the output in to a high-impedance mode. This allows the outputs of multiple amplifiers to be tied together for use in multiplexing applications. • Output current = 150mA • Differential gain/phase = 0.01%/0.01° Typical applications for these families include cable driving, filtering, A/D and D/A buffering, multiplexing and summing within video, communications, and instrumentation designs. • Video amplifiers • Power-down to 13µA (EL5202) • -3dB bandwidth = 400MHz • ±0.1dB bandwidth = 35MHz • Low supply current = 5mA per amplifier • Slew rate = 3500V/µs • Low offset voltage = 5mV max • AVOL = 2000 • Pb-free (RoHS compliant) Applications • PCMCIA applications • A/D drivers • Line drivers • Portable computers • High speed communications • RGB applications • Broadcast equipment • Active filtering January 17, 2014 FN7331.9 1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-468-3774 | Copyright Intersil Americas LLC 2002-2008, 2014. All Rights Reserved Intersil (and design) is a trademark owned by Intersil Corporation or one of its subsidiaries. All other trademarks mentioned are the property of their respective owners. EL5202, EL5203 Ordering Information PART NUMBER (Note 3) PART MARKING EL5202IYZ (Note 2) BAAAD TEMP RANGE (°C) -40 to +85 PACKAGE (Pb-free) PKG DWG. # 10 Ld MSOP (3.0mm) M10.118A EL5202IYZ-T7 (Notes 1, 2) BAAAD -40 to +85 10 Ld MSOP (3.0mm) M10.118A EL5202IYZ-T13 (Notes 1, 2) BAAAD -40 to +85 10 Ld MSOP (3.0mm) M10.118A EL5203ISZ (Note 2) 5203ISZ -40 to +85 8 Ld SOIC (150 mil) M8.15E EL5203ISZ-T7 (Notes 1, 2) 5203ISZ -40 to +85 8 Ld SOIC (150 mil) M8.15E EL5203ISZ-T13 (Notes 1, 2) 5203ISZ -40 to +85 8 Ld SOIC (150 mil) M8.15E EL5203IYZ (Note 2) BAAAE -40 to +85 8 Ld MSOP (3.0mm) M8.118A EL5203IYZ-T7 (Notes 1, 2) BAAAE -40 to +85 8 Ld MSOP (3.0mm) M8.118A EL5203IYZ-T13 (Notes 1, 2) BAAAE -40 to +85 8 Ld MSOP (3.0mm) M8.118A NOTES: 1. Please refer to TB347 for details on reel specifications. 2. These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020. 3. For Moisture Sensitivity Level (MSL), please see product information page for EL5202, EL5203 . For more information on MSL, please see tech brief TB363. Pin Configurations EL5203 (8 LD SOIC, MSOP) TOP VIEW EL5202 (10 LD MSOP) TOP VIEW OUT 1 IN- 2 IN+ 3 + + VS- 4 CE 5 10 VS+ OUTA 1 9 OUT INA- 2 8 IN- INA+ 3 7 IN+ VS- 4 8 VS+ 7 OUTB + 6 INB+ 5 INB+ 6 CE 2 FN7331.9 January 17, 2014 EL5202, EL5203 Absolute Maximum Ratings (TA = +25°C) Thermal Information Supply Voltage between VS+ and VS-. . . . . . . . . . . . . . . . . . . . . . . . . . 13.2V Maximum Supply Slew Rate between VS+ and VS- . . . . . . . . . . . . . . 1V/µs Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±VS Differential Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±4V Maximum Continuous Output Current . . . . . . . . . . . . . . . . . . . . . . . . . 80mA Maximum Current into IN+, IN-, CE . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±5mA Thermal Resistance (Typical) θJA (°C/W) θJC (°C/W) 10 Ld MSOP Package (Notes 4, 5) . . . . . . . 160 75 8 Ld SOIC Package (Notes 4, 5) . . . . . . . . . 125 75 8 Ld MSOP Package (Notes 4, 5) . . . . . . . . 170 80 Storage Temperature Range. . . . . . . . . . . . . . . . . . . . . . . -65°C to +150°C Ambient Operating Temperature Range . . . . . . . . . . . . . . -40°C to +85°C Operating Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . +150°C Pb-Free Reflow Profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . see link below http://www.intersil.com/pbfree/Pb-FreeReflow.asp CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and result in failures not covered by warranty. NOTES: 4. θJA is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief TB379 for details. 5. For θJC, the “case temp” location is taken at the package top center. IMPORTANT NOTE: All parameters having Min/Max specifications are guaranteed. Typical values are for information purposes only. Unless otherwise noted, all tests are at the specified temperature and are pulsed tests, therefore: TJ = TC = TA DC Electrical SpecificationsMVS+ = +5V, VS- = -5V, TA = +25°C, RL = 500Ω, VCE = 0V, Unless Otherwise Specified. PARAMETER VOS TCVOS DESCRIPTION CONDITIONS MIN (Note 9) Offset Voltage TYP MAX (Note 9) UNIT 1 5 mV Offset Voltage Temperature Coefficient Measured from TMIN to TMAX IB Input Bias Current VIN = 0V -12 2 12 µA IOS Input Offset Current VIN = 0V -8 1 8 µA TCIOS Input Bias Current Temperature Coefficient Measured from TMIN to TMAX PSRR Power Supply Rejection Ratio VS = ±4.75V to ±5.25V CMRR Common Mode Rejection Ratio VCM = -3V to 3.0V CMIR Common Mode Input Range Guaranteed by CMRR test RIN Input Resistance Common mode CIN Input Capacitance SO package IS,ON Supply Current - Enabled, Per Amplifier IS,OFF Supply Current - Shut-down, Per Amplifier Open Loop Gain AVOL 10 50 nA/°C -70 -80 dB -60 -80 dB -3 ±3.3 200 400 kΩ 1 pF IOUT Output Voltage Swing Output Current 3 V 4.6 5.2 5.8 mA VS+ +1 +9 +25 µA VS- -25 -13 -1 µA VOUT = ±2.5V, RL = 1kΩ to GND 58 66 dB 60 dB VOUT = ±2.5V, RL = 150Ω to GND VOUT µV/°C RL = 1kΩ to GND ±3.5 ±3.9 V RL = 150Ω to GND ±3.4 ±3.7 V AV = 1, RL = 10Ω to 0V ±80 ±150 mA VCE-ON CE Pin Voltage for Power-up (VS+) -5 (VS+) -3 V VCE-OFF CE Pin Voltage for Shut-down (VS+) -1 VS+ V ICE-ON CE Pin Current - Enabled CE = 0V -1 0 +1 µA ICE-OFF CE Pin Current - Disabled CE = +5V 1 14 25 µA 3 FN7331.9 January 17, 2014 EL5202, EL5203 Closed Loop AC Electrical Specifications Unless Otherwise Specified. (Note 6) PARAMETER VS+ = +5V, VS- = -5V, TA = +25°C, VCE = 0V, AV = +1, RF = 0Ω, RL = 150Ω to GND, DESCRIPTION CONDITIONS BW -3dB Bandwidth (VOUT = 400mVP-P) AV = 1, RF = 0Ω SR Slew Rate AV = +2, RL = 100Ω, VOUT = -3V to +3V MIN (Note 9) MAX (Note 9) 400 1100 RL = 500Ω, VOUT = -3V to +3V tR,tF TYP 2200 UNIT MHz 5000 V/µs 4000 V/µs Rise Time, Fall Time ±0.1V step 2.8 ns OS Overshoot ±0.1V step 10 % tS 0.1% Settling Time VS = ±5V, RL = 500Ω, AV = 1, VOUT = ±3V 20 ns dG Differential Gain (Note 7) AV = 2, RF = 1kΩ 0.01 % dP Differential Phase (Note 7) AV = 2, RF = 1kΩ 0.01 ° eN Input Noise Voltage f = 10kHz 12 nV/√Hz iN Input Noise Current f = 10kHz 11 pA/√Hz tDIS Disable Time (Note 8) 50 ns tEN Enable Time (Note 8) 25 ns NOTES: 6. All AC tests are performed on a “warmed up” part, except slew rate, which is pulse tested. 7. Standard NTSC signal = 286mVP-P, f = 3.58MHz, as VIN is swept from 0.6V to 1.314V.RL is DC coupled. 8. Disable/Enable time is defined as the time from when the logic signal is applied to the CE pin to when the supply current has reached half its final value. 9. Compliance to datasheet limits is assured by one or more methods: production test, characterization and/or design. 4 FN7331.9 January 17, 2014 EL5202, EL5203 Typical Performance Curves 5 3 2 180 120 60 PHASE (°) NORMALIZED GAIN (dB) 240 VS = ±5V AV = +1 RF = 0 RL = 500Ω CL = +3.3pF 4 1 0 -1 -2 VS = ±5V AV = +1 RF = 0 RL = 500Ω CL = +3.3pF 0 -60 -120 -3 -4 -180 -3dB BW @ 438MHz -240 -5 0.1M 1M 10M 100M FREQUENCY (Hz) 1G 0.1M 70 0.5 VS = ±5V AV = +1 RF = 0 RL = 500Ω CL = +3.3pF 0.2 0.1 VS = ±5V RL = 500Ω 0.1dB BW @ 35MHz 0 -0.1 100M 1G GAIN = 40dB or 100 FREQUENCY = 1.64 MHz GAIN BW PRODUCT = 1.64 x 100 = 164MHz 60 GAIN (dB) NORMALIZED GAIN (dB) 0.3 10M FREQUENCY (Hz) FIGURE 2. PHASE vs FREQUENCY FIGURE 1. GAIN vs FREQUENCY (-3dB BANDWIDTH) 0.4 1M 50 40 -0.2 30 -0.3 -0.4 -0.5 1M 10M FREQUENCY (Hz) 100M 20 0.1M 300 5 RL = 500Ω 4 250 200 150 100 3 VS = ±5V RL = 500Ω CL = +3.3pF 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 SUPPLY VOLTAGES (±V) FIGURE 5. GAIN BANDWIDTH PRODUCT vs SUPPLY VOLTAGES 5 AV = +2 RF = RG = 400Ω 2 AV = +1 RF = 0 1 0 -1 -2 AV = +5 RF = 1.6k, RG = 400 -3 -4 50 2.0 100M FIGURE 4. GAIN BANDWIDTH PRODUCT NORMALIZED GAIN (dB) GAIN-BANDWIDTH PRODUCT (MHz) FIGURE 3. 0.1dB BANDWIDTH 1M 10M FREQUENCY (Hz) -5 0.1M 1M 10M 100M 1G FREQUENCY (Hz) FIGURE 6. GAIN vs FREQUENCY FOR VARIOUS +AV FN7331.9 January 17, 2014 EL5202, EL5203 Typical Performance Curves NORMALIZED GAIN (dB) 4 3 2 5 AV = +1 RF = 0 RL = 500Ω CL = +3.3pF 4 NORMALIZED GAIN (dB) 5 1 0 -1 VS = ±6 VS = ±5V VS = ±4V -2 -3 VS = ±3V -4 -5 (Continued) 1M 10M 100M 2 RL = 500Ω 0 -1 -2 RL = 150Ω -3 RL = 75Ω -5 1G RL = 50Ω 0.1M 1M FIGURE 7. GAIN vs FREQUENCY FOR VARIOUS ±VS 3 2 5 VS = ±5V AV = +2 RF = 402Ω CL = +3.9pF RL = 500Ω RL = 1kΩ 0 -1 RL = 50Ω RL = 70Ω -3 -4 -5 RL = 150Ω 1M 0.1M 10M 100M FREQUENCY (Hz) 3 2 CL = 8.2pF 0 -1 CL = 3.3pF -3 CL = 0pF -4 -5 0.1M RL = 1kΩ 0 -1 RL = 50Ω -2 -3 RL = 75Ω RL = 150Ω 0.1M 1M 10M 100M FREQUENCY (Hz) FIGURE 11. GAIN vs FREQUENCY FOR VARIOUS CLOAD (AV = +1) 6 1M 10M FREQUENCY (Hz) 100M FIGURE 10. GAIN vs FREQUENCY FOR VARIOUS RLOAD (AV = +5) CL = 27pF CL = 15pF -2 1G RL = 500Ω 1 5 VS = ±5V AV = +1 RF = 0 RL = 500Ω 1 2 -5 1G 4 NORMALIZED GAIN (dB) NORMALIZED GAIN (dB) 4 3 -4 FIGURE 9. GAIN vs FREQUENCY FOR VARIOUS RLOAD (AV = +2) 5 VS = ±5V AV = +5 RF = 402Ω CL = +3.9pF 4 1 -2 100M FIGURE 8. GAIN vs FREQUENCY FOR VARIOUS RLOAD (AV = +1) NORMALIZED GAIN (dB) NORMALIZED GAIN (dB) 4 10M FREQUENCY (Hz) FREQUENCY (Hz) 5 RL = 1kΩ 1 -4 VS = ±2.5V 0.1M 3 VS = ±5V AV = +1 RF = 0 CL = +3.3pF 3 2 VS = ±5V AV = +2 RF = 400Ω RL = 500Ω CL = 47pF CL = 18pF 1 0 -1 CL = 8.2pF -2 -3 CL = 0pF -4 1G CL = 33pF -5 0.1M 1M 10M 100M FREQUENCY (Hz) 1G FIGURE 12. GAIN vs FREQUENCY FOR VARIOUS CLOAD (AV = +2) FN7331.9 January 17, 2014 EL5202, EL5203 Typical Performance Curves VS = ±5V AV = +5 RF = 400Ω RL = 500Ω NORMALIZED GAIN (dB) 4 3 2 CL = 150pF 5 CL = 220pF CL = 100pF 1 0 -1 CL = 56pF -2 -3 -4 -5 3 2 1M 0 -1 RF = 50Ω -2 RF = 25Ω -3 RF = 0Ω -4 10M -5 100M 0.1M 1M FREQUENCY (Hz) 3 2 VS = ±5V AV = +2 RL = 500Ω CL = +8pF 5 RF = 1.0kΩ RF = 680Ω 1 0 -1 RF = 402Ω -2 RF = 274Ω -3 -4 -5 1M 10M VS = ±5V AV = +5 RL = 500Ω CL = +12pF 4 3 2 100M 1G 0 -1 RF = 100Ω RF = 1kΩ -2 -3 RF = 402Ω -5 0.1M 2 1 -1 CIN = 1pF -3 CIN = 0pF -4 -5 0.1M 1M 10M 100M FREQUENCY (Hz) FIGURE 17. GAIN vs FREQUENCY FOR VARIOUS CIN(-) (AV = +2) 7 5 CIN = 4.7pF 0 -2 10M 100M FIGURE 16. GAIN vs FREQUENCY FOR VARIOUS RF (AV = +5) 4 NORMALIZED GAIN (dB) NORMALIZED GAIN (dB) 3 VS = ±5V CIN = 3.3pF AV = +2 RF = RG = 402Ω CIN = 2.2pF RL = 500Ω CL= +8pF 1M FREQUENCY (Hz) FIGURE 15. GAIN vs FREQUENCY FOR VARIOUS RF (AV = +2) 4 RF = 4kΩ 1 FREQUENCY (MHz) 5 1G RF = 2kΩ -4 RF = 100Ω 0.1M 100M FIGURE 14. GAIN vs FREQUENCY FOR VARIOUS RF (AV = +1) NORMALIZED GAIN (dB) NORMALIZED GAIN (dB) 4 10M FREQUENCY (Hz) FIGURE 13. GAIN vs FREQUENCY FOR VARIOUS CLOAD (AV = +5) 5 RF = 150Ω RF = 100Ω 1 CL = 0pF 0.1M VS = ±5V AV = +1 RL = 500Ω CL = +3pF 4 NORMALIZED GAIN (dB) 5 (Continued) 3 2 1 VS = ±5V AV = +5 RG = 402Ω RF = 1600Ω CL = +12pF CIN = 8.2pF CIN = 10pF CIN = 6.8pF 0 -1 -2 CIN = 0pF CIN = 4.7pF -3 -4 1G -5 0.1M 1M 10M FREQUENCY (Hz) 100M FIGURE 18. GAIN vs FREQUENCY FOR VARIOUS CIN(-) (AV = +5) FN7331.9 January 17, 2014 EL5202, EL5203 80 -45 70 0 45 PHASE 50 90 40 135 30 180 20 225 GAIN 10 270 0 315 -10 -20 10 360 VS = ±5V 100 100 PHASE (°) GAIN (dB) 60 (Continued) OUTPUT IMPEDANCE (Ω) Typical Performance Curves 1k 10k 100k 1M AV = +2 VS = ±5V 10 1 0.1 0.01 405 10M 100M 1G 10k 100k -30 -10 -40 -20 -50 -60 -70 -30 -40 -50 -80 -60 -90 -70 -100 -80 -110 1k 10k 100k 1M 10M -90 1k 100M 500M +PSRR -PSRR 10k RLOAD = 1kΩ 8 GROUP DELAY (ns) MAX OUTPUT VOLTAGE SWING (VP-P) 10 7 6 5 4 2 1 0 VS = ±5V AV = +2 RF = RG = 402Ω CL = 8pF 0.1M RLOAD = 150Ω 1M 10M 100M 1G FREQUENCY (Hz) FIGURE 23. MAX OUTPUT VOLTAGE SWING vs FREQUENCY 8 1M 10M 100M 500M FIGURE 22. PSRR vs FREQUENCY FIGURE 21. CMRR vs FREQUENCY 9 100k FREQUENCY (Hz) FREQUENCY (Hz) 3 100M AV = +1 VS = ±5V 0 PSRR (dB) CMRR (dB) 10 AV = +5 VS = ±5V -20 10M FIGURE 20. OUTPUT IMPEDANCE vs FREQUENCY FIGURE 19. OPEN LOOP GAIN AND PHASE vs FREQUENCY -10 1M FREQUENCY (Hz) FREQUENCY (Hz) 30 25 VS = ±5V A = +1 20 RV = 0 F 15 RL = 500Ω 10 5 0 -5 -10 -15 -20 -25 -30 0.1M 1M 10M 100M FREQUENCY (Hz) 1G FIGURE 24. GROUP DELAY vs FREQUENCY FN7331.9 January 17, 2014 EL5202, EL5203 Typical Performance Curves -20 ISOLATION (dB) -30 VS = ±5V AV = +1 RF = 0 CHIP DISABLED OUTPUT TO INPUT -40 -50 -60 INPUT TO OUTPUT GAIN (dB) -10 (Continued) -70 -80 -90 -100 0.1M 1M 10M 100M 1G 10 NOTE: 0 VS = ±5V This was done on the -10 AV = +1 EL5203 (Dual Op-Amps) R =0 -20 RF = 500Ω L -30 BIN TO AOUT -40 -50 AIN TO BOUT -60 -70 -80 -90 -100 -110 -120 0.1M 1M 10M 100M FREQUENCY (Hz) FIGURE 25. INPUT AND OUTPUT ISOLATION -40 -50 -60 -20 VS = ±5V AV = +1 RF = 0 RL = 500Ω CL = 3.3pF VOUT = 2VP-P -70 FIGURE 26. CHANNEL-TO-CHANNEL ISOLATION -40 T.H.D 2nd HD -80 -70 ENABLE SIGNAL 4 3 VS = ±5V AV = +1 RF = 0 RL = 500Ω VOUT = 2VP-P OUTPUT SIGNAL 2 -100 100M 1 0 2 9 3 4 5 6 7 8 DISABLE SIGNAL OUTPUT SIGNAL 1 0 -2 FIGURE 29. TURN-ON TIME 2 VS = ±5V 5 AV = +1 RF = 0 4 R = 500Ω L 3 VOUT = 2VP-P -1 TIME (ns) 1 6 -2 0 200 400 600 800 1000 1200 1400 1600 0 FIGURE 28. TOTAL HARMONIC DISTORTION vs OUTPUT VOLTAGES -1 -3 -600 -400 -200 FIN = 1MHz OUTPUT VOLTAGES (VP-P) AMPLITUDE (V) 1M 10M FUNDAMENTAL FREQUENCY (Hz) 6 AMPLITUDE (V) -60 -90 3rd HD FIGURE 27. HARMONIC DISTORTION vs FREQUENCY 5 -50 FIN = 10MHz -80 -90 -100 0.1M VS = ±5V AV = +5 RG = 402Ω RF = 1600Ω RL = 500Ω CL = 12pF -30 THD (dBc) HARMONIC DISTORTION (dBc) -30 1G FREQUENCY (Hz) -3 -600 -400 -200 0 200 400 600 800 1000 1200 1400 1600 TIME (ns) FIGURE 30. TURN-OFF TIME FN7331.9 January 17, 2014 EL5202, EL5203 Typical Performance Curves (Continued) 0.5 VS = ±5V 0.4 AV = +1 RF = 0 0.3 AMPLITUDE (V) NOISE VOLTAGE (nV/√Hz) 1000 VS = ±5V 100 10 0.2 tFALL = 0.9ns 0.1 0.0 tRISE = 0.923ns -0.1 -0.2 1 10 100 1k 10k -0.3 -20 100k 0 20 FREQUENCY (Hz) FIGURE 31. EQUIVALENT NOISE VOLTAGE vs FREQUENCY 4 AMPLITUDE (V) 3 VS = ±5V AV = +5 RG = 25Ω 6.0 RL = 500Ω CL = 5pF VOUT = 4.0V 5.8 2 1 tFALL = 1.167ns 0 tRISE = 1.243ns -1 -2 -3 0 20 40 -10 -20 -30 -40 -50 5.4 5.2 5.0 4.8 4.6 Please note that the curve showed positive Current. The negative current was almost the same. 4.4 40 35 2f2-f1 = -77.0dBm @ 1.15MHz 2f1-f2 = -76.8dBm -60 @ 0.85MHz -70 6.0 30 25 20 15 -80 10 -90 5 -100 0.8M 5.5 VS = ±5V AV = +5 RF = 1600Ω RL = 100Ω CL = 12pF 45 f2 = 1dBm @ 1.05MHz f1 = 1dBm @ 0.95MHz 3.5 4.0 4.5 5.0 SUPPLY VOLTAGE (V) 50 ΔIM = (1) - (-77) = 78dB IP3 = 1+ (78/2) = 40dBm VS = ±5V AV = +5 RF = 1600Ω RL = 100Ω CL = 12pF 3.0 FIGURE 34. SUPPLY CURRENT vs SUPPLY VOLTAGE IP3 (dBm) 0 5.6 4.0 2.5 60 80 100 120 140 160 TIME (ns) FIGURE 33. LARGE SIGNAL STEP RESPONSE RISE AND FALL TIME 10 60 80 100 120 140 160 TIME (ns) AV = +1 RF = 0 RL = 500Ω CL = 3.3pF 4.2 -20 40 FIGURE 32. SMALL SIGNAL STEP RESPONSE RISE AND FALL TIME SUPPLY CURRENT (mA) 5 AMPLITUDE (dBm) RL = 500Ω CL = 3.3pF VOUT = 400mV 0.9M 1.0M FREQUENCY (Hz) 1.1M 1.2M FIGURE 35. THIRD ORDER IMD INTERCEPT (IP3) 0 1M 10M FREQUENCY (Hz) 100M FIGURE 36. THIRD ORDER IMD INTERCEPT vs FREQUENCY For additional products, see www.intersil.com/en/products.html Intersil products are manufactured, assembled and tested utilizing ISO9001 quality systems as noted in the quality certifications found at www.intersil.com/en/support/qualandreliability.html Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com 10 FN7331.9 January 17, 2014 EL5202, EL5203 Package Outline Drawing M10.118A (JEDEC MO-187-BA) 10 LEAD MINI SMALL OUTLINE PLASTIC PACKAGE (MSOP) Rev 0, 9/09 3.0 ± 0.1 A 0.25 10 DETAIL "X" CAB 0.18 ± 0.05 SIDE VIEW 2 4.9 ± 0.15 3.0 ± 0.1 1.10 Max B PIN# 1 ID 1 2 0.95 BSC 0.5 BSC TOP VIEW Gauge Plane 0.86 ± 0.09 H 0.25 C 3°±3° SEATING PLANE 0.10 ± 0.05 0.23 +0.07/ -0.08 0.08 C A B 0.55 ± 0.15 0.10 C DETAIL "X" SIDE VIEW 1 5.80 4.40 3.00 NOTES: 0.50 0.30 1. Dimensions are in millimeters. 2. Dimensioning and tolerancing conform to AMSE Y14.5m-1994. 3. Plastic or metal protrusions of 0.15mm max per side are not included. Plastic interlead protrusions of 0.25mm max per side are not included. 4. 1.40 5. Dimensions “D” and “E1” are measured at Datum Plane “H”. TYPICAL RECOMMENDED LAND PATTERN 6. This replaces existing drawing # MDP0043 MSOP10L. 11 FN7331.9 January 17, 2014 EL5202, EL5203 Package Outline Drawing M8.118A 8 LEAD MINI SMALL OUTLINE PLASTIC PACKAGE (MSOP) Rev 0, 9/09 3.0±0.1 8 A 0.25 CAB 3.0±0.1 4.9±0.15 DETAIL "X" 1.10 Max PIN# 1 ID B SIDE VIEW 2 1 0.18 ± 0.05 2 0.65 BSC TOP VIEW 0.95 BSC 0.86±0.09 H GAUGE PLANE C 0.25 SEATING PLANE 0.33 +0.07/ -0.08 0.08 C A B 0.10 ± 0.05 3°±3° 0.10 C 0.55 ± 0.15 DETAIL "X" SIDE VIEW 1 5.80 NOTES: 4.40 3.00 1. Dimensions are in millimeters. 2. Dimensioning and tolerancing conform to JEDEC MO-187-AA and AMSE Y14.5m-1994. 3. Plastic or metal protrusions of 0.15mm max per side are not included. 4. Plastic interlead protrusions of 0.25mm max per side are not included. 5. Dimensions “D” and “E1” are measured at Datum Plane “H”. 6. This replaces existing drawing # MDP0043 MSOP 8L. 0.65 0.40 1.40 TYPICAL RECOMMENDED LAND PATTERN 12 FN7331.9 January 17, 2014 EL5202, EL5203 Package Outline Drawing M8.15E 8 LEAD NARROW BODY SMALL OUTLINE PLASTIC PACKAGE Rev 0, 08/09 4 4.90 ± 0.10 A DETAIL "A" 0.22 ± 0.03 B 6.0 ± 0.20 3.90 ± 0.10 4 PIN NO.1 ID MARK 5 (0.35) x 45° 4° ± 4° 0.43 ± 0.076 1.27 0.25 M C A B SIDE VIEW “B” TOP VIEW 1.75 MAX 1.45 ± 0.1 0.25 GAUGE PLANE C SEATING PLANE 0.10 C 0.175 ± 0.075 SIDE VIEW “A 0.63 ±0.23 DETAIL "A" (0.60) (1.27) NOTES: (1.50) (5.40) 1. Dimensions are in millimeters. Dimensions in ( ) for Reference Only. 2. Dimensioning and tolerancing conform to AMSE Y14.5m-1994. 3. Unless otherwise specified, tolerance : Decimal ± 0.05 4. Dimension does not include interlead flash or protrusions. Interlead flash or protrusions shall not exceed 0.25mm per side. 5. The pin #1 identifier may be either a mold or mark feature. 6. Reference to JEDEC MS-012. TYPICAL RECOMMENDED LAND PATTERN 13 FN7331.9 January 17, 2014