CA5420AMZ - Intersil

DATASHEET
0.5MHz, Low Supply Voltage, Low Input Current BiMOS
Operational Amplifiers
CA5420A
Features
The CA5420A is an integrated circuit operational amplifier that
combines PMOS transistors and bipolar transistors on a single
monolithic chip. It is designed and guaranteed to operate in
microprocessor logic systems that use V+ = 5V, V- = GND, since it
can operate down to ±1V supplies. It will also be suitable for 3.3V
logic systems.
• CA5420A at 5V supply voltage with full military temperature
range guaranteed specifications
The CA5420A BiMOS operational amplifier features
gate-protected PMOS transistors in the input circuit to provide
very high input impedance, very low input currents (less than
1pA). The internal bootstrapping network features a unique
guardbanding technique for reducing the doubling of leakage
current for every +10°C increase in temperature. The CA5420A
operates at total supply voltages from 2V to 20V either single or
dual supply. This operational amplifier is internally phase
compensated to achieve stable operation in the unity gain
follower configuration. Additionally, it has access terminals for a
supplementary external capacitor if additional frequency roll-off is
desired. Terminals are also provided for use in applications
requiring input offset voltage nulling. The use of PMOS in the
input stage results in common-mode input voltage capability
down to 0.45V below the negative supply terminal, an important
attribute for single supply application. The output stage uses a
feedback OTA type amplifier that can swing essentially from
rail-to-rail. The output driving current of 1.0mA (Min) is provided by
using nonlinear current mirrors.
• Rail-to-rail output swing (Drive ±2mA into 1kΩ load)
• CA5420A guaranteed to operate from ±1V to ±10V supplies
• 2V supply at 350µA supply current
• 1pA (Typ) input current (essentially constant to +85°C)
• Pin compatible with 741 op amp
• Pb-free (RoHS compliant)
Applications
• pH probe amplifiers
• Picoammeters
• Electrometer (High Z) instruments
• Portable equipment
• Inaccessible field equipment
• Battery dependent equipment (medical and military)
• 5V logic systems
• Microprocessor interface
This device has guaranteed specifications for 5V operation
over the full military temperature range of -55°C to +125°C.
The CA5420A has the same 8 lead pinout used for the industry
standard 741.
X1
BiMOS
+
BiMOS
X1
BUFFER AMPS;
BOOTSTRAPPED
INPUT PROTECTION
NETWORK
HIGH GAIN
(50k)
TA BUFER
(X2)
FIGURE 1. FUNCTIONAL DIAGRAM
February 11, 2015
FN1925.9
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Copyright Intersil Americas LLC 1998, 2005, 2009, 2011, 2013, 2015. All Rights Reserved
Intersil (and design) is a trademark owned by Intersil Corporation or one of its subsidiaries.
All other trademarks mentioned are the property of their respective owners.
CA5420A
Ordering Information
PART NUMBER
(Notes 1, 2, 3)
PART
MARKING
CA5420AMZ
TEMP. RANGE
(°C)
5420 AMZ
PACKAGE
(RoHS Compliant)
-55 to +125
8 Ld SOIC
PKG.
DWG. #
M8.15
NOTES:
1. Add “96” suffix for Tape and Reel. Please refer to TB347 for details on reel specifications.
2. These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte
tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil
Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
3. For Moisture Sensitivity Level (MSL), please see product information page for CA5420A. For more information on MSL please see techbrief TB363.
Pin Configuration
CA5420A
(8 LD SOIC)
TOP VIEW
OFFSET
1
NULL
INV.
2
INPUT
NON-INV.
INPUT
3
V-
4
+
8
STROBE
7
V+
6
OUTPUT
5
OFFSET
NULL
Pin is connected to Case.
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FN1925.9
February 11, 2015
CA5420A
Absolute Maximun Ratings
Thermal Information
Supply Voltage (Between V+ and V- Terminals) . . . . . . . . . . . . . . . . . . . 22V
Differential Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15V
Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . (V+ + 8V) to (V- -0.5V)
Input Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1mA
Output Short Circuit Duration (Note 4). . . . . . . . . . . . . . . . . . . . . . Indefinite
Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -55°C to +125°C
Thermal Resistance (Typical, Note 5)
JA (°C/W)
JC (°C/W)
SOIC Package . . . . . . . . . . . . . . . . . . . . . . . .
157
N/A
Maximum Junction Temperature (Plastic Package) . . . . . . . . . . . +150°C
Maximum Storage Temperature Range (All Types) . . . . . . . -65°C to +150°C
Pb-Free Reflow Profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . see TB493
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product
reliability and result in failures not covered by warranty.
NOTES:
4. Short circuit may be applied to ground or to either supply.
5. JA is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief TB379 for details.
Electrical Specifications
Typical Values Intended Only for Design Guidance. V+ = +5V; V- = GND, TA = +25°C
PARAMETER
SYMBOL
TEST CONDITIONS
CA5420A
UNITS
Input Resistance
RI
150
TΩ
Input Capacitance
CI
4.9
pF
Output Resistance
RO
300
Ω
Equivalent Input
Noise Voltage
eN
62
nV/Hz
38
nV/Hz
IOM+
2.6
mA
IOM-
2.4
mA
Gain Bandwidth Product
fT
0.5
MHz
Slew Rate
SR
0.5
V/µs
0.7
µs
RS = 100Ω
f = 10kHz
Short-Circuit Current To Opposite Source
Supply
Sink
Transient Response
f = 1kHz
Rise Time
tr
Overshoot
OS
15
%
Current from Terminal 8 To V-
I8 +
20
µA
Current from Terminal 8 To V+
I8 -
2
mA
Settling Time
Electrical Specifications
RL = 2kΩ, CL = 100pF
0.01%
AV = 1
2VP-P Input
8
µs
0.10%
AV = 1
2VP-P Input
4.5
µs
+
TA = +25°C, V+ = 5V, V- = 0, Unless Otherwise Specified.
CA5420A
PARAMETER
TEST
CONDITIONS
SYMBOL
MIN
(Note 6)
TYP
MAX
(Note 6)
UNITS
Input Offset Voltage
VIO
VO = 2.5V
1
5
mV
Input Offset Current
IIO
VO = 2.5V
0.02
4
pA
II
VO = 2.5V
0.02
5
Input Current
pA
Common Mode Rejection Ratio
CMRR
VCM = 0 to 3.7V, VO = 2.5V
75
83
dB
Common Mode Input Voltage Range
VlCR+
VO = 2.5V
3.7
4
V
VlCR-
-0.3
0
V
V+ = 1V; V- = 1V
70
83
dB
VO = 0.5 to 4V
RL = 
85
87
dB
VO = 0.5 to 4V
RL = 10kΩ
85
87
dB
VO = 0.7 to 3V
RL = 2kΩ
70
85
dB
VO = 0V
1.2
2.7
mA
Power Supply Rejection Ratio
PSRR
Large Signal Voltage Gain
AOL
Source Current
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ISOURCE
3
FN1925.9
February 11, 2015
CA5420A
Electrical Specifications
TA = +25°C, V+ = 5V, V- = 0, Unless Otherwise Specified. (Continued)
CA5420A
PARAMETER
TEST
CONDITIONS
SYMBOL
MIN
(Note 6)
TYP
MAX
(Note 6)
UNITS
Sink Current
ISINK
VO = 5V
1.2
2.1
mA
Output Voltage
VOM+
RL = 
4.85
4.94
V
VOMVOM+
0.13
RL = 10kΩ
4.7
RL = 2kΩ
3.5
ISUPPLY
Electrical Specifications
temperature range, -55°C to +125°C.
V
0.12
0.15
V
4.6
VOMSupply Current
V
4.9
VOMVOM+
0.15
V
0.1
0.15
V
VO = 0V
400
550
µA
VO = 2.5V
430
600
µA
TA = -55°C to +125°C, V+ = 5V, V- = 0, Unless Otherwise Specified. Boldface limits apply across the operating
CA5420A
PARAMETER
SYMBOL
TEST
CONDITIONS
MIN
(Note 6)
TYP
MAX
(Note 6)
UNITS
Input Offset Voltage
VIO
VO = 2.5V
2
10
mV
Input Offset Current
IIO
VO = 2.5V
1.5
3
nA
2
10
pA
2
5
nA
10
15
pA
Up to TA = +85°C
II
Input Current
VO = 2.5V
Up to TA = +85°C
Common Mode Rejection Ratio
CMRR
VCM = 0 to 3.7V,
VO = 2.5V
70
80
dB
Common Mode Input Voltage Range
VlCR+
VO = 2.5V
3.7
4
V
VlCR-
-0.3
0
V
V+ = 1V;
V- = 1V
70
83
dB
VO = 0.5 to 4V
RL = 
65
75
dB
VO = 0.7 to 4V
RL = 10kΩ
80
87
dB
VO = 0.7 to 2.5V
RL = 2kΩ
70
80
dB
ISOURCE
VO = 0V
1
2.7
mA
Sink Current
ISINK
VO = 5V
1
2.1
mA
Output Voltage
VOM+
RL = 
4.8
4.9
V
RL = 10kΩ
4.7
Power Supply Rejection Ratio
PSRR
Large Signal Voltage Gain
AOL
Source Current
VOMVOM+
0.16
VOMVOM+
0.15
RL = 2kΩ
VOMSupply Current
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ISUPPLY
4
3
0.2
4.9
V
V
0.2
4
V
V
0.14
0.2
V
VO = 0V
430
600
µA
VO = 2.5V
480
650
µA
FN1925.9
February 11, 2015
CA5420A
Electrical Specifications
For Equipment Design at VSUPPLY = ±1V, TA = +25°C, Unless Otherwise Specified.
CA5420A
PARAMETER
SYMBOL
TEST
CONDITIONS
MIN
(Note 6)
TYP
MAX
(Note 6)
UNITS
Input Offset Voltage
VIO
2
5
mV
Input Offset Current
IIO
0.01
4
pA
Input Current
II
0.02
5
pA
Large Signal Voltage Gain
AOL
Common Mode Rejection Ratio
RL = 10kΩ
10
100
kV/V
80
100
dB
560
µV/V
50
65
dB
V
CMRR
Common Mode Input Voltage Range
VlCR+
0.2
0.5
VlCR-
-1
-1.3
Power Supply Rejection Ratio
PSRR
Maximum Output Voltage
VOM+
RL = 
VOMSupply Current
Device Dissipation
Input Offset Voltage Temperature Drift
Electrical Specifications
V
32
425
µV/V
70
90
dB
0.9
0.95
V
-0.85
-0.91
V
ISUPPLY
350
650
µA
PD
0.7
1.1
mW
VIO/T
4
µV/°C
For Equipment Design at VSUPPLY = ±10V, TA = +25°C, Unless Otherwise Specified.
CA5420A
PARAMETER
SYMBOL
TEST
CONDITIONS
MIN
(Note 6)
TYP
MAX
(Note 6)
UNITS
2
5
mV
Input Offset Voltage
VIO
Input Offset Current
IIO
0.03
4
pA
Input Current
II
0.05
5
pA
Large Signal Voltage Gain
AOL
Common Mode Rejection Ratio
RL = 10kΩ
20
100
kV/V
80
100
dB
CMRR
100
70
Common Mode Input Voltage Range
Power Supply Rejection Ratio
dB
9
9.3
V
VlCR-
-10
-10.3
V
32
70
VOM+
VOM-
Supply Current
µV/V
VlCR+
PSRR
Maximum Output Voltage
320
80
RL = 
320
µV/V
90
dB
9.7
9.9
V
-9.7
-9.85
V
ISUPPLY
450
1000
µA
Device Dissipation
PD
9
14
mW
Input Offset Voltage
Temperature Drift
VIO/T
4
µV/°C
NOTE:
6. Compliance to datasheet limits is assured by one or more methods: production test, characterization and/or design.
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FN1925.9
February 11, 2015
CA5420A
Typical Applications
High Input Resistance Voltmeter
Picoammeter Circuit
The exceptionally low input current (typically 0.2pA) makes the
CA5420A highly suited for use in a picoammeter circuit. With only
a single 10GΩ resistor, this circuit covers the range from ±1.5pA.
Higher current ranges are possible with suitable switching
techniques and current scaling resistors. Input transient protection
is provided by the 1MΩ resistor in series with the input. Higher
current ranges require that this resistor be reduced. The 10MΩ
resistor connected to pin 2 of the CA5420A decouples the
potentially high input capacitance often associated with lower
current circuits and reduces the tendency for the circuit to oscillate
under these conditions.
Advantage is taken of the high input impedance of the CA5420A in
a high input resistance DC voltmeter. Only two 1.5V “AA” type penlite
batteries power this exceedingly high-input resistance (>1,000,
000M) DC voltmeter. Full-scale deflection is ±500mV, ±150mV,
and ±15mV. Higher voltage ranges are easily added with external
input voltage attenuator networks.
The meter is placed in series with the gain network, thus
eliminating the meter temperature coefficient error term.
Supply current in the standby position with the meter
undeflected is 300µA. At full-scale deflection this current rises to
800µA. Carbon-zinc battery life should be in excess of 1,000
hours.
10GΩ
+1.5V
+1.5V
10pF
2
1MΩ
10MΩ
3
CA5420A
3
+
1
6
±50pA
BATTERY
RETURNS
10kΩ
10MΩ
100pF
M
4
5
22MΩ
500 to 0 to 500
µA
7
-
500 to 0 to 500
µA
7
+
6
CA5420A
-
2
1.5kΩ
1
5
±500mV
4
BATTERY
RETURNS
10kΩ
±15pA
1.5kΩ
1%
±5pA
1kΩ
430Ω
1%
±1.5pA
150Ω
1%
M
±150mV
1.5kΩ
1%
±50mV
1kΩ
430Ω
1%
±15mV
150Ω
1%
-1.5V
-1.5V
1.1kΩ
11kΩ
1.5kΩ
68Ω
1%
68Ω
1%
FIGURE 3. HIGH INPUT RESISTANCE VOLTMETER
FIGURE 2. PICOAMMETER CIRCUIT
1.0
TA = +25°C
0.8 R = 100k
L
0.6
0.4
0.2
VO -
0
-0.2
VO +
-0.4
VICR-
-0.6
VICR+
-0.8
-1.0
0
1
5
10
SUPPLY VOLTAGE (V)
15
FIGURE 4. OUTPUT VOLTAGE SWING AND COMMON MODE INPUT
VOLTAGE RANGE vs SUPPLY VOLTAGE
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OUTPUT STAGE TRANSISTOR SATURATION
VOLTAGE, Q19 (mV)
INPUT AND OUTPUT VOLTAGE EXCURSIONS
FROM THE POSITIVE AND NEGATIVE
SUPPLY VOLTAGE (V)
Typical Performance Curves
10
TA = +25°C
V- = 0V
V+ = 2V
100
V+ = 5V
V+ = 10V
V+ = 20V
1000
0.001
0.1
1
LOAD (SOURCING) CURRENT (mA)
10
FIGURE 5. OUTPUT VOLTAGE vs LOAD SOURCING CURRENT
FN1925.9
February 11, 2015
CA5420A
1000
TA = +25°C
V+ = 0V
V+ = 5V
V- = GND
SUPPLY CURRENT (µA)
OUTPUT STAGE TRANSISTOR SATURATION
VOLTAGE, Q17 (mV)
Typical Performance Curves (Continued)
V- = -20V
V- = -10V
V- = -5V
V- = -2V
100
2400
2000
1600
1200
800
400
10
0.01
0.1
1
LOAD (SINKING) CURRENT (mA)
0
10
FIGURE 6. OUTPUT VOLTAGE vs LOAD SINKING CURRENT
4
5
800
TA = +25°C
V+ = 5V
V- = GND
RL TO GND
3.75
700
INPUT BIAS CURRENT (pA)
2.50
1.25
V+ = 5V
V- = GND
600
500
400
300
200
100
0
0
1
10
100
LOAD RESISTANCE (kΩ)
0
25
1k
OPEN LOOP VOLTAGE GAIN (dB)
101
103
104
105
FREQUENCY (Hz)
FIGURE 10. INPUT NOISE VOLTAGE vs FREQUENCY
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7
65
75
85
95
105
115
125
FIGURE 9. INPUT BIAS CURRENT DRIFT (IB/T)
100
102
55
TA =+ 25°C
V+ = +10V, V- = 10V
RL = 10kΩ
CL = 0pF
TA = +25°C
VS = ±10V
VS = ±5V
VS = ±1V
1
101
45
TEMPERATURE (°C)
FIGURE 8. OUTPUT VOLTAGE SWING vs LOAD RESISTANCE
1000
35
106
100
0
-45
80
-90
60
-135
-180
40
OPEN LOOP PHASE (°)
OUTPUT VOLTAGE SWING (V)
2
3
OUTPUT VOLTAGE (V)
FIGURE 7. SUPPLY CURRENT vs OUTPUT VOLTAGE
5.00
EQUIVALENT INPUT NOISE VOLTAGE (nV√Hz)
1
20
0
1
101
102
103
104
105
106
FREQUENCY (Hz)
FIGURE 11. OPEN LOOP GAIN AND PHASE SHIFT RESPONSE
FN1925.9
February 11, 2015
CA5420A
Revision History
The revision history provided is for informational purposes only and is believed to be accurate, but not warranted. Please go to web to make sure you
have the latest revision.
DATE
REVISION
CHANGE
February 11, 2015
FN1925.9
Electrical Specifications Table: On page 3, Large signal voltage gain Vo = 0.7 to 3V Min limit changed from 80
to 70, and page 4 Large signal voltage gain Vo = 0.7 to 2.5V Min limit changed from 75 to 70.
September 25, 2013
FN1925.8
Page 5 - Changed CMRR limits for ±1V spec table from 60dB to 50dB
Page 9 - Updated POD to rev 4. Changes from rev 3: Changed Note 1 "1982" to "1994".
July 8, 2011
FN1925.7
page 1 Features: Change "2V Supply at 300µA....." to "2V Supply at 350µA....."
page 3 Updated Thermal Resistance note for package.
page 3 Electrical Spec Table, V+ = 5V, V- = 0V (lower table): change PSRR min from 75dB to 70dB.
page 4 Electrical Spec Table, V+ = 5V, V- = 0V (upper table) Change Supply Current Vo =0V Max from 500µA to
550µA, and V0 = 2.5V change max from 550µA to 600µA.
page 4 Electrical Spec Table, TA = -55 to +125 V+ = 5V, V- = 0V (lower table) change Supply Current VO=0V Max
from 550µA to 600µA, change Vo=2.5V max from 600uA to 650uA.
page 5 Electrical Spec Table Vsupply =+/-1V (upper table) Common Mode Rejection Ratio, delete 1000uV/V
MAX spec and leave only a typ spec. PSRR change 320uV/V max to 425µV/V max.
page 9 POD M8.15 Updated to new POD format by removing table and moving dimensions onto drawing and
adding land pattern. Changed in Typical Recommended Land Pattern the following:
2.41(0.095) to 2.20(0.087)
0.76 (0.030) to 0.60(0.023)
0.200 to 5.20(0.205)
December 08, 2009
FN1925.6
Electrical Specifications Table; TA = 25°C, V+ = 5V, V- = 0V; Change Input Offset Current Max from 0.5pA to 4pA
P3, same table as above; Input Current Max from 1pA to 5pA.
P4: same table as above; Output Voltage VOM+: Minimum spec for RL = Infinity from 4.9V to 4.85V
P5: In Vsupply = +/-1V, Large Signal Voltage Gain spec : Min from 20kV/V to 10kV/V and from 86dB to 80dB
P4; Large Signal Voltage Gain RL = inf; change min to 65dB and typ to75dB (was 85dB Min and 87dB Typ)
Updated Pb-free bullet in Features and Pb-free note in Ordering Information per Mark Kwoka's new verbiage
based on lead finish. Added TB347 link to ordering information for reel specifications. Added MSL link to Order
Info
Updated Caution statement in Abs Max per legal's new verbiage.
Added Pb-Free Reflow link to Thermal Info
Added POD to last page
Added standard Over Temp note to applicable elec spec tables
Corrected Input Offset Current Max from 0.4pA to 4pA
December 21, 2005
FN1925.5
Added redline release FGs to ordering information table.
September 1998
FN1925.4
Initial Release
About Intersil
Intersil Corporation is a leading provider of innovative power management and precision analog solutions. The company's products
address some of the largest markets within the industrial and infrastructure, mobile computing and high-end consumer markets.
For the most updated datasheet, application notes, related documentation and related parts, please see the respective product
information page found at www.intersil.com.
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For additional products, see www.intersil.com/en/products.html
Intersil products are manufactured, assembled and tested utilizing ISO9001 quality systems as noted
in the quality certifications found at www.intersil.com/en/support/qualandreliability.html
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time
without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be
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FN1925.9
February 11, 2015
CA5420A
Package Outline Drawing
M8.15
8 LEAD NARROW BODY SMALL OUTLINE PLASTIC PACKAGE
Rev 4, 1/12
DETAIL "A"
1.27 (0.050)
0.40 (0.016)
INDEX
6.20 (0.244)
5.80 (0.228)
AREA
0.50 (0.20)
x 45°
0.25 (0.01)
4.00 (0.157)
3.80 (0.150)
1
2
8°
0°
3
0.25 (0.010)
0.19 (0.008)
TOP VIEW
SIDE VIEW “B”
2.20 (0.087)
SEATING PLANE
5.00 (0.197)
4.80 (0.189)
1.75 (0.069)
1.35 (0.053)
1
8
2
7
0.60 (0.023)
1.27 (0.050)
3
6
4
5
-C-
1.27 (0.050)
0.51(0.020)
0.33(0.013)
SIDE VIEW “A
0.25(0.010)
0.10(0.004)
5.20(0.205)
TYPICAL RECOMMENDED LAND PATTERN
NOTES:
1. Dimensioning and tolerancing per ANSI Y14.5M-1994.
2. Package length does not include mold flash, protrusions or gate burrs.
Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006
inch) per side.
3. Package width does not include interlead flash or protrusions. Interlead
flash and protrusions shall not exceed 0.25mm (0.010 inch) per side.
4. The chamfer on the body is optional. If it is not present, a visual index
feature must be located within the crosshatched area.
5. Terminal numbers are shown for reference only.
6. The lead width as measured 0.36mm (0.014 inch) or greater above the
seating plane, shall not exceed a maximum value of 0.61mm (0.024 inch).
7. Controlling dimension: MILLIMETER. Converted inch dimensions are not
necessarily exact.
8. This outline conforms to JEDEC publication MS-012-AA ISSUE C.
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FN1925.9
February 11, 2015