SIGNS N EW D E R O F D NT ND E LACEME COMME P E E R R T D O E N D nter at OMMEN pport Ce m/tsc u S l NO RE C a ic n tersil.co our Tech contact ERSIL or www.in T 1-888-IN DATASHEET Programmable Temperature Controlled MOSFET Driver ISL25700 Features The Temperature Controlled MOSFET Driver is a highly integrated solution that combines a MOSFET driver with overcurrent protection and two 8-bit resolution DACs on a monolithic CMOS integrated circuit (IC). • User-programmable setpoint via I2C serial interface • Setpoint temperature range from +40°C to +110°C • Operational temperature range from -40°C to +125°C • 3°C initial setpoint accuracy The ISL25700 sets up and monitors temperature at the point of interest, compares it with the user programmable setpoint, and adjusts the output until the set temperature is reached. An external power MOSFET, a heater, an NTC thermistor and the ISL25700 are parts of the temperature control loop. • Coarse and fine tuning setpoint control - +15°C coarse adjustment - +0.1°C fine adjustment • ±0.5°C long-term drift error It also features programmable overcurrent protection of the MOSFET. The current protection automatically adjusts the output voltage in order to keep MOSFET power under user defined limits. The protection settings always override the temperature settings that cause violation of the current limit. • Programmable current protection of external MOSFET • 5-bit Selectable Gain Control • Wide Power Supply Range: 3V to 15V • Works with 20k to 200k External NTC Thermistor There is an additional 8-bit General Purpose DAC that is available for application specific use. • General Purpose 8-bit DAC - 0.4% Output Resolution • High Reliability - Endurance: 10,000 Data Changes per Bit per Register - Register Data Retention: 10 years @ T +125°C The ISL25700 can be used in a variety of applications where constant temperature is a key parameter. Applications • 10 Lead µTQFN 2.1mmx1.6mm Package • Oven Controlled Applications with Micro Temperature Chamber in: - Basestations - Spectrometers - Precision Meters - Precision Generators • Pb-free (RoHS Compliant) Related Literature • AN1825, “Overcoming the Minimum VDD Ramp Rate Limitation of the ISL25700” 100 TEMPERATURE (°C) 80 60 40 20 0 0 3 6 9 12 15 TIME (MINUTES) FIGURE 1. TYPICAL TEMPERATURE SETTLING TIME July 23, 2014 FN6885.1 1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-468-3774 | Copyright Intersil Americas LLC 2010, 2014. All Rights Reserved Intersil (and design) is a trademark owned by Intersil Corporation or one of its subsidiaries. All other trademarks mentioned are the property of their respective owners. ISL25700 Block Diagram/Application Circuit 3V TO 15V VDD SCL VOLATILE & NON-VOLATILE REGISTERS I2C BUS CONTROL SDA K3 R PROGRAMMABLE OVERCURRENT PROTECTION K1 8-BIT FTC DAC K2 REFERENCE GENERATOR & POWER CIRCUITRY RSENSE ISENSE C ADJUSTABLE SYSTEM LOOP GAIN VREF RTH VOUT PMOS VINT THERMISTOR RINT VREF 8-BIT GP DAC VDAC HEATER GND Submit Document Feedback 2 CCOMP FN6885.1 July 23, 2014 ISL25700 Pin Configuration ISL25700 (10 LD µTQFN) TOP VIEW 10 NC O 1 9 CCOMP SCL 2 8 ISENSE SDA 3 7 VOUT GND 4 6 VDAC 5 VDD RTH Pin Descriptions µTQFN PIN SYMBOL 1 VDD Power supply. This pins supplies the power necessary to operate the chip. 2 SCL I2C interface input clock. This input is the serial clock of the I2C serial interface. SCL requires an external pull-up resistor. It has an internal pull-down resistor of ~3MΩ to prevent a floating input if the pin will be left unconnected. 3 SDA Open Drain Serial Data Input/Output for the I2C interface. The SDA is a bidirectional serial data input/output pin for I2C interface. It receives device address, operation code and data from an I2C external master device at the rising edge of the serial clock SCL, and it shifts out data after each falling edge of the serial clock. The SDA pin requires an external pull-up resistor. It has an internal pull-down resistor of ~3MΩ to prevent a floating input if the pin will be left unconnected. 4 GND Ground. Bias and reference ground of the chip. 5 RTH External NTC thermistor. An external NTC thermistor makes one shoulder of the Wheatstone bridge and must be connected between the RTH pin and GND. 6 VDAC DAC Output. This is the output of the precision 8-bit DAC. Default DAC output is in the range of 0V to 2V. The DAC output range can be extended with a gain of 2 by setting the DAC Gain bit. 7 VOUT Output voltage that controls an external P-MOSFET. This pin drives an external P-MOSFET proportional to unbalanced condition of the Wheatstone bridge. 8 ISENSE Current Sense input. This pin monitors voltage drop over an external current sense resistor RSENSE. Power dissipation of the P-MOSFET will be limited when ISENSE exceeds the voltage drop limit set in the Current Sense Register. 9 CCOMP Compensation capacitor. A compensation ceramic capacitor must be added between CCOMP and GND to increase chip stability. This capacitor provides a negative feedback for the operational amplifier and its value can be from 30pF to 1000pF. 10 NC Submit Document Feedback DESCRIPTION Not internally connected. 3 FN6885.1 July 23, 2014 ISL25700 Ordering Information PART NUMBER (Notes 1, 2, 3) PART MARKING UNITS PER REEL TEMP RANGE (°C) PACKAGE (Pb-free) PKG. DWG. # ISL25700FRUZ-T GT 3000 -40 to +125 10 Ld 2.1x1.6 µTQFN L10.2.1x1.6A ISL25700FRUZ-TK GT 1000 -40 to +125 10 Ld 2.1x1.6 µTQFN L10.2.1x1.6A ISL25700FRUZ-T7A GT 250 -40 to +125 10 Ld 2.1x1.6 µTQFN L10.2.1x1.6A NOTES: 1. Please refer to TB347 for details on reel specifications. 2. These Intersil Pb-free plastic packaged products employ special Pb-free material sets; molding compounds/die attach materials and NiPdAu plate e4 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020. 3. For Moisture Sensitivity Level (MSL), please see device information page for ISL25700. For more information on MSL please see techbrief TB363. Submit Document Feedback 4 FN6885.1 July 23, 2014 ISL25700 Absolute Maximum Ratings Thermal Information Voltage at any Digital Interface Pin with respect to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 6V VDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +16.5V ESD Rating Human Body Model (Tested per JESD22-A114F) . . . . . . . . . . . . . . . . 5kV Machine Model (Tested per JESD22-A115B) . . . . . . . . . . . . . . . . . . 200V Latchup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Class II, Level A at +125°C Thermal Resistance (Typical) JA (°C/W) JC (°C/W) 10 Ld µTQFN Package (Note 4, 5) . . . . . . . 135 75 Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-65°C to +150°C Maximum Junction Temperature (Plastic Package) . . . . . . . . . . . .+150°C Pb-Free Reflow Profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . see link below http://www.intersil.com/pbfree/Pb-FreeReflow.asp Recommended Operating Conditions Temperature Range (Full-range Industrial) . . . . . . . . . . . . . . . . . . . -40°C to +125°C VDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3V to 15V CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and result in failures not covered by warranty. NOTES: 4. JA is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief TB379 for details. 5. For JC, the “case temp” location is taken at the package top center. Analog Specifications Over recommended operating conditions unless otherwise stated. Boldface limits apply over the operating temperature range, -40°C to +125°C. SYMBOL TSET PARAMETER Temperature Set Point MIN (Note 13) TEST CONDITIONS TSET must be above ambient TYP (Note 6) MAX (Note 13) UNITS MIN 40 °C MAX 110 °C Temperature Set Point Accuracy 3 sigma standard deviation ±3 °C TSET_COARSE Coarse Adjustment of Set Point RTH = 100k @ +25°C, B25/85 = 4100k (Note 14) 15 °C TSET_FINE Fine Adjustment of Set Point 0.1 °C TSET_FINE_INL (Note 9) Fine Control Integral Non-linearity TSET_FINE_DNL (Note 8) Fine Control Differential Non-linearity TDRIFT Long-term Drift of Set Point ITH Thermistor Current Range NTC Thermistor Range Resistance @ +25°C VOUT External P-MOSFET Gate Voltage IOUT = 0µA VOUT Swing @ Fixed VDD IOUT = 0µA IOUT Output Current Overcurrent Protection Set Point ±0.9 +2.5 LSB (Note 7) -2 ±0.5 +2 LSB (Note 7) 1000h, Reg.1 = x2h, Reg.2 = 80h, Reg.3 = 90h RTH VSENSE -2.5 ±0.5 °C 25 40 55 µA 20 100 200 kΩ VDD V 7 µA 0.25 MIN VDD - 2.5 VSENSE = ISENSE x RSENSE; see Table 3 V 200 to 1750 mV GENERAL PURPOSE DAC (MEASUREMENTS BETWEEN GND AND VDAC) VDAC MAX Maximum DAC Output Using internal VREF, VDD 5V, No load, Gain = 1 2 2.5 V VDD > 5V, No load, Gain = 2 4 5.0 V INL (Note 9) Integral Non-Linearity No load -1 ±0.4 +1 LSB (Note 7) DNL (Note 8) Differential Non-linearity No load -0.75 ±0.3 +0.75 LSB (Note 7) Submit Document Feedback 5 FN6885.1 July 23, 2014 ISL25700 Analog Specifications Over recommended operating conditions unless otherwise stated. Boldface limits apply over the operating temperature range, -40°C to +125°C. (Continued) SYMBOL PARAMETER VDAC_OFFSET Offset DAC register set to 0, No load ROUT DAC Output Impedance PSRR Power Supply Rejection Ratio Temperature Coefficient TCV (Notes 10, 11) TEST CONDITIONS MIN (Note 13) TYP (Note 6) MAX (Note 13) 0 0.2 1 UNITS LSB (Note 7) 350 Ω DAC at middle scale, frequency from 0Hz to 25kHz -85 dB DAC register set between 20 hex and FF hex ±45 ppm/°C Operating Specifications Over the recommended operating conditions unless otherwise specified. Boldface limits apply over the operating temperature range, -40°C to +125°C. SYMBOL PARAMETER TEST CONDITIONS IDD1 VDD Supply Current (Non-Volatile Write/read) fSCL = 400kHz; SDA = Open; (for I2C, Active, Read and Write States) IPMOS = 0mA, DAC unload IDD2 VDD Supply Current (Volatile Write/read) IPMOS = 0mA, DAC unload Leakage Current, at SDA and SCL Pins Voltage at pin from GND to VCC DAC Settling Time From bus STOP condition to VDAC change ILkgDig tDAC (Note 11) Power-On Recall Voltage Minimum VDD at which memory recall occurs VDD Ramp VDD Ramp Rate @ any level from 0V to 15V tD (Note 11) Power-Up Delay VDD above VPOR, to DAC Register recall completed, and I2C Interface in standby state VPOR MIN (Note 13) TYP (Note 6) -3 2.5 0.2 MAX (Note 13) UNITS 4 mA 2.8 mA 3 µA 3 µs 2.9 V 50 V/ms 1 ms EEPROM SPECIFICATIONS EEPROM Endurance EEPROM Retention 10,000 Cycles Temperature +55°C 50 Years Temperature +125°C 10 Years 2.7 SERIAL INTERFACE SPECIFICATIONS VI2C I2C Bus Voltage VI2C VDD VIL SDA, and SCL Input Buffer LOW Voltage VI2C from 2.7V to 5.5V VIH SDA, and SCL Input Buffer HIGH Voltage VI2C from 2.7V to 5.5V Hysteresis (Note 11) SDA and SCL Input Buffer Hysteresis VOL (Note 11) SDA Output Buffer LOW Voltage, Sinking 4mA Cpin (Note 11) fSCL 5.5 V 0.8 V 1.4 V 0.05*VI2C V 0 0.4 V SDA, and SCL Pin Capacitance 10 pF SCL Frequency 400 kHz 50 ns 900 ns tIN (Note 11) Pulse Width Suppression Time at SDA and SCL Inputs tAA (Note 11) SCL Falling Edge to SDA Output Data SCL falling edge crossing 30% of VI2C, until SDA exits the 30% to 70% of VI2C window Valid Submit Document Feedback 6 Any pulse narrower than the max spec is suppressed FN6885.1 July 23, 2014 ISL25700 Operating Specifications Over the recommended operating conditions unless otherwise specified. Boldface limits apply over the operating temperature range, -40°C to +125°C. (Continued) SYMBOL PARAMETER TEST CONDITIONS MIN (Note 13) TYP (Note 6) MAX (Note 13) UNITS Time the Bus Must be Free Before the Start of a New Transmission SDA crossing 70% of VI2C during a STOP condition, to SDA crossing 70% of VI2C during the following START condition 1300 ns tLOW Clock LOW Time Measured at the 30% of VI2C crossing 1300 ns tHIGH Clock HIGH Time Measured at the 70% of VI2C crossing 600 ns tSU:STA START Condition Setup Time SCL rising edge to SDA falling edge. Both crossing 70% of VI2C 600 ns tHD:STA START Condition Hold Time From SDA falling edge crossing 30% of VI2C to SCL falling edge crossing 70% of VI2C 600 ns tSU:DAT Input Data Setup Time From SDA exiting the 30% to 70% of VI2C window, to SCL rising edge crossing 30% of VI2C 100 ns tHD:DAT Input Data Hold Time From SCL falling edge crossing 70% of VI2C to SDA entering the 30% to 70% of VI2C window 0 ns tSU:STO STOP Condition Setup Time From SCL rising edge crossing 70% of VI2C, to SDA rising edge crossing 30% of VI2C 600 ns tDH Output Data Hold Time From SCL falling edge crossing 30% of VI2C, until SDA enters the 30% to 70% of VI2C window 0 ns tR SDA and SCL Rise Time From 30% to 70% of VI2C 20 + 0.1 * Cb 250 ns tF SDA and SCL Fall Time From 70% to 30% of VI2C 20 + 0.1 * Cb 250 ns Capacitive Loading of SDA or SCL Total on-chip and off-chip 10 400 SDA and SCL Bus Pull-Up Resistor Off-Chip Maximum is determined by tR and tF. For Cb = 400pF, max is about 2~2.5k. For Cb = 40pF, max is about 15~20k 1 tBUF (Note 11) Cb Rpu (Note 11) tWC (Notes 11, 12) Non-Volatile Write Cycle Time pF k 15 20 ms NOTES: 6. Typical values are for TA = +25°C and 12V supply voltage. 7. LSB: [VDAC255 – VDAC0]/255. VDAC255 and VDAC0 are the DAC output voltage when DAC register set to FF hex and 00 hex respectively. 8. DNL = [VDACi – VDACi-1]/LSB-1, for i = 1 to 255. i is the DAC register setting. 9. INL = [VDACi – (i • LSB + VDAC0)]/LSB for i = 1 to 255. VDAC i T – VDAC i 40°C 10 6 TC V = ------------------------------------------------------------------------- --------------------------- T – 40 °C for i = 1 to 255 decimal, T = -40°C to +125°C, referenced to 40°C. VDAC i 40°C 10. 11. Limits established by characterization and are not production tested. 12. tWC is the time from a valid STOP condition at the end of a Write sequence of a I2C serial interface Write operation, to the end of the self-timed internal non-volatile write cycle. The Busy Polling method can be used to determine the end of the non-volatile write cycle. 13. Parameters with MIN and/or MAX limits are 100% tested at +25°C, unless otherwise specified. Temperature limits established by characterization and are not production tested. 14. B25/85 is a thermistor material specific constant; represents the slope of the Resistance vs. Temperature curve. Submit Document Feedback 7 FN6885.1 July 23, 2014 ISL25700 SDA vs SCL Timing tHIGH tF SCL tLOW tR tWC tSU:DAT tSU:STA tHD:DAT tHD:STA SDA (INPUT TIMING) tSU:STO tAA tDH tBUF SDA (OUTPUT TIMING) Typical Performance Curves 2.5 VDD = 12V VDD = 15V MEASURED AT RT PIN CCOMP = 10nF AFTER 10 MIN SETTLING TIME MARKER = 14.6µV/√Hz 2.0 15 1.0 0.5 0.0 -40 NOISE (µV/√Hz) IDD (mA) 1.5 VDD = 5V VDD = 3V -20 0 20 40 60 80 100 120 10 5 0 0.1 1.0 FREQUENCY (Hz) 10 100 TEMPERATURE (°C) FIGURE 2. SUPPLY CURRENT IDD vs VDD FIGURE 3. NOISE LEVEL AT RTH INPUT IN CLOSE LOOP APPLICATION 2µV/√Hz @ 1Hz VDD = 12V VOUT VDAC 0.5ms/DIVISION FIGURE 4. VOUT POWER-UP DELAY Submit Document Feedback 8 0.5µs/DIVISION FIGURE 5. GP DAC SETTLING TIME (FULL SCALE, GAIN = 2) FN6885.1 July 23, 2014 ISL25700 Typical Performance Curves 0.2 (Continued) 0.2 GAIN = 1 0.1 0.0 0.0 DNL (LSB) DNL (LSB) GAIN = 1 0.1 -0.1 -0.2 -0.1 -0.2 GAIN = 2 -0.3 0 50 100 150 200 -0.3 250 0 50 CODE (DECIMAL) 100 150 250 FIGURE 7. GP DAC DNL vs CODE VDD = 5V FIGURE 6. GP DAC DNL vs CODE VDD = 3V 0.5 0.2 GAIN = 1 GAIN = 1 0.1 0.3 0 0.1 INL (LSB) DNL (LSB) 200 CODE (DECIMAL) -0.1 -0.1 -0.3 -0.2 GAIN = 2 -0.3 0 50 100 150 200 -0.5 0 250 50 CODE (DECIMAL) 100 FIGURE 8. GP DAC DNL vs CODE VDD = 15V 250 0.5 0.3 0.3 GAIN = 1 GAIN = 1 0.1 INL (LSB) INL (LSB) 200 FIGURE 9. GP DAC INL vs CODE VDD = 3V 0.5 -0.1 -0.3 -0.5 0 150 CODE (DECIMAL) 100 150 200 CODE (DECIMAL) FIGURE 10. GP DAC INL vs CODE VDD = 5V Submit Document Feedback 9 -0.1 -0.3 GAIN = 2 50 0.1 GAIN = 2 250 -0.5 0 50 100 150 200 250 CODE (DECIMAL) FIGURE 11. GP DAC INL vs CODE VDD = 15V FN6885.1 July 23, 2014 ISL25700 Typical Performance Curves (Continued) 0.5 GAIN ERROR (%) 0.3 0.1 VDD = 15V VDD = 5V -0.1 -0.3 -0.5 5 55 105 155 205 255 CODE (DECIMAL) FIGURE 12. GP DAC GAIN ERROR Principles of Operation The ISL25700 allows for precisely controlling the temperature of an external object and/or power dissipation of the external P-MOSFET. The temperature control is done by continuously sensing resistance of the NTC thermistor, and adjusting the current flow through the P-MOSFET (temperature controlling element). ISL25700 drives the P-MOSFET proportionally inverted to the difference between the object temperature and target temperature set point (TSET), set by the user through the I2C serial interface. Temperature is sensed by the external NTC thermistor and converted to a driving voltage by the Wheatstone bridge and its amplifier. One leg of the currentmode Wheatstone bridge contains an external NTC thermistor with the programmable 8-bit FTC DAC and another leg contains the selectable current source k1 that feeds an internal resistor RINT. The 8-bit FTC DAC allows fine-tuning the TSET with resolution better than +0.1°C within a +15°C coarse temperature range window. The TSET temperature is set through the Temperature Coarse Range Control Register, Reg.01h[2:0], and the Fine Temperature Control Register, Reg.02h[7:0]; refer to “ISL25700 MEMORY MAP” on page 11. A +15°C temperature coarse range window can be centered on TSET point based on the thermistor’s parameters, such as resistance, R/T curve type, tolerance and NTC slope and by adjusting a current ratio flowing through the legs of the Wheatstone bridge. Note that the TSET target temperature should be higher than the anticipated maximum ambient temperature for the application. current sensing resistor RSENSE, serial with the P-MOSFET, is required. A current limit can be selected for the chosen RSENSE. It should have an effective voltage drop from 200mV to 1750mV and be inside the safe operating area of the MOSFET. A General Purpose 8-bit DAC, GP DAC provides a programmable voltage output VDAC through the General Purpose DAC Register, Reg.04h[7:0]. The output swing of General Purpose DAC can be set through the Gain Control bit in Reg.03h[6] or totally disabled by resetting the DAC Enable Bit in Reg.03h[7]. Memory Map The are two types of memory banks in the chip; volatile (RAM) and non-volatile (EEPROM). Volatile registers from address 00h to 07h are identical to non-volatile registers in terms of the register’s name and bit definitions. All the data is recalled from non-volatile registers and maintained in the volatile registers at power-up. It is possible to do independent write/read to the volatile and non-volatile banks after power-up by setting NV bit in the Control/Status Register, Reg.08h[7]. Note that the data written to the non-volatile registers will be automatically written to corresponding volatile registers, however no direct reading from non-volatile registers is possible. All the readings are from corresponding volatile registers. The Memory Map of the chip is in Table 1. There are total of 32 system gain settings available in the Gain Control Register, Reg.03h[4:0], with 0.35dB resolution per step. The gain control allows to prevent the thermal system from oscillation by adjusting the total system gain remotely, without use of external components. The internal current sensing circuitry provides the ability to control and adjust the power dissipated in the P-MOSFET through the Current Sense Register, Reg.01h[7:3]. This function allows for adjusting the initial turn on heating curve and protects from over-heating of the P-MOSFET. An external Submit Document Feedback 10 FN6885.1 July 23, 2014 ISL25700 TABLE 1. ISL25700 MEMORY MAP BIT MAP REGISTER ADDRESS 7 6 5 4 3 2 1 0 DEFAULT SETTINGS Device ID (Read Only) 00h ID[7] ID[6] ID[5] ID[4] ID[3] ID[2] ID[1] ID[0] 00h Current Sense/ Coarse Temperature Control 01h CS[4] CS[3] CS[2] CS[1] CS[0] CTC[2] CTC[1] CTC[0] 03h Fine Temperature Control 02h FTC[7] FTC[6] FTC[5] FTC[4] FTC[3] FTC[2] FTC[1] FTC[0] 80h Gain Control (DAC Enable/ DAC Gain/System Loop Gain) 03h DAC Enable DAC Gain NA SLG[4] SLG[3] SLG[2] SLG[1] SLG[0] 90h General Purpose DAC 04h DAC[7] DAC[6] DAC[5] DAC[4] DAC[3] DAC[2] DAC[1] DAC[0] 80h General Purpose Register 1 05h GP1[7] GP1[6] GP1[5] GP1[4] GP1[3] GP1[2] GP1[1] GP1[0] 00h General Purpose Register 2 06h GP2[7] GP2[6] GP2[5] GP2[4] GP2[3] GP2[2] GP2[1] GP2[0] 00h RINT Absolute Error (Read Only) 07h sign bit ERR[6] ERR[5] ERR[4] ERR[3] ERR[2] ERR[1] ERR[0] XX Control/Status Register (Volatile Only) 08h NV NA NA NA NA NA NA BUSY 00h REGISTER NAME –6 Device ID Register (Reg.00h) = 5 10 - 2nd order temperature coefficient, ppm/°C2; This is a read only register. It contains device ID code 00h. T - temperature in Celsius. Coarse Temperature Control (Reg.01h [2:0]) The k1, k2 and k3 coefficients and the thermistor value range for each Coarse Temperature setting in Reg.01h[2:0] should be taken according to Table 2. These 3 bits allow one to choose one of the seven coarse windows for the temperature set point. The default set point is about +59°C for the 100k RTH thermistor with a temperature coefficient of -4.25%/°C at +25°C, i.e. Reg.01h[2:0] = 011b. The temperature set point can be changed to any other set point within an operational range from +40°C to +110°C, or use another type of thermistor, including different resistance value or R/T curve type (NTC slope), and then center the +15°C coarse range temperature window on that new setting based on the ratio of RINT/RTH according to Equation 1: Code K2 + K3 --------------R INT T 255 ---------------------------------------- = -------------------------------------------R TH setpoint K1 (EQ. 1) where: RINT - is an internal 9kΩ resistor, forming another leg of the Wheatstone Bridge; k1, k2 and k3 - are coefficients representing the ratio of the current flowing through the legs of the Wheatstone Bridge; Code - is the decimal code in the Fine Temperature Control register 02h. The value of internal resistor RINT can vary from part to part and depends on the package temperature. The actual RINT at temperature T can be calculated using Equation 2: R INT T = R INT 25 x 1 + T – 25 + T – 25 2 TABLE 2. COARSE TEMPERATURE RANGE Register 01h[2:0] k1 k2 000 k3 THERMISTOR RESISTANCE RANGE AT SET POINT (kΩ) Do not use 001 3 3 2 5.4 to 9.0 010 4 3 2 7.2 to 12.0 100 5 3 2 9.0 to 15.0 011 7 3 2 12.6 to 21.0 101 8 3 2 14.4 to 24.0 110 9 3 2 16.2 to 27.0 111 12 3 2 21.6 to 36.0 Current Sense Threshold (Reg.01h [7:3]) This register sets the current limit trip point. When the voltage applied to the ISENSE pin falls below the programmed voltage threshold, VOUT goes high, thus forming a negative feedback loop proportional to ISENSE x RSENSE. The value for this register should be taken according to Table 3. (EQ. 2) where: RINT(25) = 9000 + RINT abs. error x 15 - is internal resistor value at +25°C in Ohms; RINT abs. error - is a signed integer value of absolute error stored in Reg.07h[7:0] converted to a decimal number; bit [7] represents a sign bit, 0 for “+” and 1 for “-”; –6 = – 1337 10 - 1st order temperature coefficient, ppm/°C; Submit Document Feedback 11 FN6885.1 July 23, 2014 ISL25700 System Loop Gain (Reg.03h [4:0]) TABLE 3. CURRENT SENSE THRESHOLD This 5 bits allow one to adjust a total system loop gain in ±0.35dB per step, according to Table 4. Register 01h[7:3] Value SENSE RESISTOR VOLTAGE DROP THRESHOLD VDD - (ISENSE X RSENSE) VDD = 3V VDD = 15V 00000 VDD - 200mV ±5 +20 00001 VDD - 250mV ±5 +20 00010 VDD - 300mV ±5 +20 00011 VDD - 350mV ±5 +20 Reg.03h[4:0] LOOP GAIN ADJUSTMENT (dB) 00100 VDD - 400mV ±5 +20 00000 -5.60 00101 VDD - 450mV ±5 +20 00001 -5.25 00110 VDD - 500mV ±5 +20 00010 -4.90 00111 VDD - 550mV ±5 +20 00011 -4.55 01000 VDD - 600mV ±5 +20 00100 -4.20 01001 VDD - 650mV ±5 +20 00101 -3.85 01010 VDD - 700mV ±5 +20 00110 -3.50 01011 VDD - 750mV ±5 +20 00111 -3.15 01100 VDD - 800mV ±5 +20 01000 -2.80 01101 VDD - 850mV ±5 +20 01001 -2.45 01110 VDD - 900mV ±5 +20 01010 -2.10 01111 VDD - 950mV ±5 +20 01011 -1.75 10000 VDD - 1000mV ±5 +20 01100 -1.40 10001 VDD - 1050mV ±5 +20 01101 -1.05 10010 VDD - 1100mV ±5 +20 01110 -0.70 10011 VDD - 1150mV ±5 +20 01111 -0.35 10100 VDD - 1200mV ±5 +20 10000 Initial Gain (default) 10101 VDD - 1250mV ±5 +20 10001 0.35 10110 VDD - 1300mV ±5 +20 10010 0.70 10111 VDD - 1350mV ±5 +20 10011 1.05 11000 VDD - 1400mV ±5 +20 10100 1.40 11001 VDD - 1450mV ±5 +20 10101 1.75 11010 VDD - 1500mV ±5 +20 10110 2.10 11011 VDD - 1550mV ±5 +20 10111 2.45 11100 VDD - 1600mV ±5 +20 11000 2.80 11101 VDD - 1650mV ±5 +20 11001 3.15 11110 VDD - 1700mV ±5 +20 11010 3.50 11111 VDD - 1750mV ±5 +20 11011 3.85 11100 4.20 11101 4.55 11110 4.90 11111 5.25 TYPICAL ERROR (%) Fine Temperature Control Register (Reg.02h [7:0]) This register allows fine tuning to the final temperature TSET within the predetermined range set in Reg.01h[2:0] by choosing appropriate code for the 8-bit FTC DAC. The final temperature can be adjusted with approximately +0.07°C increment/decrement resolution per step. Submit Document Feedback 12 The default system loop gain depends on the MOSFET type, thermal conductivity and level of insulation from the ambient temperature. TABLE 4. SYSTEM LOOP GAIN ADJUSTMENT FN6885.1 July 23, 2014 ISL25700 DAC Enable and Gain Control (Reg.03h [7:6]) When the DAC Enable bit, Reg.03h[7], is 0, the DAC output is disabled, regardless of Reg.04h settings. When DAC Enable bit is 1, the DAC output depends on the settings of the DAC Gain bit Reg.03[6] and Reg.04h[7:0]. When the DAC Gain bit, Reg.03h[6], is 0, the DAC output range is from 0V to 2V, i.e. Gain = 1. When the DAC Gain bit is 1, the DAC output range is from 0V to 4V, i.e. Gain = 2. General Purpose DAC Register (Reg.04h [7:0]) This 8-bit register writes directly to the GP DAC to set the output voltage. The default setting of this register is 80h. The DAC output depends on the Gain setting in Reg.03h[6]. General Purpose Registers (Reg.05h and Reg.06h) These 8-bit General Purpose non-volatile and volatile registers can be used for application specific purposes. For example, they can be used to store calibration data or other valuable system information. RINT Absolute Error Register (Reg.07h [7:0]) This register contains the difference between the nominal value and the real value of the internal resistor RINT. The nominal value of this resistor is 9k and the voltage drop on this resistor represents the temperature setpoint. The LSB weight of the RINT absolute error is 15Ω. Refer to Equation 2 for calculation of RINT. Control/Status Register (Reg.08h [7:0]) The setting of the NV bit, Reg.08h[7], determines if data is to be read or written to the non-volatile and/or volatile memory. When this bit is 0, all operation will be targeted to non-volatile memory, and the data will be copied to volatile memory simultaneously. When this bit is 1, all operation will be targeted to the volatile memory only. The default setting of the NV bit is 0. The Busy bit, Reg.08h[0], is a read only bit. When “1” is read from this bit, it indicates that the non-volatile cycle is in progress. Reading from this bit eliminates getting a NACK if the host attempts to write to the non-volatile memory before the previous data is stored. I2C Serial Interface The ISL25700 supports a bidirectional bus oriented protocol. The protocol defines any device that sends data onto the bus as a transmitter and the receiving device as the receiver. The device controlling the transfer is a master and the device being controlled is the slave. The master always initiates data transfers and provides the clock for both transmit and receive operations. Therefore, the ISL25700 operates as a slave device in all applications. All communication over the I2C interface is conducted by sending the MSB of each byte of data first. Protocol Conventions indicating START and STOP conditions (see Figure 13). On power-up of the ISL25700, the SDA pin is in the input mode. All I2C interface operations must begin with a START condition, which is a HIGH to LOW transition of SDA while SCL is HIGH. The ISL25700 continuously monitors the SDA and SCL lines for the START condition and does not respond to any command until this condition is met (see Figure 13). A START condition is ignored during the power-up sequence and during internal non-volatile write cycles. All I2C interface operations must be terminated by a STOP condition, which is a LOW to HIGH transition of SDA while SCL is HIGH (see Figure 13). A STOP condition at the end of a read operation, or at the end of a write operation to volatile bytes, only places the device in its standby mode. A STOP condition during a write operation to a non-volatile byte initiates an internal nonvolatile write cycle. The device enters its standby state when the internal non-volatile write cycle is completed. An ACK, Acknowledge, is a software convention used to indicate a successful data transfer. The transmitting device, either master or slave, releases the SDA bus after transmitting 8 bits. During the ninth clock cycle, the receiver pulls the SDA line LOW to acknowledge the reception of the 8 bits of data (see Figure 14). The ISL25700 responds with an ACK after recognition of a START condition, followed by a valid Identification Byte, and once again after successful receipt of an Address Byte. The ISL25700 also responds with an ACK after receiving a Data Byte of a write operation. The master must respond with an ACK after receiving a Data Byte of a read operation. A valid Identification Byte contains 0101000 in seven MSBs. The LSB is the Read/Write bit. Its value is “1” for a Read operation and “0” for a Write operation (see Table 5). TABLE 5. IDENTIFICATION BYTE FORMAT 0 1 0 1 (MSB) 0 0 0 R/W (LSB) Write Operation A Write operation requires a START condition, followed by a valid Identification Byte, a valid Address Byte, a Data Byte, and a STOP condition. After each of the three bytes, the ISL25700 responds with an ACK. At this time, if the Data Byte is to be written only to volatile registers, then the device enters its standby state. If the Data Byte is to be written also to non-volatile memory, the ISL25700 begins its internal write cycle to non-volatile memory. During the internal nonvolatile write cycle, the device ignores transitions at the SDA and SCL pins, and the SDA output is at a high impedance state. When the internal non-volatile write cycle is completed, the ISL25700 enters its standby state (see Figure 14). The byte at address 08h determines if the Data Byte is to be written to volatile and/or non-volatile memory (see “Memory Map” on page 10). A 20ms delay is required between two consecutive writes to the non-volatile registers. Data states on the SDA line can change only during SCL LOW periods. The SDA state changes during SCL HIGH are reserved for Submit Document Feedback 13 FN6885.1 July 23, 2014 ISL25700 SCL SDA START DATA STABLE DATA CHANGE DATA STABLE STOP FIGURE 13. VALID DATA CHANGES, START, AND STOP CONDITIONS SCL FROM MASTER 1 8 9 SDA OUTPUT FROM TRANSMITTER HIGH IMPEDANCE HIGH IMPEDANCE SDA OUTPUT FROM RECEIVER START ACK FIGURE 14. ACKNOWLEDGE RESPONSE FROM RECEIVER WRITE SIGNALS FROM THE MASTER SIGNAL AT SDA S T A IDENTIFICATION R BYTE T ADDRESS BYTE 0 1 0 1 0 0 0 0 SIGNALS FROM THE ISL25700 S T O P DATA BYTE 0 0 0 0 A C K A C K A C K FIGURE 15. BYTE WRITE SEQUENCE SIGNALS FROM THE MASTER S T A IDENTIFICATION R BYTE WITH T R/W = 0 SIGNAL AT SDA 0 1 0 1 0 0 0 0 ADDRESS BYTE READ A C K S T O P A C K 0 1 0 1 0 0 0 1 0 0 0 0 A C K SIGNALS FROM THE SLAVE S T A IDENTIFICATIO R N BYTE WITH T R/W = 1 A C K A C K FIRST READ DATA BYTE LAST READ DATA BYTE FIGURE 16. READ SEQUENCE Submit Document Feedback 14 FN6885.1 July 23, 2014 ISL25700 Polling Method Current Sense Resistor and MOSFET Selection It is possible to check if the non-volatile memory write cycle is finished or is in progress by polling (reading) the BUSY bit in Control/Status Register, Reg.08h[0] (see “Control/Status Register (Reg.08h [7:0])” on page 13). The non-volatile write cycle is in progress when the BUSY bit is 1. No other write attempt is allowed when the BUSY bit is 1. The non-volatile write cycle is finished when the BUSY bit is 0. The current sense resistor should be selected with consideration of system maximum power consumption, maximum current, and minimum resolution. It is recommended to select a current sense resistor in the range from 0.1Ω to 10Ω. The 0.1Ω resistor allows sensing and will limit the maximum current from 2A to 17.5A, while a 10Ω resistor allows selecting a current limit from 20mA to 175mA. The type and size of current sense resistor should have an appropriate power rating. Read Operation A Read operation consists of a three byte instruction followed by one or more Data Bytes (see Figure 16). The master initiates the operation issuing the following sequence: a START, the Identification byte with the R/W bit set to “0”, an Address Byte, a second START, and a second Identification byte with the R/W bit set to “1”. After each of the three bytes, the ISL25700 responds with an ACK. Then the ISL25700 then transmits the Data Byte. The master then terminates the read operation (issuing a STOP condition) following the last bit of the Data Byte (see Figure 16). The byte at address 08h determines if the Data Bytes being read are from volatile or non-volatile memory (see “Memory Map” on page 10). Application Information In order to get the correct temperature setting, it is very important to chose an appropriate thermistor and calibrate the complete system. The following sequence describes the thermistor selection and calibration procedure. 1. Select a thermistor type and get the RT curve from manufacturer. 2. Find out a thermistor resistance at the desired temperature and select the coarse temperature range from Table 2. The thermistor value at set point should be in the middle of the coarse range. Note, the coarse ranges overlap. 3. Set the Current Sense limit in Reg.01h[7:3] and System Loop Gain in Reg. 03h[4:0] as high as possible to enable fast settling yet prevent thermal oscillation. The ISL25700 will work only with the P-type of power MOSFETs or Darlington pair. Since the driving capability is limited, it is not recommended to drive a bipolar transistor. The power MOSFET can be used as a heater inside a micro temperature chamber. System Loop Gain Setting Assemble the application circuit including ISL25700, the power MOSFET, heating element and thermistor. The System Loop Gain allows controlling thermal stability of the feedback system. In other words, current through the power MOSFET should settle fast and without oscillation when setpoint changes from one temperature to another. Settling time of the current can be monitored by oscilloscope with the current probe. Another way to determine system stability is to obtain a phase margin of the system by analyzing Bode plots. Bode plots of the gain and phase margins can be obtained by disconnecting the thermistor from RTH - breaking the loop, and connecting a low frequency signal analyzer between the RTH pin and the thermistor. That will allow analysis of the system transfer function vs. frequency. Note the thermistor has to be biased with 30µA DC current from an external supply. The signal analyzer sweeps the frequency at input node (RTH) and measures the phase change of the output node (thermistor). As a rule of thumb, phase margin should be at least 45° when the system gain reaches 0dB. It is not recommended to change the system loop gain when it is determined. 4. Perform system calibration and fine tuning using an external temperature sensor. Thermistor Selection Chose the thermistor whose resistance at the desired temperature set point TSET will be within the range specified in Table 2. The R/T characteristics of the thermistor are usually provided by the manufacturer as a table or as a curve. For example, you are going to stabilize the temperature at TSET = +91.5°C. You decided to use a 100k NTC thermistor from Vishay, NTCS0805E3104FXT. The resistance at +91.5°C will be 8109.12Ω, according to the manufacturer data provided online at http://www.vishay.com/doc?29100. This resistance fits in the coarse temperature range settings of 001b or 002b, as per Table 2. Submit Document Feedback 15 FN6885.1 July 23, 2014 ISL25700 Calibration Procedure Power-up the circuit and program Reg.01h[2:0] = 001b of ISL25700. Use an externally calibrated temperature sensor to measure the temperature of the thermistor. When the thermistor temperature is stabilized, it can be adjusted to the desired point by changing the Fine Temperature Control settings in Reg.02h[7:0] until the external thermometer indicates +91.5°C (for this example). The decimal FTC code can be calculated by solving for Equations 1 and 2 as follows: K1 R INT T – K2 R TH T Code = ----------------------------------------------------------------------------- 255 K3 R TH T (EQ. 3) Note, the final application system temperature depends on the allowed power consumption and the level of insulation from the ambient temperature. Two different calibration point settings can be stored in General Purpose non-volatile registers. More calibrated temperature points can be stored and used as a look-up table in an external memory. Placement and Layout Consideration It is recommended to place the ISL25700 and thermistor as close as possible to each other, inside the insulated area to achieve higher accuracy and keep the ground trace between the thermistor and the device as short as possible. The device ground pin and the system ground should be connected at a single point, known as the “single point ground”, preventing picking up the common ground noise into the RTH feedback pin. The ISL25700 also can be placed outside of the insulated area and far away from the thermistor, but the setpoint accuracy will decrease, due to the wide ambient temperature range. It is recommended to use a look-up table based on Equation 2 to compensate for the setpoint shift. Put a 1µF capacitor in parallel with 0.1µF decoupling capacitor close to the VDD pin. It is recommended to have a pull-up resistor of 500k or higher, or a high-pass RC filter, as shown in the “Block Diagram/Application Circuit” on page 2, to the gate of a P-MOSFET in order to prevent a high current spike through the MOSFET at power-up. The time constant of the high-pass filter should be in the range of 1µs to 20µs. Submit Document Feedback 16 FN6885.1 July 23, 2014 ISL25700 Revision History The revision history provided is for informational purposes only and is believed to be accurate, but not warranted. Please go to web to make sure you have the latest Rev. DATE REVISION CHANGE July 23, 2014 FN6885.1 Added Related Literature on page 1. Operating Specification table on “Voltage at pin from GND to VCC” on page 6: Changed the value for Min from -2 to -3 and Max from 2 to 3. September 3, 2010 FN6885.0 Initial release. About Intersil Intersil Corporation is a leading provider of innovative power management and precision analog solutions. The company's products address some of the largest markets within the industrial and infrastructure, mobile computing and high-end consumer markets. For the most updated datasheet, application notes, related documentation and related parts, please see the respective product information page found at www.intersil.com. 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No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com Submit Document Feedback 17 FN6885.1 July 23, 2014 ISL25700 Package Outline Drawing L10.2.1x1.6A 10 LEAD ULTRA THIN QUAD FLAT NO-LEAD PLASTIC PACKAGE Rev 5, 3/10 8. PIN 1 INDEX AREA 2.10 A B PIN #1 ID 1 0.05 MIN. 1 8. 4 4X 0.20 MIN. 1.60 0.10 MIN. 10 5 0.80 10X 0.40 0.10 6 9 2X 6X 0.50 10 X 0.20 4 TOP VIEW 0.10 M C A B M C BOTTOM VIEW (10 X 0.20) SEE DETAIL "X" (0.05 MIN) PACKAGE OUTLINE 1 MAX. 0.55 0.10 C (10X 0.60) C (0.10 MIN.) (2.00) SEATING PLANE 0.08 C SIDE VIEW (0.80) (1.30) C 0 . 125 REF (6X 0.50 ) (2.50) 0-0.05 TYPICAL RECOMMENDED LAND PATTERN DETAIL "X" NOTES: Submit Document Feedback 18 1. Dimensioning and tolerancing conform to ASME Y14.5M-1994. 2. All Dimensions are in millimeters. Angles are in degrees. Dimensions in ( ) for Reference Only. 3. Unless otherwise specified, tolerance : Decimal ± 0.05 4. Lead width dimension applies to the metallized terminal and is measured between 0.15mm and 0.30mm from the terminal tip. 5. Maximum package warpage is 0.05mm. 6. Maximum allowable burrs is 0.076mm in all directions. 7. Same as JEDEC MO-255UABD except: No lead-pull-back, MIN. Package thickness = 0.45 not 0.50mm Lead Length dim. = 0.45mm max. not 0.42mm. 8. The configuration of the pin #1 identifier is optional, but must be located within the zone indicated. The pin #1 identifier may be either a mold or mark feature. FN6885.1 July 23, 2014