Application Note 1145 Author: Daniel Goodhew A Compendium of Application Circuits for Intersil Digitally-Controlled (XDCP) Potentiometers Introduction This application note lists a number of application circuits for Intersil’s digitally-controlled (XDCP) potentiometers. The application circuits illustrate the wide variety of possible functions which can be implemented using the variability of the potentiometer in conjunction with standard active devices like operational amplifiers and comparators. The types of circuits include control circuits, converters, filters, signal processing circuits, regulators, wave shapers, analog computing circuits and signal sources. The circuits are shown in basic form and do not include supply decoupling or proper grounding techniques. The user must account for these in the final design. Electronic digitally-controlled (XDCP) potentiometers provide three powerful application advantages: 1. The variability and reliability of a solid-state potentiometer. 2. The flexibility of computer-based digital controls. 3. The retentivity of nonvolatile memory used for the storage of multiple potentiometer settings or data. In addition, the packages of the potentiometers are completely compatible with other electronic components and hence reduce manufacturing assembly costs. Intersil’s potentiometers are controlled through the 2-wire, I2C, 3-wire, or SPI computer serial-interfaces or buses. For front panel, push button type applications, Intersil’s push pots are recommended. Applications VR VR VW I THREE TERMINAL POTENTIOMETER; VARIABLE VOLTAGE DIVIDER TWO TERMINAL VARIABLE RESISTOR; VARIABLE CURRENT FIGURE 1. BASIC CONFIGURATIONS OF ELECTRONIC POTENTIOMETERS January 9, 2013 AN1145.1 1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. Copyright Intersil Americas Inc. 2013. All Rights Reserved. 1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a trademark owned by Intersil Corporation or one of its subsidiaries. All other trademarks mentioned are the property of their respective owners. Application Note 1145 Application Circuits +V +V R1 +V +5V VW VREF ISL28177 + VOUT – X VW +V –5V VW VOUT = VW (a) FIGURE 3. CASCADING TECHNIQUES FIGURE 2. BUFFERED REFERENCE VOLTAGE VS (b) ISL28110 + VIN VO – VO (REG) 317 R1 R2 Iadj R1 R2 VO = (1+R2/R1)VS VO (REG) = 1.25V (1+R2/R1)+Iadj R2 FIGURE 4. NONINVERTING AMPLIFIER FIGURE 5. VOLTAGE REGULATOR +5V R1 R2 VS VS 2.2kΩ ISL28915 – 100kΩ + – VO VO + ISL28110 +12V 10kΩ -12V FIGURE 6. OFFSET VOLTAGE ADJUSTMENT 2 } 10kΩ } 10kΩ R1 R2 VUL = {R1/(R1+R2)} VO(MAX) VLL = {R1/(R1+R2)} VO(MIN) FIGURE 7. COMPARATOR WITH HYSTERISIS AN1145.1 January 9, 2013 Application Note 1145 Application Circuits (Continued) C VS + VO R2 R1 – – VS R VO + ISL28108 R3 R4 R2 R1 = R 3 = R4 R1 R2 = 2R1 GO = 1 + R2/R1 fc = 1/(2πRC) V O = G VS -1/2 ≤ G ≤ +1/2 FIGURE 8. ATTENUATOR FIGURE 9. FILTER R2 C1 R2 VS } } R1 ISL28117 VS ISL28117 + – – VO + R1 ZIN ISL28107 R3 ZIN = R2 + s R2 (R1 + R3) C1 = R2 + s Leq (R1 + R3) >> R2 VO = G VS G = - R2/R1 FIGURE 10. INVERTING AMPLIFIER FIGURE 11. EQUIVALENT L-R CIRCUIT C R2 – R1 – + ISL28217 } RA + ISL28217 } RB FREQUENCY ∝ R1, R2, C AMPLITUDE ∝ RA, RB FIGURE 12. FUNCTION GENERATOR 3 AN1145.1 January 9, 2013 Application Note 1145 Application Circuits (Continued) R1 R1 R3 VR R2 R1 + R1 – VO + IS IS R – ISL28110 RL ISL28210 R1 + – VO / IS = -R3(1+R2/R1) + R2 IS = VR/R FIGURE 13. I TO V CONVERTER FIGURE 14. CURRENT SOURCE R1 VS ISL28217 R1 – + C – + – VO R2 R1 + ISL28217 C ISL28110 R Cin CIN = C (1 + R2/R1) VO/VS = 180° – 2tan-1ω RC FIGURE 15. PHASE SHIFTER FIGURE 16. CAPACITANCEV MULTIPLIER 2R VS R R R R1 – – + + VO A2 ISL28217 A1 ISL28217 VO = |VS| R1 R FIGURE 17. ABSOLUTE VALUE AMPLIFIER WITH GAIN 4 AN1145.1 January 9, 2013 Application Note 1145 Application Circuits (Continued) VREFERENCE (VR) + VS ISL28108 } R2 } R1 – VH ISL28108 VW VOUT – + VOUT + + VR VL + VTRANSDUCER (VT) VOUT = HIGH FOR VS ≤ VOUT = LOW FOR VS ≥ R1 R2 R1 R2 – VR VR VT > VW, VOUT = HIGH R1 + R2 = RPOT VT < VW, VOUT = LOW FIGURE 18. LEVEL DETECTOR FIGURE 19. LEVEL DETECTOR VH R +5V – ISL28113 V+ VOUT + V– VL VW R2 C R3 +5V R1 Frequency ∝ R, C Duty Cycle ∝ R1, R2, R3 FIGURE 20. OSCILLATOR 5 AN1145.1 January 9, 2013 Application Note 1145 Application Circuits (Continued) VOUT +5V VH +5V VS VW +5V t ISL28113 – VW VNI VOUT +5V + t +5V VOUT VL t Δt VNI VS R C Δt = RCln 5V ( 5V – VW ) FIGURE 21. TIME DELAY Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that the Application Note or Technical Brief is current before proceeding. For information regarding Intersil Corporation and its products, see www.intersil.com 6 AN1145.1 January 9, 2013