INTERSIL ISL28210FBBZ

ISL28110, ISL28210
Features
The ISL28110, ISL28210, are single and dual JFET
amplifiers featuring low noise, high slew rate, low input
bias current and offset voltage, making them the ideal
choice for high impedance applications where precision
and low noise are important. The combination of
precision, low noise, and high speed combined with a
small footprint provides the user with outstanding value
and flexibility relative to similar competitive parts.
• Wide Supply Range. . . . . . . . . . . . . . . . . 9V to 40V
Applications for these amplifiers include precision medical
and analytical instrumentation, sensor conditioning,
precision power supply controls, industrial controls and
photodiode amplifiers.
• Low Current Consumption . . . . . . . . . . . . . 2.55mA
The ISL28110 single amplifier is available in the 8 Ld
SOIC, TDFN, and MSOP packages. The ISL28210 dual
amplifier is available in the 8 Ld SOIC and TDFN
packages. All devices are offered in standard pin
configurations and operate over the extended
temperature range from -40°C to +125°C.
• Low Voltage Noise . . . . . . . . . . . . . . . . . . 6nV/√Hz
• Input Bias Current . . . . . . . . . . . . . . . . . . . . . 2pA
• High Slew Rate. . . . . . . . . . . . . . . . . . . . . . 23V/µs
• High Bandwidth . . . . . . . . . . . . . . . . . . . .12.5MHz
• Low Input Offset . . . . . . . . . . . . . . . . .300µV, Max
• Offset Drift . . . . . . . . . . . . . . . . Grade C 10µV/°C
• Operating Temperature Range . . . -40°C to +125°C
• Small Package Offerings in Single, and Dual
• Pb-Free (RoHS compliant)
Applications*(see page 22)
• Precision Instruments
• Photodiode Amplifiers
• High Impedance Buffers
• Medical Instrumentation
• Active Filter Blocks
• Industrial Controls
Input Bias Current vs Common
Mode Input Voltage
RF
CF
V+
PHOTO
DIODE
RSH
CT
OUTPUT
+
V-
BASIC APPLICATION CIRCUIT - PHOTODIODE AMPLIFIER
December 8, 2010
FN6639.1
1
NORMALIZED INPUT BIAS CURRENT (pA)
Typical Application
10
8
VS = ±15V
6
4
2
0
-2
-4
-6
-8
-10
-15
-10
-5
0
5
10
15
VCM (V)
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Copyright Intersil Americas Inc. 2010. All Rights Reserved
Intersil (and design) is a trademark owned by Intersil Corporation or one of its subsidiaries.
All other trademarks mentioned are the property of their respective owners.
ISL28110, ISL28210
Precision Low Noise JFET Operational Amplifiers
ISL28110, ISL28210
Pin Configurations
ISL28110
(8 LD, SOIC, MSOP)
TOP VIEW
ISL28110
(8 LD TDFN)
TOP VIEW
NC 1
-IN A 2
- +
+IN A 3
V- 4
8 NC
NC
1
7 V+
-IN A
2
+IN A
3
6 VOUT A
V-
4
5 NC
6 VOUT A
PAD
5 NC
1
-IN A
2
+IN A
3
V-
4
8 V+
7 VOUT B
- +
PAD
6 -IN B
+ -
7 V+
- +
ISL28210
(8 LD SOIC)
TOP VIEW
ISL28210
(8 LD TDFN)
TOP VIEW
VOUT A
8 NC
5 +IN B
VOUT A
1
-IN A
2
+IN A
3
V-
4
8 V+
7 VOUT B
- +
+ -
6 -IN B
5 +IN B
Pin Descriptions
ISL28110
(8 Ld TDFN)
ISL28110
(8 Ld SOIC,
ISL28210
8 Ld MSOP) (8 Ld TDFN)
ISL28210
(8 Ld SOIC)
PIN
NAME
EQUIVALENT
CIRCUIT
DESCRIPTION
3
3
3
3
+IN A
Circuit 1
Amplifier A non-inverting input
2
2
2
2
-IN A
Circuit 1
Amplifier A inverting input
6
6
1
1
VOUT A
Circuit 2
Amplifier A output
4
4
4
4
V-
Circuit 3
Negative power supply
5
5
+IN B
Circuit 1
Amplifier B non-inverting input
6
6
-IN B
Circuit 1
Amplifier B inverting input
7
7
VOUT B
Circuit 2
Amplifier B output
8
8
V+
Circuit 3
Positive power supply
7
7
1, 5, 8
1, 5, 8
No connect
PAD
PAD
IN-
PAD
V+
V+
IN+
OUT
V-
V-
CIRCUIT 1
CIRCUIT 2
2
Thermal Pad is electrically
isolated from active circuitry. Pad
can float, connect to Ground or to
a potential source that is free
from signals or noise sources.
V+
CAPACITIVELY
TRIGGERED
ESD CLAMP
VCIRCUIT 3
FN6639.1
December 8, 2010
ISL28110, ISL28210
Ordering Information
PART NUMBER
(Notes 1, 2, 3)
PART
MARKING
TCVOS
(µV/°C)
PACKAGE
(Pb-free)
PKG.
DWG. #
ISL28110FBZ
28110 FBZ -C
10 (C Grade)
8 Ld SOIC
M8.15E
ISL28210FBZ
28210 FBZ -C
10 (C Grade)
8 Ld SOIC
M8.15E
Coming Soon
ISL28110FRTZ
-C 8110
10 (C Grade)
8 Ld TDFN
L8.3x3A
Coming Soon
ISL28210FRTZ
-C 8210
10 (C Grade)
8 Ld TDFN
L8.3x3A
Coming Soon
ISL28110FRTBZ
8110
4 (B Grade)
8 Ld TDFN
L8.3x3A
Coming Soon
ISL28210FRTBZ
8210
4 (B Grade)
8 Ld TDFN
L8.3x3A
Coming Soon
ISL28110FBBZ
28110 FBZ -C
4 (B Grade)
8 Ld SOIC
M8.15E
Coming Soon
ISL28210FBBZ
28210 FBZ
4 (B Grade)
8 Ld SOIC
M8.15E
Coming Soon
ISL28110FUBZ
8110Z
4 (B Grade)
8 Ld MSOP
M8.118
Coming Soon
ISL28110FUZ
8110Z
10 (C Grade)
8 Ld MSOP
M8.118
NOTES:
1. Add “-T*” suffix for tape and reel. Please refer to TB347 for details on reel specifications..
2. These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach
materials, and 100% matte tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both
SnPb and Pb-free soldering operations). Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that
meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
3. For Moisture Sensitivity Level (MSL), please see device information page for ISL28110, ISL28210. For more information on
MSL please see techbrief TB363.
3
FN6639.1
December 8, 2010
ISL28110, ISL28210
Absolute Voltage Ratings
Thermal Information
Maximum Supply Voltage . . . . . . . . . . . . . . . . . . . . . . 42V
Maximum Supply Turn On Voltage Slew Rate . . . . . . . . 1V/µs
Maximum Differential Input Voltage . . . . . . . . . . . . . . . 33V
Min/Max Input Voltage . . . . . . . . . . . V- - 0.5V to V+ + 0.5V
Max/Min Input Current for Input Voltage >V+ or <V- . .±20mA
Output Short-Circuit Duration
(1 output at a time) . . . . . . . . . . . . . . . . . . . . Indefinite
ESD Ratings
Human Body Model . . . . . . . . . . . . . . . . . . . . . . . 4000V
Machine Model . . . . . . . . . . . . . . . . . . . . . . . . . . . 400V
Charged Device Model . . . . . . . . . . . . . . . . . . . . . 2000V
Thermal Resistance (Typical)
θJA (°C/W) θJC (°C/W)
8 Ld SOIC (Notes 5, 7)
ISL28110 . . . . . . . . . . . . . . . . .
125
70
ISL28210 . . . . . . . . . . . . . . . . .
120
50
8 Ld TDFN (Notes 4, 6)
ISL28110 . . . . . . . . . . . . . . . . .
48
7.8
ISL28210 . . . . . . . . . . . . . . . . .
46
4.5
8 Ld MSOP (Notes 5, 7)
ISL28110 . . . . . . . . . . . . . . . . .
158
60
Ambient Operating Temperature Range . . . -40°C to +125°C
Storage Temperature Range . . . . . . . . . . . -65°C to +150°C
Operating Junction Temperature . . . . . . . . . . . . . . +150°C
Pb-Free Reflow Profile . . . . . . . . . . . . . . . . . .see link below
http://www.intersil.com/pbfree/Pb-FreeReflow.asp
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact
product reliability and result in failures not covered by warranty.
NOTES:
4. θJA is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach”
features. See Tech Brief TB379.
5. θJA is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief
TB379 for details.
6. For θJC, the “case temp” location is the center of the exposed metal pad on the package underside.
7. For θJC, the “case temp” location is taken at the package top center.
Electrical Specifications
PARAMETER
VS = ±5V, VCM = 0, VOUT = 0V, TA = +25°C, unless otherwise noted. Boldface limits apply
over the operating temperature range, -40°C to +125°C.
DESCRIPTION
CONDITIONS
MIN
(Note 8)
TYP
MAX
(Note 8)
UNITS
INPUT CHARACTERISTICS
VOS
Input Offset Voltage
-40°C < TA < +125°C
TCVOS
IB
Input Offset Voltage
Temperature Coefficient
Input Bias Current
ISL28110
Input Bias Current
ISL28210
IOS
Input Offset Current
ISL28110
-40°C < TA < +60°C
4
1
10
µV/C
±0.3
2
pA
5.3
pA
-5.3
-40°C < TA < +85°C
-36
36
pA
-40°C < TA < +125°C
-235
235
pA
2
pA
-2
±0.3
-40°C < TA < +60°C
-4.5
4.5
pA
-40°C < TA < +85°C
-50
50
pA
-40°C < TA < +125°C
-245
245
pA
1
pA
-40°C < TA < +60°C
-2.25
2.25
pA
-40°C < TA < +85°C
-30
30
pA
105
pA
1
pA
3.5
pA
-1
-40°C < TA < +60°C
±0.15
-105
-1
-40°C < TA < +125°C
Differential Input Capacitance
µV
µV
-2
-40°C < TA < +85°C
CIN-DIFF
300
1300
-40°C < TA < +125°C
-40°C < TA < +125°C
Input Offset Current
ISL28210
-300
-1300
±0.15
-3.5
-32
32
pA
-245
245
pA
8.3
pF
FN6639.1
December 8, 2010
ISL28110, ISL28210
Electrical Specifications
PARAMETER
CIN-CM
VS = ±5V, VCM = 0, VOUT = 0V, TA = +25°C, unless otherwise noted. Boldface limits apply
over the operating temperature range, -40°C to +125°C. (Continued)
DESCRIPTION
CONDITIONS
MIN
(Note 8)
TYP
MAX
(Note 8)
UNITS
Common Mode Input
Capacitance
11.8
pF
Differential Input Resistance
530
GΩ
RIN-CM
Common Mode Input Resistance
560
GΩ
VCMIR
Common Mode Input Voltage
Range
Guaranteed by CMRR test
CMRR
Common Mode Rejection Ratio
VCM = -3.5V to +3.5V
RIN-DIFF
AVOL
Open-loop Gain
V- + 1.5
V+ - 1.5
V- + 2.5
V+ - 2.5
V
V
90
dB
dB
VCM = -2.5V to +2.5V
88
100
RL = 10kΩ to ground
VO = -3V to +3V
104
108
103
dB
dB
DYNAMIC PERFORMANCE
GBWP
SR
THD+N
ts
Gain-bandwidth Product
G = 100, RL = 100kΩ, CL = 4pF
Slew Rate, VOUT 20% to 80%
G = -1, RL = 2kΩ, 4V Step
Total Harmonic Distortion +
Noise
11
12.5
MHz
20
V/µs
G = 1, f = 1kHz, 4VP-P, RL = 2kΩ
0.0002
%
G = 1, f = 1kHz, 4VP-P, RL = 600Ω
0.0003
%
Settling Time to 0.1%
4V Step; 10% to VOUT
AV = 1, VOUT = 4VP-P, RL = 2kΩ to VCM
0.4
µs
Settling Time to 0.01%
4V Step; 10% to VOUT
AV = 1, VOUT = 4VP-P, RL = 2kΩ to VCM
1
µs
580
nVP-P
NOISE PERFORMANCE
enP-P
en
in
Peak-to-Peak Input Voltage
Noise
0.1Hz to 10Hz
Input Voltage Noise Spectral
Density
f = 10Hz
Input Current Noise Spectral
Density
14
nV/√Hz
f = 100Hz
7
nV/√Hz
f = 1kHz
6
nV/√Hz
f = 10kHz
6
nV/√Hz
f = 1kHz
9
fA/√Hz
OUTPUT CHARACTERISTICS
VOL
Output Voltage Low, VOUT to V-
RL = 10kΩ
0.8
RL = 2kΩ
VOH
Output Voltage High, V+ to VOUT
0.9
RL to GND = 10kΩ
0.8
RL to GND = 2kΩ
ISC
Output Short Circuit Current
0.9
RL = 10Ω to V+. V-
1.0
V
1.1
V
1.1
V
1.2
V
1.0
V
1.1
V
1.1
V
1.2
V
±50
mA
POWER SUPPLY
VSUPPLY
PSRR
Supply Voltage Range
Guaranteed by PSRR
±4.5
Power Supply Rejection Ratio
VS = ± 4.5V to ±5V
102
±20V
115
dB
100
IS
Supply Current/Amplifier
5
V
dB
2.5
2.9
mA
3.8
mA
FN6639.1
December 8, 2010
ISL28110, ISL28210
Electrical Specifications
PARAMETER
VS = ±15V, VCM = 0, VO = 0V, TA = +25°C, unless otherwise noted. Boldface limits apply
over the operating temperature range, -40°C to +125°C.
DESCRIPTION
CONDITIONS
MIN
(Note 8)
MAX
(Note 8)
UNITS
-300
300
µV
-1300
1300
µV
1
10
µV/C
±2
TYP
INPUT CHARACTERISTICS
VOS
Input Offset Voltage
-40°C < TA < +125°C
TCVOS
IB
IB
IOS
IOS
CIN-DIFF
Input Offset Voltage Temperature
Coefficient (Grade C)
Input Bias Current
ISL28110
Input Bias Current
ISL28210
Input Offset Current
ISL28110
Input Offset Current
ISL28210
-40°C < TA < +125°C
4.5
pA
-40°C < TA < +60°C
-25
4.5
25
pA
-40°C < TA < +85°C
-85
85
pA
-40°C < TA < +125°C
-950
950
pA
5
pA
5
±2
-40°C < TA < +60°C
-350
350
pA
-40°C < TA < +85°C
-700
700
pA
-40°C < TA < +125°C
-3600
3600
pA
2.5
pA
-2.5
±0.5
-40°C < TA < +60°C
-25
25
pA
-40°C < TA < +85°C
-85
85
pA
-40°C < TA < +125°C
-650
650
pA
2.5
pA
-2.5
±0.5
-40°C < TA < +60°C
-285
285
pA
-40°C < TA < +85°C
-445
445
pA
-40°C < TA < +125°C
-2000
2000
pA
8.3
pF
Common Mode Input Capacitance
11.8
pF
Differential Input Resistance
530
GΩ
RIN-CM
Common Mode Input Resistance
560
GΩ
VCMIR
Common Mode Input Voltage Range Guaranteed by CMRR test
CMRR
Common Mode Rejection Ratio
VCM = -13.5V to +13.5V
80
100
dB
Open-loop Gain
RL = 10kΩ to ground
VO = -12.5V to +12.5V
107
109
dB
-40°C < TA < +125°C
106
CIN-CM
RIN-DIFF
AVOL
Differential Input Capacitance
V- + 1.5
V+ - 1.5
V
dB
DYNAMIC PERFORMANCE
GBWP
SR
THD+N
Gain-bandwidth Product
G = 100, RL = 100kΩ, CL = 4pF
Slew Rate, VOUT 20% to 80%
G = -1, RL = 2kΩ, 10V Step
Total Harmonic Distortion + Noise
G = 1, f = 1kHz,
10VP-P, RL = 2kΩ
G = 1, f = 1kHz,
10VP-P, RL = 600Ω
ts
11
12.5
MHz
20
V/µs
0.00025
%
0.0003
%
Settling Time to 0.1%
10V Step; 10% to VOUT
AV = 1, VOUT = 10VP-P, RL = 2kΩ
to VCM
1.3
µs
Settling Time to 0.01%
10V Step; 10% to VOUT
AV = 1, VOUT = 10VP-P, RL = 2kΩ
to VCM
1.6
µs
6
FN6639.1
December 8, 2010
ISL28110, ISL28210
Electrical Specifications
PARAMETER
VS = ±15V, VCM = 0, VO = 0V, TA = +25°C, unless otherwise noted. Boldface limits apply
over the operating temperature range, -40°C to +125°C. (Continued)
DESCRIPTION
CONDITIONS
MIN
(Note 8)
TYP
MAX
(Note 8)
UNITS
NOISE PERFORMANCE
enP-P
Peak-to-Peak Input Voltage Noise
0.1Hz to 10Hz
en
Input Voltage Noise Spectral Density
in
Input Current Noise Spectral Density
600
nVP-P
f = 10Hz
18
nV/√Hz
f = 100Hz
7.8
nV/√Hz
f = 1kHz
6
nV/√Hz
f = 10kHz
6
nV/√Hz
f = 1kHz
9
fA/√Hz
OUTPUT CHARACTERISTICS
VOL
Output Voltage Low,
VOUT to V-
RL = 10kΩ
0.8
RL = 2kΩ
VOH
Output Voltage High,
V+ to VOUT
0.9
RL to GND = 10kΩ
0.8
RL to GND = 2kΩ
ISC
Output Short Circuit Current
0.9
RL = 10Ω to V+. V-
1.0
V
1.1
V
1.1
V
1.2
V
1.0
V
1.1
V
1.1
V
1.2
V
±50
mA
115
dB
POWER SUPPLY
PSRR
Power Supply Rejection Ratio
VS = ±4.5V to ±20V
102
100
IS
Supply Current/Amplifier
dB
2.55
3.1
mA
3.9
mA
NOTE:
8. Compliance to datasheet limits is assured by one or more methods: production test, characterization and/or design.
7
FN6639.1
December 8, 2010
ISL28110, ISL28210
Typical Performance Curves
VS = ±15V, VCM = 0V, RL = Open, T = +25°C, unless otherwise
specified.
25
250
NUMBER OF AMPLIFIERS
NUMBER OF AMPLIFIERS
200
150
100
50
0
-150
-100
-50
0
50
100
150
200
20
15
10
5
0
250
-10
-8
-6
FIGURE 1. INPUT OFFSET VOLTAGE (VOS)
DISTRIBUTION
0
-2
2
4
8
6
10
FIGURE 2. TCVOS DISTRIBUTION, -40°C to +125°C
1.6
10
1.4
0
1.2
-10
-20
1.0
IB (pA)
INPUT BIAS CURRENT (pA)
-4
TCVOS(µV/C)
VOS (µV)
0.8
0.6
VS = ±5V
-30
VS = ±15V
-40
-50
0.4
-60
0.2
0
VS = ±15V
TA = -40°C TO +125°C
VS = ±15V
-70
5
6
7
8
9
10
11
±VSUPPLY (±V)
12
13
14
-80
-40
15
FIGURE 3. INPUT BIAS CURRENT (IB) vs SUPPLY
VOLTAGE
-20
0
20
40
60
80
TEMPERATURE (°C)
100
120
140
FIGURE 4. ISL28110 INPUT BIAS CURRENT (IB) vs
TEMPERATURE
20
100
-200
10
VS = ±5V
-300
-400
VS = ±15V
IOS (pA)
INPUT BIAS (pA)
0
-100
-500
-600
VS = ±5V
0
-700
-800
-10
VS = ±15V
-900
-1000
-1100
-40
-20
0
20
40
60
80
TEMPERATURE (°C)
100
120
140
FIGURE 5. ISL28210 INPUT BIAS CURRENT (IB) vs
TEMPERATURE
8
-20
-40
-20
0
20
40
60
80
TEMPERATURE (°C)
100
120
140
FIGURE 6. ISL28110 INPUT OFFSET CURRENT (IOS) vs
TEMPERATURE
FN6639.1
December 8, 2010
ISL28110, ISL28210
Typical Performance Curves
VS = ±15V, VCM = 0V, RL = Open, T = +25°C, unless otherwise
specified. (Continued)
20
300
VS = ±5V
VS = ±15V
250
IOS CHA
200
IOS CHA
IOS (pA)
IOS (pA)
10
0
-10
150
IOS CHB
100
50
IOS CHB
0
-20
0
20
40
60
80
TEMPERATURE (°C)
100
120
NORMALIZED INPUT BIAS CURRENT (pA)
3.5
VS = ±5V
3.0
2.5
2.0
1.5
1.0
0.5
0
-0.5
-1.0
-5
-4
-3
-2
-1
0
1
-20
0
20
2
3
4
5
80
100
120
140
10
8
VS = ±15V
6
4
2
0
-2
-4
-6
-8
-10
-15
-10
-5
0
5
10
15
VCM (V)
FIGURE 9. NORMALIZED INPUT BIAS CURRENT (IB) vs
INPUT COMMON MODE VOLTAGE (VCM),
VS = ±5V
500
FIGURE 10. NORMALIZED INPUT BIAS CURRENT (IB)
vs INPUT COMMON MODE VOLTAGE (VCM),
VS = ±15V
500
VS = ±5V
400
VS = ±15V
400
300
NORMALIZED VOS (uV)
NORMALIZED VOS (uV)
60
FIGURE 8. ISL28210 INPUT OFFSET CURRENT (IOS) vs
TEMPERATURE, VS = ±15V
VCM (V)
200
100
0
-100
-200
-300
-400
-500
-5
40
TEMPERATURE (°C)
FIGURE 7. ISL28210 INPUT OFFSET CURRENT (IOS) vs
TEMPERATURE, VS = ±5V
4.0
-50
-40
140
NORMALIZED INPUT BIAS CURRENT (pA)
-20
-40
300
200
100
0
-100
-200
-300
-400
-4
-3
-2
-1
0
1
VCM (V)
2
3
4
5
FIGURE 11. NORMALIZED INPUT OFFSET VOLTAGE
(VOS) vs INPUT COMMON MODE VOLTAGE
(VCM), VS = ±5V
9
-500
-15
-10
-5
0
VCM (V)
5
10
15
FIGURE 12. NORMALIZED INPUT OFFSET VOLTAGE
(VOS) vs INPUT COMMON MODE VOLTAGE
(VCM), VS = ±15V
FN6639.1
December 8, 2010
ISL28110, ISL28210
Typical Performance Curves
VS = ±15V, VCM = 0V, RL = Open, T = +25°C, unless otherwise
specified. (Continued)
100
INPUT NOISE CURRENT
10
10
1
0.1
1
10
100
1k
10k
INPUT NOISE VOLTAGE (nV/√Hz)
INPUT NOISE VOLTAGE
100
1000
1000
VS = ±18V
INPUT NOISE VOLTAGE
100
INPUT NOISE CURRENT
10
10
1
100k
1
0.1
1
10
100
1k
FREQUENCY (Hz)
FREQUENCY (Hz)
FIGURE 13. INPUT NOISE VOLTAGE (en) AND CURRENT
(in) vs FREQUENCY, VS = ±5V
1000
VS = ±5V
AV = 10k
800
600
400
200
0
-200
-400
-600
-800
-1000
0
1
2
3
4
5
6
7
8
9
600
400
200
0
-200
-400
-600
-800
-1000
10
VS = ±18V
AV = 10k
800
0
1
2
3
4
TIME (s)
+25°C
0.001
-40°C
0.1
VS = ±15V
CL = 4pF
RL = 600
VOUT = 10VP-P
C-WEIGHTED
22Hz to 500kHz
-40°C
+25°C
100
+125°C
AV = 10
+125°C
0.01
8
9
10
VS = ±15V
CL = 4pF
RL = 2k
VOUT = 10VP-P
-40°C
+25°C
+125°C
AV = 10
0.001
-40°C
1k
10k
FREQUENCY (Hz)
+25°C
+125°C
AV = 1
100k
FIGURE 17. THD+N vs FREQUENCY vs TEMPERATURE,
AV = 1, 10, VOUT = 10VP-P, RL = 600Ω
10
7
C-WEIGHTED
22Hz to 500kHz
AV = 1
0.0001
10
6
FIGURE 16. 0.1Hz TO 10Hz VP-P NOISE VOLTAGE,
VS = ±18V
THD + N (%)
THD + N (%)
0.01
5
TIME (s)
FIGURE 15. 0.1Hz TO 10Hz VP-P NOISE VOLTAGE,
VS =±5V
0.1
1
100k
10k
FIGURE 14. INPUT NOISE VOLTAGE (en) AND CURRENT
(in) vs FREQUENCY, VS = ±18V
INPUT NOISE VOLTAGE (nVP-P)
INPUT NOISE VOLTAGE (nVP-P)
1000
100
INPUT NOISE CURRENT (fA/√Hz)
1000
VS = ±5V
INPUT NOISE CURRENT (fA/√Hz)
INPUT NOISE VOLTAGE (nV/√Hz)
1000
0.0001
10
100
1k
FREQUENCY (Hz)
10k
100k
FIGURE 18. THD+N vs FREQUENCY vs TEMPERATURE,
VOUT = 10VP-P, RL = 2kΩ
FN6639.1
December 8, 2010
ISL28110, ISL28210
Typical Performance Curves
VS = ±15V, VCM = 0V, RL = Open, T = +25°C, unless otherwise
specified. (Continued)
1
+25°C
0.001
-40°C
5
10
15
VOUT (VP-P)
20
25
30
FIGURE 19. THD+N vs OUTPUT VOLTAGE (VOUT) vs
TEMPERATURE, AV = 1 f = 1kHz, RL = 600Ω
0
RL_RECEIVE = 10k
-60
RL-TRANSMIT = ∞
RL_RECEIVE = ∞
5
10
15
VOUT (VP-P)
20
25
30
VS = ±15V
VOUT = 100mVP-P
50
40
AV = 10
AV = -1
30
AV = 1
20
10
-120
1
10
100
1k
10k
100k
FREQUENCY (Hz)
1M
10M
0.01
0.1
1
LOAD CAPACITANCE (nF)
10
100
FIGURE 22. SMALL SIGNAL OVERSHOOT vs LOAD
CAPACITANCE (CL)
70
60
PHASE
ACL = 1000
GAIN
40
30
20
10
0
100
1k
10k 100k 1M 10M 100M 1G
FREQUENCY (Hz)
FIGURE 23. OPEN LOOP GAIN-PHASE vs FREQUENCY
11
RF = 100kΩ, RG = 100Ω
RF = 100kΩ, RG = 1kΩ
50
GAIN (dB)
200
180
160
140
120
100
80
60
40
20
0
-20
-40
-60 VS = ±15V
-80 RL=1MΩ
-100
0.1
1
10
0
0.001
100M
FIGURE 21. CROSSTALK vs FREQUENCY
GAIN (dB)
-40°C
FIGURE 20. THD+N vs OUTPUT VOLTAGE (VOUT) vs
TEMPERATURE, AV = 1 f =1kHz, RL = 2kΩ
OVERSHOOT (%)
CROSSTALK (dB)
RL-TRANSMIT = 2k
-40
-140
+25°C
+125°C
60
VS = ±15V
-20 CL = 4pF
VCM = 1VP-P
-100
0.01
0.0001
0
-80
C-WEIGHTED
22Hz to 22kHz
0.001
+125°C
0
AV = 1
VS = ±15V
CL= 4pF
RL= 2k
0.1 f = 1kHz
C-WEIGHTED
22Hz to 22kHz
0.01
0.0001
1
AV = 1
THD + N (%)
THD + N (%)
VS = ±15V
CL = 4pF
RL = 600
0.1 f = 1kHz
ACL = 100
VS = ±5V & ±15V
CL = 4pF
RL = OPEN
VOUT = 100mVP-P
ACL = 10
RF = 100kΩ, RG = 10kΩ
ACL = 1
-10
1k
RF = 0, RG = ∞
10k
100k
1M
10M
100M
FREQUENCY (Hz)
FIGURE 24. CLOSED LOOP GAIN vs FREQUENCY
FN6639.1
December 8, 2010
ISL28110, ISL28210
Typical Performance Curves
VS = ±15V, VCM = 0V, RL = Open, T = +25°C, unless otherwise
specified. (Continued)
120
PSRR-
90
CMRR (dB)
PSRR (dB)
80
70
60
50
40
30
20
10
VS = ±15V
AV = 1
CL = 4pF
RL = 10k
VCM = 1VP-P
0
10
PSRR+
100
1k
10k
100k
1M
10M
130
120
110
100
90
80
70
60
50
40
30
20 VS = ±15V
10 SIMULATION
0
0.1
1
10
100
1k
10k 100k
FREQUENCY (Hz)
FREQUENCY (Hz)
5
15
4
14
-40°C
3
+125°C
+25°C
VS = ±5V
1 A =2
V
-1 R = R = 100k
F
G
-2 VIN = 2.5VP-P
VOL
+85°C
-3
-5
10
20
30
40
I-FORCE (mA)
50
60
70
INPUT
INPUT (mV)
120
OUTPUT
AV = 1
80
8
40
0
0
2
4
6
8
10
12
TIME (µs)
14
16
18
-13
0°C
0
10
20
30
40
I-FORCE (mA)
50
60
70
0
INPUT
-40
-4
-80
-8
-12
-120
OUTPUT
4
-160
0
20
-200
FIGURE 29. POSITIVE OUTPUT OVERLOAD RECOVERY
TIME
12
85°C
0
OUTPUT (V)
20
VS = ±15V
AV = 100
RL = 10k
16
VIN = 100mVP-P
OVERDRIVE = 1V
12
160
VS = ±15V
AV = 2
RF = RG = 100k
VIN = 7.5VP-P
FIGURE 28. OUTPUT VOLTAGE (VOUT) vs OUTPUT
CURRENT (IOUT) vs TEMPERATURE,
VS = ±15V
FIGURE 27. OUTPUT VOLTAGE (VOUT) vs OUTPUT
CURRENT (IOUT) vs TEMPERATURE,
VS = ±5V
200
25°C
-12
-14
-15
0°C
0
125°C
12
10
-10
-11
-4
100M
-40°C
13
11
INPUT (mV)
VOL
2
10M
FIGURE 26. COMMON-MODE REJECTION RATIO (CMRR)
vs FREQUENCY
VOH
VOH
FIGURE 25. POWER SUPPLY REJECTION RATIO (PSRR)
vs FREQUENCY
1M
0
2
4
6
8
10
12
VS = ±15V
AV = 100
RL = 10k
VIN = 100mVP-P
OVERDRIVE = 1V
14
16
18
OUTPUT (V)
110
100
-16
-20
20
TIME (µs)
FIGURE 30. NEGATIVE OUTPUT OVERLOAD RECOVERY
TIME
FN6639.1
December 8, 2010
ISL28110, ISL28210
Typical Performance Curves
VS = ±15V, VCM = 0V, RL = Open, T = +25°C, unless otherwise
specified. (Continued)
30
30
-SR
-SR
25
SLEW RATE (V/µs)
SLEW RATE (V/µs)
25
20
+SR
15
10
VS = ±5V
VOUT-PP = 4V
RL = 2k
CL = 4pF
5
0
-1
-2
-3
20
+SR
15
10
VS = ±15V
VOUT-PP = 10V
RL = 2k
CL = 4pF
5
-4
-5
-6
-7
-8
-9
0
-1
-10
-2
-3
-4
-5
GAIN
-6
-7
-8
-9
-10
GAIN
FIGURE 31. SLEW RATE vs INVERTING CLOSED LOOP
GAIN, VS = ±5V
FIGURE 32. SLEW RATE vs INVERTING CLOSED LOOP
GAIN, VS = ±15V
30
30
25
25
-SR
SLEW RATE (V/µs)
SLEW RATE (V/µs)
-SR
20
15
+SR
10
VS = ±5V
VOUT-PP = 4V
RL = 2k
CL = 4pF
5
0
1
2
3
4
5
6
GAIN
7
8
9
10
0
10
VS = ±15V
VOUT-PP = 10V
RL = 2k
CL = 4pF
1
2
3
4
5
6
GAIN
7
8
9
10
FIGURE 34. SLEW RATE vs NON-INVERTING CLOSED
LOOP GAIN, VS = ±15V
6
0.15
VS = ±15V
AV = 1
RL = 2k
CL = 4pF
0.10
2
0
0
-0.05
-2
-0.10
-4
0
0.1
0.2
VS = ±15V
AV = 1
RL = 2k
CL = 4pF
4
VOUT (V)
0.05
-0.15
+SR
15
5
FIGURE 33. SLEW RATE vs NON-INVERTING CLOSED
LOOP GAIN, VS = ±5V
VOUT (V)
20
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1.0
TIME (µs)
FIGURE 35. SMALL SIGNAL TRANSIENT RESPONSE
13
-6
0
1
2
3
4
5
6
7
8
9
10
TIME (µs)
FIGURE 36. LARGE SIGNAL UNITY GAIN TRANSIENT
RESPONSE
FN6639.1
December 8, 2010
ISL28110, ISL28210
Typical Performance Curves
VS = ±15V, VCM = 0V, RL = Open, T = +25°C, unless otherwise
specified. (Continued)
6
6
VS = ±15V
AV = +10
4 R = 2k
L
CL = 4pF
2
VS = ±15V
AV = -1
RL = 2k
CL = 4pF
4
VOUT (V)
VOUT (V)
2
0
-2
-2
-4
-4
-6
0
1
2
3
4
5
6
TIME (µs)
7
8
9
-6
10
FIGURE 37. LARGE SIGNAL 10V STEP RESPONSE AV = -1
0
VS = ±15V
VOUT = 10VP-P
RL = 2kΩ
1
2
3
4
7
8
9
10
VS = ±15V
100
G = 10
ZOUT (Ω)
0.01%
10
5
6
TIME (µs)
FIGURE 38. LARGE SIGNAL 10V STEP RESPONSE
AV = +10
1000
100
SETTLING TIME (µs)
0
0.1%
10
G = 100
1
1
0.1
0.1
1
10
100
CLOSED LOOP GAIN (V/V)
FIGURE 39. SETTLING TIME (tS) vs CLOSED LOOP GAIN
Applications Information
Functional Description
The ISL28110 and ISL28210 are single and dual 12.5
MHz precision JFET input op amps. These devices are
fabricated in the PR40 Advanced Silicon-on-Insulator
(SOI) bipolar-JFET process to ensure latch-free
operation. The precision JFET input stage provides low
input offset voltage (300µV max @ +25°C), low input
voltage noise (6nV/√Hz), and input current noise that is
very low with virtually no 1/f component. A high current
complementary NPN/PNP emitter-follower output stage
provides high slew rate and maintains excellent THD+N
performance into heavy loads (0.0003% @ 10VP-P @
1kHz into 600Ω).
Operating Voltage Range
The devices are designed to operate over the 9V (±4.5V)
to 40V (±20V) range and are fully characterized at 10V
(±5V) and 30V (±15V). The JFET input stage maintains
high impedance over a maximum input differential
14
0.01
10
G=1
100
1k
10k
100k
1M
10M
100M
FREQUENCY (Hz)
FIGURE 40. ZOUT vs FREQUENCY
voltage range of ±33V. Internal ESD protection diodes
clamp the non-inverting and inverting inputs to one diode
drop above and below the V+ and V- the power supply
rails (“Pin Descriptions” on page 2, CIRCUIT 1).
Input ESD Diode Protection
The JFET gate is a reverse-biased diode with >33V
reverse breakdown voltage which enables the device to
function reliably in large signal pulse applications without
the need for anti-parallel clamp diodes required on
MOSFET and most bipolar input stage op amps. No
special input signal restrictions are needed for power
supply operation up to ±15V, and input signal distortion
caused by nonlinear clamps under high slew rate
conditions are avoided. For power supply operation
greater than ±16V (>32V), the internal ESD clamp
diodes alone cannot clamp the maximum input
differential signal to the power supply rails without the
risk of exceeding the 33V breakdown of the JFET gate.
Under these conditions, differential input voltage limiting
is necessary to prevent damage to the JFET input stage.
FN6639.1
December 8, 2010
ISL28110, ISL28210
In applications where one or both amplifier input
terminals are at risk of exposure to voltages beyond the
supply rails, current limiting resistors may be needed at
each input terminal (see Figure 41 RIN+, RIN-) to limit
current through the power supply ESD diodes to 20mA.
V+
VINVIN+
RIN-
-
RIN
+
RL
FIGURE 41. INPUT ESD DIODE CURRENT LIMITING
JFET Input Stage Performance
The ISL28110, ISL28210 JFET input stage has the linear
gain characteristics of the MOSFET but can operate at
high frequency with much lower noise. The reversedbiased gate PN gate junction has significantly lower gate
capacitance than the MOSFET, enabling input slew rates
that rival op amps using bipolar input stages. The added
advantage for high impedance, precision amplifiers is
the lack of a significant 1/f component of current noise
(Figures 13, 14) as there is virtually no gate current.
10
INPUT OFFSET VOLTAGE (VOS)
500
VS = ±15V
T = +25°C
400
6
300
4
200
2
100
0
0
-2
-100
-4
-200
-300
INPUT BIAS (IB)
-8
-10
-15
-400
-10
-5
0
5
10
-500
15
VCM (V)
FIGURE 42. INPUT OFFSET VOLTAGE AND BIAS
CURRENT vs COMMON MODE INPUT
VOLTAGE
15
NORMALIZED VOS (uV)
NORMALIZED INPUT BIAS CURRENT (pA)
The input stage JFETs are bootstrapped to maintain a
constant JFET drain to source voltage which keeps the
JFET gate currents and input stage frequency response
nearly constant over the common mode input range of
the device. These enhancements provide excellent
CMRR, AC performance and very low input distortion
over a wide temperature range. The common mode
input performance for offset voltage and bias current is
shown in Figure 42. Note that the input bias current
remains low even after the maximum input stage
common mode voltage is exceeded (as indicated by the
abrupt change in input offset voltage).
-6
The complementary bipolar emitter follower output
stage features low output impedance (Figure 40) and is
capable of substantial current drive over the full
temperature range (Figures 27, 28) while driving the
output voltage close to the supply rails. The output
current is internally limited to approximately ±50mA at
+25°C. The amplifiers can withstand a short circuit to
either rail as long as the power dissipation limits are not
exceeded. This applies to only 1 amplifier at a time for
the dual op amp. Continuous operation under these
conditions may degrade long term reliability.
Output Phase Reversal
V-
8
Output Drive Capability
Output phase reversal is a change of polarity in the
amplifier transfer function when the input voltage
exceeds the supply voltage. The ISL28110 and ISL28210
are immune to output phase reversal, out to 0.5V
beyond the rail (VABS MAX) limit. Beyond these limits,
the device is still immune to reversal to 1V beyond the
rails but damage to the internal ESD protection diodes
can result unless these input currents are limited.
Maximizing Dynamic Signal Range
The amplifiers maximum undistorted output swing is a
figure of merit for precision, low distortion applications.
Audio amplifiers are a good example of amplifiers that
require low noise and low signal distortion over a wide
output dynamic range. When these applications operate
from batteries, raising the amplifier supply voltage to
overcome poor output voltage swing has the penalty of
increased power consumption and shorter battery life.
Amplifiers whose input and output stages can swing
closest to the power supply rails while providing low
noise and undistorted performance, will provide
maximum useful dynamic signal range and longer
battery life.
Rail-to-rail input and output (RRIO) amplifiers have the
highest dynamic signal range but their added complexity
degrades input noise and amplifier distortion. Many
contain two input pairs, one pair operating to each supply
rail. The trade-offs for these are increased input noise
and distortion caused by non-linear input bias current
and capacitance when amplifying high impedance
sources. Their rail-to-rail output stages swing to within a
few millivolts of the rail, but output impedances are high
so that their output swing decreases and distortion
increases rapidly with increasing load current. At heavy
load currents the maximum output voltage swing of RRO
op amps can be lower than a good emitter follower
output stage.
The ISL28110 and ISL28210 low noise input stage and
high performance output stage are optimized for low
THD+N into moderate loads over the full -40°C to
+125°C temperature range. Figures 19 and 20 show the
1kHz THD+N unity gain performance vs output voltage
swing at load resistances of 2kΩ and 600Ω. Figure 43
shows the unity-gain THD+N performance driving
600Ω from ±5V supplies.
FN6639.1
December 8, 2010
ISL28110, ISL28210
ISL28110 and ISL28210 SPICE Model
1
VS = ±5V
RL = 600Ω
THD+N (%)
0.1
AV = 1
+125°C
+85°C
+25°C
0.01
0.001
0°C
-40°C
0.0001
0
1
2
3
4
5
6
VP-P (V)
7
8
9
10
FIGURE 43. UNITY-GAIN THD+N vs OUTPUT VOLTAGE
vs TEMPERATURE AT VS = ±5V FOR 600Ω
LOAD
Power Dissipation
It is possible to exceed the +150°C maximum junction
temperatures under certain load and power supply
conditions. It is therefore important to calculate the
maximum junction temperature (TJMAX) for all
applications to determine if power supply voltages, load
conditions, or package type need to be modified to
remain in the safe operating area. These parameters are
related using Equation 1:
T JMAX = T MAX + θ JA xPD MAXTOTAL
(EQ. 1)
where:
• PDMAXTOTAL is the sum of the maximum power
dissipation of each amplifier in the package (PDMAX)
• PDMAX for each amplifier can be calculated using
Equation 2:
V OUTMAX
PD MAX = V S × I qMAX + ( V S - V OUTMAX ) × ---------------------------RL
(EQ. 2)
where:
• TMAX = Maximum ambient temperature
• θJA = Thermal resistance of the package
• PDMAX = Maximum power dissipation of 1 amplifier
• VS = Total supply voltage
• IqMAX = Maximum quiescent supply current of 1
amplifier
Figure 44 shows the SPICE model schematic and
Figure 45 shows the net list for the SPICE model. The
model is a simplified version of the actual device and
simulates important AC and DC parameters. AC
parameters incorporated into the model are: 1/f and
flatband noise voltage, Slew Rate, CMRR, Gain and
Phase. The DC parameters are IOS, total supply current
and output voltage swing. The model uses typical
parameters given in the “Electrical Specifications” Table
beginning on page 4. The AVOL is adjusted for 125dB
with the dominant pole at 7Hz. The CMRR is set 120dB,
f = 280kHz. The input stage models the actual device to
present an accurate AC representation. The model is
configured for ambient temperature of +25°C.
Figures 46 through 59 show the characterization vs
simulation results for the Noise Voltage, Closed Loop
Gain vs Frequency, Small Signal 0.1V Step, Large Signal
5V Step Response, Open Loop Gain Phase, CMRR and
Output Voltage Swing for ±5V and ±15V supplies.
LICENSE STATEMENT
The information in this SPICE model is protected under
the United States copyright laws. Intersil Corporation
hereby grants users of this macro-model hereto referred
to as “Licensee”, a nonexclusive, nontransferable licence
to use this model as long as the Licensee abides by the
terms of this agreement. Before using this macro-model,
the Licensee should read this license. If the Licensee
does not accept these terms, permission to use the
model is not granted.
The Licensee may not sell, loan, rent, or license the
macro-model, in whole, in part, or in modified form, to
anyone outside the Licensee’s company. The Licensee
may modify the macro-model to suit his/her specific
applications, and the Licensee may make copies of this
macro-model for use within their company only.
This macro-model is provided “AS IS, WHERE IS, AND
WITH NO WARRANTY OF ANY KIND EITHER EXPRESSED
OR IMPLIED, INCLUDING BUY NOT LIMITED TO ANY
IMPLIED WARRANTIES OF MERCHANTABILITY AND
FITNESS FOR A PARTICULAR PURPOSE.”
In no event will Intersil be liable for special, collateral,
incidental, or consequential damages in connection with
or arising out of the use of this macro-model. Intersil
reserves the right to make changes to the product and
the macro-model without prior notice.
• VOUTMAX = Maximum output voltage swing of the
application
• RL = Load resistance
16
FN6639.1
December 8, 2010
C3
6e-12
21
9
DN
19
3
2
+- +
-
NPN_CASCODE
R3
5e11
E
En
CinDif
5.87E-40
5
0
6
J1
7
Cin2
7.27e-40
4
R7
16
18
DX
Vg
Vg
Vmid
Vmid
D8
V7
1.18
D4
DBREAK
17
24 G2
PJ110_INPUT 250
R10
5
Vmid
G4
1
GAIN = 33
J3
PJ110_CASCODE
Cin1
7.27e-40
V6
1.18
25
V5
1.18
15
J4
C4
2.5e-12
27
G
GAIN = 181.819E-6
D6
V--
C5
R14
200k
E2
+ +
- E
GAIN = 0.5
2.5e-12
D10
V--
V--
VCM
INPUT STAGE
GAIN STAGE
MID SUPPLY REF V
V+
E3
+ +
- E
GAIN = 1
L3
L1
5.30532e-10
31
R17
0.001
318.319274232055
318.319274232055
G11
G9
+
+
G
G
GAIN = 0.0031415
D11
GAIN = 0.0031415
DX
C6
C8
29
10e-12
Vc
Vg
Vmid
VC
.523
R23
50
Vout
VOUT
38
L4
5.30532e-10
10e-12
GAIN = 0.0031415
R20
R22
318.319274232055
318.319274232055
V--
D13
G13
G14
+
+
G
G
GAIN = 1.11e-2 GAIN = 1.11e-2
D16
V-V-
COMMON MODE
GAIN STAGE
WITH ZERO
Vout
.523
DY
10e-12
GAIN = 0.0031415
V9
36
C9
G12
DY
+
-
+
-
FN6639.1
December 8, 2010
VCM
32
+
-
V--
C7
G10
+
-
GAIN = 1
GAIN = 1
L2
5.30532e-10
G15
Vout
GAIN = 20e-3
Vout
ISY
R18
0.001
G8
V8
37
DX
30
G6
G
35
34
D12
R16
0.001
D15
10e-12
33
2.5E-3
Vmid
D14
DX
5.30532e-10
G7
+
28
G
R15
0.001 GAIN = 1
V++
R21
DX
VCM
G5
+
G
GAIN = 1
V++
R19
V-E4
+ +
- E
GAIN = 1
0
FIGURE 44. SPICE NET LIST
CORRECTION CURRENT OUTPUT STAGE
SOURCES
Vout
G
+
-
0
++
-
V++
G16
GAIN = 20e-3
Vout
R24
50
ISL28110, ISL28210
PJ110_CASCODE
J2
14
R13
200k
VC
R8
100
GAIN = 1
Q1
NPN_CASCODE
Q5
NPN_CASCODE
pj110_input
GAIN = 1
Q2
Q4
R4
IOS
250
0.3E-12
NPN_CASCODE
R12
1e10
26
G3
+
G
Vmid
GAIN = 181.819E-6
1k
EOS Vc
+- +
E Vmid
C2
4e-12
D3 DBREAK
13
D7
R11
23
D2 DBREAK
12
1
DX
D1
1.18
DX
17
R2
5e11
R1
Vin+
PNP_MIRROR
Q6
8
1
0
110
buffer2
+- +
E
+
-
buffer1
+ +
- E
0.4
V1
20
11
PNP_MIRROR
Q7
Vin-
G1
+
R9
G
22 GAIN = 33
V4
C1
4e-12
DX
R6
5.5k
R5
5.5k
D5
D9
DX
0.7Vdc
I1
240E-6
10
DX
V3
+
-
0.7Vdc
V++
V++
V++
V2
ISL28110, ISL28210
* source ISL28110_210_presubckt_0
* Revision A, LaFontaine Nov 4th 2010
* Model for Noise 200nV/[email protected]
*11nV/rtHz base band, supply current 2.5mA,
*CMRR 120dB fcm=281kHz ,AVOL 125dB
*fd=7Hz
* SR = 20V/us, GBWP 12.6MHz, Output
*voltage clamp
*Copyright 2010 by Intersil Corporation
*Refer to data sheet “LICENSE STATEMENT”
*Use of this model indicates your acceptance
*with the terms and provisions in the License
*Statement.
* Connections:
*
+input
*
| -input
*
|
| +Vsupply
*
|
| | -Vsupply
*
|
| | | output
*
|
| | | |
.subckt ISL28110subckt Vin+ Vin- V+ V- VOUT
* source ISL28110_210_PRESUBCKT_0
*
*Voltage Noise
*
E_En
VIN+ 4 2 0 1
V_V1
1 0 0.4
D_D1
1 2 DN
R_R1
2 0 110
*
*Input Stage
*
R_R2
VIN- 3 5e11
R_R3
3 4 5e11
C_CinDif
4 VIN- 5.87E-40
C_Cin1
V-- VIN- 7.27e-40
C_Cin2
V-- 4 7.27e-40
I_IOS
4 VIN- DC 0.3E-12
R_R4
5 VIN- 250
J_J1
7 5 6 pj110_input
J_J2
15 16 14 pj110_input
J_J3
V-- 14 15 PJ110_CASCODE
J_J4
V-- 6 7 PJ110_CASCODE
Q_Q1
19 13 14 NPN_CASCODE
Q_Q2
12 13 6 NPN_CASCODE
Q_Q4
8 13 6 NPN_CASCODE
Q_Q5
12 13 14 NPN_CASCODE
Q_Q6
19 11 20 PNP_MIRROR
Q_Q7
8 11 9 PNP_MIRROR
V_V2
V++ 10 0.7Vdc
V_V3
V++ 21 0.7Vdc
R_R5
9 10 5.5k
R_R6
20 21 5.5k
E_buffer1
11 V++ 8 V++ 1
E_buffer2
13 V-- 12 V-- 1
D_D2
8 19 DBREAK
D_D3
19 8 DBREAK
I_I1
V++ 12 DC 240E-6
C_C1
19 V++ 4e-12
C_C2
V-- 19 4e-12
R_R7
16 17 250
E_EOS
17 4 VC VMID 1
*
*1st Gain Stage
*
R_R8
18 V++ 100
D_D4
V-- 18 DBREAK
D_D5
22 V++ DX
D_D6
V-- 24 DX
V_V4
22 23 1.18
V_V5
23 24 1.18
G_G1
V++ 23 19 8 33
G_G2
V-- 23 19 8 33
R_R9
23 V++ 1
R_R10
V-- 23 1
R_R11
25 23 1k
D_D7
25 VMID DX
D_D8
VMID 25 DX
R_R12
25 VMID 1e10
G_G3
V++ VG 25 VMID 181.819E-6
G_G4
V-- VG 25 VMID 181.819E-6
D_D9
26 V++ DX
D_D10
V-- 27 DX
V_V6
26 VG 1.18
V_V7
VG 27 1.18
R_R13
VG V++ 200k
R_R14
V-- VG 200k
C_C3
8 VG 6e-12
C_C4
VG V++ 2.5e-12
C_C5
V-- VG 2.5e-12
*
* Mid Supply Reference
*
E_E2
VMID V-- V++ V-- 0.5
E_E3
V++ 0 V+ 0 1
E_E4
V-- 0 V- 0 1
I_ISY
V+ V- DC 2.5E-3
*
*Common Mode Gain Stage 40dB/dec
*
G_G5
V++ 29 3 VMID 1
G_G6
V-- 29 3 VMID 1
G_G7
V++ VC 29 VMID 1
G_G8
V-- VC 29 VMID 1
L_L1
28 V++ 5.30532e-11
L_L2
30 V-- 5.30532e-11
L_L3
31 V++ 5.30532e-11
L_L4
32 V-- 5.30532e-11
R_R15
29 28 0.001
R_R16
30 29 0.001
R_R17
VC 31 0.001
R_R18
32 VC 0.001
*
*Second Pole Stage 40dB/dec
*
G_G9
V++ 33 VG VMID 0.0031415
G_G10
V-- 33 VG VMID 0.0031415
G_G11
V++ 34 33 VMID 0.0031415
G_G12
V-- 34 33 VMID 0.0031415
R_R19
33 V++ 318.319274232055
R_R20
V-- 33 318.319274232055
R_R21
34 V++ 318.319274232055
R_R22
V-- 34 318.319274232055
C_C6
33 V++ 10e-12
C_C7
V-- 33 10e-12
C_C8
34 V++ 10e-12
C_C9
V-- 34 10e-12
*
* Output Stage
*
D_D11
34 35 DX
D_D12
36 34 DX
D_D13
V-- 37 DY
D_D14
V++ 37 DX
D_D15
V++ 38 DX
D_D16
V-- 38 DY
G_G13
37 V-- VOUT 34 1.11e-2
G_G14
38 V-- 34 VOUT 1.11e-2
G_G15
VOUT V++ V++ 34 20e-3
G_G16
V-- VOUT 34 V-- 20e-3
V_V8
35 VOUT -.384
V_V9
VOUT 36 -.384
R_R23
VOUT V++ 50
R_R24
V-- VOUT 50
*
*
.model pj110_input pjf
+ vto=-1.4
+ beta=0.0025
+ lambda=0.03
+ is=2.68e-015
+ pb=0.73
+ cgd=8.6e-012
+ cgs=9.05e-012
+ fc=0.5 kf=0
+ af=1
+ tnom=35
*
.model NPN_CASCODE npn
+ is=5.02e-016
+ bf=150
+ va=300
+ ik=0.017
+ rb=0.01
+ re=0.011
+ rc=900
+ cje=2e-013
+ cjc=1.6e-028
+ kf=0
+ af=1
*
.model PJ110_CASCODE pjf
+ vto=-1.4
+ beta=0.000617
+ lambda=0.03
+ is=3.96e-016
+ pb=0.73
+ cgd=2.2e-012
+ cgs=3e-012
+ fc=0.5
+ kf=0
+ af=1
+ tnom=35
*
.model DBREAK d
+ bv=43
+ rs=1
*
.model PNP_MIRROR pnp
+ is=4e-015
+ bf=150
+ va=50
+ ik=0.138
+ rb=0.01
+ re=0.101
+ rc=180
+ cje=1.34e-012
+ cjc=4.4e-013
+ kf=0
+ af=1
*
.model DN D(KF=6.69e-12 AF=1)
.MODEL DX D(IS=1E-12 Rs=0.1)
.MODEL DY D(IS=1E-15 BV=50 Rs=1)
.ends ISL28110subckt
FIGURE 45. SPICE NET LIST
18
FN6639.1
December 8, 2010
ISL28110, ISL28210
Characterization vs Simulation Results
1000
VS = ±18V
INPUT NOISE VOLTAGE
100
100
10
10
1
0.1
1
10
100
1k
FREQUENCY (Hz)
1000
INPUT NOISE VOLTAGE (nV/√Hz)
INPUT NOISE VOLTAGE (nV/√Hz)
1000
INPUT NOISE VOLTAGE
100
1
100k
10k
FIGURE 46. CHARACTERIZED INPUT NOISE VOLTAGE
10
RF = 100kΩ, RG = 100Ω
20
10
0
60
RF = 100kΩ, RG = 1kΩ
ACL = 100
10
100
1k
FREQUENCY (Hz)
VS = ±5V & ±15V
CL = 4pF
RL = OPEN
VOUT = 100mVP-P
ACL = 10
RF = 100kΩ, RG = 10kΩ
40
30
20
0
RF = 0, RG = ∞
10k
100k
1M
10M
VS = ±5V & ±15V
CL = 4pF
RL = OPEN
VOUT = 100mVP-P
ACL = 10
RF = 100kΩ, RG = 10kΩ
ACL = 1
-10
1k
100M
RF = 0, RG = ∞
10k
100k
1M
10M
100M
FREQUENCY (Hz)
FIGURE 48. CHARACTERIZED CLOSED LOOP GAIN vs
FREQUENCY
FIGURE 49. SIMULATED CLOSED LOOP GAIN vs
FREQUENCY
0.15
0.15
VS = ±15V
0.10 AV = 1
RL = 2k
CL = 4pF
0.05
VS = ±15V
AV = 1
RL = 2k
CL = 4pF
0.10
VOUT (V)
0.05
VOUT (V)
100k
RF = 100kΩ, RG = 1kΩ
FREQUENCY (Hz)
0
0
-0.05
-0.05
-0.10
-0.10
-0.15
10k
RF = 100kΩ, RG = 100Ω
ACL = 100
10
ACL = 1
-10
1k
ACL = 1000
50
GAIN (dB)
GAIN (dB)
30
1
70
ACL = 1000
50
40
0.1
FIGURE 47. SIMULATED INPUT NOISE VOLTAGE
70
60
VS = ±18V
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1.0
TIME (µs)
FIGURE 50. CHARACTERIZED SMALL SIGNAL
TRANSIENT RESPONSE vs RL, VS = ±0.9V,
±2.5V
19
-0.15
0
0.2
0.4
0.6
0.8
1.0
TIME (µs)
FIGURE 51. SIMULATED SMALL SIGNAL TRANSIENT
RESPONSE vs RL, VS = ±0.9V, ±2.5V
FN6639.1
December 8, 2010
ISL28110, ISL28210
Characterization vs Simulation Results (Continued)
6
6
VS = ±15V
AV = 1
RL = 2k
CL = 4pF
4
2
VOUT (V)
VOUT (V)
2
0
0
-2
-2
-4
-4
-6
0
1
2
VS = ±15V
AV = 1
RL = 2k
CL = 4pF
4
3
4
5
6
7
8
9
-6
10
0
2
4
TIME (µs)
PHASE
GAIN
100
1k
10k 100k 1M 10M 100M 1G
200
180
160
140
120
100
80
60
40
20
0
-20
-40
-60 VS = ±15V
-80 RL=1MΩ
-100
0.1
1
10
FREQUENCY (Hz)
1M
10M
FIGURE 56. SIMULATED (DESIGN) CMRR
20
CMRR (dB)
PHASE
GAIN
100
1k
10k 100k 1M 10M 100M 1G
FIGURE 55. SIMULATED (SPICE) OPEN-LOOP GAIN,
PHASE vs FREQUENCY
CMRR (dB)
100
1k
10k 100k
FREQUENCY (Hz)
10
FREQUENCY (Hz)
FIGURE 54. SIMULATED (DESIGN) OPEN-LOOP GAIN,
PHASE vs FREQUENCY
130
120
110
100
90
80
70
60
50
40
30
20 VS = ±15V
10 SIMULATION
0
0.1
1
10
8
FIGURE 53. SIMULATED LARGE SIGNAL TRANSIENT
RESPONSE vs RL, VS = ±0.9V, ±2.5V
GAIN (dB)
GAIN (dB)
FIGURE 52. CHARACTERIZED LARGE SIGNAL
TRANSIENT RESPONSE vs RL, VS = ±0.9V,
±2.5V
200
180
160
140
120
100
80
60
40
20
0
-20
-40
-60 VS = ±15V
-80 RL=1MΩ
-100
0.1
1
10
6
TIME (µs)
100M
130
120
110
100
90
80
70
60
50
40
30
20 VS = ±15V
10 SIMULATION
0
0.1
1
10
100
1k
10k 100k
FREQUENCY (Hz)
1M
10M
100M
FIGURE 57. SIMULATED (SPICE) CMRR
FN6639.1
December 8, 2010
ISL28110, ISL28210
Characterization vs Simulation Results (Continued)
15V
OUTPUT VOLTAGE SWING (V)
5.0
10V
5V
0V
0
-5V
-10V
VS = ±5V
-15V
-5.0
0
0.2
0.4
0.6
0.8
1.0
TIME (m s)
FIGURE 58. SIMULATED OUTPUT VOLTAGE SWING ±5V
21
0
0.2
0.4
0.6
0.8
1.0
TIME (m s)
FIGURE 59. SIMULATED OUTPUT VOLTAGE SWING ±15V
FN6639.1
December 8, 2010
ISL28110, ISL28210
Revision History
The revision history provided is for informational purposes only and is believed to be accurate, but not warranted. Please go to
web to make sure you have the latest Rev.
DATE
REVISION
11/29/10
FN6639.1
11/23/10
CHANGE
Removed label on right side of characterization curve, Figure 46 (Input Noise Current).
Page 1 Updated Trademark statement
Page 3 Ordering Information: Removed "coming soon" from ISL28110FBZ
Page 4 Electrical Specifications: Added ISL28110 IB and IOS specs @ VS=±5V.
Page 5 Electrical Specifications: Changed AVOL limits fro V/mV to dB
Page 5 Electrical Specifications, Dynamic Performance, Slew Rate: Added "4V Step" to
conditions; changed TYP limit from 23V/µs to 20V/µs
Page 6 Electrical Specifications, Dynamic Performance, Slew Rate:
Added "10V Step" to conditions; changed TYP limit from 23V/µs to 20V/µs
Page 6 Electrical Specifications: Added ISL28110 IB and IOS specs @ VS= ±15V.
Changed AVOL limits from V/mV to dB. Changed ts, settling time to 0.1% from 0.9µs to 1.3µs
and changed ts, settling time to 0.01% from 1.2µs to 1.6µs.
Page 7 Replaced Elect Spec table Notes 8 & 9 (Note 8 "Parameters with MIN and/or MAX limits
are 100% tested at +25°C, unless otherwise specified. Temperature limits established by
characterization and are not production tested./Note 9 Limits established by characterization
and are not production tested.)" With: "Compliance to datasheet limits is assured by one or
more methods: production test, characterization and/or design."
Page 8 Characteristic Curves: Added ISL28110 IB vs Temperature (Fig 4)
Page 8 Characteristic Curves: Added ISL28110 IOS vs Temperature (Fig 6)
Pages 17-21: Added PSPICE model section
9/13/10
FN6639.0
Initial Release.
Products
Intersil Corporation is a leader in the design and manufacture of high-performance analog semiconductors. The Company's products
address some of the industry's fastest growing markets, such as, flat panel displays, cell phones, handheld products, and notebooks.
Intersil's product families address power management and analog signal processing functions. Go to www.intersil.com/products for a
complete list of Intersil product families.
*For a complete listing of Applications, Related Documentation and Related Parts, please see the respective device information page on
intersil.com: ISL28110, ISL28210
To report errors or suggestions for this datasheet, please go to www.intersil.com/askourstaff
FITs are available from our website at http://rel.intersil.com/reports/search.php
For additional products, see www.intersil.com/product_tree
Intersil products are manufactured, assembled and tested utilizing ISO9000 quality systems as noted
in the quality certifications found at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications
at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by
Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any
infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any
patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
22
FN6639.1
December 8, 2010
ISL28110, ISL28210
Package Outline Drawing
L8.3x3A
8 LEAD THIN DUAL FLAT NO-LEAD PLASTIC PACKAGE
Rev 4, 2/10
( 2.30)
3.00
( 1.95)
A
B
3.00
( 8X 0.50)
6
PIN 1
INDEX AREA
(4X)
(1.50)
( 2.90 )
0.15
PIN 1
TOP VIEW
(6x 0.65)
( 8 X 0.30)
TYPICAL RECOMMENDED LAND PATTERN
SEE DETAIL "X"
2X 1.950
PIN #1
INDEX AREA
0.10 C
0.75 ±0.05
6X 0.65
C
0.08 C
1
SIDE VIEW
6
1.50 ±0.10
8
8X 0.30 ±0.05
8X 0.30 ± 0.10
2.30 ±0.10
C
4
0.10 M C A B
0 . 2 REF
5
0 . 02 NOM.
0 . 05 MAX.
DETAIL "X"
BOTTOM VIEW
NOTES:
1.
Dimensions are in millimeters.
Dimensions in ( ) for Reference Only.
2.
Dimensioning and tolerancing conform to ASME Y14.5m-1994.
3.
Unless otherwise specified, tolerance : Decimal ± 0.05
4.
Dimension applies to the metallized terminal and is measured
between 0.15mm and 0.20mm from the terminal tip.
5.
Tiebar shown (if present) is a non-functional feature.
6.
The configuration of the pin #1 identifier is optional, but must be
located within the zone indicated. The pin #1 identifier may be
7.
Compliant to JEDEC MO-229 WEEC-2 except for the foot length.
either a mold or mark feature.
23
FN6639.1
December 8, 2010
ISL28110, ISL28210
Package Outline Drawing
M8.118
8 LEAD MINI SMALL OUTLINE PLASTIC PACKAGE
Rev 3, 3/10
5
3.0±0.05
A
DETAIL "X"
D
8
1.10 MAX
SIDE VIEW 2
0.09 - 0.20
4.9±0.15
3.0±0.05
5
0.95 REF
PIN# 1 ID
1
2
B
0.65 BSC
GAUGE
PLANE
TOP VIEW
0.55 ± 0.15
0.25
3°±3°
0.85±010
H
DETAIL "X"
C
SEATING PLANE
0.25 - 0.036
0.08 M C A-B D
0.10 ± 0.05
0.10 C
SIDE VIEW 1
(5.80)
NOTES:
(4.40)
(3.00)
1. Dimensions are in millimeters.
(0.65)
(0.40)
(1.40)
TYPICAL RECOMMENDED LAND PATTERN
24
2. Dimensioning and tolerancing conform to JEDEC MO-187-AA
and AMSEY14.5m-1994.
3. Plastic or metal protrusions of 0.15mm max per side are not
included.
4. Plastic interlead protrusions of 0.15mm max per side are not
included.
5. Dimensions are measured at Datum Plane "H".
6. Dimensions in ( ) are for reference only.
FN6639.1
December 8, 2010
ISL28110, ISL28210
Package Outline Drawing
M8.15E
8 LEAD NARROW BODY SMALL OUTLINE PLASTIC PACKAGE
Rev 0, 08/09
4
4.90 ± 0.10
A
DETAIL "A"
0.22 ± 0.03
B
6.0 ± 0.20
3.90 ± 0.10
4
PIN NO.1
ID MARK
5
(0.35) x 45°
4° ± 4°
0.43 ± 0.076
1.27
0.25 M C A B
SIDE VIEW “B”
TOP VIEW
1.75 MAX
1.45 ± 0.1
0.25
GAUGE PLANE
C
SEATING PLANE
0.10 C
0.175 ± 0.075
SIDE VIEW “A
0.63 ±0.23
DETAIL "A"
(0.60)
(1.27)
NOTES:
(1.50)
(5.40)
1.
Dimensions are in millimeters.
Dimensions in ( ) for Reference Only.
2.
Dimensioning and tolerancing conform to AMSE Y14.5m-1994.
3.
Unless otherwise specified, tolerance : Decimal ± 0.05
4.
Dimension does not include interlead flash or protrusions.
Interlead flash or protrusions shall not exceed 0.25mm per side.
5.
The pin #1 identifier may be either a mold or mark feature.
6.
Reference to JEDEC MS-012.
TYPICAL RECOMMENDED LAND PATTERN
25
FN6639.1
December 8, 2010