M65667FP Picture-in-Picture Signal Processing REJ03F0185-0201 Rev.2.01 Mar 31, 2008 Description The M65667FP is a NTSC PIP (Picture in Picture) signal processing LSI, whose sub and main-picture inputs are composite and Y/C separated signals, respectively. The built-in field memory (96 Kbit RAM), V-chip data slicer and analog circuitries lead the PIP system low cost and small size. Features • • • • • Built-in 96 Kbit field memory (sub-picture data storage) Internal V-chip data slicer (for sub-picture) Vertical filter for sub-picture (Y signal) Single sub-picture (selectable picture size: 1/9, 1/16) Sub-picture processing specification (1/9 size / 1/16 size) Quantization bits Y, B-Y, R-Y: 6 bits Horizontal sampling 171 pixels (Y), 28.5 pixels (B-Y, R-Y) Vertical lines 69/52 lines • Frame (sub-picture) on/off • Built-in analog circuits Two 8-bit A/D converters (main and sub-picture signals) Two 8-bit D/A converters (Y and C sub-picture signals) Sync-tip-clamp, VCXO, Analog switch, etc. • I2C BUS control (parallel/serial control) PIP on/off, Sub-picture size (1/9 or 1/16), Frame on/off (programmable luma level), PIP position (4 corners fixed position), Picture freeze, Y delay adjustment, Chroma level, Tint, Black level, Contrast, etc. Application NTSC color TV Recommended Operating Condition Supply voltage range …………………………… 3.1 to 3.5 V Operating frequency …………………………… 14.32 MHz Operating temperature ………………………… –20 to 75°C Input voltage (CMOS interface) "H" …………… Vdd ± 0.7 to Vdd V "L" …………… 0 to Vdd ± 0.3 V Output current (output buffer) ………………… 4 mA (Max) Output load capacitance ……………………… 20 pF (Max) Note2 Circuit current ………………………………… 160 mA Notes: 1. Connect a 0.1 µF or larger capacitor between Vdd and Vss pins. 2. Include pin capacitance (7 pF) REJ03F0185-0201 Rev.2.01 Mar 31, 2008 Page 1 of 12 M65667FP Block Diagram SCK CSYNC (s) /TEST1 BGP (s) /TEST0 Yin Y-PlP Sync tip clamp Cin Vdd/Vss 15 For test 3 DATA CLK ACK Vin (s) 3 Vrt (m) Vrb (m) Bias C-PlP RAM (1H) V-chip data slicer I2C I/F Y Delay Luma clamp Y A/D 8 bit Sync tip clamp Bias 6 Back porch clamp Y/C SEP (LPF, BPF) Sync sep 2 Phase select HD C Demod Tint B-Y 6 R-Y 6 SWMG /TEST7 2 HPLL Yout-sub Y B-Y R-Y 4 fsc Delay D/A 8 bit Delay Delay Cout-sub Encode MIX D/A 8 bit Vrt (m) Vrb (m) fsc Y 6 B-Y Timing gen (Memory cont) RAM 96 Kbits VD /CSYNC /TEST6 6 R-Y HD /TEST5 Level detect ADJ-Csub Vin (m) LPF &MPY 6 Demux (I C) ADJ-Ysub Bias A/D 8 bit FILTER BIAS Phase detect Burst data sampling 4 fsc Lock/Free-run via I2C 2 RESET MCK REJ03F0185-0201 Rev.2.01 Mar 31, 2008 Page 2 of 12 Y-PlPin Vert-filter & MUX Timing gen (Decode) AFC C-PlPin BGP (m) /TEST2 fsc /TEST3 SWM /TEST4 VCXO driver VCXO in VCXO VCXO out M65667FP Pin Arrangement 33 NC 34 LOCK/TEST7 35 DVdd3 36 DVss3 37 Cout-sub 38 ADJ-Csub 39 Yout-sub 40 ADJ-Ysub 41 Y-PlPin 42 AVss4 (da) 43 AVss4 (da) 44 C-PlPin 45 AVdd4 (da) 46 AVdd4 (da) 47 AVdd4 (da) 48 C-PlP M65667FP NC 49 32 NC TEST8 50 31 VD/CSYNC/TEST6 Y-PlP 51 30 HD/TEST5 TEST9 52 29 SWM/TEST4 Yin 53 28 MCK TESTEN 54 27 fsc/TEST3 Cin 55 26 BGP (m)/TEST2 AVss (ana) 56 25 DVdd2 (ram) AVss3 (vcxo) 57 24 DVss2 (ram) VCXO out 58 23 CLK VCXO in 59 22 DATA FILTER 60 21 ACK BIAS 61 20 CSYNC (s)/TEST1 AVdd3 (vcxo) 62 19 SCK (Top view) Outline: PRQP0064GA-A (64P6N-A) REJ03F0185-0201 Rev.2.01 Mar 31, 2008 Page 3 of 12 NC 16 DVss1 14 DVdd1 15 RESET 13 AVss1 (s) 12 AVss1 (s) 11 Vrb (s) 10 Vrt (s) 9 Vin (s) 8 AVdd1 (s) 7 AVdd1 (s) 6 AVss2 (m) 5 Vrb (m) 3 AVss2 (m) 4 17 NC Vrt (m) 2 18 BGP (s)/TEST0 AVdd2 (m) 64 Vin (m) 1 AVdd2 (m) 63 NC: No connection M65667FP Pin Description Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 Name Vin (m) Vrt (m) Vrb (m) AVss2 (m) AVss2 (m) AVdd1 (s) AVdd1 (s) Vin (s) Vrt (s) Vrb (s) AVss1 (s) AVss1 (s) RESET I/O I O O GND GND Vdd Vdd I O O GND GND I Function Chroma signal input (main-picture) A/D Vref+ (main-picture) A/D Vref– (main-picture) Connect to analog GND Connect to analog GND Connect to analog power supply Connect to analog power supply Composite video signal input (sub-picture) A/D Vref+ (sub-picture) A/D Vref– (sub-picture) Connect to analog GND Connect to analog GND Power on reset input signal ("L" reset) 14 DVss1 GND Connect to digital GND 15 16 DVdd1 NC Vdd — Connect to digital power supply No connection 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 NC BGP (s) /TEST0 SCK CSYNC (s) /TEST1 ACK DATA CLK DVss2 (ram) DVdd2 (ram) BGP (m) /TEST2 fsc/TEST3 MCK SWM/TEST4 HD/TEST5 VD/CSYNC/TEST6 NC NC SWMG/TEST7 DVdd3 — (I/) O I I (/O) O I I GND Vdd (I/) O I (/O) I (I/) O I (/O) I (/O) — — I (/O) Vdd No connection For test For test (connect to digital GND) For test (connect to digital GND) I2C bus-data/Acknowledge output signal I2C bus-data input signal I2C bus-clock input signal Connect to digital GND Connect to digital power supply For test For test (pull down to digital GND by resistor 15 kΩ) For test (connect to digital GND) For test Horizontal sync input signal (Positive going edge is used) Vertical sync input signal (active "H") No connection No connection Enable input signal to display sub picture ("H" enable) Connect to digital power supply 36 37 38 39 40 41 42 43 44 45 46 47 48 DVss3 Cout-sub ADJ-Csob Yout-sub ADJ-Ysub Y-PIPin AVss4 (da) AVss4 (da) C-PIPin AVdd4 (da) AVdd4 (da) AVdd4 (da) C-PIP GND O I O I I GND GND I Vdd Vdd Vdd O Connect to digital GND D/A output signal (Chroma signal of sub-picture) D/A adjust for chroma signal (sub-picture) D/A output signal (Luma signal of sub-picture) D/A adjust for luma signal (sub-picture) PIP luma signal re-input Connects to analog GND Connects to analog GND PIP chroma signal re-input Connect to analog power supply Connect to analog power supply Connect to analog power supply PIP chroma signal output REJ03F0185-0201 Rev.2.01 Mar 31, 2008 Page 4 of 12 Remarks 100 kΩ to Vdd, 10 µF to GND Non connect Connect to GND Pull down 15 kΩ Non connect Pull down 15 kΩ Connect to GND Non connect Pull down 15 kΩ M65667FP Pin Description (cont.) Pin No. 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 Name NC TEST8 Y-PIP TEST9 Yin TESTEN Cin AVss (ana) AVss3 (vcxo) VCXO out VCXO in FILTER BIAS AVdd3 (vcxo) AVdd2 (m) AVdd2 (m) I/O — I O I I I I GND GND O I I O Vdd Vdd Vdd Function No connection For test (connect to analog GND) PIP luma signal output For test (connect to analog GND) Luma input signal (main-picture) For test (connect to analog GND) Chroma input signal (main-picture) Connect to analog GND Connects to analog GND VCXO output signal VCXO input signal Filter Bias Connect to analog power supply Connect to analog power supply Connect to analog power supply REJ03F0185-0201 Rev.2.01 Mar 31, 2008 Page 5 of 12 Remarks Pull up 15 kΩ Connect to GND Connect to GND M65667FP Absolute Maximum Ratings (Vss = 0 V) Limits Min Max Unit Supply voltage (3.3 V) Input voltage Output voltage Output current Note1 Item VDD3 VI VO IO –0.3 –0.3 –0.3 — V V V mA Power dissipation Operating temperature Storage temperature Pd Topr Tstg — –20 –50 4.6 VDD3 + 0.3 VDD3 + 0.3 IOL = 20 IOH = –26 1400 75 125 Note: Symbol 1. Output current per output terminal. But Pd limits all current. Thermal Derating (Maximum Rating) Power Dissipation Pd (mW) 2000 1600 1280 1200 800 400 0 0 25 50 75 100 Ambient Temperature Ta (°C) REJ03F0185-0201 Rev.2.01 Mar 31, 2008 Page 6 of 12 125 mW °C °C M65667FP DC Characteristics (Ta = 25°C, unless otherwise noted, Vss = 0 V) Item Symbol Input voltage (CMOS interface) Min Limits Typ Max Unit — — — — — — — — — — — — — 7 7 7 0.81 3.6 1.65 2.4 1.2 0.05 — — –4 1 1 1 1 15 15 15 V V V V V V V mA mA µA µA µA µA pF pF pF — 140 mA L H – + VIL VIH VT– VT+ Hysteresis L H L H L H L H Input pin capacitance Output pin capacitance Bidirectional pin capacitance VH VOL VOH IOL IOH IIL IIH IOZL IOZH CI CO CIO 0 2.52 0.5 1.4 0.3 — 3.25 4 — –1 –1 –1 –1 — — — Operating current 3.3 V supply IDD — Input voltage schmitt trigger (CMOS interface) Output voltage Output current Input current Output leakage current REJ03F0185-0201 Rev.2.01 Mar 31, 2008 Page 7 of 12 Test Conditions VDD = 2.7 V VDD = 3.6 V VDD = 3.3V VDD = 3.3 V, |IO| < 1 µA VDD = 3.0 V, VOL = 0.4 V VDD = 3.0 V, VOH = 2.6 V VDD = 3.6 V, VI = 0 V VDD = 3.6 V, VI = 3.6 V VDD = 3.6 V, VO = 0 V VDD = 3.6 V, VO = 3.6 V f = 1 MHz, VDD = 0 V M65667FP PIP TV System Block Diagram (BASIC) Composite video signal Y/C Separation Y Y M65667FP Y C C C BLPLL B-LD Y/C separated video signal Y C CV + PIP signal processing Y Video signal processing Deflection unit Yoke C HD VD Driving Method and Operating Specification for Serial Interface Data (1) Serial data transmission completion and start A low-to-high transition of the DATA (serial data) line while the CLK (serial clock) is high, that completes the serial transmission and makes the bus free. A high-to-low transition of the DATA line while the CLK is high, that starts the serial transmission and waits for the following CLK and DATA inputs. (2) Serial data transmission The data are transmitted in the most significant bit (MSB) first by one-byte unit on the DATA line successively. One-byte data transmission is completed by 9 clock cycles, the former 8 cycles are for address/data and the latter one is for acknowledge detection. (In reading state, ACK is "H" under these two conditions; 1. The coincidence of two address data for the address data transmission. 2. The completion of 8-bit setting data transfer. In writing state, ACK is "H" with the address coincidence and ACK is "L" for detecting acknowledge input from the master (micro processor) after sending 8-bit setting data). For address/data transmission, DATA must change while CLK is "L". (The data change while CLK is "H" or the simultaneous change of CLK and DATA, that will be a false operation because of undistinguished condition from the completion/start of serial data transfer.) After the beginning of serial data transmission, the total number of data bytes that can be transferred are not limited. (3) The byte format of data transmission (The sequence of data transmission) 1. The byte format during data setting to M65667FP are shown as follows. In right after the forming of serial data transmitting state, the slave address 24h (00100100b) is transferred. Afterwards, the internal register address (1 byte) and setting data (by 1 byte unit) are transferred successively. Several bytes of setting data can be handled in the one transmission. In this operation, the setting data are written into the address resister whose address is increased one in initially transferred internal register address. (The next address of 7Fh, it returns to 00h.) 2. The byte format during data reading from M65667FP are shown as follows. Before data reading from M65667FP, whose internal address need to be set by the data reading/transmitting. After the data reading/transmitting, the operation of "serial data transmission completion and start" (described in (1)) is necessary. Continuously, the slave address 25h (00100101b) is sent, and then the inverted read out data are available on ACK. Several bytes of writing data can be handled in the one transmission, too. In this operation, the setting data also are written into the address register whose address is increased one in initially transferred internal register address. (The next address of 7Fh, it returns to 00h.) REJ03F0185-0201 Rev.2.01 Mar 31, 2008 Page 8 of 12 M65667FP The Examples of Serial Byte Transmission Format (1) The writing operation of the setting data (AAh) into M65667FP internal address of 00h Confirmation of bus free (DATA = 'H') Transmission activation Yes S 24h A 00h A AAh A D E No S: Operation of serial transmission start A: Acknowledge detection D: Dummy clock feed for the release of acknowledge output state E: Operation of serial transmission completion is applied on CLK for the release of output state (2) The writing operation of the setting data (FFh, 80h, EEh) into M65667FP internal address of 04h to 06h Transmission activation Confirmation of bus free (DATA = 'H') Yes S 24h A 04h A FFh A 80h A EEh A D E No is applied on CLK for the release of output state (3) The reading operation of the setting data from M65667FP internal address of 00h Transmission activation Confirmation of bus free (DATA = 'H') Yes S 24h A 00h A D E S 25h A $$h A No A: Bus free operation by the master (micro processor) is applied on CLK for the release of output state (4) The reading operation of the setting data from M65667FP internal address of 04h to 06h Transmission activation Confirmation of bus free (DATA = 'H') Yes S 24h A 04h A D E S 25h A $$h A No is applied on CLK for the release of output state REJ03F0185-0201 Rev.2.01 Mar 31, 2008 Page 9 of 12 A: Output L operation by the master (micro processor) $$h A $$h A M65667FP Timing Diagram (1) (2) (3) (4) (5) (6) (7) (8) (9) (1) CLK DATA Bit7 (MSB) Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 (LSB) Bit7 (MSB) Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 (LSB) ACK Detec. Bit7 (MSB) ACK _Acknowledge ACK _Readout data REJ03F0185-0201 Rev.2.01 Mar 31, 2008 Page 10 of 12 Bit7 (MSB) M65667FP 10 µF + 150 pF Dig 360 Ω 10 µF 48 15 kΩ Ana. PIP Luma signal output Luma signal input (main-picture) 104 F 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 49 32 50 31 51 30 52 29 53 28 54 27 104 F 55 26 51 Ω 14 pF 104 F 330 Ω 103 F 470 kΩ 25 M65667FP 57 24 58 23 59 22 60 21 + 10 µF 3.3 µF 100 kΩ 61 20 62 19 63 18 103 F 100 Ω SCL Dig 5 V 12 kΩ SDA 47 kΩ 10 µF 10 kΩ Dig 5 V 100 Ω 12 kΩ 100 Ω 47 kΩ Digital +3.3 V power supply 3 4 5 6 7 8 9 10 11 12 13 14 15 16 + + 103 F 103 F 10 µF 10 µF 103 F 103 F Ana. Ana. 104 F 100 kΩ + 103 F 103 F Analog +3.3 V power supply Composite video input signal (sub-picture) 2 104 F Digital GND Analog GND 560 Ω 330 Ω 17 1 Note: Dig 2 kΩ 64 Ana. 10 kΩ + 56 Ana. 103 F 104 F 15 kΩ Chroma input signal (main-picture) 103 F 103 F + 103 F 103 F 104 F 10 µF Dig SYNC SEP Circuit (Optional) + Separate Y/C signals by using LC-tank circuit or LPF, BPF for Y/C signals level adjust. And then mix both signals for sub-picture input video signal. REJ03F0185-0201 Rev.2.01 Mar 31, 2008 Page 11 of 12 I2C BUS DATA input/output signal Ana. Ana. I2C BUS Clock input signal 470 Ω 68 pF Horizontal sync input signal (main-picture) Ana. Vertical sync input signal (main-picture) Sub-picture displaying on/off PIP Chroma signal output Application Example M65667FP Package Dimensions JEITA Package Code P-QFP64-14x14-0.80 RENESAS Code PRQP0064GA-A Previous Code 64P6N-A MASS[Typ.] 1.1g HD *1 D 48 33 49 32 *2 E HE NOTE) 1. DIMENSIONS "*1" AND "*2" DO NOT INCLUDE MOLD FLASH. 2. DIMENSION "*3" DOES NOT INCLUDE TRIM OFFSET. 17 1 ZD ZE Reference Symbol 64 16 c A2 Index mark A A1 F L Detail F e y D E A2 HD HE A A1 bp c *3 b p REJ03F0185-0201 Rev.2.01 Mar 31, 2008 Page 12 of 12 e y ZD ZE L Dimension in Millimeters Min Nom Max 13.8 14.0 14.2 13.8 14.0 14.2 2.8 16.5 16.8 17.1 16.5 16.8 17.1 3.05 0.1 0.2 0 0.3 0.35 0.45 0.13 0.15 0.2 0° 10° 0.65 0.8 0.95 0.10 1.0 1.0 0.4 0.6 0.8 Sales Strategic Planning Div. Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100-0004, Japan Notes: 1. This document is provided for reference purposes only so that Renesas customers may select the appropriate Renesas products for their use. Renesas neither makes warranties or representations with respect to the accuracy or completeness of the information contained in this document nor grants any license to any intellectual property rights or any other rights of Renesas or any third party with respect to the information in this document. 2. Renesas shall have no liability for damages or infringement of any intellectual property or other rights arising out of the use of any information in this document, including, but not limited to, product data, diagrams, charts, programs, algorithms, and application circuit examples. 3. You should not use the products or the technology described in this document for the purpose of military applications such as the development of weapons of mass destruction or for the purpose of any other military use. When exporting the products or technology described herein, you should follow the applicable export control laws and regulations, and procedures required by such laws and regulations. 4. All information included in this document such as product data, diagrams, charts, programs, algorithms, and application circuit examples, is current as of the date this document is issued. Such information, however, is subject to change without any prior notice. Before purchasing or using any Renesas products listed in this document, please confirm the latest product information with a Renesas sales office. Also, please pay regular and careful attention to additional and different information to be disclosed by Renesas such as that disclosed through our website. (http://www.renesas.com ) 5. Renesas has used reasonable care in compiling the information included in this document, but Renesas assumes no liability whatsoever for any damages incurred as a result of errors or omissions in the information included in this document. 6. When using or otherwise relying on the information in this document, you should evaluate the information in light of the total system before deciding about the applicability of such information to the intended application. Renesas makes no representations, warranties or guaranties regarding the suitability of its products for any particular application and specifically disclaims any liability arising out of the application and use of the information in this document or Renesas products. 7. With the exception of products specified by Renesas as suitable for automobile applications, Renesas products are not designed, manufactured or tested for applications or otherwise in systems the failure or malfunction of which may cause a direct threat to human life or create a risk of human injury or which require especially high quality and reliability such as safety systems, or equipment or systems for transportation and traffic, healthcare, combustion control, aerospace and aeronautics, nuclear power, or undersea communication transmission. If you are considering the use of our products for such purposes, please contact a Renesas sales office beforehand. Renesas shall have no liability for damages arising out of the uses set forth above. 8. Notwithstanding the preceding paragraph, you should not use Renesas products for the purposes listed below: (1) artificial life support devices or systems (2) surgical implantations (3) healthcare intervention (e.g., excision, administration of medication, etc.) (4) any other purposes that pose a direct threat to human life Renesas shall have no liability for damages arising out of the uses set forth in the above and purchasers who elect to use Renesas products in any of the foregoing applications shall indemnify and hold harmless Renesas Technology Corp., its affiliated companies and their officers, directors, and employees against any and all damages arising out of such applications. 9. You should use the products described herein within the range specified by Renesas, especially with respect to the maximum rating, operating supply voltage range, movement power voltage range, heat radiation characteristics, installation and other product characteristics. Renesas shall have no liability for malfunctions or damages arising out of the use of Renesas products beyond such specified ranges. 10. Although Renesas endeavors to improve the quality and reliability of its products, IC products have specific characteristics such as the occurrence of failure at a certain rate and malfunctions under certain use conditions. Please be sure to implement safety measures to guard against the possibility of physical injury, and injury or damage caused by fire in the event of the failure of a Renesas product, such as safety design for hardware and software including but not limited to redundancy, fire control and malfunction prevention, appropriate treatment for aging degradation or any other applicable measures. Among others, since the evaluation of microcomputer software alone is very difficult, please evaluate the safety of the final products or system manufactured by you. 11. In case Renesas products listed in this document are detached from the products to which the Renesas products are attached or affixed, the risk of accident such as swallowing by infants and small children is very high. You should implement safety measures so that Renesas products may not be easily detached from your products. Renesas shall have no liability for damages arising out of such detachment. 12. This document may not be reproduced or duplicated, in any form, in whole or in part, without prior written approval from Renesas. 13. Please contact a Renesas sales office if you have any questions regarding the information contained in this document, Renesas semiconductor products, or if you have any other inquiries. http://www.renesas.com RENESAS SALES OFFICES Refer to "http://www.renesas.com/en/network" for the latest and detailed information. Renesas Technology America, Inc. 450 Holger Way, San Jose, CA 95134-1368, U.S.A Tel: <1> (408) 382-7500, Fax: <1> (408) 382-7501 Renesas Technology Europe Limited Dukes Meadow, Millboard Road, Bourne End, Buckinghamshire, SL8 5FH, U.K. Tel: <44> (1628) 585-100, Fax: <44> (1628) 585-900 Renesas Technology (Shanghai) Co., Ltd. Unit 204, 205, AZIACenter, No.1233 Lujiazui Ring Rd, Pudong District, Shanghai, China 200120 Tel: <86> (21) 5877-1818, Fax: <86> (21) 6887-7858/7898 Renesas Technology Hong Kong Ltd. 7th Floor, North Tower, World Finance Centre, Harbour City, Canton Road, Tsimshatsui, Kowloon, Hong Kong Tel: <852> 2265-6688, Fax: <852> 2377-3473 Renesas Technology Taiwan Co., Ltd. 10th Floor, No.99, Fushing North Road, Taipei, Taiwan Tel: <886> (2) 2715-2888, Fax: <886> (2) 3518-3399 Renesas Technology Singapore Pte. Ltd. 1 Harbour Front Avenue, #06-10, Keppel Bay Tower, Singapore 098632 Tel: <65> 6213-0200, Fax: <65> 6278-8001 Renesas Technology Korea Co., Ltd. Kukje Center Bldg. 18th Fl., 191, 2-ka, Hangang-ro, Yongsan-ku, Seoul 140-702, Korea Tel: <82> (2) 796-3115, Fax: <82> (2) 796-2145 Renesas Technology Malaysia Sdn. Bhd Unit 906, Block B, Menara Amcorp, Amcorp Trade Centre, No.18, Jln Persiaran Barat, 46050 Petaling Jaya, Selangor Darul Ehsan, Malaysia Tel: <603> 7955-9390, Fax: <603> 7955-9510 © 2008. Renesas Technology Corp., All rights reserved. Printed in Japan. Colophon .7.2