GAL26V12 - Lattice Semiconductor

GAL®26V12 Device Datasheet
September 2010
All Devices Discontinued!
Product Change Notifications (PCNs) have been issued to discontinue all devices in this
data sheet.
The original datasheet pages have not been modified and do not reflect those changes.
Please refer to the table below for reference PCN and current product status.
Product Line
GAL26V12
Ordering Part Number
GAL26V12C-10LP
GAL26V12C-15LP
GAL26V12C-20LP
GAL26V12C-10LPI
GAL26V12C-15LPI
GAL26V12C-20LPI
GAL26V12C-7LJ
GAL26V12C-10LJ
GAL26V12C-15LJ
GAL26V12C-20LJ
GAL26V12C-10LJI
GAL26V12C-15LJI
GAL26V12C-20LJI
Product Status
Reference PCN
PCN#06-07
Discontinued
PCN#13-10
5555 N.E. Moore Ct.  Hillsboro, Oregon 97124-6421  Phone (503) 268-8000  FAX (503) 268-8347
Internet: http://www.latticesemi.com
GAL26V12
High Performance E2CMOS PLD
Generic Array LogicTM
FEATURES
FUNCTIONAL BLOCK DIAGRAM
2
®
I/CLK 1
INPUT
PRESET
8
I/O/Q
OLMC 0
INPUT
8
OLMC 1
I/O/Q
OLMC 2
I/O/Q
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• LOW POWER CMOS
— 90 mA Typical Icc
10
INPUT/CLK 2
12
INPUT
INPUT
• TWELVE OUTPUT LOGIC MACROCELLS
— Maximum Flexibility for Complex Logic Designs
INPUT
• PRELOAD AND POWER-ON RESET OF REGISTERS
— 100% Functional Testability
INPUT
• APPLICATIONS INCLUDE:
— DMA Control
— State Machine Control
— High Speed Graphics Processing
— Standard Logic Speed Upgrade
OLMC 3
PROGRAMMABLE
AND-ARRAY
(150X52)
• E2 CELL TECHNOLOGY
— Reconfigurable Logic
— Reprogrammable Cells
— 100% Tested/Guaranteed 100% Yields
— High Speed Electrical Erasure (<100ms)
— 20 Year Data Retention
INPUT
14
OLMC 5
I/O/Q
OLMC 6
14
OLMC 7
12
OLMC 8
INPUT
10
OLMC 9
INPUT
8
OLMC 10
INPUT
DESCRIPTION
8
OLMC 11
INPUT
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/O/Q
RESET
PACKAGE DIAGRAMS
DIP
The generic architecture provides maximum design flexibility by
allowing the Output Logic Macrocell (OLMC) to be configured by
the user. The GAL26V12 is fully function/fuse map/parametric
compatible with other 26V12 devices.
I/CLK1
I
I
I/O/Q
II/CLK1
2
28
5
I/O/Q
7
GAL26V12
I
I
Top View
9
23
21
I
I/O/Q
I/O/Q
I/O/Q
19
18
16
I/O/Q
14
I
12
I
11
I
I
I/O/Q
26
I
VCC
I
I
I
I/O/Q
28
I/O/Q
I/CLK2
25
1
I
I/O/Q
4
I
I
PLCC
I
I/CLK2
Unique test circuitry and reprogrammable cells allow complete
AC, DC, and functional testing during manufacture. As a result,
LATTICE is able to guarantee 100% field programmability and
functionality of all GAL® products. LATTICE also guarantees 100
erase/rewrite cycles.
I/O/Q
16
• ELECTRONIC SIGNATURE FOR IDENTIFICATION
The GAL26V12, at 7.5ns maximum propagation delay time, combines a high performance CMOS process with Electrically Erasable (E2) floating gate technology to provide the highest performance available of any 26V12 device on the market. E2 technology offers high speed (<100ms) erase times, providing the ability
to reprogram or reconfigure the device quickly and efficiently.
OLMC 4
16
INPUT
I/O/Q
GAL
26V12
I
Vcc
7
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I
I/O/Q
I
GND
I
I/O/Q
I/O/Q
I
I/O/Q
I/O/Q
I
I/O/Q
21
I
I
GND
I/O/Q
I/O/Q
14
15
I/O/Q
Copyright ©2000 Lattice Semiconductor Corp. GAL, E2CMOS and UltraMOS are registered trademarks of Lattice Semiconductor Corp. Generic Array Logic is a trademark of Lattice Semiconductor Corp. The specifications herein are subject to change without notice.
LATTICE SEMICONDUCTOR CORP., 5555 N.E. Moore Ct., Hillsboro, Oregon 97124 U.S.A.
Tel. (503) 268-8000 or 1-800-LATTICE; FAX (503) 268-8556
November 2000
Select devices have been discontinued.
See Ordering Information section for product status.
• HIGH PERFORMANCE E CMOS TECHNOLOGY
— 7.5 ns Maximum Propagation Delay
— Fmax = 142.8 MHz
— 4.5 ns Maximum from Clock Input to Data Output
— TTL Compatible 16 mA Outputs
— UltraMOS® Advanced CMOS Technology
Specifications GAL26V12
GAL26V12 ORDERING INFORMATION
Commercial Grade Specifications
Tpd (ns)
Tsu (ns)
Tco (ns)
Icc (mA)
7.5
6
4.5
130
7
15
10
8
GAL26V12C-7LJ
28-Lead PLCC
1
28-Pin Plastic DIP
130
GAL26V12C-10LP
130
GAL26V12C-10LJ
28-Lead PLCC
105
GAL26V12C-15LP1
28-Pin Plastic DIP
105
GAL26V12C-15LJ
28-Lead PLCC
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7
Package
20
12
12
1
105
GAL26V12C-20LP
28-Pin Plastic DIP
105
GAL26V12C-20LJ
28-Lead PLCC
Industrial Grade Specifications
Tpd (ns)
Tsu (ns)
Tco (ns)
Icc (mA)
10
7
7
150
GAL26V12C-10LPI1
28-Pin Plastic DIP
150
GAL26V12C-10LJI
28-Lead PLCC
150
GAL26V12C-15LPI1
28-Pin Plastic DIP
150
GAL26V12C-15LJI
28-Lead PLCC
15
20
10
12
8
12
150
Ordering #
GAL26V12C-20LPI
150
Package
28-Pin Plastic DIP
1
28-Lead PLCC
GAL26V12C-20LJI
1. Discontinued per PCN #06-07. Contact Rochester Electronics for available inventory.
PART NUMBER DESCRIPTION
XXXXXXXX _ XX
X
X X
GAL26V12C Device Name
Grade
Speed (ns)
L = Low Power Power
Blank = Commercial
I = Industrial
Package P = Plastic DIP
J = PLCC
2
Select devices have been discontinued.
See Ordering Information section for product status.
10
Ordering #
Specifications GAL26V12
OUTPUT LOGIC MACROCELL (OLMC)
The GAL26V12 has a variable number of product terms per
OLMC. Of the ten available OLMCs, four OLMCs have access
to eight product terms (pins 15, 16, 26 and 27), two have ten product terms (pins 17 and 25), two have twelve product terms (pins
18 and 24), two have fourteen product terms (pins 19 and 23), and
two OLMCs have sixteen product terms (pins 20 and 22). In addition to the product terms available for logic, each OLMC has an
additional product-term dedicated to output enable control.
The output polarity of each OLMC can be individually programmed
to be true or inverting, in either combinatorial or registered mode.
This allows each output to be individually configured as either
active high or active low.
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The GAL26V12 has a product term for Asynchronous Reset (AR)
and a product term for Synchronous Preset (SP). These two
product terms are common to all registered OLMCs. The Asynchronous Reset sets all registers to zero any time this dedicated
product term is asserted. The Synchronous Preset sets all registers to a logic one on the rising edge of the next clock pulse after
this product term is asserted.
AR
D
Q
4 TO 1
MUX
Q
CLK1/
CLK2
NOTE: The AR and SP product terms will force the Q output of
the flip-flop into the same state regardless of the polarity of the
output. Therefore, a reset operation, which sets the register output
to a zero, may result in either a high or low at the output pin,
depending on the pin polarity chosen.
SP
2 TO 1
MUX
GAL26V12 OUTPUT LOGIC MACROCELL (OLMC)
OUTPUT LOGIC MACROCELL CONFIGURATIONS
COMBINATORIAL MODE
In combinatorial mode the pin associated with an individual OLMC
is driven by the output of the sum term gate. Logic polarity of the
output signal at the pin may be selected by specifying that the
output buffer drive either true (active high) or inverted (active low).
Output tri-state control is available as an individual product-term
for each output, and may be individually set by the compiler as
either “on” (dedicated output), “off” (dedicated input), or “productterm driven” (dynamic I/O).
Each of the Macrocells of the GAL26V12 has two primary functional modes: registered, and combinatorial I/O. The modes and
the output polarity are set by four architecture bits (S0, S1, S2 and
S3), which are normally controlled by the logic compiler. Each
of these two primary modes, and the bit settings required to enable
them, are described below and on the following page.
REGISTERED MODE
In registered mode the output pin associated with an individual
OLMC is driven by the Q output of that OLMC’s D-type flip-flop.
Logic polarity of the output signal at the pin may be selected by
specifying that the output buffer drive either true (active high) or
inverted (active low). Output tri-state control is available as an individual product-term for each OLMC, and can therefore be defined by a logic equation.
In combinatorial mode there are also two options for the feedback.
The first feedback option into the AND array is from the I/O pin
side of the output buffer. Both polarities (true and inverted) of the
pin are fed back into the AND array. The second option is to drive
the feedback from /Q of the buried register. This option provides
the combinatorial output with the ability to register the feedback
of the same combinatorial output.
There are two options for the feedback of the registered mode - internal /Q feedback and I/O pin feedback. The D flip-flop’s /Q
output is fed back into the AND array, with both the true and complement of the feedback available as inputs to the AND array.
Similarly the I/O pin feedback with both true and complement input
to the AND array. The resulting polarity depends on the input
polarity selection as well as the registered I/O output polarity
configuration.
3
Select devices have been discontinued.
See Ordering Information section for product status.
In the registered mode configuration the clock source for the
register can be selected. The two clock options, CLK1 and CLK2,
originate from input pin1 and pin4 respectively.
Specifications GAL26V12
REGISTERED MODE
AR
Q
D
A
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Q
CLK1/
CLK2
CLK1/
CLK2
Q
Q
SP
SP
ACTIVE HIGH REGISTERED OUTPUT
WITH BURIED FEEDBACK
ACTIVE LOW REGISTERED OUTPUT
WITH BURIED FEEDBACK
S0 = 0
S1 = 0
S3 = 1
S0 = 1
S1 = 0
S3 = 1
S2 = 1 Selects CLK1
S2 = 0 Selects CLK2
S2 = 1 Selects CLK1
S2 = 0 Selects CLK2
AR
AR
D
D
Q
CLK1/
CLK2
CLK1/
CLK2
Q
SP
Q
SP
ACTIVE LOW REGISTERED OUTPUT
WITH I/O FEEDBACK
S0 = 0
S1 = 0
S3 = 0
Q
ACTIVE HIGH REGISTERED OUTPUT
WITH I/O FEEDBACK
S2 = 1 Selects CLK1
S2 = 0 Selects CLK2
S0 = 1
S1 = 0
S3 = 0
4
S2 = 1 Selects CLK1
S2 = 0 Selects CLK2
Select devices have been discontinued.
See Ordering Information section for product status.
D
AR
Specifications GAL26V12
ACTIVE HIGH COMBINATORIAL OUTPUT
WITH I/O FEEDBACK
ACTIVE LOW COMBINATORIAL OUTPUT
WITH I/O FEEDBACK
S0 = 0
S1 = 1
S3 = 1
S0 = 1
S1 = 1
S3 = 1
S2 = 1 Selects CLK1
S2 = 0 Selects CLK2
S2 = 1 Selects CLK1
S2 = 0 Selects CLK2
AR
D
AR
Q
CLK1/
CLK2
D
CLK1/
CLK2
Q
SP
Q
SP
ACTIVE LOW COMBINATORIAL OUTPUT
WITH BURIED REGISTER FEEDBACK
S0 = 0
S1 = 1
S3 = 0
Q
ACTIVE HIGH COMBINATORIAL OUTPUT
WITH BURIED REGISTER FEEDBACK
S2 = 1 Selects CLK1
S2 = 0 Selects CLK2
S0 = 1
S1 = 1
S3 = 0
5
S2 = 1 Selects CLK1
S2 = 0 Selects CLK2
Select devices have been discontinued.
See Ordering Information section for product status.
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COMBINATORIAL MODE
Specifications GAL26V12
GAL26V12 LOGIC DIAGRAM / JEDEC FUSEMAP
1
0
4
8
12
16
20
24
28
32
36
40
44
48
28
ASYNCH
RESET
0000
0520
.
.
.
0936
OLMC 26
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OLMC 27
S0-7800
S1-7812
S2-7824
S3-7836
2
S0-7801
S1-7813
S2-7825
S3-7837
3
0988
.
.
.
.
1508
OLMC 25
S0-7802
S1-7814
S2-7826
S3-7838
4
1560
.
.
.
.
.
2184
OLMC 24
S0-7803
S1-7815
S2-7827
S3-7839
27
26
25
24
5
2236
.
.
.
.
.
.
2964
OLMC 23
S0-7804
S1-7816
S2-7828
S3-7840
23
6
7
VCC
3016
.
.
.
.
.
.
.
3848
OLMC 22
S0-7805
S1-7817
S2-7829
S3-7841
8
0
4
8
12
16
20
24
28
32
36
6
40
44
48
CLK1 CLK2 AR
SP
22
21
Select devices have been discontinued.
See Ordering Information section for product status.
0052
.
.
.
0468
Specifications GAL26V12
GAL26V12 LOGIC DIAGRAM / JEDEC FUSEMAP (CONT.)
0
4
8
12
16
20
24
28
32
36
40
44
48
CLK1 CLK2 AR
OLMC 20
S0-7806
S1-7818
S2-7830
S3-7842
20
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9
4784
.
.
.
.
.
.
5512
OLMC 19
S0-7807
S1-7819
S2-7831
S3-7843
19
10
5564
.
.
.
.
.
6136
OLMC 18
S0-7808
S1-7820
S2-7832
S3-7844
18
11
6188
.
.
.
.
6760
OLMC 17
S0-7809
S1-7821
S2-7833
S3-7845
12
6812
.
.
.
7228
OLMC 16
7280
.
.
.
7696
OLMC 15
S0-7810
S1-7822
S2-7834
S3-7846
13
S0-7811
S1-7823
S2-7835
S3-7847
14
SYNCH
PRESET
7748
0
4
8
12
B0
16
B1
7848 7849...
20
L
S
B
24
M
S
B
B3
28
B4
32
B5
36
B6
B7
Electronic Signature ...7910 7911
7
40
44
48
17
16
15
Select devices have been discontinued.
See Ordering Information section for product status.
3900
.
.
.
.
.
.
.
4732
SP
Specifications
SpecificationsGAL26V12C
GAL26V12
RECOMMENDED OPERATING COND.
ABSOLUTE MAXIMUM RATINGS(1)
Commercial Devices:
Ambient Temperature (TA) ............................. 0 to +75°C
Supply voltage (VCC)
with Respect to Ground ..................... +4.75 to +5.25V
Supply voltage VCC ....................................... -0.5 to +7V
Industrial Devices:
Ambient Temperature (TA) ........................... –40 to 85°C
Supply voltage (VCC)
with Respect to Ground ......................... +4.5 to +5.5V
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1. Stresses above those listed under the “Absolute Maximum
Ratings” may cause permanent damage to the device. These
are stress only ratings and functional operation of the device
at these or at any other conditions above those indicated in
the operational sections of this specification is not implied
(while programming, follow the programming specifications).
DC ELECTRICAL CHARACTERISTICS
Over Recommended Operating Conditions (Unless Otherwise Specified)
SYMBOL
VIL
VIH
IIL1
IIH
VOL
VOH
IOL
IOH
IOS2
MIN.
TYP.4
MAX.
UNITS
Input Low Voltage
Vss – 0.5
—
0.8
V
Input High Voltage
2.0
—
Vcc+1
V
PARAMETER
CONDITION
Input or I/O Low Leakage Current
0V ≤ VIN ≤ VIL (MAX.)
—
—
–10
μA
Input or I/O High Leakage Current
3.5V ≤ VIN ≤ VCC
—
—
10
μA
Output Low Voltage
IOL = MAX. Vin = VIL or VIH
—
—
0.5
V
Output High Voltage
IOH = MAX. Vin = VIL or VIH
2.4
—
—
V
Low Level Output Current
—
—
16
mA
High Level Output Current
—
—
–3.2
mA
–30
—
–130
mA
-7/-10
—
90
130
mA
-15/-20
—
75
105
mA
-10/-15/-20
—
110
150
mA
Output Short Circuit Current
COMMERCIAL
ICC3
Operating Power
Supply Current
INDUSTRIAL
ICC3
Operating Power
Supply Current
VCC = 5V
VIL = 0.5V VIH = 3.0V
VOUT = 0.5V
ftoggle = 15MHz
Outputs Open
VIL = 0.5V VIH = 3.0V
ftoggle = 15MHz
TA = 25°C
Outputs Open
1) The leakage current is due to the internal pull-up on all pins. See Input Buffer section for more information.
2) One output at a time for a maximum duration of one second. Vout = 0.5V was selected to avoid test problems caused by tester
ground degradation. Guaranteed but not 100% tested.
3) Icc specified for a ten-bit binary counter pattern.
4) Typical values are at Vcc = 5V and TA = 25 °C
8
Select devices have been discontinued.
See Ordering Information section for product status.
Input voltage applied ........................... -2.5 to VCC +1.0V
Off-state output voltage applied........... -2.5 to VCC +1.0V
Storage Temperature.................................. -65 to 150°C
Ambient Temperature with
Power Applied ......................................... -55 to 125°C
Specifications
SpecificationsGAL26V12C
GAL26V12
Commercial
AC SWITCHING CHARACTERISTICS
Over Recommended Operating Conditions
PARAM.
TEST
COND.1
MIN.
MAX. MIN.
-15
MAX. MIN.
-20
MAX. MIN.
MAX.
UNITS
Input or I/O to Combinatorial Output
—
7.5
—
10
—
15
—
20
ns
A
Clock to Output Delay
—
4.5
—
7
—
8
—
12
ns
—
Clock to Feedback Delay
—
2
—
2.5
—
2.5
—
10
ns
—
Setup Time, Input or Fdbk before Clk↑
6
—
7
—
10
—
12
—
ns
—
Synch. Preset before Clk↑
5.5
—
6.5
—
10
—
12
—
ns
—
Hold Time, Input or Feedback after Clock↑
0
—
0
—
0
—
0
—
ns
A
Maximum Clock Frequency with
External Feedback, 1/(tsu + tco)
95.2
—
71.4
—
55.5
—
41.6
—
MHz
A
Maximum Clock Frequency with
Internal Feedback, 1/(tsu + tcf)
125.0
—
105.2
—
80.0
—
45.4
—
MHz
A
Maximum Clock Frequency with
No Feedback
142.8
—
125
—
83.3
—
62.5
—
MHz
—
Clock Pulse Duration, High
3.5
—
4
—
6
—
8
—
ns
—
Clock Pulse Duration, Low
3.5
—
4
—
6
—
8
—
ns
B
Input or I/O to Output Enabled
—
7.5
—
10
—
15
—
20
ns
C
Input or I/O to Output Disabled
—
7.5
—
10
—
15
—
20
ns
A
Input or I/O to Asynch. Reset of Register
—
9
—
13
—
20
—
20
ns
—
Asynchronous Reset Pulse Duration
6
—
8
—
10
—
15
—
ns
—
Asynch. Reset to Clock Recovery Time
5
—
8
—
10
—
15
—
ns
—
Synch. Preset to Clock Recovery Time
5
—
8
—
10
—
12
—
ns
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A
fmax3
twh
twl
ten
tdis
tar
tarw
tarr
tspr
1) Refer to Switching Test Conditions section.
2) Calculated from fmax with internal feedback. Refer to fmax Description section.
3) Refer to fmax Description section.
CAPACITANCE (TA = 25°C, f = 1.0 MHz)
SYMBOL
PARAMETER
MAXIMUM*
UNITS
TEST CONDITIONS
CI
Input Capacitance
8
pF
VCC = 5.0V, VI = 2.0V
CI/O
I/O Capacitance
8
pF
VCC = 5.0V, VI/O = 2.0V
*Guaranteed but not 100% tested.
9
Select devices have been discontinued.
See Ordering Information section for product status.
tpd
tco
tcf2
tsu1
tsu2
th
-10
-7
DESCRIPTION
Specifications
SpecificationsGAL26V12C
GAL26V12
Commercial
AC SWITCHING CHARACTERISTICS
Over Recommended Operating Conditions
PARAM.
TEST
COND.1
MIN.
-15
MAX. MIN.
-20
MAX. MIN.
MAX.
UNITS
Input or I/O to Combinatorial Output
—
10
—
15
—
20
ns
A
Clock to Output Delay
—
7
—
8
—
12
ns
—
Clock to Feedback Delay
—
2.5
—
2.5
—
10
ns
—
Setup Time, Input or Fdbk before Clk↑
7
—
10
—
12
—
ns
—
Synch. Preset before Clk↑
6.5
—
10
—
12
—
ns
—
Hold Time, Input or Feedback after Clock↑
0
—
0
—
0
—
ns
A
Maximum Clock Frequency with
External Feedback, 1/(tsu + tco)
71.4
—
55.5
—
41.6
—
MHz
A
Maximum Clock Frequency with
Internal Feedback, 1/(tsu + tcf)
105.2
—
80.0
—
45.4
—
MHz
A
Maximum Clock Frequency with
No Feedback
125.0
—
83.3
—
62.5
—
MHz
—
Clock Pulse Duration, High
4
—
6
—
8
—
ns
—
Clock Pulse Duration, Low
4
—
6
—
8
—
ns
B
Input or I/O to Output Enabled
—
10
—
15
—
20
ns
C
Input or I/O to Output Disabled
—
10
—
15
—
20
ns
A
Input or I/O to Asynch. Reset of Register
—
13
—
20
—
20
ns
—
Asynchronous Reset Pulse Duration
8
—
10
—
15
—
ns
—
Asynch. Reset to Clock Recovery Time
8
—
10
—
15
—
ns
—
Synch. Preset to Clock Recovery Time
8
—
10
—
12
—
ns
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fmax3
twh
twl
ten
tdis
tar
tarw
tarr
tspr
1) Refer to Switching Test Conditions section.
2) Calculated from fmax with internal feedback. Refer to fmax Description section.
3) Refer to fmax Description section.
CAPACITANCE (TA = 25°C, f = 1.0 MHz)
SYMBOL
PARAMETER
MAXIMUM*
UNITS
TEST CONDITIONS
CI
Input Capacitance
8
pF
VCC = 5.0V, VI = 2.0V
CI/O
I/O Capacitance
8
pF
VCC = 5.0V, VI/O = 2.0V
*Guaranteed but not 100% tested.
10
Select devices have been discontinued.
See Ordering Information section for product status.
tpd
tco
tcf2
tsu1
tsu2
th
-10
DESCRIPTION
Specifications GAL26V12
SWITCHING WAVEFORMS
INPUT or
I/O FEEDBACK
INPUT or
I/O FEEDBACK
VALID INPUT
VALID INPUT
ts u
t pd
th
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tc o
REGISTERED
OUTPUT
Combinatorial Output
1 / fm a x
(external fdbk)
Registered Output
INPUT or
I/O FEEDBACK
t dis
t en
OUTPUT
CLK
1 / fm ax (int ern al fd bk )
Input or I/O to Output Enable/Disable
tc f
t su
REGISTERED
FEEDBACK
fmax with Feedback
tw l
tw h
CLK
Clock Width
th
INPUT or
I/O FEEDBACK
DRIVING AR
INPUT or
I/O FEEDBACK
DRIVING SP
ta r w
ta r r
ts u
ts p r
CLK
REGISTERED
OUTPUT
tc o
REGISTERED
OUTPUT
ta r
CLK
Synchronous Preset
Asynchronous Reset
11
Select devices have been discontinued.
See Ordering Information section for product status.
CLK
COMBINATORIAL
OUTPUT
Specifications GAL26V12
fmax DESCRIPTIONS
CLK
LOGIC
A RRA Y
CLK
LOGIC
ARRAY
RE GIST ER
ts u
tc o
tc f
tp d
fmax with External Feedback 1/(tsu+tco)
Note: fmax with external feedback is calculated from measured tsu and tco.
fmax with Internal Feedback 1/(tsu+tcf)
Note: tcf is a calculated value, derived by subtracting tsu from the period of fmax w/internal
feedback (tcf = 1/fmax - tsu). The value of tcf is
used primarily when calculating the delay from
clocking a register to a combinatorial output
(through registered feedback), as shown above.
For example, the timing from clock to a combinatorial output is equal to tcf + tpd.
CLK
LOGI C
ARRAY
REGISTER
fmax With No Feedback
Note: fmax with no feedback may be less
than 1/twh + twl. This is to allow for a clock
duty cycle of other than 50%.
SWITCHING TEST CONDITIONS
Input Pulse Levels
GND to 3.0V
Input Rise and Fall Times
+5V
2ns 10% – 90%
Input Timing Reference Levels
1.5V
Output Timing Reference Levels
1.5V
Output Load
R1
See Figure
3-state levels are measured 0.5V from steady-state active
level.
FROM OUTPUT (O/Q)
UNDER TEST
TEST POINT
Output Load Conditions (see figure)
R1
R2
CL
300Ω
390Ω
50pF
Active High
∞
390Ω
50pF
Active Low
300Ω
390Ω
50pF
Active High
∞
390Ω
5pF
Active Low
300Ω
390Ω
5pF
Test Condition
A
B
C
R2
C L*
*C L INCLUDES TEST FIXTURE AND PROBE CAPACITANCE
12
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See Ordering Information section for product status.
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REGISTER
Specifications GAL26V12
OUTPUT REGISTER PRELOAD
ELECTRONIC SIGNATURE
An electronic signature is provided in every GAL26V12 device.
It contains 64 bits of reprogrammable memory that can contain
user-defined data. Some uses include user ID codes, revision
numbers, or inventory control. The signature data is always
available to the user independent of the state of the security cell.
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SECURITY CELL
A security cell is provided in every GAL26V12 device to prevent
unauthorized copying of the array patterns. Once programmed,
this cell prevents further read access to the functional bits in the
device. This cell can only be erased by re-programming the
device, so the original configuration can never be examined once
this cell is programmed. The Electronic Signature is always available to the user, regardless of the state of this control cell.
The GAL26V12 device includes circuitry that allows each registered output to be synchronously set either high or low. Thus, any
present state condition can be forced for test sequencing. If
necessary, approved GAL programmers capable of executing test
vectors perform output register preload automatically.
INPUT BUFFERS
LATCH-UP PROTECTION
GAL26V12 devices are designed with TTL level compatible input buffers. These buffers have a characteristically high impedance, and present a much lighter load to the driving logic than bipolar TTL devices.
GAL26V12 devices are designed with an on-board charge pump
to negatively bias the substrate. The negative bias minimizes the
potential for latch-up caused by negative input undershoots.
Additionally, outputs are designed with n-channel pull-ups instead
of the traditional p-channel pull-ups in order to eliminate latch-up
due to output overshoots.
DEVICE PROGRAMMING
GAL devices are programmed using a Lattice-approved Logic
Programmer, available from a number of manufacturers (see the
the GAL Development Tools section). Complete programming of
the device takes only a few seconds. Erasing of the device is
transparent to the user, and is done automatically as part of the
programming cycle.
13
Select devices have been discontinued.
See Ordering Information section for product status.
When testing state machine designs, all possible states and state
transitions must be verified in the design, not just those required
in the normal machine operations. This is because certain events
may occur during system operation that throw the logic into an
illegal state (power-up, line voltage glitches, brown-outs, etc.). To
test a design for proper treatment of these conditions, a way must
be provided to break the feedback paths, and force any desired
(i.e., illegal) state into the registers. Then the machine can be
sequenced and the outputs tested for correct next state conditions.
Specifications GAL26V12
POWER-UP RESET
Circuitry within the GAL26V12 provides a reset signal to all registers during power-up. All internal registers will have their Q outputs set low after a specified time (tpr, 1μs MAX). As a result, the
state on the registered output pins (if they are enabled) will be
either high or low on power-up, depending on the programmed
polarity of the output pins. This feature can greatly simplify state
machine design by providing a known state on power-up. The
timing diagram for power-up is shown below. Because of the
asynchronous nature of system power-up, some conditions must
be met to guarantee a valid power-up reset of the GAL26V12.
First, the VCC rise must be monotonic. Second, the clock input
must be at static TTL level as shown in the diagram during power
up. The registers will reset within a maximum of tpr time. As in normal system operation, avoid clocking the device until all input and
feedback path setup times have been met. The clock must also
meet the minimum pulse width requirements.
4.0 V
Vcc
CLK
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Internal Register
Reset to Logic "0"
ACTIV E LOW
OUTPUT REGIS TER
Device Pin
Reset to Logic "1"
ACTIVE HIGH
OUTPUT REGIS TER
Device Pin
Reset to Logic "0"
INPUT/OUTPUT EQUIVALENT SCHEMATICS
Output
Data
PIN
PIN
Feedback
Active Pull-up
Circuit
Vcc
T ri - S t a t e
Cont rol
Vcc
ESD
Protection
Circuit
Vcc
Vref
Vcc
Output
Data
PIN
PIN
ESD
Protection
Circuit
Feedback
(To Input Buffer)
Output
Input
14
Select devices have been discontinued.
See Ordering Information section for product status.
tpr
INTERNAL
RE GISTER
Q - OUTP UT
Specifications GAL26V12
TYPICAL AC AND DC CHARACTERISTIC DIAGRAMS
Normalized Tpd vs Vcc
1.2
1.2
1.1
1
1.1
1
0.9
1.1
1
0.9
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Normalized Tsu
Normalized Tco
1.2
0.8
0.8
4.75
5.00
5.25
5.50
0.8
4.50
4.75
5.00
5.25
5.50
4.50
5.00
5.25
5.50
Supply Voltage (V)
Supply Voltage (V)
Normalized Tpd vs Temp
Normalized Tco vs Temp
Normalized Tsu vs Temp
1.2
1.2
1.1
1
0.9
0.8
0.7
1.4
Normalized Tsu
1.3
Normalized Tco
1.3
1.1
1
0.9
0.8
0.7
-25
0
25
50
75
100
1.3
1.2
1.1
1
0.9
0.8
0.7
-55
125
-25
0
25
50
75
100
-55
125
-25
Delta Tpd vs # of Outputs
Switching
Delta Tco vs # of Outputs
Switching
0
Delta Tco (ns)
0
-0.25
-0.5
-0.75
-0.25
-0.5
-0.75
-1
-1
1
2
3
4
5
6
7
8
9
10 11 12
1
Number of Outputs Switching
2
3
4
5
6
7
8
9
10 11 12
Number of Outputs Switching
Delta Tpd vs Output Loading
Delta Tco vs Output Loading
12
RISE
8
FALL
Delta Tco (ns)
12
10
6
4
2
10
RISE
8
FALL
6
4
2
0
0
-2
-2
0
50
100
150
200
250
300
0
Output Loading (pF)
50
100
150
200
250
Output Loading (pF)
15
0
25
50
75
100
Temperature (deg. C)
Temperature (deg. C)
Temperature (deg. C)
Delta Tpd (ns)
-55
4.75
Supply Voltage (V)
Delta Tpd (ns)
Normalized Tpd
4.50
300
125
Select devices have been discontinued.
See Ordering Information section for product status.
Normalized Tpd
Normalized Tsu vs Vcc
Normalized Tco vs Vcc
Specifications GAL26V12
TYPICAL AC AND DC CHARACTERISTIC DIAGRAMS
Vol vs Iol
Voh vs Ioh
3
5
2.5
4
4
1
Voh (V)
1.5
3.75
3
2
3.25
1
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0.5
3.5
0
0
20.00
40.00
60.00
80.00
100.00
3
0.00
30.00 40.00
50.00 60.00
0.00
2.00
3.00
Ioh(mA)
Normalized Icc vs Vcc
Normalized Icc vs Temp
Normalized Icc vs Freq.
1.3
1.50
1.2
1.2
1.40
1.1
1
0.9
0.8
Normalized Icc
1.3
4.50
1.00
Ioh(mA)
0.7
1.1
1
0.9
0.8
4.75
5.00
5.25
5.50
-25
0
25
50
75
100
125
Temperature (deg. C)
0
10
Iik (mA)
6
4
2
20
30
40
50
0
60
0.00 0.50 1.00 1.50 2.00 2.50 3.00 3.50 4.00
Vin (V)
1.20
1.10
1.00
-2.00
-1.50
-1.00
Vik (V)
16
-0.50
0
25
50
75
Frequency (MHz)
Input Clamp (Vik)
Delta Icc vs Vin (1 input)
8
1.30
0.80
-55
10
4.00
0.90
0.7
Supply Voltage (V)
Delta Icc (mA)
10.00 20.00
Iol (mA)
Normalized Icc
Normalized Icc
0.00
0.00
100
Select devices have been discontinued.
See Ordering Information section for product status.
Voh (V)
2
Vol (V)
Voh vs Ioh