GAL®22LV10 Device Datasheet June 2010 All Devices Discontinued! Product Change Notifications (PCNs) have been issued to discontinue all devices in this data sheet. The original datasheet pages have not been modified and do not reflect those changes. Please refer to the table below for reference PCN and current product status. Product Line GAL22LV10C GAL22LV10D Ordering Part Number GAL22LV10C-7LJ GAL22LV10C-7LJN GAL22LV10C-10LJ GAL22LV10C-10LJN GAL22LV10C-15LJ GAL22LV10C-15LJN GAL22LV10D-4LJ GAL22LV10D-4LJN GAL22LV10D-5LJ GAL22LV10D-5LJN Product Status Reference PCN PCN#06-07 Discontinued PCN#09-10 Discontinued PCN#09-10 5555 N.E. Moore Ct. z Hillsboro, Oregon 97124-6421 z Phone (503) 268-8000 z FAX (503) 268-8347 Internet: http://www.latticesemi.com Ne Tolew 5V Inp rant 22Luts on V10 D Features GAL22LV10 Low Voltage E2CMOS PLD Generic Array Logic™ Functional Block Diagram • HIGH PERFORMANCE E2CMOS® TECHNOLOGY — 4 ns Maximum Propagation Delay — Fmax = 250 MHz — 3 ns Maximum from Clock Input to Data Output — UltraMOS® Advanced CMOS Technology RESET I/CLK 8 OLMC I/O/Q OLMC I/O/Q OLMC I/O/Q OLMC I/O/Q OLMC I/O/Q OLMC I/O/Q OLMC I/O/Q OLMC I/O/Q OLMC I/O/Q OLMC I/O/Q I • 3.3V LOW VOLTAGE 22V10 ARCHITECTURE — JEDEC-Compatible 3.3V Interface Standard — 5V Compatible Inputs — I/O Interfaces with Standard 5V TTL Devices (GAL22LV10C) A D LL IS C DE O N VIC TI N ES U ED 10 I 12 I • E2 CELL TECHNOLOGY — Reconfigurable Logic — Reprogrammable Cells — 100% Tested/100% Yields — High Speed Electrical Erasure (<100ms) — 20 Year Data Retention PROGRAMMABLE AND-ARRAY (132X44) • ACTIVE PULL-UPS ON ALL PINS (GAL22LV10D) I I I • TEN OUTPUT LOGIC MACROCELLS — Maximum Flexibility for Complex Logic Designs — Programmable Output Polarity I • PRELOAD AND POWER-ON RESET OF ALL REGISTERS — 100% Functional Testability 14 16 16 14 I • APPLICATIONS INCLUDE: — Glue Logic for 3.3V Systems — DMA Control — State Machine Control — High Speed Graphics Processing — Standard Logic Speed Upgrade 12 I 10 I 8 • ELECTRONIC SIGNATURE FOR IDENTIFICATION I • LEAD-FREE PACKAGE OPTIONS Description PRESET Pin Configuration 4 I I/O/Q 28 I/O/Q NC 2 Vcc I I I/CLK PLCC The GAL22LV10D, at 4 ns maximum propagation delay time, provides the highest speed performance available in the PLD market. The GAL22LV10C can interface with both 3.3V and 5V signal levels. The GAL22LV10 is manufactured using Lattice Semiconductor's advanced 3.3V E2CMOS process, which combines CMOS with Electrically Erasable (E2) floating gate technology. High speed erase times (<100ms) allow the devices to be reprogrammed quickly and efficiently. 26 5 25 7 23 I I The generic architecture provides maximum design flexibility by allowing the Output Logic Macrocell (OLMC) to be configured by the user. I/O/Q GAL22LV10 NC I Unique test circuitry and reprogrammable cells allow complete AC, DC, and functional testing during manufacture. As a result, Lattice Semiconductor delivers 100% field programmability and functionality of all GAL products. In addition, 100 erase/write cycles and data retention in excess of 20 years are specified. Top View 9 I/O/Q NC 21 I I/O/Q I/O/Q 11 I I/O/Q I/O/Q I/O/Q 19 18 16 NC 14 I I 12 GND I I/O/Q Copyright © 2008 Lattice Semiconductor Corp. All brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. LATTICE SEMICONDUCTOR CORP., 5555 Northeast Moore Ct., Hillsboro, Oregon 97124, U.S.A. Tel. (503) 268-8000; 1-800-LATTICE; FAX (503) 268-8556; http://www.latticesemi.com 22lv10_07 1 August 2008 Specifications GAL22LV10 GAL22LV10 Ordering Information Conventional Packaging Commercial Grade Specifications Tpd (ns) Tsu (ns) Tco (ns) Icc (mA) 4 3 3 130 Ordering # Package GAL22LV10D-4LJ 28-Lead PLCC 3.5 3.5 130 GAL22LV10D-5LJ 28-Lead PLCC 6.5 5 75 GAL22LV10C-7LJ1 28-Lead PLCC 10 7.5 6. 5 75 GAL22LV10C-10LJ 28-Lead PLCC 15 10 10 75 GAL22LV10C-15LJ 28-Lead PLCC A D LL IS C DE O N VIC TI N ES U ED 5 7.5 Lead-Free Packaging Commercial Grade Specifications Tpd (ns) Tsu (ns) Tco (ns) Icc (mA) Ordering # Package 4 3 3 130 GAL22LV10D-4LJN Lead-Free 28-Lead PLCC 5 3.5 3.5 130 GAL22LV10D-5LJN Lead-Free 28-Lead PLCC 7.5 6.5 5 75 GAL22LV10C-7LJN1 Lead-Free 28-Lead PLCC 10 7.5 6.5 75 GAL22LV10C-10LJN Lead-Free 28-Lead PLCC 15 10 10 75 GAL22LV10C-15LJN Lead-Free 28-Lead PLCC 1. Discontinued per PCN #06-07. Contact Rochester Electronics for available inventory. Part Number Description XXXXXXXX _ XX X X X GAL22LV10D Device Name GAL22LV10C Speed (ns) L = Low Power Grade Power Blank = Commercial Package J = PLCC JN = Lead-Free PLCC 2 Specifications GAL22LV10 Output Logic Macrocell (OLMC) The GAL22LV10 has a variable number of product terms per OLMC. Of the ten available OLMCs, two OLMCs have access to eight product terms (pins 17 and 27), two have ten product terms (pins 18 and 26), two have twelve product terms (pins 19 and 25), two have fourteen product terms (pins 20 and 24), and two OLMCs have sixteen product terms (pins 21 and 23). In addition to the product terms available for logic, each OLMC has an additional product-term dedicated to output enable control. The GAL22LV10 has a product term for Asynchronous Reset (AR) and a product term for Synchronous Preset (SP). These two product terms are common to all registered OLMCs. The Asynchronous Reset sets all registers to zero any time this dedicated product term is asserted. The Synchronous Preset sets all registers to a logic one on the rising edge of the next clock pulse after this product term is asserted. NOTE: The AR and SP product terms will force the Q output of the flip-flop into the same state regardless of the polarity of the output. Therefore, a reset operation, which sets the register output to a zero, may result in either a high or low at the output pin, depending on the pin polarity chosen. A D LL IS C DE O N VIC TI N ES U ED The output polarity of each OLMC can be individually programmed to be true or inverting, in either combinatorial or registered mode. This allows each output to be individually configured as either active high or active low. A R D 4 TO 1 MUX Q CLK Q SP 2 TO 1 MUX GAL22LV10 OUTPUT LOGIC MACROCELL (OLMC) Output Logic Macrocell Configurations NOTE: In registered mode, the feedback is from the /Q output of the register, and not from the pin; therefore, a pin defined as registered is an output only, and cannot be used for dynamic I/O, as can the combinatorial pins. Each of the Macrocells of the GAL22LV10 has two primary functional modes: registered, and combinatorial I/O. The modes and the output polarity are set by two bits (SO and S1), which are normally controlled by the logic compiler. Each of these two primary modes, and the bit settings required to enable them, are described below and on the following page. COMBINATORIAL I/O In combinatorial mode the pin associated with an individual OLMC is driven by the output of the sum term gate. Logic polarity of the output signal at the pin may be selected by specifying that the output buffer drive either true (active high) or inverted (active low). Output tri-state control is available as an individual product-term for each output, and may be individually set by the compiler as either “on” (dedicated output), “off” (dedicated input), or “product-term driven” (dynamic I/O). Feedback into the AND array is from the pin side of the output enable buffer. Both polarities (true and inverted) of the pin are fed back into the AND array. REGISTERED In registered mode the output pin associated with an individual OLMC is driven by the Q output of that OLMC’s D-type flip-flop. Logic polarity of the output signal at the pin may be selected by specifying that the output buffer drive either true (active high) or inverted (active low). Output tri-state control is available as an individual product-term for each OLMC, and can therefore be defined by a logic equation. The D flip-flop’s /Q output is fed back into the AND array, with both the true and complement of the feedback available as inputs to the AND array. 3 Specifications GAL22LV10 Registered Mode AR AR Q Q D A D LL IS C DE O N VIC TI N ES U ED D CLK Q CLK SP Q SP ACTIVE LOW ACTIVE HIGH S0 = 0 S1 = 0 S0 = 1 S1 = 0 Combinatorial Mode ACTIVE LOW ACTIVE HIGH S0 = 0 S1 = 1 S0 = 1 S1 = 1 4 Specifications GAL22LV10 GAL22LV10 Logic Diagram/JEDEC Fuse Map PLCC Package Pinout 2 0 4 8 12 16 20 24 28 32 36 40 ASYNCHRONOUS RESET (TO ALL REGISTERS) 0000 0044 . . . 0396 8 OLMC S0 5808 S1 5809 0440 . . . . 0880 OLMC 26 A D LL IS C DE O N VIC TI N ES U ED 10 27 S0 5810 S1 5811 3 0924 . . . . . 1452 12 OLMC S0 5812 S1 5813 4 1496 . . . . . . 2112 14 OLMC 25 24 S0 5814 S1 5815 5 2156 . . . . . . . 2860 16 OLMC 23 S0 5816 S1 5817 6 2904 . . . . . . . 3608 16 OLMC 21 S0 5818 S1 5819 7 3652 . . . . . . 4268 14 OLMC 20 S0 5820 S1 5821 9 4312 . . . . . 4840 12 OLMC S0 5822 S1 5823 10 4884 . . . . 5324 10 OLMC S0 5824 S1 5825 11 5368 . . . 5720 8 OLMC S0 5826 S1 5827 12 SYNCHRONOUS PRESET (TO ALL REGISTERS) 5764 13 5828, 5829 ... Electronic Signature ... 5890, 5891 Byte 7 Byte 6 Byte 5 Byte 4 Byte 3 Byte 2 Byte 1 Byte 0 M S B L S B 5 19 18 17 16 Specifications Specifications GAL22LV10D GAL22LV10 Absolute Maximum Ratings(1) Recommended Operating Conditions Supply voltage VCC .................................... -0.5 to +4.6V Input voltage applied ................................. -0.5 to +5.6V I/O voltage applied .................................... -0.5 to +4.6V Off-state output voltage applied ................ -0.5 to +4.6V Storage Temperature ................................. -65 to 150°C Ambient Temperature with Power Applied ......................................... -55 to 125°C Commercial Devices: Ambient Temperature (TA) ............................... 0 to 75°C Supply voltage (VCC) with Respect to Ground ......................... +3.0 to +3.6V A D LL IS C DE O N VIC TI N ES U ED 1.Stresses above those listed under the “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress only ratings and functional operation of the device at these or at any other conditions above those indicated in the operational sections of this specification is not implied (while programming, follow the programming specifications). DC Electrical Characteristics Over Recommended Operating Conditions (Unless Otherwise Specified) SYMBOL VIL VIH IIL1 IIH VOL VOH MIN. TYP.3 MAX. UNITS Input Low Voltage Vss - 0.3 — 0.8 V Input High Voltage 2.0 — 5.25 V I/O High Voltage 2.0 — Vcc+0.5 V PARAMETER CONDITION Input or I/O Low Leakage Current 0V ≤ VIN ≤ VIL (MAX.) — — -100 μA Input or I/O High Leakage Current (Vcc-0.2)V ≤ VIN ≤ VCC — — 10 μA Input High Leakage Current Vcc ≤ VIN ≤ 5.25V — — 10 μA I/O High Leakage Current Vcc ≤ VIN ≤ 4.6V — — 20 mA Output Low Voltage IOL = MAX. Vin = VIL or VIH — — 0.4 V IOL = 500μA Vin = VIL or VIH — — 0.2 V IOH = MAX. Vin = VIL or VIH 2.4 — — V Vcc-0.2V — — V Low Level Output Current — — 8 mA High Level Output Current — — –8 mA -15 — -80 mA — 90 130 mA Output High Voltage IOH = -100μA Vin = VIL or VIH IOL IOH IOS2 Output Short Circuit Current COMMERCIAL ICC Operating Power Supply Current VIL = 0V VCC = 3.3V VOUT = 0.5V TA= 25°C VIH = 3.0V Unused Inputs at VIL ftoggle = 1MHz Outputs Open 1) The leakage current is due to the internal pull-up resistor on all pins. See Input Buffer section for more information. 2) One output at a time for a maximum duration of one second. Vout = 0.5V was selected to avoid test problems caused by tester ground degradation. Characterized but not 100% tested. 3) Typical values are at Vcc = 3.3V and TA = 25 °C 6 Specifications Specifications GAL22LV10D GAL22LV10 AC Switching Characteristics Over Recommended Operating Conditions PARAMETER COM -4 -5 DESCRIPTION MIN. MAX. MIN. MAX. UNITS A Input or I/O to Combinational Output 1 4 1 5 ns A Clock to Output Delay 1 3 1 3.5 ns — Clock to Feedback Delay — 2.5 — 3 ns — Setup Time, Input or Feedback before Clock↑ 3 — 3.5 — ns — Hold Time, Input or Feedback after Clock↑ 0 — 0 — ns A Maximum Clock Frequency with External Feedback, 1/(tsu + tco) 167 — 143 — MHz A Maximum Clock Frequency with Internal Feedback, 1/(tsu + tcf) 182 — 154 — MHz A Maximum Clock Frequency with No Feedback 250 — 200 — MHz — Clock Pulse Duration, High 2 — 2.5 — ns — Clock Pulse Duration, Low 2 — 2.5 — ns B Input or I/O to Output Enabled 1 5 1 6 ns C Input or I/O to Output Disabled 1 5 1 6 ns A Input or I/O to Asynchronous Reset of Register 1 4.5 1 5.5 ns — Asynchronous Reset Pulse Duration 4.5 — 5.5 — ns — Asynchronous Reset to Clock↑ Recovery Time 3.5 — 4 — ns — Synchronous Preset to Clock↑ Recovery Time 3.5 — 4 — ns A D LL IS C DE O N VIC TI N ES U ED tpd2 tco2 tcf3 tsu th TEST COND1. COM fmax4 twh4 twl4 ten tdis tar tarw tarr tspr 1) 2) 3) 4) Refer to Switching Test Conditions section. Minimum values for tpd and tco are not 100% tested but established by characterization. Calculated from fmax with internal feedback. Refer to fmax Descriptions section. Refer to fmax Descriptions section. Characterized but not 100% tested. Capacitance (TA = 25°C, f = 1.0 MHz) SYMBOL PARAMETER TYPICAL UNITS TEST CONDITIONS CI Input Capacitance 5 pF VCC = 3.3V, VI = 0V CI/O I/O Capacitance 5 pF VCC = 3.3V, VI/O = 0V 7 Specifications SpecificationsGAL22LV10C GAL22LV10 Absolute Maximum Ratings(1) Recommended Operating Conditions Supply voltage VCC .................................... -0.5 to +5.6V Commercial Devices: Ambient Temperature (TA) ............................. 0 to +75°C Supply voltage (VCC) with Respect to Ground ......................... +3.0 to +3.6V Input voltage applied ................................. -0.5 to +5.6V Off-state output voltage applied ................ -0.5 to +5.6V Storage Temperature ................................. -65 to 150°C Ambient Temperature with Power Applied ......................................... -55 to 125°C A D LL IS C DE O N VIC TI N ES U ED 1. Stresses above those listed under the “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress only ratings and functional operation of the device at these or at any other conditions above those indicated in the operational sections of this specification is not implied (while programming, follow the programming specifications). DC Electrical Characteristics Over Recommended Operating Conditions (Unless Otherwise Specified) SYMBOL VIL VIH IIL IIH VOL VOH IOL IOH IOS1 MIN. TYP.2 MAX. UNITS Input Low Voltage Vss – 0.5 — 0.8 V Input High Voltage 2.0 — 5.25 V PARAMETER CONDITION Input or I/O Low Leakage Current 0V ≤ VIN ≤ VIL (MAX.) — — -10 μA Input or I/O High Leakage Current (VCC - 0.2)V ≤ VIN ≤ VCC — — 10 μA VCC ≤ VIN ≤ 5.25V — — 30 mA IOL = 8mA Vin = VIL or VIH — — 0.4 V IOL = 16 mA Vin = VIL or VIH — — 0.5 V IOL = 0.5 mA Vin = VIL or VIH — — 0.2 V IOH = MAX. Vin = VIL or VIH 2.4 — — V IOH = -0.5 mA Vin = VIL or VIH Vcc-0.45 — — V IOH = -100 μA Vin = VIL or VIH Vcc-0.2 — — V VOL = 0.4 V — — 8 mA VOL = 0.5V — — 16 mA — — -4 mA -15 — -60 mA — 45 75 mA Output Low Voltage Output High Voltage Low Level Output Current High Level Output Current Output Short Circuit Current COMMERCIAL ICC Operating Power Supply Current VCC = 3.3V VIL = 0.0V VIH = 3.0V ftoggle = 1MHz Outputs Open VOUT = 0.5V TA = 25°C 1) One output at a time for a maximum duration of one second. Vout = 0.5V was selected to avoid test problems by tester ground degradation. Characterized but not 100% tested. 2) Typical values are at Vcc = 3.3V and TA = 25 °C 8 Specifications SpecificationsGAL22LV10C GAL22LV10 AC Switching Characteristics Over Recommended Operating Conditions PARAM TEST COND.1 COM COM -7 -10 -15 DESCRIPTION MIN. MAX. MIN. MAX. MIN. MAX. UNITS A Input or I/O to Combinatorial Output 2 7.5 2 10 2 15 ns A Clock to Output Delay 1 5 1 6.5 1 10 ns A D LL IS C DE O N VIC TI N ES U ED tpd2 tco2 tcf3 tsu th COM fmax4 twh twl ten tdis tar tarw tarr tspr — Clock to Feedback Delay — 3 — 5 — 5 ns — Setup Time, Input or Fdbk before Clk↑ 6 — 7.5 — 10 — ns — Hold Time, Input or Fdbk after Clk↑ 0 — 0 — 0 — ns A Maximum Clock Frequency with External Feedback, 1/(tsu + tco) 91 — 71 — 50 — MHz A Maximum Clock Frequency with Internal Feedback, 1/(tsu + tcf) 111 — 80 — 66 — MHz A Maximum Clock Frequency with No Feedback 125 — 111 — 83 — MHz — Clock Pulse Duration, High 3.5 — 4 — 6 — ns — Clock Pulse Duration, Low 3.5 — 4 — 6 — ns B Input or I/O to Output Enabled 2 10 2 12 2 15 ns C Input or I/O to Output Disabled 2 10 2 12 2 15 ns A Input or I/O to Asynch. Reset of Reg. 2 11 2 13 2 20 ns — Asynch. Reset Pulse Duration 6 — 8 — 10 — ns — Asynch. Reset to Clk↑ Recovery Time 6 — 8 — 10 — ns — Synch. Preset to Clk↑ Recovery Time 6 — 8 — 10 — ns 1) Refer to Switching Test Conditions section. 2) Minimum values for tpd and tco are not 100% tested but established by characterization. 3) Calculated from fmax with internal feedback. Refer to fmax Description section. 4) Refer to fmax Description section. Capacitance (TA = 25°C, f = 1.0 MHz) SYMBOL PARAMETER TYPICAL UNITS TEST CONDITIONS CI Input Capacitance 8 pF VCC = 3.3V, VI = 0V CI/O I/O Capacitance 8 pF VCC = 3.3V, VI/O = 0V 9 Specifications GAL22LV10 Switching Waveforms INPUT or I/O FEEDBACK INPUT or I/O FEEDBACK VALID INPUT VALID INPUT ts u t pd th CLK COMBINATORIAL OUTPUT tc o A D LL IS C DE O N VIC TI N ES U ED REGISTERED OUTPUT Combinatorial Output 1 / fm a x (external fdbk) Registered Output INPUT or I/O FEEDBACK t dis t en OUTPUT CLK 1 / fm ax (int ern al fd bk ) Input or I/O to Output Enable/Disable t su tc f REGISTERED FEEDBACK fmax with Feedback tw l tw h CLK 1 / fm a x (w/o fdbk) Clock Width INPUT or I/O FEEDBACK DRIVING SP tsu th INPUT or I/O FEEDB ACK DRIVI NG AR tspr CLK tarw CLK tarr tco R E G I S T ER E D OUTPUT REGISTERED OUTPUT tar Synchronous Preset Asynchronous Reset 10 Specifications GAL22LV10 fmax Descriptions CLK LOGIC ARRAY CLK REGISTER LOGIC ARRAY tco REGISTER A D LL IS C DE O N VIC TI N ES U ED tsu fmax with External Feedback 1/(tsu+tco) Note: fmax with external feedback is calculated from measured tsu and tco. CLK LOGIC ARRAY t cf t pd fmax with Internal Feedback 1/(tsu+tcf) REGISTER Note: tcf is a calculated value, derived by subtracting tsu from the period of fmax w/internal feedback (tcf = 1/fmax - tsu). The value of tcf is used primarily when calculating the delay from clocking a register to a combinatorial output (through registered feedback), as shown above. For example, the timing from clock to a combinatorial output is equal to tcf + tpd. tsu + th fmax with No Feedback Note: fmax with no feedback may be less than 1/(twh + twl). This is to allow for a clock duty cycle of other than 50%. 11 Specifications GAL22LV10 GAL22LV10D: Switching Test Conditions Input Pulse Levels GND to 3.0V Input Rise and Fall Times 1.5ns 10% – 90% Input Timing Reference Levels 1.5V Output Timing Reference Levels 1.5V Output Load +1.45V See Figure TEST POINT A D LL IS C DE O N VIC TI N ES U ED Output Load Conditions (see figure) R1 R1 CL 50Ω 50Ω 50Ω 50Ω 50Ω 35pF 35pF 35pF 35pF 35pF Test Condition A B C High Z to Active High at 1.9V High Z to Active Low at 1.0V Active High to High Z at 1.9V Active Low to High Z at 1.0V FROM OUTPUT (O/Q) UNDER TEST Z0 = 50Ω, CL = 35pF* *CL includes test fixture and probe capacitance. GAL22LV10C: Switching Test Conditions Input Pulse Levels +3.3V GND to 3.0V Input Rise and Fall Times 2.0ns 10% – 90% Input Timing Reference Levels 1.5V Output Timing Reference Levels R1 1.5V Output Load See Figure FROM OUTPUT (O/Q) UNDER TEST 3-state levels are measured 0.5V from steady-state active level. R2 Output Load Conditions (see figure) Test Condition A B C Active High Active Low Active High Active Low TEST POINT R1 R2 CL 316Ω 316Ω 316Ω 316Ω 316Ω 348Ω 348Ω 348Ω 348Ω 348Ω 35pF 35pF 35pF 5pF 5pF C L* *C L INCLUDES TEST FIXTURE AND PROBE CAPACITANCE 12 Specifications GAL22LV10 Electronic Signature Output Register Preload An electronic signature (ES) is provided in every GAL22LV10 device. It contains 64 bits of reprogrammable memory that can contain user-defined data. Some uses include user ID codes, revision numbers, or inventory control. The signature data is always available to the user independent of the state of the security cell. When testing state machine designs, all possible states and state transitions must be verified in the design, not just those required in the normal machine operations. This is because certain events may occur during system operation that throw the logic into an illegal state (power-up, line voltage glitches, brown-outs, etc.). To test a design for proper treatment of these conditions, a way must be provided to break the feedback paths, and force any desired (i.e., illegal) state into the registers. Then the machine can be sequenced and the outputs tested for correct next state conditions. A D LL IS C DE O N VIC TI N ES U ED The electronic signature is an additional feature not present in other manufacturers' 22V10 devices. To use the extra feature of the userprogrammable electronic signature it is necessary to choose a Lattice Semiconductor 22V10 device type when compiling a set of logic equations. In addition, many device programmers have two separate selections for the device, typically a GAL22LV10 and a GAL22V10-UES (UES = User Electronic Signature) or GAL22V10ES. This allows users to maintain compatibility with existing 22V10 designs, while still having the option to use the GAL device's extra feature. The GAL22LV10 device includes circuitry that allows each registered output to be synchronously set either high or low. Thus, any present state condition can be forced for test sequencing. If necessary, approved GAL programmers capable of executing test vectors perform output register preload automatically. Input Buffers The JEDEC map for the GAL22LV10 contains the 64 extra fuses for the electronic signature, for a total of 5892 fuses. However, the GAL22LV10 device can still be programmed with a standard 22V10 JEDEC map (5828 fuses) with any qualified device programmer. GAL22LV10 devices are designed with TTL level compatible input buffers. These buffers have a characteristically high impedance, and present a much lighter load to the driving logic than bipolar TTL devices. Security Cell The input and I/O pins on the GAL22LV10D also have built-in active pull-ups. As a result, floating inputs will float to a TTL high (logic 1). However, Lattice Semiconductor recommends that all unused inputs and tri-stated I/O pins be connected to an adjacent active input, Vcc, or ground. Doing so will tend to improve noise immunity and reduce Icc for the device. (See equivalent input and I/O schematics on the following page.) A security cell is provided in every GAL22LV10 device to prevent unauthorized copying of the array patterns. Once programmed, this cell prevents further read access to the functional bits in the device. This cell can only be erased by re-programming the device, so the original configuration can never be examined once this cell is programmed. The Electronic Signature is always available to the user, regardless of the state of this control cell. Typical Input Pull-up Characteristic Latch-Up Protection 0 -10 Input Current (μA) GAL22LV10 devices are designed with an on-board charge pump to negatively bias the substrate. The negative bias is of sufficient magnitude to prevent input undershoots from causing the circuitry to latch. Device Programming -20 -30 -40 -50 -60 -70 GAL devices are programmed using a Lattice Semiconductorapproved Logic Programmer, available from a number of manufacturers (see the the GAL Development Tools section). Complete programming of the device takes only a few seconds. Erasing of the device is transparent to the user, and is done automatically as part of the programming cycle. Input Voltage (V) 13 4 3.5 3 2.5 2 1.5 1 0.5 0 -80 Specifications GAL22LV10 Power-Up Reset Vcc Vcc (min.) t su t wl CLK t pr Internal Register Reset to Logic "0" ACTIVE LOW OUTPUT REGISTER Device Pin Reset to Logic "1" ACTIVE HIGH OUTPUT REGISTER Device Pin Reset to Logic "0" A D LL IS C DE O N VIC TI N ES U ED INTERNAL REGISTER Q - OUTPUT Circuitry within the GAL22V10 provides a reset signal to all registers during power-up. All internal registers will have their Q outputs set low after a specified time (tpr, 1μs MAX). As a result, the state on the registered output pins (if they are enabled) will be either high or low on power-up, depending on the programmed polarity of the output pins. This feature can greatly simplify state machine design by providing a known state on power-up. The timing diagram for power-up is shown below. Because of the asyn- chronous nature of system power-up, some conditions must be met to provide a valid power-up reset of the GAL22V10. First, the Vcc rise must be monotonic. Second, the clock input must be at static TTL level as shown in the diagram during power up. The registers will reset within a maximum of tpr time. As in normal system operation, avoid clocking the device until all input and feedback path setup times have been met. The clock must also meet the minimum pulse width requirements. Input/Output Equivalent Schematics PIN PIN Feedback Vcc Active Pull-up Circuit (GAL22LV10D Only) Active Pull-up Circuit (GAL22LV10D Only) Vcc ESD Protection Circuit Vref Tri-State Control Vcc Vcc Vref Data Output PIN PIN ESD Protection Circuit Typ. Vref = Vcc Typ. Vref = Vcc Typical Input Feedback (To Input Buffer) Typical Output 14 Specifications GAL22LV10 GAL22LV10D: Typical AC and DC Characteristic Diagrams Normalized Tpd vs Vcc 1.2 1.2 1.05 1.1 PT L->H 1 0.9 RISE 1.025 Normalized Tsu Normalized Tco PT H->L FALL 1 0.975 PT H->L 1.1 PT L->H 1 0.9 A D LL IS C DE O N VIC TI N ES U ED Normalized Tpd Normalized Tsu vs Vcc Normalized Tco vs Vcc 0.8 3.00 3.15 3.30 3.45 0.95 3.00 3.60 3.15 Supply Voltage (V) 0.8 3.00 3.60 1 0.9 0.8 -25 0 25 50 75 100 RISE 1.1 FALL 1 0.9 0.8 -25 Temperature (deg. C) 0 25 50 75 Delta Tpd vs # of Outputs Switching PT L->H 1.1 1 0.9 0.8 100 -55 125 -25 0 RISE -0.2 FALL -0.3 -0.4 -0.5 -0.1 -0.2 -0.3 RISE -0.4 FALL -0.5 1 2 3 4 5 6 7 8 9 10 1 2 3 4 5 6 7 8 9 10 Number of Outputs Switching Number of Outputs Switching Delta Tpd vs Output Loading Delta Tco vs Output Loading 20 RISE 12 FALL Delta Tco (ns) 20 16 8 4 0 -4 -8 16 RISE 12 FALL 8 4 0 -4 0 50 100 150 200 250 300 0 Output Loading (pF) 50 100 150 200 250 Output Loading (pF) 15 25 50 75 100 Temperature (deg. C) 0 Delta Tco (ns) Delta Tpd (ns) PT H->L 1.2 Delta Tco vs # of Outputs Switching 0 Delta Tpd (ns) 1.3 Temperature (deg. C) -0.1 3.60 0.7 0.7 -55 125 3.45 1.4 1.2 Normalized Tsu Normalized Tco PT L->H 1.1 3.30 Normalized Tsu vs Temp 1.3 PT H->L 1.2 3.15 Supply Voltage (V) Normalized Tco vs Temp 1.3 Normalized Tpd 3.45 Supply Voltage (V) Normalized Tpd vs Temp 0.7 -55 3.30 300 125 Specifications GAL22LV10 GAL22LV10D: Typical AC and DC Characteristic Diagrams Vol vs Iol Voh vs Ioh Voh (V) Vol (V) 0.8 0.6 0.4 4 3.1 3 3 Voh (V) 1 Voh vs Ioh 2 1 2.8 A D LL IS C DE O N VIC TI N ES U ED 0.2 2.9 0 0 0.00 5.00 10.00 15.00 20.00 2.7 0.00 25.00 30.00 5.00 Iol (mA) 1.00 0.80 3.45 1.30 1.2 1.25 1.1 1 0.9 0.8 3.60 -25 0 25 50 75 100 125 Temperature (deg. C) 0 10 Iik (mA) 5 5 4 3 15 20 2 25 1 30 0.50 1.00 1.50 2.00 Vin (V) 2.50 3.00 3.50 4.00 1.20 1.15 1.10 1.05 35 -2.00 -1.50 -1.00 Vik (V) 16 -0.50 0 25 50 75 Frequency (MHz) Input Clamp (Vik) Delta Icc vs Vin (1 input) 6 3.00 1.00 -55 7 2.00 Normalized Icc vs Freq. 0.7 3.30 1.00 Ioh(mA) Normalized Icc Normalized Icc Normalized Icc 1.20 3.15 0.00 1.3 Supply Voltage (V) Delta Icc (mA) 20.00 Normalized Icc vs Temp 1.40 0 0.00 15.00 Ioh(mA) Normalized Icc vs Vcc 0.60 3.00 10.00 0.00 100 Specifications GAL22LV10 GAL22LV10C: Typical AC and DC Characteristic Diagrams Normalized Tpd vs Vcc 1.2 1.2 1.05 PT L->H 1 0.9 RISE 1.025 Normalized Tsu 1.1 Normalized Tco PT H->L FALL 1 0.975 PT H->L 1.1 PT L->H 1 0.9 A D LL IS C DE O N VIC TI N ES U ED Normalized Tpd Normalized Tsu vs Vcc Normalized Tco vs Vcc 0.8 0.95 3.00 3.15 3.30 3.45 3.60 0.8 3.00 3.15 Supply Voltage (V) 3.45 3.60 3.00 1 0.9 0.8 0.7 FALL 1.1 1 0.9 0.8 0.7 0 25 50 75 100 125 -25 Temperature (deg. C) 0 25 50 75 PT H->L 1.2 PT L->H 1.1 1 0.9 0.8 100 -55 125 -25 Temperature (deg. C) Delta Tpd vs # of Outputs Switching Delta Tpd (ns) 1.3 0.7 -55 0 0 -0.1 -0.1 -0.2 -0.3 RISE -0.4 FALL -0.5 -0.2 -0.3 RISE -0.4 FALL -0.5 1 2 3 4 5 6 7 8 9 10 1 Number of Outputs Switching 2 3 4 5 6 7 8 9 10 Number of Outputs Switching Delta Tpd vs Output Loading Delta Tco vs Output Loading 26 28 24 22 RISE Delta Tco (ns) 20 FALL 16 12 8 4 0 RISE 18 FALL 14 10 6 2 -2 -4 -8 -6 0 50 100 150 200 250 0 300 Output Loading (pF) 50 100 150 200 250 Output Loading (pF) 17 0 25 50 75 100 Temperature (deg. C) Delta Tco vs # of Outputs Switching Delta Tco (ns) -25 Delta Tpd (ns) -55 3.60 1.4 RISE 1.2 Normalized Tsu Normalized Tco PT L->H 1.1 3.45 Normalized Tsu vs Temp 1.3 PT H->L 3.30 Supply Voltage (V) Normalized Tco vs Temp 1.3 1.2 3.15 Supply Voltage (V) Normalized Tpd vs Temp Normalized Tpd 3.30 300 125 Specifications GAL22LV10 GAL22LV10C: Typical AC and DC Characteristic Diagrams Vol vs Iol Voh vs Ioh Voh (V) Vol (V) 0.8 0.6 0.4 4 3.1 3 3 Voh (V) 1 Voh vs Ioh 2 1 2.8 A D LL IS C DE O N VIC TI N ES U ED 0.2 2.9 0 0.00 10.00 20.00 30.00 0 0.00 40.00 2.7 0.00 20.00 1.00 2.00 3.00 Ioh(mA) Normalized Icc vs Vcc Normalized Icc vs Temp Normalized Icc vs Freq. 1.2 1.20 1.00 0.80 1.1 1 0.9 0.8 3.00 3.15 3.30 3.45 3.60 Supply Voltage (V) -25 0 25 50 75 100 125 Temperature (deg. C) 0 10 Iik (mA) 3 2 1 20 30 40 50 0.50 1.00 1.50 2.00 Vin (V) 2.50 3.00 3.50 1.40 1.20 1.00 60 -2.00 -1.50 -1.00 Vik (V) 18 -0.50 0 25 50 75 Frequency (MHz) Input Clamp (Vik) Delta Icc vs Vin (1 input) 4 1.60 0.80 -55 5 4.00 1.80 Normalized Icc Normalized Icc Normalized Icc 15.00 Ioh(mA) 0.60 Delta Icc (mA) 10.00 Iol (mA) 1.40 0 0.00 5.00 0.00 100 Specifications GAL22LV10 Revision History Version Change Summary - 22lv10_05 Previous Lattice release. August 2006 22lv10_06 Updated for lead-free package options. August 2008 22lv10_07 Correction for DC electrical characteristics. A D LL IS C DE O N VIC TI N ES U ED Date 19