GAL16V8Z

GAL®16V8Z/GAL16V8ZD Device Datasheet
June 2010
All Devices Discontinued!
Product Change Notifications (PCNs) have been issued to discontinue all devices in this
data sheet.
The original datasheet pages have not been modified and do not reflect those changes.
Please refer to the table below for reference PCN and current product status.
Product Line
GAL16V8Z
GAL16V8ZD
Ordering Part Number
GAL16V8Z-12QS
GAL16V8Z-15QS
GAL16V8Z-12QJ
GAL16V8Z-12QP
GAL16V8Z-15QJ
GAL16V8Z-15QP
GAL16V8ZD-12QJ
GAL16V8ZD-12QP
GAL16V8ZD-15QJ
GAL16V8ZD-15QP
Product Status
Reference PCN
PCN#06-07
Discontinued
PCN#09-10
Discontinued
PCN#06-07
5555 N.E. Moore Ct. z Hillsboro, Oregon 97124-6421 z Phone (503) 268-8000 z FAX (503) 268-8347
Internet: http://www.latticesemi.com
GAL16V8Z
GAL16V8ZD
Zero Power E2CMOS PLD
Functional Block Diagram
Features
I/CLK
• ZERO POWER E2CMOS TECHNOLOGY
— 100μA Standby Current
— Input Transition Detection on GAL16V8Z
— Dedicated Power-down Pin on GAL16V8ZD
— Input and Output Latching During Power Down
CLK
8
OLMC
I/O/Q
8
OLMC
I/O/Q
8
OLMC
I/O/Q
8
OLMC
I/O/Q
8
OLMC
I/O/Q
8
OLMC
I/O/Q
8
OLMC
I/O/Q
8
OLMC
I/O/Q
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• HIGH PERFORMANCE E2CMOS TECHNOLOGY
— 12 ns Maximum Propagation Delay
— Fmax = 83.3 MHz
— 8 ns Maximum from Clock Input to Data Output
— TTL Compatible 16 mA Output Drive
— UltraMOS® Advanced CMOS Technology
PROGRAMMABLE
AND-ARRAY
(64 X 32)
I
I/DPP
• E2 CELL TECHNOLOGY
— Reconfigurable Logic
— Reprogrammable Cells
— 100% Tested/100% Yields
— High Speed Electrical Erasure (<100ms)
— 20 Year Data Retention
I
I
• EIGHT OUTPUT LOGIC MACROCELLS
— Maximum Flexibility for Complex Logic Designs
— Programmable Output Polarity
— Architecturally Similar to Standard GAL16V8
I
• PRELOAD AND POWER-ON RESET OF ALL REGISTERS
— 100% Functional Testability
I
• APPLICATIONS INCLUDE:
— Battery Powered Systems
— DMA Control
— State Machine Control
— High Speed Graphics Processing
I
OE
I/OE
• ELECTRONIC SIGNATURE FOR IDENTIFICATION
Description
Pin Configuration
The GAL16V8Z and GAL16V8ZD, at 100 μA standby current and
12ns
propagation delay provides the highest speed and lowest
DESCRIPTION
power combination PLD available in the market. The GAL16V8Z/
ZD is manufactured using Lattice Semiconductor's advanced zero
power E2CMOS process, which combines CMOS with Electrically
Erasable (E2) floating gate technology.
DIP/SOIC
3
The GAL16V8Z uses Input Transition Detection (ITD) to put the
device in standby mode and is capable of emulating the full functionality of the standard GAL16V8. The GAL16V8ZD utilizes a
dedicated power-down pin (DPP) to put the device in standby mode.
It has 15 inputs available to the AND array.
I/DPP
1
19
4
18
GAL16V8Z
I
I
I/O/Q
I/CLK
Vcc
I
I
PLCC
6
GAL16V8ZD
Top View
16
I
Unique test circuitry and reprogrammable cells allow complete AC,
DC, and functional testing during manufacture. As a result,
Lattice Semiconductor delivers 100% field programmability and
functionality of all GAL products. In addition, 100 erase/write cycles
and data retention in excess of 20 years are specified.
8
9
14
13
11
1
20
Vcc
I
2
19
I/ O/ Q
I
I/O/Q
3
GAL
18
I/ O/ Q
I/ O/ Q
I/D P P
4
I/O/Q
I
5
16V8Z 17
16V8ZD 16
I/O/Q
I
6
15
I/ O/ Q
I/O/Q
I
7
14
I/O/Q
I
8
13
I/O/Q
I
9
12
I/ O/ Q
10
11
I /O E
I/O/Q
I/ O/ Q
I/O/Q
I/O/Q
I/OE
GND
I
I
I/C LK
GND
Copyright © 1997 Lattice Semiconductor Corp. All brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject
to change without notice.
LATTICE SEMICONDUCTOR CORP., 5555 Northeast Moore Ct., Hillsboro, Oregon 97124, U.S.A.
Tel. (503) 268-8000; 1-800-LATTICE; FAX (503) 268-8556; http://www.latticesemi.com
16v8zzd_03
1
December 1997
Specifications GAL16V8Z
GAL16V8ZD
GAL16V8Z/ZD Ordering Information
GAL16V8Z: Commercial Grade Specifications
Tpd (ns)
Tsu (ns)
Tco (ns)
Icc (mA)
Isb (μA)
12
10
8
55
100
GAL16V8Z-12QP
55
100
GAL16V8Z-12QJ
15
10
55
100
GAL16V8Z-12QS
55
100
GAL16V8Z-15QP
55
100
GAL16V8Z-15QJ
Package
20-Pin Plastic DIP
20-Lead PLCC
1
20-Lead SOIC
20-Pin Plastic DIP
20-Lead PLCC
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15
Ordering #
55
100
GAL16V8Z-15QS
1
20-Lead SOIC
GAL16V8ZD: Commercial Grade Specifications
Tpd (ns)
12
Tsu (ns)
10
Tco (ns)
8
Icc (mA)
55
55
15
15
10
Isb (μA)
Ordering #
Package
100
GAL16V8ZD-12QP
1
20-Pin Plastic DIP
100
1
20-Lead PLCC
GAL16V8ZD-12QJ
1
55
100
GAL16V8ZD-15QP
55
100
GAL16V8ZD-15QJ1
20-Pin Plastic DIP
20-Lead PLCC
1. Discontinued per PCN #06-07. Contact Rochester Electronics for available inventory.
Part Number Description
XXXXXXXX _ XX
Device Name
GAL16V8Z (Zero Power ITD)
GAL16V8ZD (Zero Power DPP)
X X X
Grade
Blank = Commercial
Package
P = Plastic DIP
J = PLCC
S = SOIC
Speed (ns)
Active Power
Q = Quarter Power
2
Specifications GAL16V8Z
GAL16V8ZD
Output Logic Macrocell (OLMC)
The following discussion pertains to configuring the output logic
macrocell. It should be noted that actual implementation is accomplished by development software/hardware and is completely transparent to the user.
each macrocell controls the polarity of the output in any of the three
modes, while the AC1 bit of each of the macrocells controls the input/output configuration. These two global and 16 individual architecture bits define all possible configurations in a GAL16V8Z/ZD.
The information given on these architecture bits is only to give a
better understanding of the device. Compiler software will transparently set these architecture bits from the pin definitions, so the
user should not need to directly manipulate these architecture bits.
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There are three global OLMC configuration modes possible:
simple, complex, and registered. Details of each of these modes
is illustrated in the following pages. Two global bits, SYN and AC0,
control the mode configuration for all macrocells. The XOR bit of
Compiler Support for OLMC
In complex mode pin 1 and pin 11 become dedicated inputs and
use the feedback paths of pin 19 and pin 12 respectively. Because
of this feedback path usage, pin 19 and pin 12 do not have the
feedback option in this mode.
Software compilers support the three different global OLMC modes
as different device types. Most compilers also have the ability to
automatically select the device type, generally based on the register
usage and output enable (OE) usage. Register usage on the device
forces the software to choose the registered mode. All combinatorial outputs with OE controlled by the product term will force the
software to choose the complex mode. The software will choose
the simple mode only when all outputs are dedicated combinatorial
without OE control. For further details, refer to the compiler software manuals.
In simple mode all feedback paths of the output pins are routed
via the adjacent pins. In doing so, the two inner most pins ( pins
15 and 16) will not have the feedback option as these pins are
always configured as dedicated combinatorial output.
When using the standard GAL16V8 JEDEC fuse pattern generated
by the logic compilers for the GAL16V8ZD, special attention must
be given to pin 4 (DPP) to make sure that it is not used as one of
the functional inputs.
When using compiler software to configure the device, the user
must pay special attention to the following restrictions in each mode.
In registered mode pin 1 and pin 11 are permanently configured
as clock and output enable, respectively. These pins cannot be configured as dedicated inputs in the registered mode.
3
Specifications GAL16V8Z
GAL16V8ZD
Registered Mode
In the Registered mode, macrocells are configured as dedicated
registered outputs or as I/O functions.
Registered outputs have eight product terms per output. I/Os have
seven product terms per output.
Architecture configurations available in this mode are similar to
the common 16R8 and 16RP4 devices with various permutations
of polarity, I/O and register placement.
Pin 4 is used as dedicated power-down pin on GAL16V8ZD. It
cannot be used as functional input.
The JEDEC fuse numbers, including the User Electronic Signature
(UES) fuses and the Product Term Disable (PTD) fuses, are
shown on the logic diagram on the following page.
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All registered macrocells share common clock and output enable
control pins. Any macrocell can be configured as registered or
I/O. Up to eight registers or up to eight I/Os are possible in this
mode. Dedicated input or output functions can be implemented
as subsets of the I/O function.
CLK
Registered Configuration for Registered Mode
D
XOR
- SYN=0.
- AC0=1.
- XOR=0 defines Active Low Output.
- XOR=1 defines Active High Output.
- AC1=0 defines this output configuration.
- Pin 1 controls common CLK for the registered outputs.
- Pin 11 controls common OE for the registered outputs.
- Pin 1 & Pin 11 are permanently configured as CLK & OE
for registered output configuration.
Q
Q
OE
Combinatorial Configuration for Registered Mode
- SYN=0.
- AC0=1.
- XOR=0 defines Active Low Output.
- XOR=1 defines Active High Output.
- AC1=1 defines this output configuration.
- Pin 1 & Pin 11 are permanently configured as CLK & OE
for registered output configuration.
XOR
Note: The development software configures all of the architecture control bits and checks for proper pin usage automatically.
4
Specifications GAL16V8Z
GAL16V8ZD
Registered Mode Logic Diagram
DIP, SOIC & PLCC Package Pinouts
1
0
4
8
12
16
20
28
24
2128
PTD
0000
OLMC
0224
19
XOR-2048
AC1-2120
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2
0256
OLMC
0480
18
XOR-2049
AC1-2121
3
0512
OLMC
0736
17
XOR-2050
AC1-2122
* 4
0768
OLMC
0992
16
XOR-2051
AC1-2123
5
1024
OLMC
1248
15
XOR-2052
AC1-2124
6
1280
OLMC
1504
14
XOR-2053
AC1-2125
7
1536
OLMC
1760
13
XOR-2054
AC1-2126
8
1792
OLMC
2016
12
XOR-2055
AC1-2127
9
2191
64-USER ELECTRONIC SIGNATURE FUSES
2056, 2057, ....
.... 2118, 2119
Byte7 Byte6 ....
.... Byte1 Byte0
MSB
OE
11
SYN-2192
AC0-2193
* Note: Input not available on GAL16V8ZD
LSB
5
Specifications GAL16V8Z
GAL16V8ZD
Complex Mode
In the Complex mode, macrocells are configured as output only or
I/O functions.
All macrocells have seven product terms per output. One product
term is used for programmable output enable control. Pins 1 and
11 are always available as data inputs into the AND array.
Architecture configurations available in this mode are similar to the
common 16L8 and 16P8 devices with programmable polarity in
each macrocell.
Pin 4 is used as dedicated power-down pin on GAL16V8ZD. It cannot be used as functional input.
The JEDEC fuse numbers including the UES fuses and PTD fuses
are shown on the logic diagram on the following page.
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Up to six I/Os are possible in this mode. Dedicated inputs or outputs
can be implemented as subsets of the I/O function. The two outer
most macrocells (pins 12 & 19) do not have input capability. Designs requiring eight I/Os can be implemented in the Registered
mode.
Combinatorial I/O Configuration for Complex Mode
- SYN=1.
- AC0=1.
- XOR=0 defines Active Low Output.
- XOR=1 defines Active High Output.
- AC1 has no effect on this mode.
- Pin 13 through Pin 18 are configured to this function.
XOR
Combinatorial Output Configuration for Complex Mode
- SYN=1.
- AC0=1.
- XOR=0 defines Active Low Output.
- XOR=1 defines Active High Output.
- AC1 has no effect on this mode.
- Pin 12 and Pin 19 are configured to this
function.
XOR
Note: The development software configures all of the architecture control bits and checks for proper pin usage automatically.
6
Specifications GAL16V8Z
GAL16V8ZD
Complex Mode Logic Diagram
DIP, SOIC & PLCC Package Pinouts
1
2128
0
4
8
12
16
20
24
28
PTD
0000
OLMC
19
XOR-2048
AC1-2120
0224
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2
0256
OLMC
18
XOR-2049
AC1-2121
0480
3
0512
OLMC
17
XOR-2050
AC1-2122
0736
* 4
0768
OLMC
16
XOR-2051
AC1-2123
0992
5
1024
OLMC
15
XOR-2052
AC1-2124
1248
6
1280
OLMC
14
XOR-2053
AC1-2125
1504
7
1536
OLMC
13
XOR-2054
AC1-2126
1760
8
1792
OLMC
12
XOR-2055
AC1-2127
2016
9
11
2191
64-USER ELECTRONIC SIGNATURE FUSES
2056, 2057, ....
.... 2118, 2119
Byte7 Byte6 ....
.... Byte1 Byte0
MSB
SYN-2192
AC0-2193
* Note: Input not available on GAL16V8ZD
LSB
7
Specifications GAL16V8Z
GAL16V8ZD
Simple Mode
In the Simple mode, macrocells are configured as dedicated inputs
or as dedicated, always active, combinatorial outputs.
Pins 1 and 11 are always available as data inputs into the AND
array. The center two macrocells (pins 15 & 16) cannot be used
in the input configuration.
Architecture configurations available in this mode are similar to the
common 10L8 and 12P6 devices with many permutations of generic output polarity or input choices.
Pin 4 is used as dedicated power-down pin on GAL16V8ZD. It cannot be used as functional input.
All outputs in the simple mode have a maximum of eight porduct
terms that can control the logic. In addition, each output has programmable polarity.
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The JEDEC fuse numbers including the UES fuses and PTD fuses
are shown on the logic diagram.
Combinatorial Output with Feedback Configuration
for Simple Mode
Vcc
- SYN=1.
- AC0=0.
- XOR=0 defines Active Low Output.
- XOR=1 defines Active High Output.
- AC1=0 defines this configuration.
- All OLMC except pins 15 & 16 can be configured to
this function.
XOR
Combinatorial Output Configuration for Simple Mode
- SYN=1.
- AC0=0.
- XOR=0 defines Active Low Output.
- XOR=1 defines Active High Output.
- AC1=0 defines this configuration.
- Pins 15 & 16 are permanently configured to this
function.
Vcc
XOR
Dedicated Input Configuration for Simple Mode
- SYN=1.
- AC0=0.
- XOR=0 defines Active Low Output.
- XOR=1 defines Active High Output.
- AC1=1 defines this configuration.
- All OLMC except pins 15 & 16 can be configured to
this function.
Note: The development software configures all of the architecture control bits and checks for proper pin usage automatically.
8
Specifications GAL16V8Z
GAL16V8ZD
Simple Mode Logic Diagram
DIP, SOIC & PLCC Package Pinouts
1
2128
0
4
8
12
16
24
20
28
PTD
0000
OLMC
XOR-2048
AC1-2120
0224
19
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2
0256
OLMC
XOR-2049
AC1-2121
0480
18
3
0512
OLMC
XOR-2050
AC1-2122
0736
17
* 4
0768
OLMC
XOR-2051
AC1-2123
0992
16
5
OLMC
1024
XOR-2052
AC1-2124
1248
15
6
OLMC
1280
XOR-2053
AC1-2125
1504
14
7
1536
OLMC
XOR-2054
AC1-2126
1760
13
8
1792
OLMC
XOR-2055
AC1-2127
2016
9
12
11
2191
64-USER ELECTRONIC SIGNATURE FUSES
2056, 2057, ....
.... 2118, 2119
Byte7 Byte6 ....
.... Byte1 Byte0
MSB
LSB
SYN-2192
AC0-2193
* Note: Input not available on GAL16V8ZD
9
Specifications GAL16V8Z
GAL16V8ZD
Absolute Maximum Ratings(1)
Recommended Operating Conditions
Supply voltage VCC ........................................ –.5 to +7V
Input voltage applied .......................... –2.5 to VCC +1.0V
Off-state output voltage applied ......... –2.5 to VCC +1.0V
Storage Temperature ................................ –65 to 150°C
Ambient Temperature with
Power Applied ........................................... –55 to 125°C
Commercial Devices:
Ambient Temperature (TA) ............................... 0 to 75°C
Supply voltage (VCC)
with Respect to Ground ..................... +4.75 to +5.25V
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1. Stresses above those listed under the “Absolute Maximum
Ratings” may cause permanent damage to the device. These
are stress only ratings and functional operation of the device
at these or at any other conditions above those indicated in
the operational sections of this specification is not implied
(while programming, follow the programming specifications).
DC Electrical Characteristics
Over Recommended Operating Conditions (Unless Otherwise Specified)
SYMBOL
VIL
VIH
IIL
IIH
VOL
VOH
MIN.
TYP.2
MAX.
UNITS
Input Low Voltage
Vss – 0.5
—
0.8
V
Input High Voltage
2.0
—
Vcc+1
V
PARAMETER
CONDITION
Input or I/O Low Leakage Current
0V ≤ VIN ≤ VIL (MAX.)
—
—
–10
μA
Input or I/O High Leakage Current
3.5V ≤ VIN ≤ VCC
—
—
10
μA
Output Low Voltage
IOL = MAX. Vin = VIL or VIH
—
—
0.5
V
Output High Voltage
IOH = MAX. Vin = VIL or VIH
2.4
—
—
V
Vcc-1
—
—
V
Low Level Output Current
—
—
16
mA
High Level Output Current
—
—
–3.2
mA
–30
—
–150
mA
IOH = -100 μA Vin = VIL or VIH
IOL
IOH
IOS1
Output Short Circuit Current
COMMERCIAL
ISB
Stand-by Power
VCC = 5V VOUT = 0.5V
VIL = GND VIH = Vcc Outputs Open
Z-12/-15
ZD-12/-15
—
50
100
μA
VIL = 0.5V VIH = 3.0V
ftoggle = 15 MHz Outputs Open
Z-12/-15
ZD-12/-15
—
—
55
mA
Supply Current
ICC
Operating Power
Supply Current
TA = 25°C
1) One output at a time for a maximum duration of one second. Vout = 0.5V was selected to avoid test problems by tester ground
degradation. Characterized but not 100% tested.
2) Typical values are at Vcc = 5V and TA = 25 °C
Capacitance (TA = 25°C, f = 1.0 MHz)
SYMBOL
PARAMETER
MAXIMUM*
UNITS
TEST CONDITIONS
CI
Input Capacitance
10
pF
VCC = 5.0V, VI = 2.0V
CI/O
I/O Capacitance
10
pF
VCC = 5.0V, VI/O = 2.0V
*Characterized but not 100% tested.
10
Specifications GAL16V8Z
Specifications
GAL16V8Z
GAL16V8ZD
AC Switching Characteristics
Over Recommended Operating Conditions
PARAMETER
COM
-12
-15
MIN. MAX.
MIN. MAX.
DESCRIPTION
UNITS
A
Input or I/O to Combinational Output
3
12
3
15
ns
A
Clock to Output Delay
2
8
2
10
ns
—
Clock to Feedback Delay
—
6
—
7
ns
—
Setup Time, Input or Feedback before Clock↑
10
—
15
—
ns
—
Hold Time, Input or Feedback after Clock↑
0
—
0
—
ns
A
Maximum Clock Frequency with
External Feedback, 1/(tsu + tco)
55
—
40
—
MHz
A
Maximum Clock Frequency with
Internal Feedback, 1/(tsu + tcf)
62.5
—
45.5
—
MHz
A
Maximum Clock Frequency with
No Feedback
83.3
—
62.5
—
MHz
—
Clock Pulse Duration, High
6
—
8
—
ns
—
Clock Pulse Duration, Low
6
—
8
—
ns
B
Input or I/O to Output Enabled
—
12
—
15
ns
B
OE to Output Enabled
—
12
—
15
ns
C
Input or I/O to Output Disabled
—
15
—
15
ns
C
OE to Output DIsabled
—
12
—
15
ns
—
Last Active Input to Standby
60
140
50
150
ns
—
Standby to Active Output
6
13
5
15
ns
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tpd
tco
tcf2
tsu
th
TEST
COND1.
COM
fmax3
twh
twl
ten
tdis
tas
tsa4
1) Refer to Switching Test Conditions section.
2) Calculated from fmax with internal feedback. Refer to fmax Specification section.
3) Refer to fmax Specification section.
4) Add tsa to tpd, tsu, ten and tdis when the device is coming out of standby state.
Standby Power Timing Waveforms
Icc
POWER
Isb
t as
tsa
tpd
INPUT or
I/O FEEDBACK
ten, tdis
OE
*
tsu
* Note: Rising clock edges
are allowed during tsa but
outputs are not guaranteed.
CLK
tco
OUTPUT
11
Specifications GAL16V8ZD
AC Switching Characteristics
Over Recommended Operating Conditions
PARAMETER
COM
-12
-15
MIN. MAX.
MIN. MAX.
DESCRIPTION
UNITS
A
Input or I/O to Combinational Output
3
12
3
15
ns
A
Clock to Output Delay
2
8
2
10
ns
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tpd
tco
tcf2
tsu
th
TEST
COND1.
COM
fmax3
twh
twl
ten
tdis
—
Clock to Feedback Delay
—
6
—
7
ns
—
Setup Time, Input or Feedback before Clock↑
10
—
15
—
ns
—
Hold Time, Input or Feedback after Clock↑
0
—
0
—
ns
A
Maximum Clock Frequency with
External Feedback, 1/(tsu + tco)
55
—
40
—
MHz
A
Maximum Clock Frequency with
Internal Feedback, 1/(tsu + tcf)
62.5
—
45.5
—
MHz
A
Maximum Clock Frequency with
No Feedback
83.3
—
62.5
—
MHz
—
Clock Pulse Duration, High
6
—
8
—
ns
—
Clock Pulse Duration, Low
6
—
8
—
ns
B
Input or I/O to Output Enabled
—
12
—
15
ns
B
OE to Output Enabled
—
12
—
15
ns
C
Input or I/O to Output Disabled
—
15
—
15
ns
C
OE to Output Disabled
—
12
—
15
ns
1) Refer to Switching Test Conditions section.
2) Calculated from fmax with internal feedback. Refer to fmax Specification section.
3) Refer to fmax Specification section.
12
Specifications GAL16V8ZD
Dedicated Power-Down Pin Specifications
Over Recommended Operating Conditions
PARAMETER
twhd
twld
TEST
COND1.
COM
COM
-12
-15
MIN. MAX.
MIN. MAX.
DESCRIPTION
UNITS
—
DPP Pulse Duration High
12
—
15
—
ns
—
DPP Pulse Duration Low
25
—
30
—
ns
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ACTIVE TO STANDBY
tivdh
tgvdh
tcvdh
tdhix
tdhgx
tdhcx
—
Valid Input before DPP High
5
—
8
—
ns
—
Valid OE before DPP High
0
—
0
—
ns
—
Valid Clock Before DPP High
0
—
0
—
ns
—
Input Don't Care after DPP High
—
2
—
5
ns
—
OE Don't Care after DPP High
—
6
—
9
ns
—
Clock Don't Care after DPP High
—
8
—
11
ns
—
DPP Low to Valid Input
12
—
15
—
ns
—
DPP Low to Valid OE
16
—
20
—
ns
—
DPP Low to Valid Clock
18
—
20
—
ns
A
DPP Low to Valid Output
5
24
5
30
ns
STANDBY TO ACTIVE
tdliv
tdlgv
tdlcv
tdlov
1) Refer to Switching Test Conditions section.
Dedicated Power-Down Pin Timing Waveforms
DPP
tivdh
tdhix
tdliv
tgvdh
tdhgx
tdlgv
INPUT or
I/O FEEDBACK
OE
tcvdh
tdhcx
tdlcv
CLK
tco
t pd, t en, t dis
OUTPUT
13
tdlov
Specifications GAL16V8Z
GAL16V8ZD
Switching Waveforms
INPUT or
I/O FEEDBACK
INPUT or
I/O FEEDBACK
VALID INPUT
VALID INPUT
tsu
tpd
th
CLK
COMBINATIONAL
OUTPUT
tco
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REGISTERED
OUTPUT
1/fmax
(external fdbk)
Combinatorial Output
INPUT or
I/O FEEDBACK
Registered Output
tdis
ten
COMBINATIONAL
OUTPUT
OE
tdis
Input or I/O to Output Enable/Disable
ten
REGISTERED
OUTPUT
OE to Output Enable/Disable
twh
twl
CLK
CLK
1/ fmax
(w/o fb)
1/ fmax (internal fdbk)
t cf
REGISTERED
FEEDBACK
Clock Width
fmax with Feedback
14
tsu
Specifications GAL16V8Z
GAL16V8ZD
fmax Descriptions
CLK
LOGIC
ARRAY
REGISTER
CLK
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LOGIC
ARRAY
tsu
tco
REGISTER
fmax with External Feedback 1/(tsu+tco)
Note: fmax with external feedback is calculated from
measured tsu and tco.
t cf
t pd
CLK
fmax with Internal Feedback 1/(tsu+tcf)
LOGIC
ARRAY
Note: tcf is a calculated value, derived by subtracting
tsu from the period of fmax w/internal feedback (tcf
= 1/fmax - tsu). The value of tcf is used primarily
when calculating the delay from clocking a register
to a combinatorial output (through registered feedback), as shown above. For example, the timing
from clock to a combinatorial output is equal to tcf
+ tpd.
REGISTER
tsu + th
fmax with No Feedback
Note: fmax with no feedback may be less than 1/(twh
+ twl). This is to allow for a clock duty cycle of other
than 50%.
Switching Test Conditions
Input Pulse Levels
Input Rise and Fall Times
Input Timing Reference Levels
Output Timing Reference Levels
Output Load
GND to 3.0V
3ns 10% – 90%
1.5V
1.5V
+5V
R1
See Figure
3-state levels are measured 0.5V from steady-state active
level.
FROM OUTPUT (O/Q)
UNDER TEST
TEST POINT
Output Load Conditions (see figure)
Test Condition
A
B
Active High
Active Low
C
Active High
Active Low
R1
300Ω
∞
300Ω
∞
300Ω
R2
390Ω
390Ω
390Ω
390Ω
390Ω
CL
50pF
50pF
50pF
5pF
5pF
R2
C L*
*C L INCLUDES TEST FIXTURE AND PROBE CAPACITANCE
15
Specifications GAL16V8Z
GAL16V8ZD
Electronic Signature
Output Register Preload
An electronic signature word is provided in every GAL16V8Z/ZD
device. It contains 64 bits of reprogrammable memory that can
contain user defined data. Some uses include user ID codes,
revision numbers, or inventory control. The signature data is
always available to the user independent of the state of the security cell.
When testing state machine designs, all possible states and state
transitions must be verified in the design, not just those required
in the normal machine operations. This is because, in system
operation, certain events occur that may throw the logic into an
illegal state (power-up, line voltage glitches, brown-outs, etc.). To
test a design for proper treatment of these conditions, a way must
be provided to break the feedback paths, and force any desired
(i.e., illegal) state into the registers. Then the machine can be
sequenced and the outputs tested for correct next state conditions.
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NOTE: The electronic signature is included in checksum calculations. Changing the electronic signature will alter checksum.
Security Cell
The GAL16V8Z/ZD devices includes circuitry that allows each registered output to be synchronously set either high or low. Thus,
any present state condition can be forced for test sequencing. If
necessary, approved GAL programmers capable of executing test
vectors perform output register preload automatically.
A security cell is provided in the GAL16V8Z/ZD devices to prevent unauthorized copying of the array patterns. Once programmed, this cell prevents further read access to the functional
bits in the device. This cell can only be erased by re-programming the device, so the original configuration can never be examined once this cell is programmed. The electronic signature
data is always available to the user, regardless of the state of this
security cell.
Input Buffers
GAL16V8Z/ZD
devices are designed with TTL level compatible
INPUT BUFFERS
input buffers. These buffers, with their characteristically high impedance, load driving logic much less than traditional bipolar devices. This allows for a greater fan out from the driving logic.
Device Programming
GAL devices are programmed using a Lattice Semiconductorapproved Logic Programmer, available from a number of manufacturers (see the Development Tools Section of the Data Book).
Complete programming of the device takes only a few seconds.
Erasing of the device is transparent to the user, and is done automatically as part of the programming cycle.
GAL16V8Z/ZD input buffers have latches within the buffers. As
a result, when the device goes into standby mode the inputs will
be latched to its values prior to standby. In order to overcome the
input latches, they will have to be driven by an external source.
Lattice Semiconductor recommends that all unused inputs and
tri-stated I/O pins for both devices be connected to another active input, VCC, or GND. Doing this will tend to improve noise immunity and reduce ICC for the device.
Input Transition Detection (ITD)
The GAL16V8Z relies on its internal input detection circuitry to
put the device in to power down mode. If there is no input transition for the specified period of time, the device will go into the
power down state. Any valid input transition will put the device
back into the active state. The first rising clock transition from
power-down state only acts as a wake up signal to the device and
will not clock the data input through to the output (refer to standby
power timing waveform for more detail). Any input pulse widths
greater than 5ns at input voltage level of 1.5V will be detected as
input transition. The device will not detect any input pulse widths
less than 1ns measured at input voltage level of 1.5V as an input transition.
Typical Input Characteristic
40
Input Current (μA)
30
Dedicated Power-Down Pin
20
10
0
-10
-20
-30
-40
The GAL16V8ZD uses pin 4 as the dedicated power-down signal
to put the device in to the power-down state. DPP is an active high
signal where a logic high driven on this signal puts the device into
power-down state. Input pin 4 cannot be used as a functional input
on this device.
0
1
2
3
Input Voltage (Volts)
16
4
5
Specifications GAL16V8Z
GAL16V8ZD
Power-Up Reset
Vcc
Vcc (min.)
t su
t wl
CLK
t pr
INTERNAL REGISTER
Q - OUTPUT
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Internal Register
Reset to Logic "0"
FEEDBACK/EXTERNAL
OUTPUT REGISTER
Device Pin
Reset to Logic "1"
Circuitry within the GAL16V8Z/ZD provides a reset signal to all
registers during power-up. All internal registers will have their
Q outputs set low after a specified time (tpr, 1μs MAX). As a result,
the state on the registered output pins (if they are enabled) will
always be high on power-up, regardless of the programmed
polarity of the output pins. This feature can greatly simplify state
machine design by providing a known state on power-up. The
timing diagram for power-up is shown below. Because of the
asynchronous nature of system power-up, some conditions must
be met to provide a valid power-up reset of the GAL16V8Z/ZD.
First, the VCC rise must be monotonic. Second, the clock input
must be at static TTL level as shown in the diagram during power
up. The registers will reset within a maximum of tpr time. As in
normal system operation, avoid clocking the device until all input and feedback path setup times have been met. The clock
must also meet the minimum pulse width requirements.
Input/Output Equivalent Schematics
PIN
PIN
Feedback
Vcc
Vcc
Tri-State
Control
Vcc
ESD
Protection
Circuit
Vcc
Data
Output
PIN
PIN
ESD
Protection
Circuit
Feedback
(To Input Buffer)
Typical Input
Typical Output
17
Specifications GAL16V8Z
GAL16V8ZD
Typical AC and DC Characteristics
Normalized Tpd vs Vcc
1.4
1.2
PT L->H
1
1.1
FALL
1
0.9
1.3
PT H->L
1.2
PT L->H
1.1
1
0.9
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0.9
RISE
Normalized Tsu
1.1
Normalized Tco
PT H->L
0.8
0.8
4.50
4.75
Supply Voltage (V)
Normalized Tpd vs Temp
5.25
4.50
5.50
PT L->H
1
0.9
0.8
Normalized Tsu vs Temp
1.2
1.1
FALL
1
0.9
0.8
PT L->H
1.1
1
0.9
0.8
-55
125
Temperature (deg. C)
Delta Tco vs # of Outputs
Switching
0
Delta Tco (ns)
0
Delta Tpd (ns)
100
75
50
Delta Tpd vs # of Outputs
Switching
-0.5
-1
RISE
-1.5
FALL
-2
-0.5
-1
RISE
-1.5
FALL
-2
3
4
5
6
7
8
1
Number of Outputs Switching
2
3
4
5
6
7
8
Number of Outputs Switching
Delta Tpd vs Output Loading
Delta Tco vs Output Loading
10
10
8
RISE
6
FALL
Delta Tco (ns)
Delta Tpd (ns)
PT H->L
1.2
0.7
25
0
-25
-55
125
100
75
50
25
0
-25
-55
1.3
Temperature (deg. C)
2
4
2
0
8
RISE
6
FALL
4
2
0
-2
0
50
100
150
5.50
1.4
RISE
Temperature (deg. C)
1
5.25
Normalized Tco vs Temp
0.7
0.7
5.00
Supply Voltage (V)
Normalized Tsu
1.1
Normalized Tco
1.2
PT H->L
4.75
Supply Voltage (V)
1.3
1.3
Normalized Tpd
5.00
200
250
-2
300
0
Output Loading (pF)
50
100
150
200
250
Output Loading (pF)
18
100
5.50
75
5.25
50
5.00
0
4.75
25
4.50
-25
0.8
300
125
1.2
Normalized Tpd
Normalized Tsu vs Vcc
Normalized Tco vs Vcc
Specifications GAL16V8Z
GAL16V8ZD
Typical AC and DC Characteristics
Vol vs Iol
1.25
Voh (V)
1
0.75
0.5
5
5
4
4.5
Voh (V)
1.5
Vol (V)
Voh vs Ioh
Voh vs Ioh
3
2
3.5
3
1
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0.25
4
0
2.5
0
0.00
20.00
40.00
0.00
60.00
10.00
20.00
30.00
40.00
50.00
0.00
60.00
1.00
2.00
3.00
4.00
Iol (mA)
Ioh(mA)
Ioh(mA)
Normalized Icc vs Vcc
Normalized Icc vs Temp
Normalized Icc vs Freq. (DPP
& ITD > 10MHz)
1.2
1.30
1.10
1.00
0.90
0.80
0.70
1.1
Normalized Icc
Normalized Icc
Normalized Icc
1.30
1.20
1
0.9
0.8
4.50
4.75
5.00
5.25
1.10
1.00
0.90
0.80
-55
5.50
1.20
Supply Voltage (V)
-25
0
25
50
75
100
125
0
Temperature (deg. C)
Delta Icc vs Vin (1 input)
50
75
100
Frequency (MHz)
Normalized Icc vs Freq. (ITD)
Input Clamp (Vik)
5
25
1
0
Normalized Icc
4
20
Iik (mA)
Delta Icc (mA)
10
3
2
1
30
40
50
60
70
0.8
0.6
0.4
0.2
80
0
90
0.00 0.50 1.00 1.50 2.00 2.50 3.00 3.50 4.00
Vin (V)
-1.00
0
-0.80
-0.60
-0.40
Vik (V)
19
-0.20
0.00
1
10
100
1000
Frequency (KHz)
10000
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Notes
PB