ETC ISPGAL22V10C-7LK

ispGAL22V10
In-System Programmable E2CMOS PLD
Generic Array Logic™
Features
Functional Block Diagram
• IN-SYSTEM PROGRAMMABLE™ (5-V ONLY)
— 4-Wire Serial Programming Interface
— Minimum 10,000 Program/Erase Cycles
— Built-in Pull-Down on SDI Pin Eliminates Discrete
Resistor on Board (ispGAL22V10C Only)
RESET
I/CLK
8
OLMC
I/O/Q
OLMC
I/O/Q
OLMC
I/O/Q
OLMC
I/O/Q
OLMC
I/O/Q
OLMC
I/O/Q
OLMC
I/O/Q
OLMC
I/O/Q
OLMC
I/O/Q
OLMC
I/O/Q
I
10
• HIGH PERFORMANCE E2CMOS® TECHNOLOGY
— 7.5 ns Maximum Propagation Delay
— Fmax = 111 MHz
— 5 ns Maximum from Clock Input to Data Output
— UltraMOS® Advanced CMOS Technology
I
12
PROGRAMMABLE
AND-ARRAY
(132X44)
I
I
• ACTIVE PULL-UPS ON ALL LOGIC INPUT AND I/O PINS
• COMPATIBLE WITH STANDARD 22V10 DEVICES
— Fully Function/Fuse-Map/Parametric Compatible
with Bipolar and CMOS 22V10 Devices
I
I
• E2 CELL TECHNOLOGY
— In-System Programmable Logic
— 100% Tested/100% Yields
— High Speed Electrical Erasure (<100ms)
— 20 Year Data Retention
I
I
• TEN OUTPUT LOGIC MACROCELLS
— Maximum Flexibility for Complex Logic Designs
14
16
16
14
12
I
• APPLICATIONS INCLUDE:
— DMA Control
— State Machine Control
— High Speed Graphics Processing
— Software-Driven Hardware Configuration
10
I
I
SDO
SDI
MODE
SCLK
• ELECTRONIC SIGNATURE FOR IDENTIFICATION
Description
8
PROGRAMMING
LOGIC
PRESET
Pin Configuration
The ispGAL22V10, at 7.5ns maximum propagation delay time,
combines a high performance CMOS process with Electrically Erasable (E2) floating gate technology to provide the industry's first insystem programmable 22V10 device. E2 technology offers high
speed (<100ms) erase times, providing the ability to reprogram or
reconfigure the device quickly and efficiently.
The generic architecture provides maximum design flexibility by allowing the Output Logic Macrocell (OLMC) to be configured by the
user. The ispGAL22V10 is fully function/fuse map/parametric compatible with standard bipolar and CMOS 22V10 devices. The standard PLCC package provides the same functional pinout as the
standard 22V10 PLCC package with No-Connect pins being used
for the ISP interface signals.
28
I/O/Q
Vcc
2
SSOP
I/O/Q
SCLK
I
4
I
I/CLK
I
PLCC
26
5
25
7
23
I
I
I/O/Q
ispGAL22V10
MODE
9
21
I
I/O/Q
I/O/Q
14
18 19
16
I/O/Q
SCLK
I/CLK
I
I
I
I
I
MODE
I
I
I
I
I
GND
1
28
7
ispGAL
22V10 22
Top View
14
15
Vcc
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/O/Q
SDO
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I
SDI
I/O/Q
I/O/Q
I
SDI
GND
I
11 12
I
I
Unique test circuitry and reprogrammable cells allow complete AC,
DC, and functional testing during manufacture. As a result, Lattice Semiconductor delivers 100% field programmability and functionality of all GAL products. In addition, 10,000 erase/write cycles
and data retention in excess of 20 years are specified.
I/O/Q
SDO
Top View
I
I/O/Q
Copyright © 1997 Lattice Semiconductor Corp. All brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject
to change without notice.
LATTICE SEMICONDUCTOR CORP., 5555 Northeast Moore Ct., Hillsboro, Oregon 97124, U.S.A.
Tel. (503) 268-8000; 1-800-LATTICE; FAX (503) 268-8556; http://www.latticesemi.com
isp22v10_02
1
July 1997
Specifications ispGAL22V10
Ordering Information
Commercial Grade Specifications
Tpd (ns)
Tsu (ns)
Tco (ns)
Icc (mA)
7.5
6.5
5
140
10
15
7
10
7
140
8
140
Ordering #
Package
ispGAL22V10C-7LJ
28-Lead PLCC
ispGAL22V10C-7LK
28-Lead SSOP
ispGAL22V10B-7LJ
28-Lead PLCC
ispGAL22V10C-10LJ
28-Lead PLCC
ispGAL22V10C-10LK
28-Lead SSOP
ispGAL22V10B-10LJ
28-Lead PLCC
ispGAL22V10C-15LJ
28-Lead PLCC
ispGAL22V10C-15LK
28-Lead SSOP
ispGAL22V10B-15LJ
28-Lead PLCC
Industrial Grade Specifications
Tpd (ns)
Tsu (ns)
Tco (ns)
Icc (mA)
15
10
8
165
Ordering #
Package
ispGAL22V10C-15LJI
28-Lead PLCC
ispGAL22V10C-15LKI
28-Lead SSOP
Part Number Description
XXXXXXXX _ XX
X
X X
ispGAL22V10C Device Name
ispGAL22V10B
Grade
Speed (ns)
L = Low Power Power
Blank = Commercial
I = Industrial
Package J = PLCC
K = SSOP
2
Specifications ispGAL22V10
Output Logic Macrocell (OLMC)
The ispGAL22V10 has a variable number of product terms per
OLMC. Of the ten available OLMCs, two OLMCs have access to
eight product terms (pins 17 and 27), two have ten product terms
(pins 18 and 26), two have twelve product terms (pins 19 and 25),
two have fourteen product terms (pins 20 and 24), and two OLMCs
have sixteen product terms (pins 21 and 23). In addition to the
product terms available for logic, each OLMC has an additional
product-term dedicated to output enable control.
The ispGAL22V10 has a product term for Asynchronous Reset (AR)
and a product term for Synchronous Preset (SP). These two product terms are common to all registered OLMCs. The Asynchronous
Reset sets all registers to zero any time this dedicated product term
is asserted. The Synchronous Preset sets all registers to a logic
one on the rising edge of the next clock pulse after this product term
is asserted.
NOTE: The AR and SP product terms will force the Q output of the
flip-flop into the same state regardless of the polarity of the output.
Therefore, a reset operation, which sets the register output to a zero,
may result in either a high or low at the output pin, depending on
the pin polarity chosen.
The output polarity of each OLMC can be individually programmed
to be true or inverting, in either combinatorial or registered mode.
This allows each output to be individually configured as either active
high or active low.
A R
D
4 TO 1
MUX
Q
CLK
Q
SP
2 TO 1
MUX
ispGAL22V10 OUTPUT LOGIC MACROCELL (OLMC)
Output Logic Macrocell Configurations
NOTE: In registered mode, the feedback is from the /Q output of
the register, and not from the pin; therefore, a pin defined as registered is an output only, and cannot be used for dynamic
I/O, as can the combinatorial pins.
Each of the Macrocells of the ispGAL22V10 has two primary functional modes: registered, and combinatorial I/O. The modes and
the output polarity are set by two bits (SO and S1), which are normally controlled by the logic compiler. Each of these two primary
modes, and the bit settings required to enable them, are described
below and on the following page.
COMBINATORIAL I/O
In combinatorial mode the pin associated with an individual OLMC
is driven by the output of the sum term gate. Logic polarity of the
output signal at the pin may be selected by specifying that the output
buffer drive either true (active high) or inverted (active low). Output tri-state control is available as an individual product-term for
each output, and may be individually set by the compiler as either
“on” (dedicated output), “off” (dedicated input), or “product-term
driven” (dynamic I/O). Feedback into the AND array is from the pin
side of the output enable buffer. Both polarities (true and inverted)
of the pin are fed back into the AND array.
REGISTERED
In registered mode the output pin associated with an individual
OLMC is driven by the Q output of that OLMC’s D-type flip-flop.
Logic polarity of the output signal at the pin may be selected by
specifying that the output buffer drive either true (active high) or
inverted (active low). Output tri-state control is available as an individual product-term for each OLMC, and can therefore be defined
by a logic equation. The D flip-flop’s /Q output is fed back into the
AND array, with both the true and complement of the feedback
available as inputs to the AND array.
3
Specifications ispGAL22V10
Registered Mode
AR
AR
Q
D
CLK
Q
D
Q
CLK
SP
Q
SP
ACTIVE LOW
ACTIVE HIGH
S0 = 0
S1 = 0
S0 = 1
S1 = 0
Combinatorial Mode
ACTIVE LOW
ACTIVE HIGH
S0 = 0
S1 = 1
S0 = 1
S1 = 1
4
Specifications ispGAL22V10
ispGAL22V10 Logic Diagram/JEDEC Fuse Map
PLCC & SSOP Package Pinout
2
0
4
8
12
16
20
24
28
32
36
40
ASYNCHRONOUS RESET
(TO ALL REGISTERS)
0000
0044
.
.
.
0396
8
OLMC
S0
5808
S1
5809
0440
.
.
.
.
0880
10
OLMC
S0
5810
S1
5811
3
0924
.
.
.
.
.
1452
12
OLMC
27
26
25
S0
5812
S1
5813
4
1496
.
.
.
.
.
.
2112
14
OLMC
24
S0
5814
S1
5815
5
2156
.
.
.
.
.
.
.
2860
16
OLMC
23
S0
5816
S1
5817
6
2904
.
.
.
.
.
.
.
3608
16
OLMC
21
S0
5818
S1
5819
7
3652
.
.
.
.
.
.
4268
14
OLMC
20
S0
5820
S1
5821
9
4312
.
.
.
.
.
4840
12
OLMC
19
S0
5822
S1
5823
10
4884
.
.
.
.
5324
10
OLMC
S0
5824
S1
5825
11
5368
.
.
.
5720
8
OLMC
S0
5826
S1
5827
12
SYNCHRONOUS PRESET
(TO ALL REGISTERS)
5764
13
5828, 5829 ...
Electronic Signature
... 5890, 5891
Byte 7 Byte 6 Byte 5 Byte 4 Byte 3 Byte 2 Byte 1 Byte 0
M
S
B
L
S
B
5
18
17
16
Specifications ispGAL22V10C
SpecificationsispGAL22V10B
ispGAL22V10
Absolute Maximum Ratings(1)
Recommended Operating Conditions
Supply voltage VCC ....................................... -0.5 to +7V
Commercial Devices:
Ambient Temperature (TA) ............................. 0 to +75°C
Supply voltage (VCC)
with Respect to Ground ..................... +4.75 to +5.25V
Input voltage applied ........................... -2.5 to VCC +1.0V
Off-state output voltage applied .......... -2.5 to VCC +1.0V
Storage Temperature ................................. -65 to 150°C
Ambient Temperature with
Power Applied ......................................... -55 to 125°C
Industrial Devices:
Ambient Temperature (TA) ............................ -40 to 85°C
Supply voltage (VCC)
with Respect to Ground ..................... +4.50 to +5.50V
1. Stresses above those listed under the “Absolute Maximum
Ratings” may cause permanent damage to the device. These
are stress only ratings and functional operation of the device
at these or at any other conditions above those indicated in
the operational sections of this specification is not implied
(while programming, follow the programming specifications).
DC Electrical Characteristics
Over Recommended Operating Conditions (Unless Otherwise Specified)
SYMBOL
VIL
VIH
IIL
MIN.
TYP.4
MAX.
UNITS
Input Low Voltage
Vss – 0.5
—
0.8
V
Input High Voltage
2.0
—
Vcc+1
V
0V ≤ VIN ≤ VIL (MAX.)
—
—
–100
µA
SDI Low Leakage Current
0V ≤ VIN ≤ VIL (MAX.)
—
—
250
µA
Input or I/O High Leakage Current
3.5V ≤ VIN ≤ VCC
—
—
10
µA
SDI High Leakage Current2
VIN = VOH (MIN.)
—
—
1
mA
Output Low Voltage
IOL = MAX. Vin = VIL or VIH
—
—
0.5
V
Output High Voltage
IOH = MAX. Vin = VIL or VIH
2.4
—
—
V
Low Level Output Current
—
—
16
mA
High Level Output Current
—
—
–3.2
mA
TA = 25°C
–30
—
–130
mA
L -7/-10/-15
—
90
140
mA
L -15
—
90
165
mA
PARAMETER
CONDITION
Input or I/O Low Leakage Current1
2
IIH
VOL
VOH
IOL
IOH
IOS3
Output Short Circuit Current
COMMERCIAL
ICC
Operating Power
Supply Current
INDUSTRIAL
ICC
Operating Power
Supply Current
VCC = 5V
VOUT = 0.5V
VIL = 0.5V VIH = 3.0V
ftoggle = 15MHz Outputs Open
VIL = 0.5V VIH = 3.0V
ftoggle = 15MHz Outputs Open
1) The leakage current is due to the internal pull-up on all pins (except SDI on ispGAL22V10C). See Input Buffer section for
more information.
2) The leakage current is due to the internal pull-down on the SDI pin (ispGAL22V10C only). See Input Buffer section for more
information.
3) One output at a time for a maximum duration of one second. Vout = 0.5V was selected to avoid test problems caused by tester
ground degradation. Characterized but not 100% tested.
4) Typical values are at Vcc = 5V and TA = 25 °C
6
Specifications ispGAL22V10C
SpecificationsispGAL22V10B
ispGAL22V10
AC Switching Characteristics
Over Recommended Operating Conditions
PARAMETER
tpd
tco
tcf2
tsu1
tsu2
th
fmax3
twh
twl
ten
tdis
tar
tarw
tarr
tspr
TEST
COND.1
COM
COM
COM/IND
-7
-10
-15
MIN. MAX.
MIN. MAX.
MIN. MAX.
DESCRIPTION
UNITS
A
Input or I/O to Combinatorial Output
—
7.5
—
10
—
15
ns
A
Clock to Output Delay
—
5
—
7
—
8
ns
—
Clock to Feedback Delay
—
2.5
—
2.5
—
2.5
ns
—
Setup Time, Input or Feedback before Clock↑
6.5
—
7
10
—
ns
—
Setup Time, SP before Clock↑
10
—
10
—
10
—
ns
—
Hold Time, Input or Feedback after Clock↑
0
—
0
—
0
—
ns
A
Maximum Clock Frequency with
External Feedback, 1/(tsu + tco)
87
—
71.4
—
55.5
—
MHz
A
Maximum Clock Frequency with
Internal Feedback, 1/(tsu + tcf)
111
—
105
—
80
—
MHz
A
Maximum Clock Frequency with
No Feedback
111
—
105
—
83.3
—
MHz
—
Clock Pulse Duration, High
4
—
4
—
6
—
ns
—
Clock Pulse Duration, Low
4
—
4
—
6
—
ns
B
Input or I/O to Output Enabled
—
8
—
10
—
15
ns
C
Input or I/O to Output Disabled
—
8
—
10
—
15
ns
A
Input or I/O to Asynchronous Reset of Register
—
13
—
13
—
20
ns
—
Asynchronous Reset Pulse Duration
8
—
8
—
15
—
ns
—
Asynchronous Reset to Clock Recovery Time
8
—
8
—
10
—
ns
—
Synchronous Preset to Clock Recovery Time
10
—
10
—
10
—
ns
1) Refer to Switching Test Conditions section.
2) Calculated from fmax with internal feedback. Refer to fmax Description section.
3) Refer to fmax Description section.
Capacitance (TA = 25°C, f = 1.0MHz)
SYMBOL
PARAMETER
MAXIMUM*
UNITS
TEST CONDITIONS
CI
Input Capacitance
8
pF
VCC = 5.0V, VI = 2.0V
CI/O
I/O Capacitance
8
pF
VCC = 5.0V, VI/O = 2.0V
*Characterized but not 100% tested.
7
Specifications ispGAL22V10
Switching Waveforms
INPUT or
I/O FEEDBACK
INPUT or
I/O FEEDBACK
VALID INPUT
VALID INPUT
ts u
t pd
COMBINATORIAL
OUTPUT
th
CLK
tc o
REGISTERED
OUTPUT
Combinatorial Output
1 / fm a x
(external fdbk)
Registered Output
INPUT or
I/O FEEDBACK
tdis
ten
OUTPUT
CLK
1 / fm ax (int ern al fd bk )
Input or I/O to Output Enable/Disable
t su
tc f
REGISTERED
FEEDBACK
tw l
tw h
fmax with Feedback
CLK
1 / fm a x
(w/o fdbk)
Clock Width
INPUT or
I/O FEEDBACK
DRIVING SP
INPUT or
I/O FEEDBACK
DRIVING AR
tsu
th
tspr
tarw
CLK
CLK
tarr
tco
REGISTERED
OUTPUT
REGISTERED
OUTPUT
tar
Asynchronous Reset
Synchronous Preset
8
Specifications ispGAL22V10
fmax Descriptions
CL K
CLK
LOGIC
ARR AY
LOGIC
ARRAY
R EG I S T E R
REGISTER
ts u
tc o
t cf
t pd
fmax with External Feedback 1/(tsu+tco)
Note: fmax with external feedback is calculated from measured tsu and tco.
fmax with Internal Feedback 1/(tsu+tcf)
CLK
LOGIC
ARRAY
Note: tcf is a calculated value, derived by subtracting tsu from the period of fmax w/internal
feedback (tcf = 1/fmax - tsu). The value of tcf is
used primarily when calculating the delay from
clocking a register to a combinatorial output
(through registered feedback), as shown above.
For example, the timing from clock to a combinatorial output is equal to tcf + tpd.
REGISTER
tsu + th
fmax with No Feedback
Note: fmax with no feedback may be less
than 1/twh + twl. This is to allow for a clock
duty cycle of other than 50%.
Switching Test Conditions
Input Pulse Levels
+5V
GND to 3.0V
Input Rise and Fall Times
3ns 10% – 90%
Input Timing Reference Levels
1.5V
Output Timing Reference Levels
1.5V
Output Load
R1
See Figure
FROM OUTPUT (O/Q)
UNDER TEST
3-state levels are measured 0.5V from steady-state active
level.
Output Load Conditions (see figure)
Test Condition
A
B
C
TEST POINT
R2
R1
R2
CL
300Ω
390Ω
50pF
Active High
∞
390Ω
50pF
Active Low
300Ω
390Ω
50pF
Active High
∞
390Ω
5pF
Active Low
300Ω
390Ω
5pF
C L*
*C L INCLUDES TEST FIXTURE AND PROBE CAPACITANCE
9
Specifications ispGAL22V10
All necessary programming is done via four TTL level logic
interface signals. These four signals are fed into the on-chip
programming circuitry where a state machine controls the programming. The interface signals are Serial Data In (SDI), Serial
Data Out (SDO), Serial Clock (SCLK) and Mode (MODE) control.
For details on the operation of the internal state machine and
programming of ispGAL22V10 devices please refer to the ISP
Architecture and Programming section in this Data Book.
Electronic Signature
An electronic signature (ES) is provided in every ispGAL22V10
device. It contains 64 bits of reprogrammable memory that can
contain user-defined data. Some uses include user ID codes,
revision numbers, or inventory control. The signature data is
always available to the user independent of the state of the
security cell.
Output Register Preload
The electronic signature is an additional feature not present in
other manufacturers' 22V10 devices. To use the extra feature of
the user-programmable electronic signature it is necessary to
choose a Lattice Semiconductor 22V10 device type when compiling a set of logic equations. In addition, many device programmers have two separate selections for the device, typically an
ispGAL22V10 and a ispGAL22V10-UES (UES = User Electronic
Signature) or ispGAL22V10-ES. This allows users to maintain
compatibility with existing 22V10 designs, while still having the
option to use the GAL device's extra feature.
When testing state machine designs, all possible states and state
transitions must be verified in the design, not just those required
in the normal machine operations. This is because certain events
may occur during system operation that throw the logic into an
illegal state (power-up, line voltage glitches, brown-outs, etc.). To
test a design for proper treatment of these conditions, a way must
be provided to break the feedback paths, and force any desired
(i.e., illegal) state into the registers. Then the machine can be
sequenced and the outputs tested for correct next state conditions.
The JEDEC map for the ispGAL22V10 contains the 64 extra fuses
for the electronic signature, for a total of 5892 fuses. However, the
ispGAL22V10 device can still be programmed with a standard
22V10 JEDEC map (5828 fuses) with any qualified device programmer.
The ispGAL22V10 device includes circuitry that allows each
registered output to be synchronously set either high or low. Thus,
any present state condition can be forced for test sequencing. If
necessary, approved GAL programmers capable of executing
test vectors perform output register preload automatically.
Security Cell
Input Buffers
A security cell is provided in every ispGAL22V10 device to
prevent unauthorized copying of the array patterns. Once programmed, this cell prevents further read access to the functional
bits in the device. This cell can only be erased by re-programming
the device, so the original configuration can never be examined
once this cell is programmed. The Electronic Signature is always
available to the user, regardless of the state of this control cell.
ispGAL22V10 devices are designed with TTL level compatible
input buffers. These buffers have a characteristically high impedance, and present a much lighter load to the driving logic than
bipolar TTL devices.
All input and I/O pins (except SDI on the ispGAL22V10C) also
have built-in active pull-ups. As a result, floating inputs will float
to a TTL high (logic 1). The SDI pin on the ispGAL22V10C has a
built-in pull-down to keep the device out of the programming state
if the pin is not actively driven. However, Lattice Semiconductor
recommends that all unused inputs and tri-stated I/O pins be
connected to an adjacent active input, Vcc, or ground. Doing so
will tend to improve noise immunity and reduce Icc for the device.
(See equivalent input and I/O schematics on the following page.)
Latch-Up Protection
ispGAL22V10 devices are designed with an on-board charge
pump to negatively bias the substrate. The negative bias is of
sufficient magnitude to prevent input undershoots from causing
the circuitry to latch. Additionally, outputs are designed with nchannel pullups instead of the traditional p-channel pullups to
eliminate any possibility of SCR induced latching.
Device Programming
Typical Input Current
The ispGAL22V10 device uses a standard 22V10 JEDEC fusemap
file to describe the device programming information. Any third
party logic compiler can produce the JEDEC file for this device.
Input Current (µA)
0
In-System Programmability
The ispGAL22V10 device features In-System Programmable
technology. By integrating all the high voltage programming
circuitry on-chip, programming can be accomplished by simply
shifting data into the device. Once the function is programmed,
the non-volatile E2CMOS cells will not lose the pattern even when
the power is turned off.
-20
-40
-60
0
1.0
2.0
3.0
Input Voltage (Volts)
10
4.0
5.0
Specifications ispGAL22V10
Power-Up Reset
Vcc (min.)
Vcc
t su
t wl
CLK
t pr
INTERNAL REGISTER
Q - OUTPUT
Internal Register
Reset to Logic "0"
ACTIVE LOW
OUTPUT REGISTER
Device Pin
Reset to Logic "1"
ACTIVE HIGH
OUTPUT REGISTER
Device Pin
Reset to Logic "0"
Circuitry within the ispGAL22V10 provides a reset signal to all registers during power-up. All internal registers will have their Q outputs
set low after a specified time (tpr, 1µs MAX). As a result, the state
on the registered output pins (if they are enabled) will be either high
or low on power-up, depending on the programmed polarity of the
output pins. This feature can greatly simplify state machine design
by providing a known state on power-up. The timing diagram for
power-up is shown below. Because of the asynchronous nature of
system power-up, some conditions must be met to provide a valid
power-up reset of the ispGAL22V10. First, the Vcc rise must be
monotonic. Second, the clock input must be at static TTL level as
shown in the diagram during power up. The registers will reset within
a maximum of tpr time. As in normal system operation, avoid clocking the device until all input and feedback path setup times have
been met. The clock must also meet the minimum pulse width
requirements.
Input/Output Equivalent Schematics
PIN
PIN
(Vref Typical = 3.2V)
Feedback
Active Pull-up
Circuit (Except SDI
on ispGAL22V10C)
Vcc
Active Pull-up
Circuit
(Vref Typical = 3.2V)
Vcc
Vref
Vcc
Tri-State
Control
ESD
Protection
Circuit
PIN
Vcc
Vref
Data
Output
PIN
ESD
Protection
Circuit
Pull-down Resistor
(SDI on ispGAL22V10C Only)
Feedback
(To Input Buffer)
Input
Output
11
Specifications ispGAL22V10
ispGAL22V10C: Typical AC and DC Characteristic Diagrams
Normalized Tpd vs Vcc
1.2
1.1
1
0.9
0.8
Normalized Tsu
1.2
Normalized Tco
Normalized Tpd
1.2
1.1
1
0.9
4.75
5.00
5.25
5.50
4.50
4.75
Supply Voltage (V)
Normalized Tpd vs Temp
1.2
1.2
1.1
1
0.9
0.8
0.7
5.00
5.25
-25
0
25
50
75
100
4.50
1
0.9
0.8
-25
0
25
50
1.2
1.1
1
0.9
0.8
75
100
125
-55
-25
0
0
-0.25
-0.5
-0.75
-0.25
-0.5
-0.75
-1
-1
4
5
6
7
8
9
10
1
Number of Outputs Switching
2
3
4
5
6
7
8
9
10
Number of Outputs Switching
Delta Tpd vs Output Loading
Delta Tco vs Output Loading
10
12
8
Delta Tco (ns)
RISE
FALL
6
4
2
10
RISE
8
FALL
6
4
2
0
0
-2
-2
0
50
100
150
200
250
0
300
Output Loading (pF)
50
100
150
200
250
Output Loading (pF)
12
25
50
75
100
Temperature (deg. C)
Delta Tco vs # of Outputs
Switching
Delta Tco (ns)
Delta Tpd (ns)
1.3
0.7
-55
0
3
5.50
1.4
Temperature (deg. C)
2
5.25
Normalized Tsu vs Temp
Delta Tpd vs # of Outputs
Switching
1
5.00
Normalized Tco vs Temp
Temperature (deg. C)
Delta Tpd(ns)
4.75
Supply Voltage (V)
1.1
125
0.9
Supply Voltage (V)
0.7
-55
1
5.50
Normalized Tsu
1.3
Normalized Tco
1.3
1.1
0.8
0.8
4.50
Normalized Tpd
Normalized Tsu vs Vcc
Normalized Tco vs Vcc
300
125
Specifications ispGAL22V10
ispGAL22V10C: Typical AC and DC Characteristic Diagrams
Vol vs Iol
Voh vs Ioh
3
4
1.5
1
4.25
Voh (V)
2
Voh (V)
3
2
0
0
0.00
20.00
40.00
60.00
80.00
100.00
3.5
0.00
10.00 20.00
30.00 40.00
1.00
2.00
3.00
Ioh(mA)
Ioh(mA)
Normalized Icc vs Vcc
Normalized Icc vs Temp
Normalized Icc vs Freq.
Normalized Icc
1.3
1.1
1
0.9
0.8
1.1
1
0.9
0.8
0.7
4.75
5.00
5.25
5.50
-25
0
25
50
75
100
125
Temperature (deg. C)
0
10
20
Iik (mA)
30
3
2
40
50
60
70
1
80
0
90
100
0.00 0.50 1.00 1.50 2.00 2.50 3.00 3.50 4.00
Vin (V)
1.00
0.90
-2.00
-1.50
-1.00
Vik (V)
13
-0.50
0
25
50
75
Frequency (MHz)
Input Clamp (Vik)
Delta Icc vs Vcc
4
1.10
0.80
-55
5
4.00
1.20
1.2
Supply Voltage (V)
Delta Icc (mA)
0.00
50.00 60.00
Iol (mA)
1.2
4.50
4
3.75
1
0.5
Normalized Icc
Vol (V)
4.5
5
2.5
Normalized Icc
Voh vs Ioh
0.00
100
Notes
14