GAL®18V10 Device Datasheet September 2010 All Devices Discontinued! Product Change Notifications (PCNs) have been issued to discontinue all devices in this data sheet. The original datasheet pages have not been modified and do not reflect those changes. Please refer to the table below for reference PCN and current product status. Product Line GAL18V10 Ordering Part Number GAL18V10B-7LJ GAL18V10B-7LP GAL18V10B-10LJ GAL18V10B-10LP GAL18V10B-15LJ GAL18V10B-15LP GAL18V10B-20LJ GAL18V10B-20LP Product Status Reference PCN PCN#06-07 Discontinued PCN#13-10 5555 N.E. Moore Ct. Hillsboro, Oregon 97124-6421 Phone (503) 268-8000 FAX (503) 268-8347 Internet: http://www.latticesemi.com GAL18V10 High Performance E2CMOS PLD Generic Array Logic™ Features Functional Block Diagram • HIGH PERFORMANCE E2CMOS® TECHNOLOGY — 7.5 ns Maximum Propagation Delay — Fmax = 111 MHz — 5.5 ns Maximum from Clock Input to Data Output — TTL Compatible 16 mA Outputs — UltraMOS® Advanced CMOS Technology RESET I/CLK 8 I/O/Q OLMC • LOW POWER CMOS — 75 mA Typical Icc I A D LL IS C DE O N VIC TI N ES U ED 8 • ACTIVE PULL-UPS ON ALL PINS OLMC I/O/Q OLMC I/O/Q OLMC I/O/Q OLMC I/O/Q OLMC I/O/Q OLMC I/O/Q OLMC I/O/Q OLMC I/O/Q OLMC I/O/Q 8 • E2 CELL TECHNOLOGY — Reconfigurable Logic — Reprogrammable Cells — 100% Tested/100% Yields — High Speed Electrical Erasure (<100ms) — 20 Year Data Retention PROGRAMMABLE AND-ARRAY (96X36) I I • TEN OUTPUT LOGIC MACROCELLS — Uses Standard 22V10 Macrocell Architecture — Maximum Flexibility for Complex Logic Designs I • PRELOAD AND POWER-ON RESET OF REGISTERS — 100% Functional Testability • APPLICATIONS INCLUDE: — DMA Control — State Machine Control — High Speed Graphics Processing — Standard Logic Speed Upgrade 8 10 10 8 I 8 8 I • ELECTRONIC SIGNATURE FOR IDENTIFICATION 8 Description I PRESET The GAL18V10, at 7.5 ns maximum propagation delay time, combines a high performance CMOS process with Electrically Erasable (E2) floating gate technology to provide a very flexible 20-pin PLD. CMOS circuitry allows the GAL18V10 to consume much less power when compared to its bipolar counterparts. The E2 technology offers high speed (<100ms) erase times, providing the ability to reprogram or reconfigure the device quickly and efficiently. Pin Configuration DIP PLCC By building on the popular 22V10 architecture, the GAL18V10 eliminates the learning curve usually associated with using a new device architecture. The generic architecture provides maximum design flexibility by allowing the Output Logic Macrocell (OLMC) to be configured by the user. The GAL18V10 OLMC is fully compatible with the OLMC in standard bipolar and CMOS 22V10 devices. I I I/CLK I I/CLK Vcc 2 20 I 18 I/O/Q I I/O/Q I I GAL18V10 6 Top View I Unique test circuitry and reprogrammable cells allow complete AC, DC, and functional testing during manufacture. As a result, Lattice Semiconductor delivers 100% field programmability and functionality of all GAL products. In addition, 100 erase/write cycles and data retention in excess of 20 years are specified. I 16 8 11 I/O/Q I/O/Q 14 9 13 20 I I/O/Q 4 1 I/O/Q I GAL 18V10 5 15 I Vcc I/O/Q I/O/Q I/O/Q I/O/Q I/O/Q I I/O/Q I I/O/Q I/O/Q I/O/Q I/O/Q GND I/O/Q I/O/Q I/O/Q GND 10 11 I/O/Q Copyright © 2003 Lattice Semiconductor Corp. All brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. LATTICE SEMICONDUCTOR CORP., 5555 Northeast Moore Ct., Hillsboro, Oregon 97124, U.S.A. Tel. (503) 268-8000; 1-800-LATTICE; FAX (503) 268-8556; http://www.latticesemi.com 18v10_04 1 November 2003 Specifications GAL18V10 GAL18V10 Ordering Information Commercial Grade Specifications Tpd (ns) Tsu (ns) Tco (ns) Icc (mA) 7.5 6 5.5 Ordering # Package 115 GAL18V10B-7LP 1 20-Pin Plastic DIP 115 1 GAL18V10B-7LJ 20-Lead PLCC GAL18V10B-10LP 20-Pin Plastic DIP 7 7 115 115 GAL18V10B-10LJ 20-Lead PLCC 15 8 10 115 GAL18V10B-15LP 20-Pin Plastic DIP A D LL IS C DE O N VIC TI N ES U ED 10 20 12 12 115 GAL18V10B-15LJ 20-Lead PLCC 115 GAL18V10B-20LP 20-Pin Plastic DIP 115 GAL18V10B-20LJ 20-Lead PLCC 1. Discontinued per PCN #06-07. Contact Rochester Electronics for available inventory. Part Number Description XXXXXXXX _ XX GAL18V10B X X X Device Name Grade Speed (ns) L = Low Power Power Blank = Commercial Package P = Plastic DIP J = PLCC 2 Specifications GAL18V10 Output Logic Macrocell (OLMC) The GAL18V10 has a product term for Asynchronous Reset (AR) and a product term for Synchronous Preset (SP). These two product terms are common to all registered OLMCs. The Asynchronous Reset sets all registered outputs to zero any time this dedicated product term is asserted. The Synchronous Preset sets all registers to a logic one on the rising edge of the next clock pulse after this product term is asserted. The GAL18V10 has a variable number of product terms per OLMC. Of the ten available OLMCs, two OLMCs have access to ten product terms (pins 14 and 15), and the other eight OLMCs have eight product terms each. In addition to the product terms available for logic, each OLMC has an additional product-term dedicated to output enable control. The output polarity of each OLMC can be individually programmed to be true or inverting, in either combinatorial or registered mode. This allows each output to be individually configured as either active high or active low. A D LL IS C DE O N VIC TI N ES U ED NOTE: The AR and SP product terms will force the Q output of the flip-flop into the same state regardless of the polarity of the output. Therefore, a reset operation, which sets the register output to a zero, may result in either a high or low at the output pin, depending on the pin polarity chosen. A R D Q CLK 4 TO 1 MUX Q SP 2 TO 1 MUX GAL18V10 OUTPUT LOGIC MACROCELL (OLMC) Output Logic Macrocell Configurations NOTE: In registered mode, the feedback is from the /Q output of the register, and not from the pin; therefore, a pin defined as registered is an output only, and cannot be used for dynamic I/O, as can the combinatorial pins. Each of the Macrocells of the GAL18V10 has two primary functional modes: registered, and combinatorial I/O. The modes and the output polarity are set by two bits (SO and S1), which are normally controlled by the logic compiler. Each of these two primary modes, and the bit settings required to enable them, are described below and on the the following page. COMBINATORIAL I/O In combinatorial mode the pin associated with an individual OLMC is driven by the output of the sum term gate. Logic polarity of the output signal at the pin may be selected by specifying that the output buffer drive either true (active high) or inverted (active low). Output tri-state control is available as an individual product-term for each output, and may be individually set by the compiler as either “on” (dedicated output), “off” (dedicated input), or “product-term driven” (dynamic I/O). Feedback into the AND array is from the pin side of the output enable buffer. Both polarities (true and inverted) of the pin are fed back into the AND array. REGISTERED In registered mode the output pin associated with an individual OLMC is driven by the Q output of that OLMC’s D-type flip-flop. Logic polarity of the output signal at the pin may be selected by specifying that the output buffer drive either true (active high) or inverted (active low). Output tri-state control is available as an individual product term for each OLMC, and can therefore be defined by a logic equation. The D flip-flop’s /Q output is fed back into the AND array, with both the true and complement of the feedback available as inputs to the AND array. 3 Specifications GAL18V10 Registered Mode AR AR Q D Q A D LL IS C DE O N VIC TI N ES U ED D CLK CLK Q Q SP SP ACTIVE LOW ACTIVE HIGH S0 = 1 S1 = 0 S0 = 0 S1 = 0 Combinatorial Mode ACTIVE LOW ACTIVE HIGH S0 = 0 S1 = 1 S0 = 1 S1 = 1 4 Specifications GAL18V10 GAL18V10 Logic Diagram/JEDEC Fuse Map DIP and PLCC Package Pinouts 1 0 4 8 12 16 20 24 28 32 ASYNCHRONOUS RESET (TO ALL REGISTERS) 0000 0036 . . . 0324 8 OLMC S0 3456 S1 3457 0360 . . . 0648 OLMC A D LL IS C DE O N VIC TI N ES U ED 8 19 S0 3458 S1 3459 2 0684 . . . 0972 8 OLMC SO 3460 S1 3461 3 1008 . . . 1296 8 OLMC S0 3462 S1 3463 4 1332 . . . . 1692 10 OLMC S0 3464 S1 3465 5 1728 . . . . 2088 10 OLMC S0 3466 S1 3467 18 17 16 15 14 6 2124 . . . 2412 8 OLMC S0 3468 S1 3469 13 7 2448 . . . 2736 8 OLMC S0 3470 S1 3471 8 2772 . . . 3060 8 OLMC S0 3472 S1 3473 3096 . . . 3384 8 OLMC S0 3474 S1 3475 SYNCHRONOUS PRESET (TO ALL REGISTERS) 3420 3476, 3477 ... Electronic Signature ... 3538, 3539 Byte 7 Byte 6 Byte 5 Byte 4 Byte 3 Byte 2 Byte 1 Byte 0 M S B L S B 5 12 11 9 Specifications GAL18V10B Absolute Maximum Ratings(1) Recommended Operating Conditions Supply voltage VCC ....................................... -0.5 to +7V Input voltage applied ........................... -2.5 to VCC +1.0V Off-state output voltage applied .......... -2.5 to VCC +1.0V Storage Temperature ................................. -65 to 150°C Ambient Temperature with Power Applied ......................................... -55 to 125°C Commercial Devices: Ambient Temperature (TA) ............................. 0 to +75°C Supply voltage (VCC) with Respect to Ground ..................... +4.75 to +5.25V A D LL IS C DE O N VIC TI N ES U ED 1. Stresses above those listed under the “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress only ratings and functional operation of the device at these or at any other conditions above those indicated in the operational sections of this specification is not implied (while programming, follow the programming specifications). DC Electrical Characteristics Over Recommended Operating Conditions (Unless Otherwise Specified) SYMBOL VIL VIH IIL1 IIH VOL VOH IOL IOH IOS2 MIN. TYP.3 MAX. UNITS Input Low Voltage Vss – 0.5 — 0.8 V Input High Voltage 2.0 — Vcc+1 V PARAMETER CONDITION Input or I/O Low Leakage Current 0V ≤ VIN ≤ VIL (MAX.) — — –100 μA Input or I/O High Leakage Current 3.5V ≤ VIN ≤ VCC — — 10 μA Output Low Voltage IOL = MAX. Vin = VIL or VIH — — 0.5 V Output High Voltage IOH = MAX. Vin = VIL or VIH 2.4 — — V Low Level Output Current — — 16 mA High Level Output Current — — –3.2 mA –30 — –130 mA — 75 115 mA Output Short Circuit Current COMMERCIAL ICC Operating Power Supply Current VCC = 5V VOUT = 0.5V TA = 25°C VIL = 0.5V VIH = 3.0V L -7/-10/-15/-20 ftoggle = 15MHz Outputs Open 1) The leakage current is due to the internal pull-up on all pins. See Input Buffer section for more information. 2) One output at a time for a maximum duration of one second. Vout = 0.5V was selected to avoid test problems caused by tester ground degradation. Characterized but not 100% tested. 3) Typical values are at Vcc = 5V and TA = 25 °C 6 Specifications GAL18V10B AC Switching Characteristics Over Recommended Operating Conditions PARAM. TEST COND.1 COM COM COM -7 -10 -15 -20 MIN. MAX. MIN. MAX. MIN. MAX. MIN. MAX. UNITS A Input or I/O to Comb. Output — 7.5 — 10 — 15 — 20 ns A Clock to Output Delay — 5.5 — 7 — 10 — 12 ns A D LL IS C DE O N VIC TI N ES U ED tpd tco tcf2 tsu th DESCRIPTION COM fmax3 twh twl ten tdis tar tarw tarr tspr — Clock to Feedback Delay — 3.5 — 3.5 — 7 — 10 ns — Setup Time, Input or Fdbk before Clk↑ 5.5 — 6 — 8 — 12 — ns — Hold Time, Input or Fdbk after Clk↑ 0 — 0 — 0 — 0 — ns A Maximum Clock Frequency with External Feedback, 1/(tsu + tco) 90.9 — 76.9 — 55.5 — 41.6 — MHz A Maximum Clock Frequency with Internal Feedback, 1/(tsu + tcf) 111 — 105 — 66.7 — 45.4 — MHz A Maximum Clock Frequency with No Feedback 111 — 105 — 66.7 — 62.5 — MHz — Clock Pulse Duration, High 4 — 4 — 6 — 8 — ns — Clock Pulse Duration, Low 4 — 4 — 6 — 8 — ns B Input or I/O to Output Enabled — 8 — 10 — 15 — 20 ns C Input or I/O to Output Disabled — 8 — 9 — 15 — 20 ns A Input or I/O to Asynch. Reset of Reg. — 13 — 13 — 20 — 20 ns — Asynch. Reset Pulse Duration 8 — 8 — 10 — 15 — ns — Asynch. Reset to Clk↑ Recovery Time 8 — 8 — 10 — 15 — ns — Synch. Preset to Clk↑ Recovery Time 10 — 10 — 10 — 12 — ns 1) Refer to Switching Test Conditions section. 2) Calculated from fmax with internal feedback. Refer to fmax Description section. 3) Refer to fmax Description section. Capacitance (TA = 25°C, f = 1.0 MHz) SYMBOL PARAMETER MAXIMUM* UNITS TEST CONDITIONS CI Input Capacitance 8 pF VCC = 5.0V, VI = 2.0V CI/O I/O Capacitance 8 pF VCC = 5.0V, VI/O = 2.0V *Characterized but not 100% tested. 7 Specifications GAL18V10 Switching Waveforms INPUT or I/O FEEDB ACK INPUT or I/O FEEDB ACK VALID INPUT VALID INPUT tsu th tp d CLK CO MB INA TO RI AL OUTPUT tco R EG I ST E RE D OUTPUT Combinatorial Output A D LL IS C DE O N VIC TI N ES U ED 1/ fma x (external fdbk) Registered Output INPUT or I/O FEEDB ACK t dis t en OUTPUT CLK 1/ fmax (internal fdbk) Input or I/O to Output Enable/Disable t cf ts u R EG I ST E RE D FEED BACK fmax with Feedback t wh t wl CLK 1/ fma x (w/o fdbk) Clock Width INPUT or I/O FEEDB ACK DRIVI NG SP INPUT or I/O FEEDB ACK DRIVI NG AR tsu th tspr tarw CLK CLK tarr tco R EG I ST E RE D OUT PUT R EG I ST E RE D OUT PUT tar Synchronous Preset Asynchronous Reset 8 Specifications GAL18V10 fmax Descriptions CLK CLK LOGIC ARRAY LOGIC ARRAY REGISTER A D LL IS C DE O N VIC TI N ES U ED REGISTER tsu tco fmax with External Feedback 1/(tsu+tco) t cf t pd Note: fmax with external feedback is calculated from measured tsu and tco. fmax with Internal Feedback 1/(tsu+tcf) CLK LOGIC ARRAY Note: tcf is a calculated value, derived by subtracting tsu from the period of fmax w/internal feedback (tcf = 1/fmax - tsu). The value of tcf is used primarily when calculating the delay from clocking a register to a combinatorial output (through registered feedback), as shown above. For example, the timing from clock to a combinatorial output is equal to tcf + tpd. REGISTER tsu + th fmax with No Feedback Note: fmax with no feedback may be less than 1/(twh + twl). This is to allow for a clock duty cycle of other than 50%. Switching Test Conditions Input Pulse Levels Input Rise and Fall Times GND to 3.0V -7/-10 2ns 10% – 90% -15/-20 3ns 10% – 90% Input Timing Reference Levels 1.5V Output Timing Reference Levels 1.5V Output Load +5V R1 See Figure FROM OUTPUT (O/Q) UNDER TEST 3-state levels are measured 0.5V from steady-state active level. Output Load Conditions (see figure) Test Condition B C R2 R1 R2 CL 300Ω 390Ω 50pF Active High ∞ 390Ω 50pF Active Low 300Ω 390Ω 50pF Active High ∞ 390Ω 5pF Active Low 300Ω 390Ω 5pF A TEST POINT C L* *C L INCLUDES TEST FIXTURE AND PROBE CAPACITANCE 9 Specifications GAL18V10 Electronic Signature Output Register Preload An electronic signature is provided in every GAL18V10 device. It contains 64 bits of reprogrammable memory that can contain userdefined data. Some uses include user ID codes, revision numbers, or inventory control. The signature data is always available to the user independent of the state of the security cell. When testing state machine designs, all possible states and state transitions must be verified in the design, not just those required in the normal machine operations. This is because certain events may occur during system operation that throw the logic into an illegal state (power-up, line voltage glitches, brown-outs, etc.). To test a design for proper treatment of these conditions, a way must be provided to break the feedback paths, and force any desired (i.e., illegal) state into the registers. Then the machine can be sequenced and the outputs tested for correct next state conditions. Security Cell A D LL IS C DE O N VIC TI N ES U ED A security cell is provided in every GAL18V10 device to prevent unauthorized copying of the array patterns. Once programmed, this cell prevents further read access to the functional bits in the device. This cell can only be erased by re-programming the device, so the original configuration can never be examined once this cell is programmed. The Electronic Signature is always available to the user, regardless of the state of this control cell. The GAL18V10 device includes circuitry that allows each registered output to be synchronously set either high or low. Thus, any present state condition can be forced for test sequencing. If necessary, approved GAL programmers capable of executing test vectors perform output register preload automatically. Input Buffers Latch-Up Protection GAL18V10 devices are designed with TTL level compatible input buffers. These buffers have a characteristically high impedance, and present a much lighter load to the driving logic than bipolar TTL devices. GAL18V10 devices are designed with an on-board charge pump to negatively bias the substrate. The negative bias is of sufficient magnitude to prevent input undershoots from causing the circuitry to latch. Additionally, outputs are designed with n-channel pullups instead of the traditional p-channel pullups to eliminate any possibility of SCR induced latching. The input and I/O pins also have built-in active pull-ups. As a result, floating inputs will float to a TTL high (logic 1). However, Lattice Semiconductor recommends that all unused inputs and tri-stated I/O pins be connected to an adjacent active input, Vcc, or ground. Doing so will tend to improve noise immunity and reduce Icc for the device. Device Programming GAL devices are programmed using a Lattice Semiconductorapproved Logic Programmer, available from a number of manufacturers (see the the GAL Development Tools section). Complete programming of the device takes only a few seconds. Erasing of the device is transparent to the user, and is done automatically as part of the programming cycle. I n p u t C u r r e n t (u A ) Typical Input Current 0 -20 -40 -60 0 1.0 2.0 3.0 In p u t V o lt ag e ( V o lt s) 10 4.0 5.0 Specifications GAL18V10 Power-Up Reset Vcc Vcc (min.) t su t wl CLK t pr Internal Register Reset to Logic "0" ACTIVE LOW OUTPUT REGISTER Device Pin Reset to Logic "1" ACTIVE HIGH OUTPUT REGISTER Device Pin Reset to Logic "0" A D LL IS C DE O N VIC TI N ES U ED INTERNAL REGISTER Q - OUTPUT conditions must be met to provide a valid power-up reset of the device. First, the VCC rise must be monotonic. Second, the clock input must be at static TTL level as shown in the diagram during power up. The registers will reset within a maximum of tpr time. As in normal system operation, avoid clocking the device until all input and feedback path setup times have been met. The clock must also meet the minimum pulse width requirements. Circuitry within the GAL18V10 provides a reset signal to all registers during power-up. All internal registers will have their Q outputs set low after a specified time (tpr, 1μs MAX). As a result, the state on the registered output pins (if they are enabled) will be either high or low on power-up, depending on the programmed polarity of the output pins. This feature can greatly simplify state machine design by providing a known state on power-up. Because of the asynchronous nature of system power-up, some Input/Output Equivalent Schematics PIN PIN Feedback Vcc (Vref Typical = 3.2V) Active Pull-up Circuit Active Pull-up Circuit Vcc ESD Protection Circuit Vref Tri-State Control Vcc Vcc (Vref Typical = 3.2V) Vref Data Output PIN ESD Protection Circuit PIN Feedback (To Input Buffer) Typical Input Typical Output 11 Specifications GAL18V10 GAL18V10B: Typical AC and DC Characteristic Diagrams Normalized Tpd vs Vcc 1.2 1.2 Normalized Tco PT L->H 1 0.9 1.1 Normalized Tsu RISE PT H->L 1.1 FALL 1 0.9 PT H->L 1.1 PT L->H 1 0.9 A D LL IS C DE O N VIC TI N ES U ED Normalized Tpd Normalized Tsu vs Vcc Normalized Tco vs Vcc 1.2 0.8 0.8 4.50 4.75 5.00 5.25 5.50 0.8 4.50 4.75 Supply Voltage (V) Normalized Tpd vs Temp 5.50 4.50 PT H->L Normalized Tco 1 0.9 Normalized Tsu vs Temp 0.9 0.7 0.7 0 25 50 75 100 125 1.3 PT H->L 1.2 PT L->H 1.1 1 0.9 0.8 0.7 -55 -25 Temperature (deg. C) 0 25 50 75 100 -55 125 -25 Delta Tco vs # of Outputs Switching 0 0 -0.5 -0.5 -1 RISE -1.5 0 -1 RISE -1.5 FALL FALL -2 -2 1 2 3 4 5 6 7 8 9 1 10 2 3 4 5 6 7 8 9 Number of Outputs Switching Number of Outputs Switching Delta Tpd vs Output Loading Delta Tco vs Output Loading 10 10 8 RISE 6 FALL Delta Tco (ns) 10 4 2 0 -2 8 RISE 6 FALL 4 2 0 -2 -4 -4 0 50 100 150 200 250 300 0 Output Loading (pF) 50 100 150 200 Output Loading (pF) 12 25 50 75 Temperature (deg. C) Temperature (deg. C) Delta Tpd vs # of Outputs Switching Delta Tpd (ns) -25 Delta Tpd (ns) -55 FALL 1 0.8 5.50 1.4 RISE 1.1 0.8 5.25 Normalized Tco vs Temp Delta Tco (ns) 1.1 5.00 Supply Voltage (V) 1.2 PT L->H 4.75 Supply Voltage (V) 1.3 1.2 Normalized Tpd 5.25 Normalized Tsu 1.3 5.00 250 300 100 125 Specifications GAL18V10 GAL18V10B: Typical AC and DC Characteristic Diagrams Vol vs Iol Voh vs Ioh 1 Voh vs Ioh 5 5.25 4 4.75 5 0.5 0.25 4.5 Voh (V) Voh (V) Vol (V) 0.75 3 2 4.25 4 3.75 3.5 A D LL IS C DE O N VIC TI N ES U ED 1 3.25 0 0 0 10 20 30 3 0 40 10 20 30 40 50 60 0 1 Normalized Icc vs Vcc Normalized Icc vs Temp 1.2 1.2 1.1 1.1 2 3 4 Ioh(mA) Ioh(mA) Iol (mA) Normalized Icc vs Freq. 1.4 1 0.9 Normalized Icc Normalized Icc Normalized Icc 1.3 1 0.9 1.2 1.1 1 0.9 0.8 0.8 0.8 4.50 4.75 5.00 5.25 5.50 -55 Supply Voltage (V) -25 0 25 50 75 100 125 Delta Icc vs Vin (1 input) Input Clamp (Vik) 8 0 7 -40 Iik (mA) Delta Icc (mA) -20 6 5 4 3 -60 -80 2 -100 1 0 0.00 -120 0.50 1.00 1.50 2.00 2.50 Vin (V) 3.00 3.50 4.00 -2.00 -1.50 -1.00 Vik (V) 13 -0.50 0 25 50 75 Frequency (MHz) Temperature (deg. C) 0.00 100 Specifications GAL18V10 GAL18V10B: Typical AC and DC Characteristic Diagrams Normalized Tpd vs. Vcc Normalized Tsu vs. Vcc 1.3 1.1 1.1 1 0.9 1.2 Normalized Tco 1.2 Normalized Tsu 1.2 Normalized Tco vs. Vcc 1.3 1 0.9 1.1 1 0.9 0.8 A D LL IS C DE O N VIC TI N ES U ED Normalized Tpd 1.3 0.8 PT H -> L 0.8 PT L -> H PT L -> H PT H -> L 0.7 4.5 4.75 5 5.25 5.5 4.5 4.5 4.75 Supply Voltage (V) 5.25 Normalized Tsu vs. Temperature 1.2 1.2 1.2 1.1 1.1 1.1 0.9 1 0.9 0.8 0.8 25 50 75 100 125 1 0.9 -25 0 25 50 75 100 0.7 -55 125 Delta Tpd vs. # of Outputs Switching 0 -2 8 1.2 6 1.1 4 2 0 -3 75 100 125 1 0.9 0.7 0 100 # of Outputs 200 300 400 4.5 4.75 IOL vs. VOL IOH vs. VOH -150 5 5.25 5.5 Supply Voltage (V) Output Loading Capacitance (pf) 250 50 0.8 -2 Max. Max. - 4 25 Normalized Icc vs. Vcc 1.3 Normalized Icc Delta Tpd (ns) -1 0 Ambient Temperature (°C) Delta Tpd vs. Output Loading 10 Max. - 8 -25 Ambient Temperature (°C) Ambient Temperature (°C) 0 5.5 0.8 0.7 -55 0.7 0 5.25 Normalized Tco vs. Temperature 1.3 Normalized Tco 1 -25 5 Supply Voltage (V) 1.3 -50 4.75 5.5 1.3 Normalized Tsu Normalized Tpd 5 Supply Voltage (V) Normalized Tpd vs. Temperature Delta Tpd (ns) 0.7 0.7 Normalized Icc vs. Temperature 1.3 Icc vs. Temperature 1.2 200 Normalized Icc IOH (mA) IOL (mA) -100 150 100 -50 Isb vs. Temperature 1.1 1 0.9 50 0.8 0 0 0 1 2 VOL (V) 3 4 0.7 0 1 2 VOH (V) 14 3 4 -55 -25 0 25 50 75 Ambient Temperature (°C) 100 125