CYPRESS CY28352OCT

CY28352
Differential Clock Buffer/Driver DDR400and DDR333-Compliant
Features
Description
• Supports 333-MHz and 400-MHz DDR SDRAM
• 60- – 200-MHz operating frequency
This PLL clock buffer is designed for 2.5-VDD and 2.5-AVDD
operation and differential output levels.
• Phase-locked loop (PLL) clock distribution for double
data rate synchronous DRAM applications
This device is a zero delay buffer that distributes a clock input
CLKIN to six differential pairs of clock outputs (CLKT[0:5],
CLKC[0:5]) and one feedback clock output FBOUT. The clock
outputs are controlled by the input clock CLKIN and the
feedback clock FBIN.
• Distributes one clock input to six differential outputs
• External feedback pin FBIN is used to synchronize
output to clock input
• Conforms to DDRI specification
• Spread Aware™ for electromagnetic interference (EMI)
reduction
The PLL in this device uses the input clock CLKIN and the
feedback clock FBIN to provide high-performance, low-skew,
low–jitter output differential clocks.
• 28-pin SSOP package
Block Diagram
CLKT0
CLKC0
CLKT1
CLKC1
SDATA
Serial
Interface
Logic
CLKIN
PLL
CLKT2
CLKC2
CLKC1
GND
SCLK
CLKT3
CLKC3
CLKIN
NC
CLKT4
CLKC4
AVDD
CLKT5
CLKC5
FBIN
CLKC0
CLKT0
VDD
CLKT1
AGND
VDD
CLKT2
CLKC2
1
2
3
4
5
6
7
8
9
10
11
12
13
14
CY28352
Pin Configuration
10
SCLK
The two-line serial bus can set each output clock pair
(CLKT[0:5], CLKC[0:5]) to the Hi-Z state. When AVDD is
grounded, the PLL is turned off and bypassed for test
purposes.
28
27
26
25
24
23
22
21
20
19
18
17
16
15
GND
CLKC5
CLKT5
CLKC4
CLKT4
VDD
SDATA
NC
FBIN
FBOUT
NC
CLKT3
CLKC3
GND
FBOUT
AVDD
28 pin SSOP
Cypress Semiconductor Corporation
Document #: 38-07371 Rev. *C
•
3901 North First Street
•
San Jose, CA 95134
•
408-943-2600
Revised Sept. 02, 2004
CY28352
Pin Description[1]
Pin Number Pin Name
8
CLKIN
20
I/O
I
FBIN
I
2,4,13,17,24,
CLKT(0:5)
26
O
1,5,14,16,25,
CLKC(0:5)
27
O
19
FBOUT
O
7
SCLK
I
22
SDATA
I/O
3,12,23
10
6,15,28
11
9, 18, 21
VDD
AVDD
GND
AGND
NC
Pin Description
Complementary Clock Input.
Feedback Clock Input. Connect to FBOUT for accessing the
PLL.
Clock Outputs
Electrical
Characteristics
Input
Input
Differential Outputs
Clock Outputs
Feedback Clock Output. Connect to FBIN for normal operation.
A bypass delay capacitor at this output will control Input
Reference/Output Clocks phase relationships.
Serial Clock Input. Clocks data at SDATA into the internal
register.
Serial Data Input. Input data is clocked to the internal register to
enable/disable individual outputs. This provides flexibility in
power management.
2.5V Power Supply for Logic
2.5V Power Supply for PLL
Ground
Analog Ground for PLL
Not Connected
Output
Data Input for the two line
serial bus
Data Input and Output for
the two line serial bus
2.5V Nominal
2.5V Nominal
Zero Delay Buffer
Power Management
When used as a zero delay buffer the CY28352 will likely be
in a nested clock tree application. For these applications the
CY28352 offers a clock input as a PLL reference. The
CY28352 can then lock onto the reference and translate with
near zero delay to low-skew outputs. For normal operation, the
external feedback input, FBIN, is connected to the feedback
output, FBOUT. By connecting the feedback output to the
feedback input the propagation delay through the device is
eliminated. The PLL works to align the output edge with the
input reference edge thus producing a near zero delay. The
reference frequency affects the static phase offset of the PLL
and thus the relative delay between the inputs and outputs.
The individual output enable/disable control of the CY28352
allows the user to implement unique power management
schemes into the design. Outputs are three-stated when
disabled through the two-line interface as individual bits are
set low in Byte0 and Byte1 registers. The feedback output
FBOUT cannot be disabled via two line serial bus. The
enabling and disabling of individual outputs is done in such a
manner as to eliminate the possibility of partial “runt” clocks.
When VDDA is strapped LOW, the PLL is turned off and
bypassed for test purposes.
Function Table
Inputs
VDDA
Outputs
CLKIN
CLKT(0:5)[2]
CLKC(0:5)[2]
PLL
FBOUT
GND
L
L
H
L
BYPASSED/OFF
GND
H
H
L
H
BYPASSED/OFF
2.5V
L
L
H
L
On
2.5V
H
H
L
H
On
2.5V
<20 MHz
Hi-Z
Hi-Z
Hi-Z
Off
Notes:
1. A bypass capacitor (0.1µF) should be placed as close as possible to each positive power pin (< 0.2”). If these bypass capacitors are not close to the pins, their
high-frequency filtering characteristic will be cancelled by the lead inductance of the traces.
2. Each output pair can be three-stated via the two-line serial interface.
Document #: 38-07371 Rev. *C
Page 2 of 8
CY28352
Serial Control Registers
Following the acknowledge of the Address Byte, two additional
bytes must be sent:
• Command Code byte
• Byte Count byte.
Byte0: Output Register1 (1 = Enable, 0 = Disable)
Bit
@Pup
Pin#
Description
7
1
2, 1
CLKT0, CLKC0
6
1
4, 5
CLKT1, CLKC1
5
1
–
Reserved
4
1
–
Reserved
3
1
13, 14
CLKT2, CLKC2
2
1
26, 27
CLKT5, CLKC5
1
1
–
0
1
24, 25
Reserved
CLKT4, CLKC4
Byte1: Output Register 2 (1 = Enable, 0 = Disable)
Bit
@Pup
Pin#
7
1
–
Description
6
1
17, 16
5
0
–
Reserved
4
0
–
Reserved
3
0
–
Reserved
2
0
–
Reserved
1
0
–
Reserved
0
0
–
Reserved
Reserved
CLKT3, CLKC3
Byte2: Test Register 3
Bit
@Pup
Pin#
7
1
–
0 = PLL leakage test, 1 = disable test
6
1
–
Reserved
5
0
–
Reserved
4
0
–
Reserved
3
0
–
Reserved
2
0
–
Reserved
1
0
–
Reserved
0
0
–
Reserved
Document #: 38-07371 Rev. *C
Description
Page 3 of 8
CY28352
Maximum Ratings[3]
Storage Temperature: ................................ –65°C to + 150°C
This device contains circuitry to protect the inputs against
damage due to high static voltages or electric field; however,
precautions should be taken to avoid application of any
voltage higher than the maximum rated voltages to this circuit.
For proper operation, VIN and VOUT should be constrained to
the range:
Operating Temperature: .................................... 0°C to +70°C
VSS < (VIN or VOUT) < VDD.
Maximum Power Supply: ................................................3.5V
Unused inputs must always be tied to an appropriate logic
voltage level (either VSS or VDD).
Input Voltage Relative to VSS:.............................. VSS – 0.3V
Input Voltage Relative to VDDQ or AVDD:............ VDD + 0.3V
DC Parameters VDDA = VDDQ = 2.5V ± 5%, TA = 0°C to +70°C[4]
Parameter
VIL
VIH
VIL
VIH
IIN
Description
Input Low Voltage
Input High Voltage
Input Voltage Low
Input Voltage High
Input Current
Condition
SDATA, SCLK
SDATA, SCLK
CLKIN, FBIN
CLKIN, FBIN
VIN = 0V or VIN = VDDQ, CLKIN,
FBIN
VDDQ = 2.375V, VOUT = 1.2V
VDDQ = 2.375V, VOUT = 1V
VDDQ = 2.375V, IOL = 12 mA
VDDQ = 2.375V, IOH = –12 mA
IOL
IOH
VOL
VOH
VOUT
VOC
IOZ
Output Low Current
Output High Current
Output Low Voltage
Output High Voltage
Output Voltage Swing[5]
Output Crossing Voltage[6]
High-Impedance Output
VO = GND or VO = VDDQ
Current
IDDQ
Dynamic Supply Current[7]
IDSTAT
IDD
Static Supply Current
PLL Supply Current
Cin
Input Pin Capacitance
tpZL, tpZH
tpLZ, tpHZ
tCCJ
tjit(h-per)
Max.
1.0
Unit
V
V
V
V
µA
0.4
2.1
–10
26
–18
10
35
–32
VDDQ/2
VDDQ – 0.4
(VDDQ/2) + 0.2
10
mA
mA
V
V
V
V
µA
235
300
mA
1
mA
9
4
12
6
mA
pF
0.6
1.7
1.1
(VDDQ/2) – 0.2
–10
VDDA only
Description
Operating Clock Frequency
Input Clock Duty Cycle
Maximum PLL lock Time
Output Clocks Slew Rate
Output Enable Time[10]
(all outputs)
Output Disable Time[10]
(all outputs)
Cycle-to-Cycle Jitter[12]
Half-period jitter[12]
Typ.
2.2
All VDDQ and VDDI,
FO = 170 MHz
AC Parameters VDD = VDDQ = 2.5V ± 5%, TA = 0°C to +70°C
Parameter
fCLK
tDC
tlock
Tr / Tf
Min.
[7, 9]
Condition
20% to 80% of VOD
f > 66 MHz
f > 66 MHz
Min.
60
40
Typ.
1
–100
–100
Max.
200
60
100
2.5
Unit
MHz
%
µs
V/ns
3
ns
3
ns
100
100
ps
ps
Notes:
3. Multiple Supplies: The voltage on any input or I/O pin cannot exceed the power pin during power-up. Power supply sequencing is NOT required.
4. Unused inputs must be held HIGH or LOW to prevent them from floating.
5. For load conditions, see Figure 7.
6. The value of VOC is expected to be |VTR + VCP|/2. In case of each clock directly terminated by a 120Ω resistor. See Figure 7.
7. All outputs switching loaded with 16 pF in 60Ω environment. SeeFigure 7.
8. Parameters are guaranteed by design and characterization. Not 100% tested in production.
9. PLL is capable of meeting the specified parameters while supporting SSC synthesizers with modulation frequency between 30 kHz and 33.3 kHz, with a down
spread of –0.5%.
10. Refers to transition of non-inverting output.
11. All differential input and output terminals are terminated with 120Ω/16 pF as shown in Figure 7.
12. Period Jitter and Half-Period Jitter specifications are separate, and must be met independently of each other.
Document #: 38-07371 Rev. *C
Page 4 of 8
CY28352
AC Parameters VDD = VDDQ = 2.5V ± 5%, TA = 0°C to +70°C (continued)[7, 9]
Parameter
tPLH
tPHL
tSKEW
tPHASE
tPHASEJ
Description
LOW-to-HIGH Propagation Delay,
CLKIN to CLKT[0:5]
Condition
HIGH-to-LOW Propagation Delay,
CLKIN to CLKT[0:5]
Any Output to Any Output Skew[11]
Phase Error[11]
Phase Error Jitter
Min.
Typ.
Max.
Unit
1.5
3.5
6
ns
1.5
3.5
6
ns
100
150
50
ps
ps
ps
–150
–50
f > 66 MHz
Parameter Measurement Information
CLKIN
1.25V
1.25V
FBIN
1.25V
1.25V
t(∅)n+1
t(∅)n
t(∅)n =
Σ n1=N
t(∅)n
(N is large number of samples)
Figure 1. Static Phase Offset
CLKIN
1.25V
1.25V
FBIN
td(∅)
t(∅)
td(∅)
td(∅)
t(∅ )
td(∅)
Figure 2. Dynamic Phase Offset
CLKT[0:5], FBOUT
CLKC[0:5]
CLKT[0:5], FBOUT
CLKC[0:5]
tsk(o)
Figure 3. Output Skew
Document #: 38-07371 Rev. *C
Page 5 of 8
CY28352
CLKT[0:5], FBOUT
CLKC[0:5]
t c(n)
CLKT[0:5], FBOUT
CLKC[0:5]
1
f(o)
t jit(hper) = t c(n) - 1
fo
Figure 4. Period Jitter
CLKT[0:5], FBO UT
CLKC[0:5]
t (hper_N+1)
t (hper_n)
1
f(o)
t jit(hper) = t hper(n) - 1
2x fo
Figure 5. Half-period Jitter
C L K T[0:5], F B O U T
C L K C [0:5]
t c (n )
t c(n)
t jit(cc) = t c(n ) -t c (n + 1)
Figure 6. Cycle-to-Cycle Jitter
T PCB
M easurem ent Point
C LKT
16 pF
C LKIN
110 Ω
50 Ω
C LKC
T PCB
M easurem ent Point
16 pF
FBIN
50 Ω
FBO U T
Figure 7. Differential Signal Using Direct Termination Resistor
Ordering Information
Part Number
Package Type
Product Flow
CY28352OC
28-pin SSOP
Commercial, 0° to 70°C
CY28352OCT
28-pin SSOP–Tape and Reel
Commercial, 0° to 70°C
CY28352OXC
28-pin SSOP
Commercial, 0° to 70°C
CY28352OXCT
28-pin SSOP–Tape and Reel
Commercial, 0° to 70°C
Lead-free
Document #: 38-07371 Rev. *C
Page 6 of 8
CY28352
Package Drawing and Dimensions
28-lead (5.3 mm) Shrunk Small Outline Package O28
51-85079-*C
Spread Aware is a trademark of Cypress Semiconductor Corporation. All product and company names mentioned in this
document are the trademarks of their respective holders.
Document #: 38-07371 Rev. *C
Page 7 of 8
© Cypress Semiconductor Corporation, 2004. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be
used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its
products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
CY28352
Document History Page
Document Title: CY28352 Differential Clock Buffer/Driver DDR400- and DDR333-Compliant,
Document Number: 38-07371
REV.
ECN No.
Issue Date
Orig. of
Change
Description of Change
**
112787
05/08/02
DMG
*A
122911
12/27/02
RBI
Add power-up requirements to maximum ratings information
*B
127012
05/28/03
RGL
Change the maximum operating clock frequency from 170 MHz to 200 MHz
Added DDR400- and DDR333-Compliant in the title.
See ECN
RGL
Added Lead-Free devices
*C
Document #: 38-07371 Rev. *C
New data sheet
Page 8 of 8