SM6451BV Audio Variable Volume IC NIPPON PRECISION CIRCUITS INC. OVERVIEW The SM6451BV is a 3-wire serial-controlled electronic variable volume IC for audio applications. It provides electronic volume control for a stereo system (left and right channels), and independent channel attenuation and muting, with greatly enhanced digital zip noise suppression. The chip address function allows up to four SM6451BV devices to be connected and individually controlled over the 3-wire control interface from a single CPU. It is available in 16-pin VSOP packages. FEATURES ■ ■ ■ ■ ■ ■ ■ Stereo inputs and outputs Attenuation function • 2-channel independent control • 1.0 dB/step over 80 steps • 0 to −80 dB range Mute function 3-wire serial data control (MDT, MCK, MLEN) Chip addressing (up to 4 devices can be connected in parallel) Low noise • 0.003 % THD + noise • 12 µVrms residual noise 2.5 to 3.6 V single power supply Silicon-gate CMOS process (Top View) RSTN 1 16 MDT ADRS1 MCK ADRS2 MLEN 6451BV ■ PINOUT DVDD LOUT LIN DVSS ROUT RIN AVDD VRL AVSS 8 9 VRR APPLICATIONS ■ PACKAGE DIMENSIONS Audio equipment (Unit: mm) P ackag e SM6451BV 16-pin V S O P + 0.1 0.05 0.15 - 0.275TYP 5.1 0.2 0 10 0.65 0.10 + 0.10 0.22 - 0.05 0.12 M 0.10 0.05 1.15 0.1 D e vice 16 pin VSOP 4.4 0.2 6.4 0.2 ORDERING INFORMATION 0.5 0.2 NIPPON PRECISION CIRCUITS—1 SM6451BV BLOCK DIAGRAM DVDD DVSS Attenuation Control LIN LOUT 1/2VDD Reference Voltage Circuits ADRS1 ADRS2 VRL Attenuation Decoder Chip Address Decoder Interface Control MLEN MCK MDT RSTN VRR 1/2VDD Attenuation Control RIN AVDD ROUT AVSS PIN DESCRIPTION 1. Number Name I/O 1 A/D1 1 RSTN Ip D System reset input (LOW -level reset) 2 ADRS1 Ip D Chip address set 1 3 ADRS2 Ip D Chip address set 2 4 DV D D – D Digital supply 5 LOUT O A Left-channel audio output 6 LIN I A Left-channel audio input 7 AV D D – A Analog supply 8 VRL O A Left-channel reference voltage (0.5V D D ). Connect a 10 µF capacitor between VRL and AV S S . 9 VRR O A Right-channel reference voltage (0.5V D D ). Connect a 10 µF capacitor between VRR and AV S S . 10 AV S S – A Analog ground 11 RIN I A Right-channel audio input 12 ROUT O A Right-channel audio output 13 DV S S – D Digital ground 14 MLEN Ip D Microcontroller latch enable input 15 MCK Ip D Microcontroller clock input 16 MDT Ip D Microcontroller data input Description Ip = input pin with pull-up, A = analog, D= digital NIPPON PRECISION CIRCUITS—2 SM6451BV SPECIFICATIONS Absolute Maximum Ratings DVSS = AVSS = 0 V, DVDD = AVDD = VDD P arameter Symbol Rating Unit Supply voltage VDD −0.3 to 7.0 V Input voltage V IN V S S − 0.3 to V D D + 0.3 V Pow er dissipation PD 150 mW Storage temperature T stg −55 to 125 °C Soldering temperature T sld 255 °C Soldering time tsld 10 s Symbol Rating Unit VDD 2.5 to 3.6 V Supply voltage deviation DV D D − AV D D , DV S S − AV S S ±0.1 V Operating temperature T opr −40 to 85 °C Recommended Operating Conditions DVSS = AVSS = 0 V, DVDD = AVDD = VDD P arameter Supply voltage DC Characteristics DVDD = AVDD = VDD = 2.5 to 3.6 V, VSS = 0 V, Ta = −40 to 85 °C Rating P arameter DVDD Current consumption Symbol ID D D 1 ID D D 2 Condition Data transfer stopped, MDT, MCK, MLEN, RSTN, ADRS1, ADRS2 = V D D A D R S 1 = A D R S 2 = 0 V, 0.8 Vr ms analog input, ATT = 0 d B , data transfer active Unit min typ max – 0.2 1.0 µA – 0.4 1.0 mA – 1.9 5.5 mA AVDD Current consumption ID D A HIGH-level input voltage 1 V IH 0.7V D D – – V voltage 1 V IL – – 0.3V D D V L O W -level input Input current 1 Input leakage 1. current 1 IIL V IN = 0 V – 70 150 µA IIH V IN = V D D – – 1.0 µA M D T, MCK, MLEN, RSTN, ADRS1, ADRS2 NIPPON PRECISION CIRCUITS—3 SM6451BV AC Digital Characteristics DVDD = AVDD = VDD = 2.5 to 3.6 V, VSS = 0 V, Ta = −40 to 85 °C Serial inputs (MDT, MCK, MLEN) Rating P arameter Symbol Unit min typ max M C K , M L E N r ise time tr – – 100 ns MCK, MLEN fall time tf – – 100 ns MDT setup time tM D S 50 – – ns MDT hold time tM D H 50 – – ns MLEN setup time tM C S 50 – – ns MLEN hold time tM C H 50 – – ns M L E N L OW -level pulsewidth tM E W L 50 – – ns MLEN HIGH-level pulsewidth tM E W H 50 – – ns 0.5VDD MDT tMDS tMDH MCK 0.5VDD tMCS tMCH MLEN 0.5VDD tMEWL tMEWH tf tr 0.9VDD MCK MLEN 0.9VDD 0.1VDD 0.1VDD 0.5VDD Reset input (RSTN) Rating P arameter R S T N L OW -level pulsewidth Symbol tR S T N Unit min typ max 100 – – ns NIPPON PRECISION CIRCUITS—4 SM6451BV AC Analog Characteristics VDD = 3.0 V, 0.8 Vrms amplitude, 1 kHz input frequency, 100 kΩ output load resistance, Ta = 25 °C, AC-coupled inputs Analog inputs (LIN, RIN) Rating P arameter Symbol Condition Unit min typ max Reference input amplitude V AI – 0.8 – Vr m s Input resistance R IN 40 50 60 kΩ – 1.1 – Vr m s Input clipping voltage VCLP THD + N = 1%, ATT = 0 dB Analog outputs (LOUT, ROUT) Rating P arameter Symbol Residual noise voltage VNS Signal-to-noise ratio SNR Total harmonic distortion + noise THD + N Condition Input signal: 0 Vr m s , A - weight filter, 0 dBr = 0.8 Vr m s , ATT = 0 dB ATT = 0 dB, 20 kHz lowpass filter Unit min typ max – 12 20 µVr m s 92 96 – dBr – 0.0025 0.005 % Gain control range RCNT – 80 – 0 dB Step size Step 0.8 1.0 1.8 dB Attenuation error (1k to 20kHz) ERR1 0 to −60 dB –2 – 1 dB ERR2 −61 to −80 dB –6 – 0 dB AT 0 ATT = 0 dB – – 0.0 – dB AT 2 ATT = −20 dB – – 20.0 – dB AT 4 ATT = −40 dB – – 40.0 – dB AT 6 ATT = −60 dB – – 60.4 – dB AT 8 ATT = −80 dB – – 84.2 – dB Mute ATT = Mute – 85.0 – 88.0 – dB Channel crosstalk CT ATT = 0 dB – 103 – 105 – dB Frequency response FR ATT = 0 dB, f = 200 kHz – 10 –8 – dB Quiescent output zip noise voltage (while ATT value adjusting) NJ 0 Vr ms input – – 3 mV RML ATT = 0 dB, THD + N = 1% – 8 12 kΩ Symbol Condition Absolute attenuation (1 kHz) Mute attenuation (1 kHz) Minimum driver load resistance Reference voltage (VRL, VRR) Rating P arameter Reference voltage output VREF Unit min typ max 0.45V D D 0.5V D D 0.55V D D V NIPPON PRECISION CIRCUITS—5 SM6451BV MEASUREMENT CIRCUIT Chip address: ADRS1 = LOW, ADRS2 = LOW 0.001µF 0.022µF MDT 16 2 ADRS1 MCK 15 3 ADRS2 MLEN 14 4 DVDD DVSS 13 5 LOUT ROUT 12 6 LIN + 10µF + 1µF 0.022µF + 7 AVDD + 10µF SM6451 + 10µF 1 RSTN 8 VRL 0.022µF CPU RIN 11 AVSS 10 VRR 9 0.022µF 1µF + 10µF + 1µF + 1µF 100kΩ 100kΩ Generator Analyzer Audio Precision System Two SYS − 2322A NIPPON PRECISION CIRCUITS—6 SM6451BV MICROCONTROLLER INTERFACE The SM6451BV uses a 3-wire serial interface comprising MDT (data), MCK (clock) and MLEN (latch enable) to select channels and attenuation levels for the addressed device. Input Timing The microcontroller data input timing is shown in figure 1. MDT D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 MCK MLEN Figure 1. Microcontroller data input timing Data is shifted into the internal shift register on the rising edge of MCK, and the attenuation value is updated on the rising edge of MLEN. Accordingly, data on MDT should be changed on the falling edge of MCK. The dotted lines for MCK and MLEN also indicate valid timing. Note, however, a minimum of 16 MCK input pulses are required. Data Format Attenuation Data 7 Attenuation Data 6 Attenuation Data 5 Attenuation Data 4 Attenuation Data 3 Attenuation Data 2 Attenuation Data 1 Attenuation Data 0 D15 D14 D13 D12 D11 D10 D9 Channel Select Channel Select Don't Care Don't Care Chip Address 2 Chip Address 1 Don't Care MDT Don't Care The format of microcontroller input data is shown in figure 2. D8 D7 D6 D5 D4 D3 D2 D1 D0 Figure 2. Microcontroller data format D15, D14 Don’t care. D13, D12 Chip address bits. D13 corresponds to ADRS1 and D12 corresponds to ADRS2. The device is addressed only when ADRS1:ADRS2 matches D13:D12. Example 1: If D13 = LOW, D12 = HIGH and ADRS1 = LOW, ADRS2 = LOW, then the device is not addressed since ADRS2 and D12 do not match. Example 2: If D13/D12 = LOW and ADRS1/ADRS2 = LOW, then the device is addressed and all input data is read and the attenuation settings updated. D11, D10 Don’t care. NIPPON PRECISION CIRCUITS—7 SM6451BV D9, D8 Channel select bits. The selected channel(s) are shown in table 1. Table 1. Channel select D9 D8 Selected channel LOW LOW Both left and right channels LOW HIGH Left channel HIGH LOW Right channel HIGH HIGH No change D7 to D0 Attenuation register (ATT) set bits. Table 2. Attenuation setting1 Attenuation 0 dB −1 dB −2 dB : −15 dB −16 dB −17 dB : −63 dB −64 dB −65 dB : −79 dB −80 dB Mute Mute : Mute Mute 1. AT T H 00 01 02 : 0F 10 11 : 3F 40 41 : 4F 50 51 52 : FE FF D7 LOW LOW LOW : LOW LOW LOW : LOW LOW LOW : LOW LOW LOW LOW : HIGH HIGH D6 LOW LOW LOW : LOW LOW LOW : LOW HIGH HIGH : HIGH HIGH HIGH HIGH : HIGH HIGH D5 LOW LOW LOW : LOW LOW LOW : HIGH LOW LOW : LOW LOW LOW LOW : HIGH HIGH D4 LOW LOW LOW : LOW HIGH HIGH : HIGH LOW LOW : LOW HIGH HIGH HIGH : HIGH HIGH D3 LOW LOW LOW : HIGH LOW LOW : HIGH LOW LOW : HIGH LOW LOW LOW : HIGH HIGH D2 LOW LOW LOW : HIGH LOW LOW : HIGH LOW LOW : HIGH LOW LOW LOW : HIGH HIGH D1 LOW LOW HIGH : HIGH LOW LOW : HIGH LOW LOW : HIGH LOW LOW HIGH : HIGH HIGH D0 LOW HIGH LOW : HIGH LOW HIGH : HIGH LOW HIGH : HIGH LOW HIGH LOW : LOW HIGH Outputs are muted after system reset. Attenuation error is changed dependent on the supply voltage when attenuation level is under – 60dB. In the case of the supply voltage being under 2.6V, mute level inverses up to the same level of – 80dB setting or more. (see Figure 6) NIPPON PRECISION CIRCUITS—8 SM6451BV ANALOG PERFORMANCE CHARACTERISTICS DVDD = AVDD = 3.0 V, 100 kΩ output load resistance, Ta = 25 °C 0.1 1 ATT=0dB 20kHz LPF 0.1 THD+N(%) THD+N(%) f=1kHz ATT=0dB 20kHz LPF VDD=3.3V VDD=3.0V VDD=2.7V VIN=0.2Vrms 0.01 0.01 VIN=0.5Vrms VIN=0.8Vrms 0.001 .1 .2 1 .5 1.2 VIN(Vrms) 0.001 20 20k -64 VIN=0.8Vrms f=1kHz 1 -68 0 Ideal Gain -72 Gain(dB) Error(dB) 10k Figure 4. THD + N vs. input frequency 2 -1 -2 -76 VDD=2.7V -3 -84 -4 -88 0 -10 -20 -30 -40 -50 -60 -70 VDD=3V -80 VDD=2.5V -92 -64 -80 -68 ATT(dB) -72 -76 -80 Mute ATT(dB) Figure 5. Attenuation error Figure 6. Attenuation characteristic (– 64dB to MUTE) 20 +10 +0 VIN=0Vrms A-Weight Filter 16 -20 12 8 VIN=0.8Vrms ATT=0dB -10 Gain(dB) Residual Noise(µVrms) 1k Frequency(Hz) Figure 3. THD + N vs. input amplitude -5 100 ATT=-20dB -30 -40 ATT=-40dB -50 -60 ATT=-60dB -70 4 -80 ATT=-80dB -90 ATT=MUTE 0 0 -10 -20 -30 -40 -50 -60 -70 ATT(dB) Figure 7. Residual noise vs. ATT -80 -100 20 100 1k 10k 100k 200k Frequency(Hz) Figure 8. Frequency response NIPPON PRECISION CIRCUITS—9 SM6451BV -40 +0 FFT Spectrum(dBr) Cross Talk(dB) VIN=0.8Vrms=0dBr f=1kHz ATT=0dB BH Window -20 VIN=0.8Vrms ATT=0dB -60 -80 -100 -40 -60 -80 -100 -120 -120 -140 20 100 1k 10k 100k 200k -140 0 2k 4k Frequency(Hz) 8k 10k 12k 14k 16k 18k 20k Frequency(Hz) Figure 9. Crosstalk frequency response Figure 10. FFT spectrum 100 6 Current Consumption(mA) VIN=0.8Vrms f=1kHz ATT=0dB 20kHz LPF 10 THD+N(%) 6k 1 0.1 0.01 0.001 1 10 Load Resistance(kΩ) 100 Figure 11. THD + N vs. load resistance 5 AVDD+DVDD ADRS1=ADRS2=0V 4 3 2 1 0 2.4 2.7 3 3.3 3.6 Power Supply(V) Figure 12. Current consumption vs. supply voltage Current Consumption(mA) 6 5 AVDD+DVDD ADRS1=ADRS2=0V 4 3 VDD=3.3V VDD=3.0V 2 VDD=2.7V 1 0 -50 -25 0 25 50 75 100 Operating Temperature(°C) Figure 13. Current consumption vs. operating temperature NIPPON PRECISION CIRCUITS—10 SM6451BV TYPICAL APPLICATIONS Connection Guidelines Decoupling capacitors of approximately 10 µF should be connected from AVDD, VRL, VRR to AVSS, and from DVDD to DVSS. In addition, approximately 0.01 µF capacitors should also be connected from AVDD, VRL, VRR to AVSS, and from DVDD to DVSS to suppress digital switch noise. An approximately 0.001 µF capacitor connected from RSTN to DVSS will force a system reset when power is applied. Connection 1 (to DAC) CPU MDT MCK MLEN LPF LIN LOUT LPF RIN ROUT L-ch OUT DAC R-ch OUT SM6451 2.5 to 3.6V DVDD DVSS AVDD AVSS ADRS1 ADRS2 Connection 2 When there is a possibility that the input peak-to-peak amplitude will exceed the supply voltage, input protection diodes should be connected to prevent device breakdown. AVDD L-ch Input LIN LOUT L-ch Output SM6451 R-ch Input RIN ROUT R-ch Output AVSS NIPPON PRECISION CIRCUITS—11 SM6451BV NIPPON PRECISION CIRCUITS INC. reserves the right to make changes to the products described in this data sheet in order to improve the design or performance and to supply the best possible products. Nippon Precision Circuits Inc. assumes no responsibility fo r the use of any circuits shown in this data sheet, conveys no license under any patent or other rights, and makes no claim that the circuits are free from patent infringement. Applications for any devices shown in this data sheet are for illustration only and Nippon Precision Circuits Inc. makes no claim or warranty that such applications will be suitable for the use specified without further testing or modification. The products described in this data sheet are not intended to use for the apparatus which influence human lives due to the failure or malfunction of the products. Customers are requested to comply with applicable laws and regulations in effect now and hereinafter, including compliance with expor t controls on the distribution or dissemination of the products. Customers shall not expor t, directly or indirectly, any products without first obtaining required licenses and approvals from appropriate government agencies. NIPPON PRECISION CIRCUITS INC. NIPPON PRECISION CIRCUITS INC. 4-3, Fukuzumi 2-chome Koto-ku, Tokyo 135-8430, Japan Telephone: 03-3642-6661 Facsimile: 03-3642-6698 NC9925AE 2000.02 NIPPON PRECISION CIRCUITS—12