LSU401 LOW NOISE, LOW DRIFT MONOLITHIC DUAL N-CHANNEL JFET Linear Systems replaces discontinued Siliconix U401 with LSU401 The U401/ LSU401 is a Low Noise, Low Drift, Monolithic Dual N-Channel JFET The U401 is a high-performance monolithic dual JFET features extremely low noise, tight offset voltage and low drift over temperature specifications, and is targeted for use in a wide range of precision instrumentation applications. This series has a wide selection of offset and drift specifications with the U401 featuring a 5-mV offset and 10-µV/°C drift. The hermetically sealed TO-71 & TO-78 packages are well suited for military applications. The 8 Pin P-DIP and 8 Pin SOIC provide ease of manufacturing, and the symmetrical pinout prevents improper orientation. (See Packaging Information). U401 / LSU401 Applications: Wideband Differential Amps High-Speed,Temp-Compensated Single-Ended Input Amps High-Speed Comparators Impedance Converters and vibrations detectors. ELECTRICAL CHARACTERISTICS @ 25°C (unless otherwise noted) SYMBOL CHARACTERISTICS MIN. BVGSS Breakdown Voltage 50 BVGGO Gate‐To‐Gate Breakdown ±50 TRANSCONDUCTANCE YfSS Full Conduction 2000 YfS Typical Operation 1000 |YFS1‐2 / Y FS| Mismatch ‐‐ DRAIN CURRENT IDSS Full Conduction 0.5 |IDSS1‐2 / IDSS| Mismatch at Full Conduction ‐‐ GATE VOLTAGE VGS(off) or Vp Pinchoff voltage ‐0.5 VGS(on) Operating Range ‐‐ GATE CURRENT ‐IGmax. Operating ‐‐ ‐IGmax. High Temperature ‐‐ ‐IGSSmax. At Full Conduction ‐‐ ‐IGSSmax. High Temperature 5 OUTPUT CONDUCTANCE YOSS Full Condtion ‐‐ YOS Operating ‐‐ COMMON MODE REJECTION CMR ‐20 log | V GS1‐2/ V DS| 95 NOISE NF Figure ‐‐ en Voltage ‐‐ CAPACITANCE CISS Input ‐‐ CRSS Reverse Transfer ‐‐ Available Packages: FEATURES LOW DRIFT LOW NOISE LOW PINCHOFF ABSOLUTE MAXIMUM RATINGS @ 25°C (unless otherwise noted) | V GS1‐2 / T| = 10µV/°C TYP. en = 6nV/Hz @ 10Hz TYP. Vp = 2.5V TYP. Maximum Temperatures Storage Temperature ‐65°C to +150°C Operating Junction Temperature +150°C Maximum Voltage and Current for Each Transistor ‐VGSS Gate Voltage to Drain or Source 50V ‐VDSO Drain to Source Voltage 50V ‐IG(f) Gate Forward Current 10mA Maximum Power Dissipation Device Dissipation @ Free Air – Total 300mW MATCHING CHARACTERISTICS @ 25°C UNLESS OTHERWISE NOTED SYMBOL CHARACTERISTICS VALUE UNITS CONDITIONS | V GS1‐2 / T| max. DRIFT VS. 10 µV/°C VDG=10V, ID=200µA TEMPERATURE TA=‐55°C to +125°C | V GS1‐2 | max. OFFSET VOLTAGE 5 mV VDG=10V, ID=200µA TYP. 60 ‐‐ ‐‐ ‐‐ 0.6 ‐‐ 1 ‐‐ ‐‐ ‐4 ‐‐ ‐‐ 5 ‐‐ 0.2 ‐‐ ‐‐ 20 ‐‐ ‐‐ MAX. ‐‐ ‐‐ 7000 2000 3 10 5 ‐2.5 ‐2.3 ‐15 ‐10 100 5 20 2 ‐‐ 0.5 ‐‐ 8 1.5 UNITS V V µmho µmho % mA % V V pA nA pA pA µmho µmho dB dB nV/Hz pF pF TO-71 / TO-78 (Top View) CONDITIONS VDS = 0 ID=1nA I G= 1nA ID= 0 IS= 0 VDG= 10V VGS= 0V f = 1kHz VDG= 15V ID= 200µA f = 1kHz VDG= 10V VGS= 0V VDS= 15V ID= 1nA VDS=15V ID=200µA VDG= 15V ID= 200µA TA= +125°C VDS =0 VDG= 15V TA= +125°C VDG= 10V VGS= 0V VDG= 15V ID= 500µA VDS = 10 to 20V ID=30µA VDS= 15V VGS= 0V RG= 10M f= 100Hz NBW= 6Hz VDS=15V ID=200µA f=10Hz NBW=1Hz VDS= 15V ID= 200µA f= 1MHz P-DIP / SOIC (Top View) U401/ LSU401 in TO-71 & TO-78 U401/ LSU401 in PDIP & SOIC U401/ LSU401 available as bare die Please contact Micross for full package and die dimensions Micross Components Ltd, United Kingdom, Tel: +44 1603 788967, Fax: +44 1603788920, Email: [email protected] Web: www.micross.com/distribution.aspx