Micron Confidential and Proprietary MMC Controller & NAND Flash 4GB, 8GB, 16GB, 32GB: e·MMC MYXFC32GJDDQ* Features e·MMC™ Memory *Advanced information. Subject to change without notice. MMC Controller and 32GB NAND Flash MTFC4GLDDQ-4M IT, MTFC8GLDDQ-4M IT MTFC16GJDDQ-4M IT, MTFC32GJDDQ-4M IT Features Figure 1: e·MMC Device Figure 1: Micron e·MMC Device • Tin-lead ball metallurgy Features • MultiMediaCard (MMC) controller and 32GB NAND Flash • MultiMediaCard (MMC) controller and NAND Flash • VCC: 2.7–3.6V • 100-ball LBGA • VCCQ (dual(RoHS voltage):6/61.65–1.95V; 2.7–3.6V compliant) • Typical current consumption • VCC: 2.7–3.6V Standby current: 90μA voltage): • VCCQ (dual Active current1.65–1.95V; (RMS): 90mA 2.7–3.6V • Industrial temperature ranges – Operating temperature: –40˚C to +85˚C MMC - Specific Features – Storage temperature: –40˚C to +85˚C • JEDEC/MMC standard version 4.41-compliant (JEDEC • Typical current consumption Standard No. 84-A441) - SPI mode supported – Standby current: 70μA (4GB, 8GB);not 90µA (16GB, 32GB) (see www.jedec.org/sites/default/files/docs/JESD84-A441.pdf) current Advanced 11-signal interface – Active (RMS): 70mA (4GB, 8GB); 90mA 32GB) x1, x4, and x8 I/Os, selectable by host (16GB, MMC power NAND Flash power MMC mode operation Command classes: class 0 (basic); class 2 (block read); MMC-Specific Features class 4 (block write); class 5 (erase); class 6 (write • JEDEC/MMC standard 4.41-compliant protection); classversion 7 (lock card) (JEDECStandard No. 84-A441) – SPIprotocols mode not MMCplus™ and MMCmobile™ supported (see www.jedec.org/sites/default/files/ Temporary write protection docs/JESD84-A441.pdf) 52 MHz clock speed (MAX) – Advanced 11-signal interface boot) Boot operation (high-speed – x1, x4, and x8 I/Os, selectable by host Sleep mode – MMCmode operationmemory block (RPMB) Replay-protected – Command classes: class Secure erase and trim0 (basic); class 2 (block read);class 4 (block write); class 5 (erase); Hardware reset signal class 6 (write class 7 (lock card) Multipleprotection); partitions with enhanced attribute – MMCplus™ and and MMCmobile™ protocols Permanent power-on write protection – Temporary write Double data protection rate (DDR) function – 52 MHz clock speed (MAX) High-priority interrupt (HPI) Enhanced (high-speed reliable write boot) – Boot operation Configurable reliability settings – Sleepmode Background operation – Replay-protected memory block (RPMB) erase Fully enhanced configurable – Secure and trim Backward-compatible with previous MMC modes – Hardware reset signal – – – – MMC controller MMC interface NAND Flash MMC-Specific Features (Continued) – Enhanced reliable write –OptionsMarking Configurable reliability settings –• Background Package (Sn63operation Pb37 solder) – Fully enhanced configurable 100-ball LFBGA BG – Backward-compatible with previous MMC (14mm x 18mm x 1.4mm) modes • Operating Temperature • ECC and block management implemented Industrial (-40°C ≤ TC ≤ +85°C) IT Multiple partitions with enhanced attribute • ECC and block management implemented Permanent and power-on write protection Double data rate (DDR) function High-priority MYXFC32GJDDQ interrupt (HPI) Revision 1.0 - 11/26/2014 1 Form #: CSI-D-685 Document 013 MMC Controller & NAND Flash MYXFC32GJDDQ* *Advanced information. Subject to change without notice. Contents 1 e·MMC Performance . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 2 General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 3 Signal Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 4 100-Ball Signal Assignments . . . . . . . . . . . . . . . . . . . . 5 5 Package Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 6Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 6.1 MMC Protocol Independent of NAND Flash Technology . . 7 6.2 Defect and Error Management . . . . . . . . . . . . . . . . . . . . 7 7 CID Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 8 CSD Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 9 ECSD Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 10 DC Electrical Specifications – Device Power . . . . . . . 15 11 Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . 17 MYXFC32GJDDQ Revision 1.0 - 11/26/2014 2 Form #: CSI-D-685 Document 013 MMC Controller & NAND Flash MYXFC32GJDDQ* *Advanced information. Subject to change without notice. 1 e·MMC Performance Table 1: MLC Partition Performance Condition MYXFC32GJDDQ Units Sequential write 20 MB/s Sequential read 44 MB/s Random write 90 IOPs Random read 1100 IOPs Note: 1. Bus in x8 I/O mode. Sequential access of 1MB chunk; random access of 4KB chunk. Additional performance data, such as power consumption or timing for different device modes, will be provided in a separate document upon customer request. 2 General Description e·MMC is a communication and mass data storage device that includes a Multi-MediaCard (MMC) interface, a NAND Flash component, and a controller on an advanced 11-signal bus, which is compliant with the MMC system specification. Its cost per bit, small package sizes, and high reliability make it an ideal choice for industrial applications like infrastructure and networking equipment, PC and servers, a variety of other industrial products. The nonvolatile e·MMC draws no power to maintain stored data, delivers high performance across a wide range of operating temperatures, and resists shock and vibration disruption. MYXFC32GJDDQ Revision 1.0 - 11/26/2014 3 Form #: CSI-D-685 Document 013 MMC Controller & NAND Flash MYXFC32GJDDQ* *Advanced information. Subject to change without notice. 3 Signal Descriptions Table 2: Signal Descriptions Symbol Type Description CLK Input Clock: Each cycle of the clock directs a transfer on the command line and on the data line(s). The frequency can vary between the minimum and the maximum clock frequency. RST_n Input Reset: The RST_n signal is used by the host for resetting the device, moving the device to the preidle state. By default, the RST_n signal is temporarily disabled in the device. The host must set ECSD register byte 162, bits[1:0] to 0x1 to enable this functionality before the host can use it. CMD I/O Command: This signal is a bidirectional command channel used for command and response transfers. The CMD signal has two bus modes: open-drain mode and push-pull mode (see Operating Modes). Commands are sent from the MMC host to the device, and responses are sent from the device to the host. DAT[7:0] I/O Data I/O: These are bidirectional data signals. The DAT signals operate in push-pull mode. By default, after power-on or assertion of the RST_n signal, only DAT0 is used for data transfer. The MMC controller can configure a wider data bus for data transfer either using DAT[3:0] (4-bit mode) or DAT[7:0] (8-bit mode). e·MMC includes internal pull-up resistors for data lines DAT[7:1]. Immediately after entering the 4-bit mode, the device disconnects the internal pull-up resistors on the DAT[3:1] lines. Upon entering the 8-bit mode, the device disconnects the internal pull-ups on the DAT[7:1] lines. VCC Supply VCC: NAND interface (I/F) I/O and NAND Flash power supply. VCCQ Supply VCCQ: e·MMC controller core and e·MMC I/F I/O power supply. VSS1 Supply VSS: NAND I/F I/O and NAND Flash ground connection. VSSQ1 Supply VSSQ: e·MMC controller core and e·MMC I/F ground connection. Internal voltage node: At least a 0.1μF capacitor is required to connect VDDIM to ground. A 1μF capacitor is recommended. Do not tie to supply voltage or ground. VDDIM NC – No connect: No internal connection is present. RFU – Reserved for future use: No internal connection is present. Leave it floating externally. Note: 1. VSS and VSSQ are connected internally. MYXFC32GJDDQ Revision 1.0 - 11/26/2014 4 Form #: CSI-D-685 Document 013 MMC Controller & NAND Flash MYXFC32GJDDQ* Micron Confidential and Proprietary 4 *Advanced to change without notice. 4GB, 8GB,information. 16GB, Subject 32GB: e·MMC 100-Ball Signal Assignments 100-Ball Signal Assignments 100-Ball Signal Assignments Figure 2: LFBGA 100-Ball LFBGA (Top View, Ball Figure 3: 100-Ball (Top View, Ball Down) Notes: 1. 2. 3. 1 2 A NC NC B NC 3 4 Down) 5 6 7 8 9 10 NC NC A NC B D RFU RFU RFU RFU RFU RFU RFU RFU D E RFU RFU VDDIM RFU RFU RFU RFU RFU E F VCC VCC VCC VCC VCC VCC VCC VCC F G VSS VSS VSS VSS VSS VSS VSS VSS G H VSSQ VCCQ RFU RFU RFU RFU VCCQ VSSQ H J RFU RFU RFU RFU RFU RFU RFU RFU J K DAT0 DAT2 RFU RFU RFU RFU DAT5 DAT7 K L VCCQ VSSQ VCCQ RFU RFU VCCQ VSSQ VCCQ L M RFU RFU VSSQ RST_n RFU VSSQ RFU RFU M N DAT1 DAT3 RFU RFU RFU RFU DAT4 DAT6 N P VSSQ VCCQ RFU CMD CLK RFU VCCQ VSSQ P T NC U NC NC NC NC T NC U 1. Connect a 1μF decoupling capacitor from VDDI to ground. 2. Some test pads on the device are not shown. They are not solder balls and are for MiConnect a 1μF decoupling capacitor from VDDI to ground. cron internal use only. Some test pads theprevious device versions are not shown. Theyproduct are notorsolder balls and are for internal use only. 3. on Some of the JEDEC mechanical specification had defined reserved for future use (RFU) balls as no connect (NC) balls. NC balls assigned in the preSome previous versions of the JEDEC product or mechanical specification had defined reserved for future vious specifications could have been connected to ground on the system board. To enause (RFU) balls asblenonew connect balls. NCsome ballsofassigned in are the assigned previousasspecifications feature(NC) introduction, these balls RFU in the v4.4could me- have specification. Any new PCB To footprint should use the newofball been connected chanical to ground on the system board. enableimplementations new feature introduction, some these balls assignments and leave the RFU balls floating on the system board. are assigned as the mechanical specification. Any new PCB footprint implementations should 4. RFU VCC, VinCCQ , Vv4.4 SS, and VSSQ balls must all be connected. Notes: use the new ball assignments and leave the RFU balls floating on the system board. 4. VCC, VCCQ, VSS, and VSSQ balls must all be connected. PDF: 09005aef8523caab emmc_4-32gb_ctrd_441_100b-it.pdf - Rev. B 9/13 EN MYXFC32GJDDQ Revision 1.0 - 11/26/2014 6 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2013 Micron Technology, Inc. All rights reserved. 5 Form #: CSI-D-685 Document 013 MMC Controller & NAND Flash MYXFC32GJDDQ* Micron Confidential and Proprietary 4GB, 8GB, 16GB, 32GB: e·MMC *Advanced information. Subject Dimensions to change without notice. Package 5Package Dimensions Package Dimensions Figure 4: 100-Ball – 14.0mm x 1.4mmx(Package Code: DQ) FigureLBGA 3: 100-Ball LBGA x– 18.00mm 14.0mm x 18.00mm 1.4mm (Package Code: DQ) Seating plane A 100X Ø0.466 Dimensions apply to solder balls postreflow on Ø0.40 SMD ball pads. 0.12 A Ball A1 ID Ball A1 ID 10 9 8 7 6 5 4 3 2 1 A B C D E F 18 ±0.1 G H 10.0 CTR J K 16.0 CTR L M N P R T 1.0 TYP U 1.3 ±0.1 1.0 TYP 9.0 CTR 0.303 MIN 14 ±0.1 36X Ø0.325 on 0.5 pitch. Ni/Au plated test pads. No solder balls. Notes:Notes: 1. Dimensions are in millimeters. 2. Solder ball material: SnAgCu (96.5% Sn, 3% Ag, 0.5% Cu). 1. Dimensions are in millimeters. 3. Test pads are not solder balls and are for Micron internal use only. 2. Solder ball material: SnAgCu (96.5% Sn, 3% Ag, 0.5% Cu). 3. Test pads are not solder balls and are for internal use only. MYXFC32GJDDQ Revision 1.0 - 11/26/2014 PDF: 09005aef8523caab emmc_4-32gb_ctrd_441_100b-it.pdf - Rev. B 9/13 EN 6 7 Form #: CSI-D-685 Document 013 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2013 Micron Technology, Inc. All rights reserved. MMC Controller & NAND Flash Micron Confidential and Proprietary MYXFC32GJDDQ* 4GB, 8GB, 16GB, 32GB: e·MMC *Advanced information. Subject to change without notice. Architecture 6 Architecture Architecture Figure 5: e·MMC Functional Block Diagram Figure 4: e·MMC Functional Block Diagram e·MMC MMC controller RST_n VDDIM VCCQ Registers CMD CLK VCC DAT[7:0] OCR CSD RCA CID ECSD DSR VSS1 VSSQ1 NAND Flash Note: 1Note: 1. VSS and VSSQ are internally connected. 1. VSS and VSSQ are internally connected. MMC Protocol Independent of NAND Flash Technology The MMC specification defines the communication protocol between a host and a de- 6.1 Defect MMC Protocol Independent of NAND Flash Technology vice. The protocol is independent of the NAND Flash features included in the device. The device has an intelligent on-board controller that manages the MMC communication protocol. The MMC specification defines the communication protocol between a host and a device. The protocol is independentThe of the NAND Flash included in the device. The device has anas intelligent on-board controller controller alsofeatures handles block management functions such logical block allocathat manages theand MMC communication protocol. tion wear leveling. These management functions require complex algorithms and depend entirely on NAND Flash technology (generation or memory cell type). The controller also handles block management functions such as logical block allocation and wear leveling. The device handles these management functions internally, making them invisible to These management functions require complex algorithms and depend entirely on NAND Flash technology the host processor. (generation or memory cell type). The device handles these management functions internally, making them the host processor. andinvisible ErrortoManagement 6.2 Micron e·MMC incorporates advanced technology for defect and error management. If a defective block is identified, the device completely replaces the defective block with Defect and Error Management one of the spare blocks. This process is invisible to the host and does not affect data space allocated for the user. e·MMC incorporates advanced technology for defect and error management. If a defective block is identified, The device also includes a built-in correction codeblocks. (ECC) algorithm to is ensure that the device completely replaces the defective blockerror with one of the spare This process invisible to the data integrity is maintained. host and does not affect data space allocated for the user. To make the best use of these advanced technologies and ensure proper data loading and storage over the life of the device, the host must exercise the following precautions: MYXFC32GJDDQ Revision 1.0 - 11/26/2014 PDF: 09005aef8523caab • Check the status after WRITE, READ, and ERASE operations. 7 • Avoid power-down during WRITE and ERASE operations. Form #: CSI-D-685 Document 013 Micron Technology, Inc. reserves the right to change products or specifications without notice. MMC Controller & NAND Flash MYXFC32GJDDQ* *Advanced information. Subject to change without notice. The device also includes a built-in error correction code (ECC) algorithm to ensure that data integrity is maintained. To make the best use of these advanced technologies and ensure proper data loading and storage over the life of the device, the host must exercise the following precautions: • Check the status after WRITE, READ, and ERASE operations. • Avoid power-down during WRITE and ERASE operations. 7 CID Register The card identification (CID) register is 128 bits wide. It contains the device identification information used during the card identification phase as required by e·MMC protocol. Each device is created with a unique identification number. Table 3: CID Register Field Parameters MYXFC32GJDDQ Revision 1.0 - 11/26/2014 Name Field Width CID Bits CID Value Manufacturer ID MID 8 [127:120] FEh Reserved – 6 [119:114] – Card/BGA CBX 2 [113:112] 01h OEM/application ID OID 8 [111:104] – Product name PNM 48 [103:56] MMC32G Product revision PRV 8 [55:48] – Product serial number PSN 32 [47:16] – Manufacturing data MDT 8 [15:8] – CRC7 checksum CRC 7 [7:1] – Not used; always 1 – 1 0 – 8 Form #: CSI-D-685 Document 013 MMC Controller & NAND Flash MYXFC32GJDDQ* *Advanced information. Subject to change without notice. 8 CSD Register The card-specific data (CSD) register provides information about accessing the device contents. The CSD register defines the data format, error correction type, maximum data access time, and data transfer speed, as well as whether the DS register can be used. The programmable part of the register (entries marked with W or E in the following table) can be changed by the PROGRAM_CSD (CMD27) command. Table 4: CSD Register Field Parameters Field CSD structure CSD_STRUCTURE 2 R [127:126] 03h System specification version SPEC_VERS 4 R [125:122] 4h Reserved2 – 2 TBD [121:120] – Data read access time 1 TAAC 8 R [119:112] 4Fh Data read access time 2 in CLK cycles (NSAC × 100) NSAC 8 R [111:104] 01h Maximum bus clock frequency TRAN_SPEED 8 R [103:96] 32h Card command classes CCC 12 R [95:84] 0F5h Maximum read data block length READ_BL_LEN 4 R [83:80] 9h Partial blocks for reads supported READ_BL_PARTIAL 1 R 79 0h Write block misalignment WRITE_BLK_MISALIGN 1 R 78 0h Read block misalignment READ_BLK_MISALIGN 77 R 77 0h DS register implemented DSR_IMP 1 R 76 0h 2 R [75:74] 1h Reserved Width Cell Type1 CSD Bits CSD Value Name Device size C_SIZE 12 R [73:62] – Maximum read current at VDD,min VDD_R_CURR_MIN 3 R [61:59] FFFh Maximum read current at VDD,max VDD_R_CURR_MAX 3 R [58:56] 7h Maximum write current at VDD,min VDD_W_CURR_MIN 3 R [55:53] 7h Maximum write current at VDD,max VDD_W_CURR_MAX 3 R [52:50] 7h Device size multiplier C_SIZE_MULT 3 R [49:47] 7h Erase group size ERASE_GRP_SIZE 5 R [46:42] 1Fh Erase group size multiplier ERASE_GRP_MULT 5 R [41:37] 1Fh Write protect group size WP_GRP_SIZE 5 R [36:32] 1Fh Write protect group enable WP_GRP_ENABLE 1 R 31 1h MYXFC32GJDDQ Revision 1.0 - 11/26/2014 9 Form #: CSI-D-685 Document 013 MMC Controller & NAND Flash MYXFC32GJDDQ* *Advanced information. Subject to change without notice. Table 4: CSD Register Field Parameters (continued) Width Cell Type1 CSD Bits CSD Value Name Field Manufacturer default ECC DEFAULT_ECC 2 R [30:29] 0h Rite-speed factor R2W_FACTOR 3 R [28:26] 2h Maximum write data block length WRITE_BL_LEN 4 R [25:22] 9h Partial blocks for writes supported WRITE_BL_PARTIAL 1 R 21 0h Reserved – 4 R [20:17] – Content protection application CONTENT_PROT_APP 1 R 16 0h File-format group FILE_FORMAT_GRP 1 R/W 15 0h Copy flag (OTP) COPY 1 R/W 14 0h Permanent write protection PERM_WRITE_PROTECT 1 R/W 13 0h Temporary write protection TMP_WRITE_PROTECT 1 R/W/E 12 0h File format FILE_FORMAT 2 R/W [11:10] 0h ECC ECC 2 R/W/E [9:8] 0h CRC CRC 7 R/W/E [7:1] – Not used; always 1 – 1 – 0 1h Notes: 1. R = Read-only R/W = One-time programmable and readable R/W/E = Multiple writable with value kept after a power cycle, assertion of the RST_n signal, and any CMD0 reset, and readable TBD = To be determined 2. Reserved bits should be read as 0. 3. The IPEAK, max driving capability can be modified according to the actual capacitive load on the e·MMC interface signals in the user application board, using CMD4. MYXFC32GJDDQ Revision 1.0 - 11/26/2014 CMD4 Argument Driving 0x01000000 0x02000000 0x04000000 0x08000000 0x10000000 0x20000000 0x40000000 0x80000000 Capability (mA) 4 8 12 (default) 16 20 24 28 32 10 Form #: CSI-D-685 Document 013 MMC Controller & NAND Flash MYXFC32GJDDQ* *Advanced information. Subject to change without notice. 9 ECSD Register The 512-byte extended card-specific data (ECSD) register defines device properties and selected modes. The most significant 320 bytes are the properties segment. This segment defines device capabilities and cannot be modified by the host. The lower 192 bytes are the modes segment. The modes segment defines the configuration in which the device is working. The host can change the properties of modes segments using the SWITCH command. Table 5: ECSD Register Field Parameters Name Field Size (Bytes) Cell Type1 ECSD Bits ECSD Value Properties Segment Reserved2 – 7 – [511:505] – Supported command sets S_CMD_SET 1 R 504 1h HPI features HPI_FEATURES 1 R 503 3h Background operations support BKOPS_SUPPORT 1 R 502 1h Reserved – 255 – [501:247] – Background operations status BKOPS_STATUS 1 R 246 0h Number of correctly programmed sectors CORRECTLY_PRG_SECTORS_NUM 4 R [245:242] – First initialization time after partitioning (first CMD1 INI_TIMEOUT_PA to device ready) 1 R 241 FFh Reserved – 1 – 240 – Power class for 52 MHz, DDR at 3.6V3 PWR_CL_DDR_52_360 1 R 239 0h Power class for 52 MHz, DDR at 1.95V3 PWR_CL_DDR_52_195 1 R 238 0h – 2 – [237:236] – Minimum write performance for 8-bit at 52 MHz in MIN_PERF_DDR_W_8_52 DDR mode 1 R 235 0h Minimum read performance for 8-bit at 52 MHz in MIN_PERF_DDR_R_8_52 DDR mode 1 R 234 0h Reserved – 1 – 233 – TRIM multiplier TRIM_MULT 1 R 232 0Fh Secure feature support SEC_FEATURE_SUPPORT 1 R 231 15h SECURE ERASE multiplier SEC_ERASE_MULT 1 R 230 06h SECURE TRIM multiplier SEC_TRIM_MULT 1 R 229 09h Boot information BOOT_INFO 1 R 228 7h Reserved – 1 – 227 – Boot partition size BOOT_SIZE_MULT 1 R 226 80h Reserved MYXFC32GJDDQ Revision 1.0 - 11/26/2014 11 Form #: CSI-D-685 Document 013 MMC Controller & NAND Flash MYXFC32GJDDQ* *Advanced information. Subject to change without notice. Table 5: ECSD Register Field Parameters (continued) Size (Bytes) Cell Type1 ECSD Bits ECSD Value ACC_SIZE 1 R 225 07h High-capacity erase unit size HC_ERASE_GRP_SIZE 1 R 224 10h High-capacity erase timeout ERASE_TIMEOUT_MULT 1 R 223 01h Reliable write-sector count REL_WR_SEC_C 1 R 222 01h High-capacity write protect group size HC_WP_GRP_SIZE 1 R 221 04h Sleep current (VCC) S_C_VCC 1 R 220 08h Sleep current (VCCQ) S_C_VCCQ 1 R 219 08h Reserved – 1 – 218 – Sleep/awake timeout S_A_TIMEOUT 1 R 217 10h Reserved – 1 – 216 – Sector count SEC_COUNT 4 R [215:212] 03B20000h Reserved – 1 – 211 – Minimum write performance for 8-bit at 52 MHz MIN_PERF_W_8_52 1 R 210 08h Minimum read performance for 8-bit at 52 MHz MIN_PERF_R_8_52 1 R 209 08h Minimum write performance for 8-bit at 26 MHz and 4-bit at 52 MHz MIN_PERF_W_8_26_4_52 1 R 208 08h Minimum read performance for 8-bit at 26 MHz and 4-bit at 52 MHz MIN_PERF_R_8_26_4_52 1 R 207 08h Minimum write performance for 4-bit at 26 MHz MIN_PERF_W_4_26 1 R 206 08h Minimum read performance for 4-bit at 26 MHz MIN_PERF_R_4_26 1 R 205 08h Reserved Name Field Access size – 1 – 204 – Power class for 26 MHz at 3.6V3 PWR_CL_26_360 1 R 203 00h Power class for 52 MHz at 3.6V3 PWR_CL_52_360 1 R 202 00h Power class for 26 MHz at 1.95V3 PWR_CL_26_195 1 R 201 00h Power class for 52 MHz at 1.95V3 PWR_CL_52_195 1 R 200 00h Partition switching timing PARTITION_SWITCH_TIME 1 R 199 1h Out-of-interrupt busy timing OUT_OF_INTERRUPT_TIME 1 R 198 02h Reserved – 1 – 197 – Card type CARD_TYPE 1 R 196 07h Reserved – 1 – 195 – CSD structure version CSD_STRUCTURE 1 R 194 2h Reserved – 1 – 193 – Extended CSD revision EXT_CSD_REV 1 R 192 5h MYXFC32GJDDQ Revision 1.0 - 11/26/2014 12 Form #: CSI-D-685 Document 013 MMC Controller & NAND Flash MYXFC32GJDDQ* *Advanced information. Subject to change without notice. Table 5: ECSD Register Field Parameters (continued) Name Field Size (Bytes) Cell Type1 ECSD Bits ECSD Value Modes Segment Command set CMD_SET 1 R/W/E_P 191 0h Reserved – 1 – 190 – Command set revision CMD_SET_REV 1 R 189 0h Reserved – 1 – 188 – Power class POWER_CLASS 1 R/W/E_P 187 0h Reserved – 1 – 186 – High-speed interface timing HS_TIMING 1 R/W/E_P 185 0h Reserved – 1 – 184 – Bus width mode BUS_WIDTH 1 W/E_P 183 0h Reserved – 1 – 182 – Erased memory content ERASED_MEM_CONT 1 R 181 0h Reserved – 1 – 180 – Partition configuration PARTITION_CONFIG 1 R/W/E, R/W/E_P 179 0h Boot configuration protection BOOT_CONFIG_PROT 1 R/W, R/W/C_P 178 0h Boot bus width BOOT_BUS_WIDTH 1 R/W/E 177 0h Reserved – 1 – 176 – High-density erase group definition ERASE_GROUP_DEF 1 R/W/E_P 175 00h Reserved – 1 – 174 – Boot area write protection register BOOT_WP 1 R/W, R/W/C_P 173 0h Reserved – 1 – 172 – User write protection register USER_WP 1 R/W, R/W/C_P, R/W/E_P 171 0h Reserved – 1 – 170 – Firmware configuration FW_CONFIG 1 R/W 169 0h RPMB size RPMB_SIZE_MULT 1 R 168 1h WR_REL_SET 1 R/W 167 00h4 Write reliability parameter register WR_REL_PARAM 1 R 166 05h Reserved – 1 – 165 – Manually start background operations BKOPS_START 1 W/E_P 164 – Enable background operations handshake BKOPS_EN 1 R/W 163 0h Hardware reset function RST_n_FUNCTION 1 R/W 162 0h HPI management HPI_MGMT 1 R/W/E_P 161 0h Partitioning support PARTITIONING_SUPPORT 1 R 160 3h Write reliability setting register3 MYXFC32GJDDQ Revision 1.0 - 11/26/2014 13 Form #: CSI-D-685 Document 013 MMC Controller & NAND Flash MYXFC32GJDDQ* *Advanced information. Subject to change without notice. Table 5: ECSD Register Field Parameters (continued) Size (Bytes) Cell Type1 ECSD Bits ECSD Value MAX_ENH_SIZE_MULT 1 R [159:157] 0001D9h Partitions attribute PARTITIONS_ATTRIBUTE 1 R/W 156 0h Partitioning setting PARTITION_SETTING_COMPLETED 1 R/W 155 0h General-purpose partition size GP_SIZE_MULT 1 R/W [154:143] 0h Enhanced user data area size ENH_SIZE_MULT 1 R/W [142:140] 0h Enhanced user data start address ENH_START_ADDR 1 R/W [139:136] 0h Reserved – 1 – 135 – Bad block management mode SEC_BAD_BLK_MGMNT 1 R/W 134 0h Reserved – 1 – [133:0] – Name Field Maximum enhanced area size Notes: 1. R R/W R/W/E R/W/C_P R/W/E_P W/E_P TBD Read-only One-time programmable and readable Multiple writable with the value kept after a power cycle, assertion of the RST_n signal, and any CMD0 reset, and readable Writable after the value is cleared by a power cycle and assertion of the RST_n signal (the value not cleared by CMD0 reset) and readable Multiple writable with the value reset after a power cycle, assertion of the RST_n signal, and any CMD0 reset, and readable Multiple writable with the value reset after power cycle, assertion of the RST_n signal, and any CMD0 reset, and not readable To be determined 2. Reserved bits should be read as 0. 3. The OCM has tested power failure under best application knowledge conditions with positive results. 4. Set at 00h when shipped for optimized write performance; can be set to 1Fh to enable protection on previously written data if power failure occurs during a WRITE operation. This byte is one-time programmable. MYXFC32GJDDQ Revision 1.0 - 11/26/2014 14 Form #: CSI-D-685 Document 013 MMC Controller & NAND Flash MYXFC32GJDDQ* Micron Confidential and Proprietary 4GB, 8GB, 16GB, 32GB: e·MMC *Advanced information. Subject to change without notice. DC Electrical Specifications – Device Power 10 DC Electrical Specifications – Device Power DC Electrical Specifications – Device Power The device current consumption for various device is configurations defined in the The device current consumption for various device configurations defined in the ispower class fields of the power class fields of the ECSD register. ECSD register. VCC is NAND used for thedevice NANDand Flash device and its interface voltage; V CCQ is used and for the VCC is used for the Flash its interface voltage; VCCQ is used for the controller the e·MMC controller and the e·MMC interface voltage. interface voltage. Figure 6: Device Power Diagram Figure 5: Device Power Diagram VCC VCCQ C3 C4 C1 C2 Core regulator NAND control signals CLK CMD DAT[7:0] C6 NAND Flash NAND I/O block C5 MMC I/O block VDDIM Core logic block NAND data bus VCCQ MMC controller VCCQ Table 6: Power Domains Table 7: Power Domains Parameter Host interface Parameter Symbol Symbol VCCQ Host interface Memory Internal VCC Memory Internal MYXFC32GJDDQ Revision 1.0 - 11/26/2014 PDF: 09005aef8523caab VDDIM VCCQ VCC VDDIM Comments Comments High voltage range = 3.3V (nominal) Low voltage 1.8V (nominal) Highrange voltage =range = 3.3V (nominal); Low voltage range = 1.8V (nominal) High voltage range = 3.3V (nominal) High voltage range = external 3.3V (nominal) The internal regulator connection to an decoupling capacitor The internal regulator connection to an external decoupling capacitor 15 17 Form #: CSI-D-685 Document 013 Micron Technology, Inc. reserves the right to change products or specifications without notice. MMC Controller & NAND Flash MYXFC32GJDDQ* *Advanced information. Subject to change without notice. Table 7: Capacitor and Resistance Specifications Parameter Symbol Min Max Typ Units Notes Pull-up resistance: CMD R_CMD 4.7 50 10 kΩ 1 Pull-up resistance: DAT[7:0] R_DAT 10 50 50 kΩ 1 Pull-up resistance: RST_n R_RST_n 4.7 50 50 kΩ 2 45 55 50 Ω 3 SR_CLK 0 47 22 Ω C1 2.2 4.7 2.2 C2 0.1 0.22 0.1 C3 2.2 4.7 2.2 C4 0.1 0.22 0.1 C3 2.2 4.7 4.7 C4 0.1 0.22 0.22 C5 1 4.7 1 C6 0.1 0.1 0.1 CLK/CMD/DAT[7:0] impedance Serial resistance on CLK VCCQ capacitor VCC capacitor (≤8GB) VCC capacitor (>8GB) VDDIM capacitor (Creg) μF 4 μF 5 μF 5 μF 6 Notes: 1. Used to prevent bus floating. 2. If host does not use H/W RESET (RST_n), pull-up resistance is not needed on RST_n line (Extended_ CSD[162] = 00h). 3. Impedance match. 4. The coupling capacitor should be connected with VCCQ and VSSQ as closely as possible. 5. The coupling capacitor should be connected with VCC and VSS as closely as possible. 6. The coupling capacitor should be connected with VDDIM and VSS as closely as possible. MYXFC32GJDDQ Revision 1.0 - 11/26/2014 16 Form #: CSI-D-685 Document 013 MMC Controller & NAND Flash MYXFC32GJDDQ* *Advanced information. Subject to change without notice. 11 Ordering Information Table 8: Ordering Information MYXFC32GJDDQ Revision 1.0 - 11/26/2014 Part Number Device Grade MYXFC32GJDDQBG-ITRL Industrial 17 Form #: CSI-D-685 Document 013 MMC Controller & NAND Flash MYXFC32GJDDQ* *Advanced information. Subject to change without notice. Document Title MMC Controller and 32GB NAND Flash Revision History Revision # History Release Date Status 1.0 Initial release November 26, 2014 Preliminary MYXFC32GJDDQ Revision 1.0 - 11/26/2014 18 Form #: CSI-D-685 Document 013