MYX4DDR3L128M16JT 2Gb - 128M x 16 DDR3 SDRAM Advanced information. Subject to change without notice. Features • Tin-lead ball metallurgy • Write leveling • VDD = VDDQ = 1.35V (1.283-1.45V) • Multipurpose register • Backward-compatible to VCC = VCCQ = 1.5V ±0.075V • Output driver calibration • Differential bidirectional data strobe • 8n-bit prefetch architecture Options Code • Differential clock inputs (CK, CK#) • Configuration: 128M x 16 128M16 • 8 internal banks • Nominal and dynamic on-die termination (ODT) for data, strobe, and mask signals • Programmable CAS (READ) latency (CL) • Programmable posted CAS additive latency (AL) • Package: FBGA (Sn63 Pb37 solder) BG Footprint: 96-ball (8mm x 14mm) JT • Timing - cycle time 1.25ns @ CL = 11 (DDR3-1600) • Programmable CAS (WRITE) latency (CWL) • Fixed burst length (BL) of 8 and burst chop (BC) of 4 (via the mode register set [MRS]) • Operating temperature • Selectable BC4 or BL8 on-the-fly (OTF) • Self refresh mode • TC of 0°C to +95°C 64ms, 8192-cycle refresh at 0°C to +85°C -125 Commercial (0°C ≤ TC ≤ +95°C) None Industrial (-40°C ≤ TC ≤ +95°C) IT • Part Marking: Label (L), Dot (D) 32ms at +85°C to +95°C • Automatic self refresh (ASR) Table 1: Key Timing Parameters Speed Grade Data Rate (MT/s) Target tRCD-tRP-CL -125* 1600 11-11-11 tRCD (ns) tRP (ns) CL (ns) 13.75 Note: Backward compatible to 1066, CL=7 (-18) and 1333, CL=9 (-15) Micron Part. No. MT41K128M16JT April 15, 2015 • Revision 2.0 Micross US (Americas) 407.298.7100 • Micross UK (EMEA & ROW) +44 (0) 1603 788967 • [email protected] • www.micross.com Form #: CSI-D-686 Document 009 MYX4DDR3L128M16JT • 2Gb -2Gb: 128M 16DDR3L DDR3 SDRAM x4, x8,xx16 SDRAM Ball Assignments and Descriptions Advanced information. Subject to change without notice. Figure 2: 96-Ball FBGA – x16 Ball Assignments (Top View) Figure 1: 96-Ball FBGA Ball Assignments (Top View), JT A B 1 2 3 V DDQ DQ13 V SSQ 4 5 6 7 8 9 DQ15 DQ12 V DDQ V SS V DD V SS UDQS# DQ14 V SSQ V DDQ DQ11 DQ9 UDQS DQ10 V DDQ V SSQ V DDQ UDM DQ8 V SSQ V DD V SS V SSQ DQ0 LDM V SSQ V DDQ V DDQ DQ2 LDQS DQ1 DQ3 V SSQ V SSQ DQ6 LDQS# V DD V SS V SSQ V REFDQ V DDQ DQ4 DQ7 DQ5 V DDQ NC V SS RAS# CK V SS NC ODT V DD CAS# CK# V DD CKE NC CS# WE# A10/AP ZQ NC V SS BA0 BA2 NC V REFCA V SS A12/BC# BA1 V DD A1 A4 V SS A11 A6 V DD NC A8 V SS C D E F G H J K L M N 1Gb: x4, x8, x16 DDR3 SDRAM Package Dimensions Figure 13: 96-Ball FBGA – x16 (JT) V DD A3 V SS A5 V DD A7 A0 P 0.155 A2 R A9 T V SS RESET# 1.8 CTR Nonconductive overmold A13 1. Ball descriptions listed in Table 4 (page 7) are listed as “x16.” Notes: 96X Ø0.45 Ball A1 ID 2. Aapply comma separates the configuration; a slash defines a selectable function. Dimensions Figure 2: Package Dimensions 96-Ball FBGA Package - x16 (JT) 9 to solder balls postreflow on Ø0.35 SMD ball pads. 8 7 3 2 Ball A1 ID 1 1Gb: x4, x8, x16 DDR3 SDRAM Package DimensionsA B C the right to change products or specifications without notice. Micron Technology, Inc. reserves © 2010 Micron Technology, Inc. All rights reserved. 4 PDF: 09005aef83ed2952 2Gb_DDR3L_SDRAM.pdf - Rev. J 4/13 EN Figure 13: 96-Ball FBGA – x16 (JT) D E 0.155 F 14 ±0.1 G H 12 CTR J 1.8 CTR Nonconductive overmold K L M N 96X Ø0.45 Dimensions apply to solder balls postreflow on Ø0.35 SMD ball pads. P Ball A1 ID 9 8 7 3 2 Notes: 1. All dimensions are in millimeters. 2. Solder ball material: Sn63/Pb37 3. Micron – MT41K128M16 April 15, 2015 • Revision 2.0 14 ±0.1 12 CTR 1 0.8 TYP Ball A1 ID R T A B 0.8 TYP C 6.4 CTR D 8 ±0.1 1.1 ±0.1 0.25 MIN E F G H J K L M Micross US (Americas) • 407.298.7100 Micross UK (EMEA & ROW) • +44 (0) 1603 788967 [email protected] www.micross.com Form #: CSI-D-686 Document 009