LTC4253 – 48V Hot Swap Controller with Sequencer DESCRIPTIO U FEATURES ■ ■ ■ ■ ■ ■ ■ ■ ■ The LTC®4253 negative voltage Hot SwapTM controller allows a board to be safely inserted and removed from a live backplane. Output current is controlled by three stages of current-limiting: a timed circuit breaker, active current limiting and a fast feedforward path that limits peak current under worst-case catastrophic fault conditions. The LTC4253 latches off after a circuit fault. Allows Safe Board Insertion and Removal from a Live – 48V Backplane Floating Topology Permits Very High Voltage Operation Programmable Analog Current Limit with Breaker Timer Ideal for Two Battery Feeds Fast Response Time Limits Peak Fault Current Latchoff After Fault Three Sequenced Power Good Outputs Programmable Soft-Start Current Limit Programmable Timer with Drain Voltage Accelerated Response Programmable Undervoltage/Overvoltage Protection Programmable undervoltage and overvoltage detectors disconnect the load whenever the input supply exceeds the desired operating range. The LTC4253’s supply input is shunt-regulated, allowing safe operation with very high supply voltages. A multifunction timer delays initial startup and controls the circuit breaker’s response time. The circuit breaker’s response time can be accelerated by sensing excessive MOSFET drain voltage, keeping the MOSFET within safe operating area (SOA). A programmable soft-start circuit controls MOSFET inrush current at start-up. U APPLICATIO S ■ ■ ■ ■ ■ ■ ■ Hot Board Insertion Electronic Circuit Breaker – 48V Distributed Power Systems Negative Power Supply Control Central Office Switching Programmable Current Limiting Circuit High Availability Servers Disk Arrays Three power good outputs are sequenced by a programmable timer to enable external power modules at start-up or disable them if the circuit breaker trips. The LTC4253 is available in 16-pin SSOP. , LTC and LT are registered trademarks of Linear Technology Corporation. Hot Swap is a trademark of Linear Technology Corporation. U ■ TYPICAL APPLICATIO – 48V/2.5A Hot Swap Controller – 48V RTN (LONG PIN) RIN 2.8k 16k(1/4W)/6 C2 100µF VIN R3 5.6k CIN 1µF R4 5.6k + C3 0.1µF R5 5.6k POWER MODULE 1 POWER MODULE 2 EN – 48V RTN (SHORT PIN) EN EN 4 VIN R1 402k 1% 5 RESET OV PWRGD1 UV PWRGD2 RESET PWRGD3 C1 10nF CSS 68nF EN3 EN2 6 14 B3100* – 48V A (LONG PINS) – 48V B B3100* † † † LTC4253 11 12 R2 32.4k 1% POWER MODULE 3 CSQ 0.1µF 13 SS DRAIN SQTIMER GATE TIMER SENSE 3 2 15 EN3 EN2 1 10 8 VIN RD 1M 9 7 VEE CT 0.33µF POWER MODULE 2 OUTPUT 16 CC 18nF RC 10Ω Q1 IRF530S VIN RS 0.02Ω † R6 POWER MODULE 1 OUTPUT R7 † *DIODES, INC. †MOC207 4253 TA01 4253f 1 LTC4253 U W W W ABSOLUTE AXI U RATI GS U W U PACKAGE/ORDER I FOR ATIO (Note 1), All voltages referred to VEE Current into VIN (100µs Pulse) ........................... 100mA Input/Output (Except SENSE and DRAIN) Voltage ...................................– 0.3V to 16V SENSE Voltage ..........................................– 0.6V to 16V Current Out of SENSE Pin (20µs Pulse) ............ – 200mA VIN, DRAIN Pin Minimum Voltage ........................ – 0.3V Current into DRAIN Pin (100µs Pulse) ................. 20mA Maximum Junction Temperature .......................... 125°C Operating Temperature Range LTC4253C ............................................... 0°C to 70°C LTC4253I ............................................ – 40°C to 85°C Storage Temperature Range ................. – 65°C to 150°C Lead Temperature (Soldering, 10 sec).................. 300°C ORDER PART NUMBER TOP VIEW EN2 1 16 PWRGD3 PWRGD2 2 15 EN3 PWRGD1 3 14 SQTIMER VIN 4 13 TIMER RESET 5 12 UV SS 6 11 OV SENSE 7 10 DRAIN VEE 8 9 LTC4253CGN LTC4253IGN GN PART MARKING GATE 4253 4253I GN PACKAGE 16-LEAD PLASTIC SSOP TJMAX = 125°C, θJA = 130°C/W Consult LTC Marketing for parts specified with wider operating temperature ranges. ELECTRICAL CHARACTERISTICS The ● denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Note 2) SYMBOL PARAMETER CONDITIONS VZ VIN to VEE Zener Voltage IIN = 2mA RZ VIN to VEE Zener Dynamic Impedance IIN = (2mA Thru 30mA) IIN VIN Supply Current UV/OV = 4V, VIN = (VZ – 0.3V) ● 0.8 2 mA VLKO VIN Undervoltage Lockout Coming Out of UVLO (rising VIN) ● 9.2 12 V VLKH VIN Undervoltage Lockout Hysteresis VIH TTL Input High Voltage ● VIL TTL Input Low Voltage ● VHYST TTL Input Buffer Hysterisis ILEAK TTL Input Leakage Current Input = 0V ● ±0.1 ±10 IRESET RESET Input Current VEE ≤ VRESET ≤ VIN ● ±0.1 ±10 µA IEN EN2, EN3 Input Current VEN = 4V VEN = 0V ● ● 120 ±0.1 180 ±10 µA µA VSS SS Voltage After End of SS Timing Cycle 2.2 V ISS SS Pin Current UV = OV = 4V, VSENSE = VEE, VSS = 0V (SOURCING) UV= OV = 0V, VSENSE = VEE, VSS = 2V (SINKING) 22 28 µA mA RSS SS Output Impedance VCB Circuit Breaker Current Limit Voltage VCB = (VSENSE – VEE) ● 40 50 60 mV VACL Analog Current Limit Voltage VACL = (VSENSE – VEE) ● 80 100 120 mV VFCL Fast Current Limit Voltage VFCL = (VSENSE – VEE) ● 150 200 300 mV VOS Analog Current Limit Offset Voltage VACL + VOS VSS Ratio (VACL + VOS) to SS Voltage ● MIN TYP MAX 12 13 14.5 UNITS V Ω 5 1 V 2 V 0.8 600 V mV 100 µA kΩ 10 mV 0.05 V/V 4253f 2 LTC4253 ELECTRICAL CHARACTERISTICS The ● denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Note 2) SYMBOL PARAMETER CONDITIONS IGATE GATE Pin Output Current UV = OV = 4V, VSENSE = VEE, VGATE = 0V (Sourcing) ● MIN TYP MAX 30 50 70 UNITS µA UV = OV = 4V, VSENSE – VEE = 0.15V, VGATE = 3V (Sinking) 17 mA UV = OV = 4V, VSENSE – VEE = 0.3V, VGATE = 1V (Sinking) 190 mA VGATE External MOSFET Gate Drive VGATE – VEE, IIN = 2mA VGATEL Gate Low Threshold (Before Gate Ramp Up) 0.5 V VGATEH Gate High Threshold VGATEH = VIN – VGATE, For PWRGD1, PWRGD2, PWRGD3 Status 2.8 V VUVHI UV Pin Threshold HIGH ● 3.075 3.225 3.375 V VUVLO UV Pin Threshold LOW ● 2.775 2.925 3.075 V VUVHST UV Pin Hysteresis VOVHI OV Pin Threshold HIGH ● 5.85 6.15 6.45 V VOVLO OV Pin Threshold LOW ● 5.55 5.85 6.15 V VOVHST OV Pin Hysteresis 0.3 V ISENSE SENSE Pin Input Current UV = 0V = 4V, VSENSE = 50mV ● – 30 –15 µA IINP UV,OV Pin Input Current UV = OV = 4V ● VTMRH TIMER Pin Voltage High Threshold 4 V VTMRL TIMER Pin Voltage Low Threshold 1 V ITMR TIMER Pin Current 5 µA Timer Off (Initial Cycle, Sinking), VTMR = 2V 28 mA Timer On (Circuit Breaker, Sourcing, IDRN = 0µA), VTMR = 2V 200 µA Timer On (Circuit Breaker, Sourcing, IDRN = 50µA), VTMR = 2V 600 µA Timer Off (Circuit Breaker, Sinking), VTMR = 2V 5 µA Timer On (Circuit Breaker with IDRN = 50µA) 8 µA/µA ● 10 12 VZ 0.3 ±0.1 Timer On (Initial Cycle/Latchoff, Sourcing), VTMR = 2V V V ±10 µA ITMRACC IDRN (ITMR at IDRN = 50µA – ITMR at IDRN = 0µA) 50µA VSQTMRH SQTIMER Pin Voltage High Threshold 4 V VSQTMRL SQTIMER Pin Voltage Low Threshold 0.33 V ISQTMR SQTIMER Pin Current SQTIMER On (Power Good Sequence, Sourcing), VSQTMR = 2V 5 µA SQTIMER On (Power Good Sequence, Sinking), VSQTMR = 2V 28 µA V VDRNL DRAIN Pin Voltage Low Threshold For PWRGD1, PWRGD2, PWRGD3 Status 2.385 IDRNL DRAIN Leakage Current VDRAIN = 5V ±0.1 VDRNCL DRAIN Pin Clamp Voltage IDRN = 50µA VPGL PWRGD1, PWRGD2, PWRGD3 Output Low Voltage IPG = 1.6mA IPG = 5mA ● ● IPGH PWRGD1, PWRGD2, PWRGD3 Output High Current VPG = 0V ● ±1 7 30 µA V 0.25 0.4 1.2 V V 50 70 µA 4253f 3 LTC4253 ELECTRICAL CHARACTERISTICS The ● denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Note 2) SYMBOL PARAMETER CONDITIONS tSQ SQTIMER Default Ramp Period SQTIMER Pin Floating, VSQTMR Ramps from 0.5V to 3.5V 250 µs tSS SS Default Ramp Period SS Pin Floating, VSS Ramps from 0.2V to 2V 250 µs tPLLUG UV Low to GATE Low 0.4 µs tPHLOG OV High to GATE Low 0.4 µs Note 1: Absolute Maximum Ratings are those values beyond which the life of a device may be impaired. MIN TYP MAX UNITS Note 2: All currents into device pins are positive; all currents out of device pins are negative. All voltages are referenced to VEE unless otherwise specified. U W TYPICAL PERFOR A CE CHARACTERISTICS rZ vs Temperature VZ vs Temperature 10 14.5 IIN = 2mA 14.0 8 100 7 13.5 VZ (V) rZ (Ω) 1000 IIN = 2mA IIN (mA) 9 IIN vs VIN 6 13.0 5 4 TA = –40°C TA = 85°C TA = 25°C TA = 125°C 10 1 12.5 3 2 –55 –35 –15 12.0 –55 –35 –15 5 25 45 65 85 105 125 TEMPERATURE (°C) 4253 G01 1000 VIN = VZ – 0.3V 11.0 1.8 10.5 1.6 VLKH (V) VLKO (V) IIN (µA) 9.0 8.5 8.0 7.5 4253 G04 7.0 –55 –35 –15 0.8 0.4 600 5 25 45 65 85 105 125 TEMPERATURE (°C) 1.0 0.6 650 500 –55 –35 –15 20 1.2 9.5 550 15 1.4 10.0 850 700 10 VIN (V) Undervoltage Lockout Hysterisis VLKH vs Temperature 900 750 5 4253 G03 Undervoltage Lockout VLKO vs Temperature 800 0 4253 G02 IIN vs Temperature 950 0.1 5 25 45 65 85 105 125 TEMPERATURE (°C) 0.2 5 25 45 65 85 105 125 TEMPERATURE (°C) 4253 G05 0 –55 –35 –15 5 25 45 65 85 105 125 TEMPERATURE (°C) 4253 G06 4253f 4 LTC4253 U W TYPICAL PERFOR A CE CHARACTERISTICS VIH vs Temperature VIL vs Temperature 4.0 VHYST vs Temperature 2.0 IIN = 2mA 3.5 1.8 1.0 IIN = 2mA 0.9 1.6 0.8 1.4 0.7 1.2 0.6 IIN = 2mA VIL (V) VIH (V) 2.5 2.0 VHYST (V) 3.0 1.0 0.8 1.5 0.5 0.4 0.6 0.3 0.4 0.2 0.2 0.1 1.0 0.5 0 –55 –35 –15 0 –55 –35 –15 5 25 45 65 85 105 125 TEMPERATURE (°C) 4253 G07 4253 G09 Circuit Breaker Current Limit Voltage VCB vs Temperature IEN (VEN = 4V) vs Temperature 150 IIN = 2mA TA = 25°C 145 140 IEN (µA) 120 100 80 60 55 IIN = 2mA VEN = 4V 54 140 53 135 52 130 51 VCB (mV) 180 160 125 120 50 49 115 48 40 110 47 20 105 46 0 0 2 4 6 8 10 VEN (V) 12 14 5 25 45 65 85 105 125 TEMPERATURE (°C) 4253 G08 IEN vs VEN IEN (µA) 0 –55 –35 –15 5 25 45 65 85 105 125 TEMPERATURE (°C) 100 –55 –35 –15 16 4253 G10 45 –55 –35 –15 5 25 45 65 85 105 125 TEMPERATURE (°C) 5 25 45 65 85 105 125 TEMPERATURE (°C) 4253 G11 Analog Current Limit Voltage VACL vs Temperature 4253 G12 Fast Current Limit Voltage VFCL vs Temperature VSS vs Temperature 150 300 2.40 140 280 2.35 130 260 120 240 110 220 100 90 2.25 VSS (V) VFCL (mV) VACL (mV) 2.30 200 180 80 160 70 140 60 120 2.20 2.15 2.10 50 –55 –35 –15 5 25 45 65 85 105 125 TEMPERATURE (°C) 4253 G13 100 –55 –35 –15 2.05 5 25 45 65 85 105 125 TEMPERATURE (°C) 4253 G14 2.00 –55 –35 –15 5 25 45 65 85 105 125 TEMPERATURE (°C) 4253 G15 4253f 5 LTC4253 U W TYPICAL PERFOR A CE CHARACTERISTICS ISS (Sinking) vs Temperature RSS vs Temperature 50 UV/OV = 0V VSENSE = VEE VSS = 2V IIN = 2mA 45 40 120 11.0 115 10.8 10.6 110 10.4 25 20 105 VOS (mV) 30 RSS (kΩ) ISS (mA) 35 VOS vs Temperature 100 10.2 10.0 95 15 9.6 90 10 9.4 5 85 0 –55 –35 –15 80 –55 –35 –15 5 25 45 65 85 105 125 TEMPERATURE (°C) 9.2 0.056 56 0.054 54 0.052 52 30 UV/OV = 4V TIMER = 0V VSENSE = VEE VGATE = 0V 20 48 46 0.044 44 0.042 42 5 40 –55 –35 –15 VGATEL vs Temperature 14.5 UV/OV = 4V TIMER = 0V VSENSE – VEE = 0.3V VGATE = 1V 14.0 13.5 1.0 UV/OV = 4V TIMER = 0V VSENSE = VEE IIN = 2mA 0.9 0.8 0.7 VGATE (V) 200 150 VGATEL (V) 13.0 250 12.5 12.0 11.5 100 50 5 25 45 65 85 105 125 TEMPERATURE (°C) 4253 G22 5 25 45 65 85 105 125 TEMPERATURE (°C) 4253 G21 VGATE vs Temperature 400 0 –55 –35 –15 0 –55 –35 –15 5 25 45 65 85 105 125 TEMPERATURE (°C) 4253 G20 IGATE (FCL, Sink) vs Temperature 300 15 10 4253 G19 350 UV/OV = 4V TIMER = 0V VSENSE – VEE = 0.15V VGATE = 3V 25 50 0.046 5 25 45 65 85 105 125 TEMPERATURE (°C) IGATE (ACL, Sink) vs Temperature IGATE (mA) 58 IGATE (µA) (VACL + VOS)/VSS (V/V) 60 0.058 0.040 –55 –35 –15 4253 G18 IGATE (Source) vs Temperature 0.060 0.048 5 25 45 65 85 105 125 TEMPERATURE (°C) 4253 G17 (VACL + VOS) / VSS vs Temperature 0.050 9.0 –55 –35 –15 5 25 45 65 85 105 125 TEMPERATURE (°C) 4253 G16 IGATE (mA) 9.8 0.6 0.5 0.4 0.3 11.0 0.2 10.5 0.1 10.0 –55 –35 –15 UV/OV = 4V TIMER = 0V GATE THRESHOLD BEFORE RAMP UP 5 25 45 65 85 105 125 TEMPERATURE (°C) 4253 G23 0 –55 –35 –15 5 25 45 65 85 105 125 TEMPERATURE (°C) 4253 G24 4253f 6 LTC4253 U W TYPICAL PERFOR A CE CHARACTERISTICS VGATEH vs Temperature UV Threshold vs Temperature 3.6 6.45 3.375 UV/OV = 4V VGATEH = VIN – VGATE IIN = 2mA 6.35 3.275 3.0 2.8 2.6 3.175 3.075 2.975 VUVL 2.4 2.0 –55 –35 –15 5 25 45 65 85 105 125 TEMPERATURE (°C) 2.775 –55 –35 –15 TIMER Threshold vs Temperature 5.0 UV/OV = 4V TIMER = 0V VSENSE – VEE = 50mV VGATE = HIGH 4.5 ISENSE (µA) ISENSE (mA) –15 –20 UV/OV = 4V TIMER = 0V GATE = HIGH TA = 25°C –0.5 0 0.5 VSENSE – VEE (V) 1 1.5 3.0 2.5 2.0 1.5 VTMRL 0 –55 –35 –15 5 25 45 65 85 105 125 TEMPERATURE (°C) 5 25 45 65 85 105 125 TEMPERATURE (°C) 4253 G29 4253 G30 ITMR (Initial Cycle, Sinking) vs Temperature ITMR (Circuit Breaker, Sourcing) vs Temperature 50 10 IIN = 2mA VTMR = 2V 45 40 240 IIN = 2mA VTMR = 2V 230 IIN = 2mA IDRN = 0µA 35 6 30 5 4 ITMR (µA) 220 7 ITMR (mA) ITMR (µA) 3.5 0.5 –30 –55 –35 –15 ITMR (Initial Cycle, Sourcing) vs Temperature 25 20 3 15 2 10 1 5 0 –55 –35 –15 VTMRH 1.0 –25 4253 G28 8 IIN = 2mA 4.0 –10 –1 5 25 45 65 85 105 125 TEMPERATURE (°C) 4253 G27 TIMER THRESHOLD (V) –5 0.1 9 5.55 –55 –35 –15 5 25 45 65 85 105 125 TEMPERATURE (°C) 0 10 VOVH 5.85 ISENSE vs Temperature 0.01 1000 –1.5 5.95 4253 G26 ISENSE vs ( VSENSE - VEE ) 100 6.05 5.65 4253 G25 1 VOVH 6.15 5.75 2.875 2.2 IIN = 2mA 6.25 VUVH UV THRESHOLD (V) 3.2 IIN = 2mA OV THRESHOLD (V) 3.4 VGATEH (V) OV Threshold vs Temperature 210 200 190 180 5 25 45 65 85 105 125 TEMPERATURE (°C) 4253 G31 0 –55 –35 –15 170 5 25 45 65 85 105 125 TEMPERATURE (°C) 4253 G32 160 –55 –35 –15 5 25 45 65 85 105 125 TEMPERATURE (°C) 4253 G33 4253f 7 LTC4253 U W TYPICAL PERFOR A CE CHARACTERISTICS ITMR (Circuit Breaker, Sinking) vs Temperature ITMR (Circuit Breaker, IDRN = 50µA, Sourcing) vs Temperature 10 675 8 7 IIN = 2mA TA = 25°C IIN = 2mA IDRN = 50µA 650 6 ITMR (µA) ITMR (µA) 10 700 IIN = 2mA 5 4 ITMR (mA) 9 ITMR vs IDRN 625 1 600 3 2 575 1 0 –55 –35 –15 550 –55 –35 –15 5 25 45 65 85 105 125 TEMPERATURE (°C) 4253 G34 4.0 8.4 3.5 7.8 1.0 7.2 0.5 4.8 4.2 4.0 –55 –35 –15 5 25 45 65 85 105 125 TEMPERATURE (°C) 5 25 45 65 85 105 125 TEMPERATURE (°C) 4253 G38 4253 G39 VDRNL vs Temperature 50 VDRNCL vs Temperature 2.60 IIN = 2mA VSQTMR = 2V 2.55 8.0 IIN = 2mA 7.8 7.6 IIN = 2mA IDRN = 50µA 2.50 35 7.4 25 20 2.45 VDRNCL (V) 30 VDRNL (V) ISQTMR (mA) 5.0 4.4 VSQTMRL 0 –55 –35 –15 ISQTMR (Power Good Sequence, Sinking) vs Temperature 40 5.2 4.6 4253 G37 45 IIN = 2mA VSQTMR = 2V 5.4 2.0 7.4 5 25 45 65 85 105 125 TEMPERATURE (°C) 5.6 2.5 1.5 7.0 –55 –35 –15 5.8 VSQTMRH 3.0 7.6 10 6.0 IIN = 2mA ISQTMR (µA) 8.6 VSQTMR (V) ∆ITMRACC/∆IDRN (mA/mA) 4.5 1 ISQTMR (Power Good Sequence, Sourcing) vs Temperature 5.0 IIN = 2mA 8.0 0.1 IDRN (mA) 4253 G36 SQTIMER Threshold vs Temperature 9.0 8.2 0.01 4253 G35 ∆ITMRACC/∆IDRN vs Temperature 8.8 0.1 0.001 5 25 45 65 85 105 125 TEMPERATURE (°C) 2.40 2.35 15 7.2 7.0 6.8 6.6 2.30 10 6.4 5 2.25 0 –55 –35 –15 2.20 –55 –35 –15 5 25 45 65 85 105 125 TEMPERATURE (°C) 4253 G40 6.2 5 25 45 65 85 105 125 TEMPERATURE (°C) 4253 G41 6.0 –55 –35 –15 5 25 45 65 85 105 125 TEMPERATURE (°C) 4253 G42 4253f 8 LTC4253 U W TYPICAL PERFOR A CE CHARACTERISTICS IPGH vs Temperature VPGL vs Temperature IDRN vs VDRAIN 100 3.0 60 IIN = 2mA IIN = 2mA 10 58 2.5 56 IPG = 10mA 1 54 TA = 85°C 0.01 TA = 125°C 1.5 IPG = 5mA 1.0 0.001 0.0001 2 4 6 8 10 VDRAIN (V) 12 14 0 –55 –35 –15 16 tPLLUG and tPHLOG vs Temperature 500 IIN = 2mA SS PIN FLOATING VSS RAMPS FROM 0.2V TO 2V 450 0.6 IIN = 2mA VSQTMR RAMPS FROM 0.5V TO 3.5V IIN = 2mA 0.5 400 260 300 240 200 150 220 100 210 50 4253 G46 0.4 250 230 5 25 45 65 85 105 125 TEMPERATURE (°C) tPLLUG DELAY (µs) 350 tSQ (µs) 270 250 5 25 45 65 85 105 125 TEMPERATURE (°C) 4253 G45 tSQ vs Temperature 300 tSS (µs) 40 –55 –35 –15 4253 G44 tSS vs Temperature 200 –55 –35 –15 48 42 5 25 45 65 85 105 125 TEMPERATURE (°C) 4253 G43 280 50 44 IPG = 1.6mA TA = –40°C 0 52 46 0.5 TA = 25°C 0.00001 290 VPGH (µA) VPGL (V) IDRN (mA) 2.0 0.1 IIN = 2mA VPWRGD = 0V 0 –55 –35 –15 tPLLOG 0.3 0.2 0.1 5 25 45 65 85 105 125 TEMPERATURE (°C) 4253 G47 0 –55 –35 –15 5 25 45 65 85 105 125 TEMPERATURE (°C) 4253 G48 4253f 9 LTC4253 U U U PI FU CTIO S EN2 (Pin 1): Power Good Status Output Two Enable. This is a TTL compatible input that is used to control PWRGD2 and PWRGD3 outputs. When EN2 is driven low, both PWRGD2 and PWRGD3 will go high. When EN2 is driven high, PWRGD2 will go low provided PWRGD1 has been active for more than one power good sequence delay (tSQT) provided by the sequencing timer. EN2 can be used to control the power good sequence. This pin is internally pulled low by a 120µA current source. PWRGD2 (Pin 2): Power Good Status Output Two. Power good sequence starts with PWRGD1 latching active low. PWRGD2 will latch active low after EN2 goes high and after one power good sequence delay tSQT provided by the sequencing timer from the time PWRGD1 goes low, whichever comes later. PWRGD2 is reset by PWRGD1 going high or EN2 going low. This pin is internally pulled high by a 50µA current source. PWRGD1 (Pin 3): Power Good Status Output One. At start-up, PWRGD1 latches active low and starts the power good sequence when the DRAIN pin is below 2.385V and GATE is within 2.8V of VIN. PWRGD1 status is reset by UV, VIN (UVLO), RESET going high or circuit breaker fault time-out. This pin is internally pulled high by a 50µA current source. VIN (Pin 4): Positive Supply Input. Connect this pin to the positive side of the supply through a dropping resistor. A shunt regulator clamps VIN at 13V above VEE. An internal undervoltage lockout (UVLO) circuit holds GATE low until the VIN pin is greater than VLKO (9.2V), overriding UV and OV. If UV is high, OV is low and VIN comes out of UVLO, TIMER starts an initial timing cycle before initiating GATE ramp up. If VIN drops below approximately 8.2V, GATE pulls low immediately. RESET (Pin 5): Circuit Breaker Reset Pin. This is an asynchronous TTL compatible input. RESET going high will pull GATE, SS, TIMER, SQTIMER low and the PWRGD outputs high. The RESET pulse must be wide enough to discharge any voltage on the TIMER pin below VTMRL. After the reset of a latched fault, the chip waits for the interlock conditions before recovering as described in Interlock Conditions in the Operation section. SS (Pin 6): Soft-Start Pin. This pin is used to ramp inrush current during start up, thereby effecting control over di/dt. A 20X attenuated version of the SS pin voltage is presented to the current limit amplifier. This attenuated voltage limits the MOSFET’s drain current through the sense resistor during the soft-start current limiting. At the beginning of the start-up cycle, the SS capacitor (CSS) is ramped by a 22µA current source. The GATE pin is held low until SS exceeds 20 • VOS = 0.2V. SS is internally shunted by 100kΩ RSS which limits the SS pin voltage to 2.2V. This corresponds to an analog current limit SENSE voltage of 100mV. If the SS capacitor is omitted, the SS pin ramps from 0V to 2.2V in about 300µs. The SS pin is pulled low under any of the following conditions: UVLO at VIN, UV, OV, during the initial timing cycle, a circuit breaker fault time-out or the RESET pin going high. SENSE (Pin 7): Circuit Breaker/Current Limit Sense Pin. Load current is monitored by a sense resistor RS connected between SENSE and VEE, and controlled in three steps. If SENSE exceeds VCB (50mV), the circuit breaker comparator activates a (200µA␣ +␣ 8␣ •␣ IDRN) TIMER pull-up current. If SENSE exceeds VACL (100mV), the analog current-limit amplifier pulls GATE down to regulate the MOSFET current at VACL/RS. In the event of a catastrophic short-circuit, SENSE may overshoot 100mV. If SENSE reaches VFCL (200mV), the fast current-limit comparator pulls GATE low with a strong pull-down. To disable the circuit breaker and current limit functions, connect SENSE to VEE. VEE (Pin 8): Negative Supply Voltage Input. Connect this pin to the negative side of the power supply. GATE (Pin 9): N-channel MOSFET Gate Drive Output. This pin is pulled high by a 50µA current source. GATE is pulled low by invalid conditions at VIN (UVLO), UV, OV, during the initial timing cycle, a circuit breaker fault time-out or the RESET pin going high. GATE is actively servoed to control 4253f 10 LTC4253 U U U PI FU CTIO S the fault current as measured at SENSE. Compensation capacitor, CC, at GATE stabilizes this loop. A comparator monitors GATE to ensure that it is low before allowing an initial timing cycle, GATE ramp up after an overvoltage event or restart after a current limit fault. During GATE start-up, a second comparator detects GATE within 2.8V of VIN before PWRGD1 can be set and power good sequencing starts. DRAIN (Pin 10): Drain Sense Input. Connecting an external resistor, RD between this pin and the MOSFET's drain (VOUT) allows voltage sensing below 6.15V and current feedback to TIMER. A comparator detects if DRAIN is below 2.385V and together with the GATE high comparator, sets the PWRGD1 flag. If VOUT is above VDRNCL, the DRAIN pin is clamped at approximately VDRNCL. RD current is internally multiplied by 8 and added to TIMER's 200µA during a circuit breaker fault cycle. This reduces the fault time and MOSFET heating. OV (Pin 11): Over-Voltage Input. The active high threshold at the OV pin is set at 6.15V with 0.3V hysteresis. If OV > 6.15V, GATE pulls low. When OV returns below 5.85V, GATE start-up begins without an initial timing cycle. If OV occurs in the middle of an initial timing cycle, the initial timing cycle is restarted after OV goes away. OV does not reset the latched fault or PWRGD1 flag. The internal UVLO at VIN always overrides OV. A 1nF to 10nF capacitor at OV prevents transients and switching noise from affecting the OV thresholds and prevents glitches at the GATE. UV (Pin 12): Under-Voltage Input. The active low threshold at the UV pin is set at 2.925V with 0.3V hysteresis. If UV < 2.925V, PWRGD1 pulls high, both GATE and TIMER pull low. If UV rises above 3.225V, this initiates an initial timing cycle followed by GATE start-up. The internal UVLO at VIN always overrides UV. A low at UV resets an internal fault latch. A 1nF to 10nF capacitor at UV prevents transients and switching noise from affecting the UV thresholds and prevents glitches at the GATE pin. TIMER (Pin 13): Timer Input. Timer is used to generate an initial timing delay at start-up, and to delay shutdown in the event of an output overload (circuit breaker fault). Timer starts an initial timing cycle when the following conditions are met: RESET is low, UV is high, OV is low, VIN clears UVLO, TIMER pin is low, GATE pin is lower than VGATEL, SS < 0.2V, and VSENSE-VEE < VCB. A pull-up current of 5µA then charges CT, generating a time delay. If CT charges to VTMRH (4V), the timing cycle terminates. TIMER quickly pulls low and GATE is activated. If SENSE exceeds 50mV while GATE is high, a circuit breaker cycle begins with a 200µA pull-up current charging CT. If DRAIN is approximately 7V during this cycle, the timer pull-up has an additional current of 8 • IDRN. If SENSE drops below 50mV before TIMER reaches 4V, a 5µA pulldown current slowly discharges the CT. In the event that CT eventually integrates up to the VTMRH (4V) threshold, the circuit breaker trips, GATE quickly pulls low and the PWRGD1 pulls high. TIMER latches high with a 5µA pullup source. This latched fault may be cleared by driving RESET high until TIMER is pulled low. Other ways of clearing the fault include pulling the VIN pin momentarily below (VLKO – VLKH), pulling TIMER low with an external device or pulling UV below 2.925V. SQTIMER (Pin 14): Sequencing Timer Input. The sequencing timer provides a delay tSQT for the power good sequencing. This delay is programmed by connecting an appropriate capacitor to this pin. If the SQTIMER capacitor is omitted, the SQTIMER pin ramps from 0V to 4V in about 300µs. EN3 (Pin 15): Power Good Status Output Three Enable. This is a TTL compatible input that is used to control the PWRGD3 output. When EN3 is driven low, PWRGD3 will go high. When EN3 is driven high, PWRGD3 will go low provided PWRGD2 has been active for for more than one power good sequence delay (tSQT). EN3 can be used to control the power good sequence. This pin is internally pulled low by a 120µA current source. PWRGD3 (Pin 16): Power Good Status Output Three. Power good sequence starts with PWRGD1 latching active low. PWRGD3 will latch active low after EN3 goes high and after one power good sequence delay tSQT provided by the sequencing timer from the time PWRGD2 goes low, whichever comes later. PWRGD3 is reset by PWRGD1 going high or EN3 going low. This pin is internally pulled high by a 50µA current source. 4253f 11 LTC4253 W BLOCK DIAGRA VIN 4 VIN VIN – 50µA 4V 5µA VEE PWRGD1 3 + 14 SQTIMER VEE EN2 1 VIN – 120µA 50µA VEE + PWRGD2 2 SQTIMER DELAY 0.33V VEE – VEE 10 DRAIN VIN EN3 15 + VIN 2.385V 8× 120µA 50µA 1× VEE 6.15V 1× PWRGD3 16 VIN SQTIMER DELAY 1× VEE 50µA 9 GATE VEE VIN 6.15V VEE – – OV 11 + + UV 12 – – VIN 2.925V + 5µA 4V – + – + LOGIC 2.8V 0.5V VIN 200µA + FCL + – + – TIMER 13 VEE – 5µA VEE 1V VIN 200mV + VEE + 22µA ACL – SS 6 10mV + – VEE 95k + RSS 7 SENSE CB 5k – VEE + – VEE 50mV VEE 8 4253 BD VEE 4253f 12 LTC4253 U OPERATIO Hot Circuit Insertion (see Figure 1). Both inrush control and short-circuit protection are provided by the MOSFET. When circuit boards are inserted into a live backplane, the supply bypass capacitors can draw huge transient currents from the power bus as they charge. The flow of current damages the connector pins and glitches the power bus, causing other boards in the system to reset. The LTC4253 is designed to turn on a circuit board supply in a controlled manner, allowing insertion or removal without glitches or connector damage. A detailed schematic is shown in Figure 2. – 48V and – 48RTN receive power through the longest connector pins and are the first to connect when the board is inserted. The GATE pin holds the MOSFET off during this time. UV/OV determines whether or not the MOSFET should be turned on based upon internal high accuracy thresholds and an external divider. UV/OV does double duty by also monitoring whether or not the connector is seated. The top of the divider detects – 48RTN by way of a short connector pin that is the last to mate during the insertion sequence. Initial Start-Up The LTC4253 resides on a removable circuit board and controls the path between the connector and load or power conversion circuitry with an external MOSFET switch PLUG-IN BOARD + –48RTN LTC4253 + CLOAD + ISOLATED DC/DC CONVERTER MODULE – –48V BACKPLANE LOW VOLTAGE CIRCUITRY – 4253 F01 Figure 1. Basic LTC4253 Hot Swap Topology LONG R1 402k 1% 4 CIN 1µF 13 CT 0.33µF 14 CSQ 0.1µF R2 32.4k 1% 1 VIN 11, 12 C1 10nF • • • RIN 10k 20k(1/4W)/2 SHORT CSS 68nF • • • –48RTN EN2 EN3 LTC4253 OV/UV PWRGD1 PWRGD2 TIMER PWRGD3 RESET SQTIMER 6 SS VEE + 15 DRAIN SENSE 8 2 16 5 • • • • • • • • • 10 GATE 7 CC 18nF 3 CLOAD 100µF TYP 9 RC 10Ω RD 1M LONG –48V RS 0.02Ω Q1 IRF530S 4253 F02 Figure 2. – 48V/2.5A Hot Swap Controller 4253f 13 LTC4253 U OPERATIO Interlock Conditions A start-up sequence commences once these “interlock” conditions are met: 1. The input voltage VIN exceeds 9.2V (UVLO). 2. The voltage at UV > 3.225V. 3. The voltage at OV < 5.85V. 4. The input voltage at RESET < 0.8V. 5. The (SENSE – VEE ) voltage < 50mV (VCB) 6. The voltage at SS is < 0.2V (20 • VOS) 7. The voltage on the TIMER capacitor ( CT ) is < 1V (VTMRL). 8. The voltage at GATE is < 0.5V (VGATEL) The first four conditions are continuously monitored and the latter four are checked prior to initial timing or GATE ramp-up. Upon exiting an OV condition, the TIMER pin voltage requirement is inhibited. Details are described in the Applications Information, Timing Waveforms section. TIMER begins the start-up sequence by sourcing 5µA into CT. If VIN, UV or OV falls out of range or RESET asserts, the start-up cycle stops and TIMER discharges CT to less than 1V, then waits until the aforementioned conditions are once again met. If CT successfully charges to 4V, TIMER pulls low and both SS and GATE pins are released. GATE sources 50µA (IGATE), charging the MOSFET gate and associated capacitance. The SS voltage ramp limits VSENSE to control the inrush current. PWRGD1 pulls active low when GATE is within 2.8V of VIN and DRAIN is lower than VDRNL. This sets off the power good sequence in which PWRGD2 and then PWRGD3 is subsequently pulled low after a delay, programmable through the SQTIMER capacitor CSQ or by external control inputs EN2 and EN3. In this way, external loads or power modules controlled by the three PWRGD signals are turned on in a controlled manner without overloading the power bus. Two modes of operation are possible during the time the MOSFET is first turned on, depending on the values of external components, MOSFET characteristics and nominal design current. One possibility is that the MOSFET will turn on gradually so that the inrush into the load capaci- tance remains a low value. The output will simply ramp to – 48V and the LTC4253 will fully enhance the MOSFET. A second possibility is that the load current exceeds the softstart current limit threshold of [VSS(t)/20 – VOS]/RS. In this case the LTC4253 will ramp the output by sourcing softstart limited current into the load capacitance. If the softstart voltage is below 1.2V, the circuit breaker TIMER is held low. Above 1.2V, TIMER ramps up. It is important to set the timer delay so that, regardless of which start-up mode is used, the TIMER ramp is less than one circuit breaker delay time. If this condition is not met, the LTC4253 may shut down after one circuit breaker delay time. Board Removal When the board is withdrawn from the card cage, the UV/OV divider is the first to lose connection. This shuts off the MOSFET and commutates the flow of current in the connector. When the power pins subsequently separate there is no arcing. Current Control Three levels of protection handle short-circuit and overload conditions. Load current is monitored by SENSE and resistor RS. There are three distinct thresholds at SENSE: 50mV for a timed circuit breaker function; 100mV for an analog current limit loop; and 200mV for a fast, feedforward comparator which limits peak current in the event of a catastrophic short-circuit. If, due to an output overload, the voltage drop across RS exceeds 50mV, TIMER sources 200µA into CT. CT eventually charges to a 4V threshold and the LTC4253 shuts off. If the overload goes away before CT reaches 4V and SENSE measures less than 50mV, CT slowly discharges (5µA). In this way the LTC4253’s circuit breaker function responds to low duty cycle overloads, and accounts for the fast heating and slow cooling characteristic of the MOSFET. Higher overloads are handled by an analog current limit loop. If the drop across RS reaches 100mV, the current limiting loop servos the MOSFET gate and maintains a constant output current of 100mV/RS. In current limit mode, VOUT (MOSFET drain-source voltage drop) typically rises and this increases MOSFET heating. If VOUT > VDRNCL (7V), connecting an external resistor, RD between VOUT 4253f 14 LTC4253 U OPERATIO and DRAIN allows the fault timing cycle to be shortened by accelerating the charging of the TIMER capacitor. The TIMER pull-up current is increased by 8 • IDRN. Note that because SENSE > 50mV, TIMER charges CT during this time, and the LTC4253 will eventually shut down. Low impedance failures on the load side of the LTC4253 coupled with 48V or more driving potential can produce current slew rates well in excess of 50A/µs. Under these conditions, overshoot is inevitable. A fast SENSE comparator with a threshold of 200mV detects overshoot and pulls GATE low much harder and hence much faster than the weaker current limit loop. The 100mV/RS current limit loop then takes over, and servos the current as previously described. As before, TIMER runs and shuts down LTC4253 when CT reaches 4V. If CT reaches 4V, the LTC4253 latches off with a 5µA pullup current source. The LTC4253 circuit breaker latch is U W U U APPLICATIO S I FOR ATIO reset by either pulling the RESET pin active high until TIMER goes low, pulling UV momentarily low, dropping the input voltage VIN below the internal UVLO threshold of 8.2V or pulsing TIMER momentarily low with a switch. Although short-circuits are the most obvious fault type, several operating conditions may invoke overcurrent protection. Noise spikes from the backplane or load, input steps caused by the connection of a second, higher voltage supply, transient currents caused by faults on adjacent circuit boards sharing the same power bus or the insertion of non-hot swappable products could cause higher than anticipated input current and temporary detection of an overcurrent condition. The action of TIMER and CT rejects these events allowing the LTC4253 to “ride out” temporary overloads and disturbances that could trip a simple current comparator and, in some cases, blow a fuse. (Refer to Block Diagram) SHUNT REGULATOR UV/OV COMPARATORS A fast responding regulator shunts the LTC4253 VIN pin. Power is derived from -48RTN by an external current limiting resistor. The shunt regulator clamps VIN to 13V (VZ). A 1µF decoupling capacitor at VIN filters supply transients and contributes a short delay at start-up. RIN should be chosen to accommodate both VIN supply current and the drive required for three optocouplers used by the PWRGD signals. Higher current through RIN results in higher dissipation for RIN and the LTC4253. An alternative is a separate NPN buffer driving the optocoupler as shown in Figure 3. Multiple 1/4W resistors can replace a single higher power RIN resistor. An UV hysteretic comparator detects undervoltage conditions at the UV pin, with the following thresholds: INTERNAL UNDERVOLTAGE LOCKOUT (UVLO) A hysteretic comparator, UVLO, monitors VIN for undervoltage. The thresholds are defined by VLKO and its hysteresis VLKH. When VIN rises above 9.2V (VLKO) the chip is enabled; below 8.2V (VLKO – VLKH) it is disabled and GATE is pulled low. The UVLO function at VIN should not be confused with the UV and OV pins. These are completely separate functions. UV low-to-high (VUVHI) = 3.225V UV high-to low (VUVLO) = 2.925V An OV hysteretic comparator detects overvoltage conditions at the OV pin, with the following thresholds: OV low-to-high (VOVHI) = 6.150V OV high-to-low (VOVLO) = 5.850V The UV and OV trip point ratio is designed to match the standard telecom operating range of 43V to 75V when connected together as in Figure 2. A divider (R1, R2) is used to scale the supply voltage. Using R1 = 402k and R2␣ =␣ 32.4k gives a typical operating range of 43.2V to 78.4V. The under and overvoltage shutdown thresholds are then 39.2V and 82.5V. One percent divider resistors are recommended to preserve threshold accuracy. 4253f 15 LTC4253 U U W U APPLICATIO S I FOR ATIO (Refer to Block Diagram) GND R4 22k RIN 10k 20k(1/4W)/2 Q2 FZT857 R5 2.2k CIN 1µF PUSH RESET CL 100µF R6 2.2k + POWER MODULE 1 R7 2.2k POWER MODULE 2 EN GND SHORT PIN EN EN 4 † † LTC4253 12 11 R2 14k 1% 5 UV PWRGD1 OV PWRGD2 RESET PWRGD3 C1 10nF CSS 68nF EN3 EN2 6 14 R3 32.4k 1% † VIN R1 432k 1% POWER MODULE 3 R10 47k CSQ 0.1µF 13 SS DRAIN SQTIMER GATE TIMER SENSE 3 2 15 EN3 EN2 1 10 VIN RD 1M 9 Q1 IRF530S 7 VEE RC 10Ω 8 CT 0.33µF POWER MODULE 2 OUTPUT 16 CC 18nF RS 0.02Ω VIN R8 POWER MODULE 1 OUTPUT R9 † † 4253 F03 †MOC207 –48V Figure 3. –48V/2.5A Application with Wider Operating Range The R1-R2 divider values shown set a standing current of slightly more than 100µA and define an impedance at UV/OV of 30kΩ. In most applications, 30kΩ impedance coupled with 300mV UV hysteresis makes the LTC4253 insensitive to noise. If more noise immunity is desired, add a 1nF to 10nF filter capacitor from UV/OV to VEE. The separate UV and OV pins can be used for wider operating range such as 35.5V to 80V range as shown in Figure 3. Other combinations are possible with different resistors arrangement. UV/OV OPERATION A low input to the UV comparator will reset the chip and pull the GATE and TIMER pins low. A low-to-high UV transition will initiate an initial timing sequence if the other interlock conditions are met. A high-to-low transition in the UV comparator immediately shuts down the LTC4253, pulls the MOSFET gate low and resets the three latched PWRGD signals high. An overvoltage condition is detected by the OV comparator and pulls GATE low, thereby shutting down the load, but it will not reset the circuit breaker TIMER and PWRGD flags. Returning from the overvoltage condition will re- start the GATE pin if all the interlock conditions except TIMER are met. Only during the initial timing cycle does OV condition have an effect of resetting TIMER. DRAIN Connecting an external resistor, RD, to this dual function DRAIN pin allows VOUT (MOSFET drain-source voltage drop) sensing without it being damaged by large voltage transients. Below 6.15V, negligible pin leakage allows a DRAIN low comparator to detect VOUT less than 2.385V (VDRNL). This, together with the GATE low comparator, sets the PWRGD flag. When VOUT > VDRNCL (7V), the DRAIN pin is clamped at about 7V and the current flowing in RD is given by: IDRN ≈ VOUT − VDRNCL RD (1) This current is scaled up 8 times during a circuit breaker fault before being added to the nominal 200µA. This accelerates the fault TIMER pull-up when the MOSFET’s drain-source voltage exceeds 7V and effectively shortens the MOSFET heating duration. 4253f 16 LTC4253 (Refer to Block Diagram) W U U TIMER The operation of the TIMER pin is somewhat complex as it handles several key functions. A capacitor CT is used at TIMER to provide timing for the LTC4253. Four different charging and discharging modes are available at TIMER: 1. 5µA slow charge; initial timing and shutdown cooling delay. 2. (200µA␣ +␣ 8␣ •␣ IDRN) fast charge; circuit breaker delay. 3. 5µA slow discharge; circuit breaker “cool-off” and shutdown cooling. 4. Low impedance switch; resets the TIMER capacitor after an initial timing delay, in UVLO, in UV and in OV during initial timing and when RESET is high. For initial timing delay, the 5µA pull-up is used. The low impedance switch is turned off and the 5µA current source is enabled when the interlock conditions are met. CT charges to 4V in a time period given by: 4V • C T t= 5µA (2) When CT reaches VTMRH ( 4V), the low impedance switch turns on and discharges CT. A GATE start-up cycle begins and both SS and GATE outputs are released. CIRCUIT BREAKER TIMER OPERATION If the SENSE pin detects more than 50mV drop across RS, the TIMER pin charges CT with (200µA␣ +␣ 8␣ •␣ IDRN). If CT charges to 4V, the GATE pin pulls low and the LTC4253 latches off. The LTC4253 remains latched off until the RESET pin is momentarily pulsed high, the UV pin is momentarily pulsed low, the TIMER pin is momentarily discharged low by an external switch or VIN dips below UVLO and is then restored. The circuit breaker timeout period is given by: t= 4V • C T 200µA + 8 • IDRN If VOUT < 6.15V, an internal PMOS isolates DRAIN pin leakage current and this makes IDRN = 0 in Equation (3). If VOUT is above 7V (VDRNCL) during the circuit breaker fault period, the charging of CT is accelerated by 8 • IDRN of Equation (1). Intermittent overloads may exceed the 50mV threshold at SENSE but, if their duration is sufficiently short, TIMER will not reach 4V and the LTC4253 will not shut the external MOSFET off. To handle this situation, the TIMER discharges CT slowly with a 5µA pull-down whenever the SENSE voltage is less than 50mV. Therefore any intermittent overload with VOUT < 6.15V and an aggregate duty cycle of 2.5% or more will eventually trip the circuit breaker and shut down the LTC4253. Figure 4 shows the circuit breaker response time in seconds normalized to 1µF. The asymmetric charging and discharging of CT is a fair gauge of MOSFET heating. The normalized circuit response time is estimated by: t 4 = C T (µF ) (200 + 8 • IDRN ) • D − 5 [ ] (4) 10 NORMALIZED RESPONSE TIME (s/µF) U APPLICATIO S I FOR ATIO 1 4 t = CT(µF) (200 + 8 • IDRN) • D – 5 0.1 0.01 0 20 40 60 80 FAULT DUTY CYCLE, D (%) 100 4253 F04 Figure 4. Circuit Breaker Response Time (3) 4253f 17 LTC4253 U W U U APPLICATIO S I FOR ATIO (Refer to Block Diagram) POWER GOOD SEQUENCING After the initial TIMER cycle, GATE ramps up to turn on the external MOSFET which in turn pulls DRAIN low. When GATE is within 2.8V of VIN and DRAIN is lower than VDRNL, the power good sequence starts with PWRGD1 pulling active low. This starts off a 5µA pull-up on the SQTIMER pin which ramps up until it reaches the 4V threshold then pulls low. When the SQTIMER pin floats, this delay tSQT is about 300µs. Connecting an external capacitor CSQ from SQTIMER to VEE modifies the delay to: tSQT 4V • C SQ = 5µA (5) PWRGD2 asserts when EN2 goes high and PWRGD1 has asserted for more than one tSQT. When PWRGD2 successfully pulls low, SQTIMER ramps up on another delay cycle. PWRGD3 asserts when EN2 and EN3 go high and PWRGD2 has asserted for more than one tSQT. All three PWRGD signals are reset in UVLO, in UV condition, if RESET is high or when CT charges up to 4V. In addition, PWRGD2 is reset by EN2 going low. PWRGD3 is reset by EN2 or EN3 going low. An overvoltage condition has no effect on the PWRGD flags. A 50µA current pulls each PWRGD pin high when reset. As power modules signal common are different from PWRGD, optoisolation is recommended. These three pins can sink an optodiode current. SOFT-START Soft-start is effective in limiting the inrush current during GATE start-up. Unduly long soft-start intervals can exceed the MOSFET’s SOA duration if powering-up into an active load. When the SS pin floats, an internal current source ramps SS from 0V to 2.2V in about 300µs. Connecting an external capacitor, CSS, from SS to ground modifies the ramp to approximate an RC response of: –t VSS (t) ≈ VSS 1 − e RSSC SS (6) An internal resistor divider (95k/5k) scales VSS(t) down by 20 times to give the analog current limit threshold: VACL (t) = VSS (t) • VOS 20 (7) This allows the inrush current to be limited to VACL(t)/RS. The offset voltage, VOS (10mV) ensures CSS is sufficiently discharged and the ACL amplifier is in current limit mode before GATE start-up. SS is discharged low during UVLO at VIN , UV, OV, during the initial timing cycle, a latched circuit breaker fault or the RESET pin going high. GATE GATE is pulled low to VEE under any of the following conditions: in UVLO, when RESET pulls high, in an undervoltage condition, in an overvoltage condition, during the initial timing cycle or a latched circuit breaker fault. When GATE turns on, a 50µA current source charges the MOSFET gate and any associated external capacitance. VIN limits the gate drive to no more than 14.5V. Gate-drain capacitance (CGD) feedthrough at the first abrupt application of power can cause a gate-source voltage sufficient to turn on the MOSFET. A unique circuit pulls GATE low with practically no usable voltage at VIN, and eliminates current spikes at insertion. A large external gate-source capacitor is thus unnecessary for the purpose of compensating CGD. Instead, a smaller value (≥10nF) capacitor CC is adequate. CC also provides compensation for the analog current limit loop. GATE has two comparators: the GATE low comparator looks for < 0.5V threshold prior to initial timing; the GATE high comparator looks for < 2.8V relative to VIN and, together with DRAIN low comparator, sets PWRGD1 output during GATE startup. SENSE The SENSE pin is monitored by the circuit breaker (CB) comparator, the analog current limit (ACL) amplifier, and the fast current limit (FCL) comparator. Each of these three measures the potential of SENSE relative to VEE. When SENSE exceeds 50mV, the CB comparator activates the 200µA TIMER pull-up. At 100mV the ACL amplifier servos the MOSFET current, and at 200mV the FCL comparator abruptly pulls GATE low in an attempt to bring the MOSFET current under control. If any of these conditions persists 4253f 18 LTC4253 U W U U APPLICATIO S I FOR ATIO (Refer to Block Diagram) long enough for TIMER to charge CT to 4V (see Equation␣ 3), the LTC4253 shuts down and pulls GATE low. If the SENSE pin encounters a voltage greater than 100mV, the ACL amplifier will servo GATE downwards in an attempt to control the MOSFET current. Since GATE overdrives the MOSFET in normal operation, the ACL amplifier needs time to discharge GATE to the threshold of the MOSFET. For a mild overload the ACL amplifier can control the MOSFET current, but in the event of a severe overload the current may overshoot. At SENSE = 200mV the FCL comparator takes over, quickly discharging the GATE pin to near VEE potential. FCL then releases, and the ACL amplifier takes over. All the while TIMER is running. The effect of FCL is to add a nonlinear response to the control loop in favor of reducing MOSFET current. Owing to inductive effects in the system, FCL typically overcorrects the current limit loop, and GATE undershoots. A zero in the loop (resistor RC in series with the gate capacitor) helps the ACL amplifier to recover. SHORT-CIRCUIT OPERATION Circuit behavior arising from a load side low impedance short is shown in Figure 5. Initially the current overshoots the analog current limit level of VSENSE␣ =␣ 200mV (trace 2) as the GATE pin works to bring VGS under control (trace 3). The overshoot glitches the backplane in the negative direction and when the current is reduced to 100mV/RS, the backplane responds by glitching in the positive direction. TIMER commences charging CT (trace 4) while the analog current limit loop maintains the fault current at 100mV/RS, which in this case is 5A (trace 2). Note that the backplane voltage (trace 1) sags under load. Timer pull-up is accelerated by VOUT. When CT reaches 4V, GATE turns off, the PWRGD signal pulls high, the load current drops to zero and the backplane rings up to over 100V. The positive peak is usually limited by avalanche breakdown in the MOSFET, and can be further limited by adding a zener diode (such as Diodes Inc. SMAT70A) across the input from – 48V to – 48RTN. A low impedance short on one card may influence the behavior of others sharing the same backplane. The initial glitch and backplane sag as seen in Figure 5 trace 1, can rob charge from output capacitors on the adjacent card. When the faulty card shuts down, current flows in to refresh the capacitors. If LTC4253s are used by the other cards, they respond by limiting the inrush current to a value of 100mV/RS. If CT is sized correctly, the capacitors will recharge long before CT times out. SUPPLY RING OWING TO CURRENT OVERSHOOT SUPPLY RING OWING TO MOSFET TURN-OFF –48RTN 0.5ms 50V SENSE 0.5ms 200mV GATE 0.5ms 10V TRACE 1 ONSET OF OUTPUT SHORT-CIRCUIT TRACE 2 FAST CURRENT LIMIT TRACE 3 ANALOG CURRENT LIMIT TIMER 0.5ms 5V CTIMER RAMP LATCH OFF TRACE 4 4253 F05 Figure 5. Output Short-Circuit Behavior of LTC4253 MOSFET SELECTION The external MOSFET switch must have adequate safe operating area (SOA) to handle short-circuit conditions until TIMER times out. These considerations take precedence over DC current ratings. A MOSFET with adequate SOA for a given application can always handle the required current but the opposite may not be true. Consult the manufacturer’s MOSFET datasheet for safe operating area and effective transient thermal impedance curves. MOSFET selection is a 3-step process by assuming the absense of soft-start capacitor. First, RS is calculated and then the time required to charge the load capacitance is determined. This timing, along with the maximum shortcircuit current and maximum input voltage, defines an operating point that is checked against the MOSFET’s SOA curve. To begin a design, first specify the required load current and Ioad capacitance, IL and CL. The circuit breaker current trip point (VCB/RS) should be set to accommodate the maximum load current. Note that maximum input current to a DC/DC converter is expected at VSUPPLY(MIN). RS is given by: 4253f 19 LTC4253 U W U U APPLICATIO S I FOR ATIO RS = VCB(MIN) IL(MAX) (Refer to Block Diagram) (8) where VCB(MIN) = 40mV represents the guaranteed minimum circuit breaker threshold. During the initial charging process, the LTC4253 may operate the MOSFET in current limit, forcing (VACL) between 80mV to 120mV across RS. The minimum inrush current is given by: IINRUSH(MIN)= 80mV RS (9) Maximum short-circuit current limit is calculated using the maximum VSENSE. This gives ISHORTCIRCUIT(MAX) = 120mV RS (10) The TIMER capacitor CT must be selected based on the slowest expected charging rate; otherwise TIMER might time out before the load capacitor is fully charged. A value for CT is calculated based on the maximum time it takes the load capacitor to charge. That time is given by: tCL(CHARGE) C • V C L • VSUPPLY(MAX) = = I IINRUSH(MIN) (11) The maximum current flowing in the DRAIN pin is given by: IDRN(MAX) = VSUPPLY(MAX) − VDRNCL RD (12) Approximating a linear charging rate, IDRN drops from IDRN(MAX) to zero, the IDRN component in Equation (3) can be approximated with 0.5 • IDRN(MAX). Rearranging the equation, TIMER capacitor CT is given by: CT = tCL(CHARGE) • (200µA + 4 • IDRN(MAX) ) 4V (13) Returning to Equation (3), the TIMER period is calculated and used in conjunction with V SUPPLY(MAX) and ISHORTCIRCUIT(MAX) to check the SOA curves of a prospective MOSFET. As a numerical design example, consider a 30W load, which requires 1A input current at 36V. If VSUPPLY(MAX) = 72V and CL = 100µA, RD = 1MΩ, Equation (8) gives RS␣ =␣ 40mΩ; Equation (13) gives CT = 441nF. To account for errors in RS, CT, TIMER current (200µA), TIMER threshold (4V), RD, DRAIN current multiplier and DRAIN voltage clamp (VDRNCL), the calculated value should be multiplied by 1.5, giving the nearest standard value of CT␣ =␣ 680nF. If a short-circuit occurs, a current of up to 120mV/40mΩ␣ =␣ 3A will flow in the MOSFET for 3.6ms as dictated by CT = 680nF in Equation (3). The MOSFET must be selected based on this criterion. The IRF530S can handle 100V and 3A for 10ms and is safe to use in this application. Computing the maximum soft-start capacitor value during soft-start to a load short is complicated by the nonlinear MOSFET’s SOA characteristics and the RSSCSS response. An overconservative but simple approach begins with the maximum circuit breaker current, given by: ICB(MAX) = 60mV RS (14) From the SOA curves of a prospective MOSFET, determine the time allowed, tSOA(MAX). CSS is given by: C SS = tSOA(MAX) 0.916 • RSS (15) In the above example, 60mV/40mΩ gives 1.5A. tSOA for the IRF530S is 40ms. From Equation (15), CSS = 437nF. Actual board evaluation showed that CSS = 100nF was appropriate. The ratio ( RSS • CSS ) to tCL(CHARGE) is a good gauge as large ratios may result in the time-out period expiring prematurely. This gauge is determined empirically with board level evaluation. SUMMARY OF DESIGN FLOW To summarize the design flow, consider the application shown in Figure 2. It was designed for 50W and CL␣ =␣ 100µF. 4253f 20 LTC4253 U W U U APPLICATIO S I FOR ATIO (Refer to Block Diagram) Calculate maximum load current: 50W/36V = 1.4A; allowing for 83% converter efficiency, IIN(MAX) = 1.7A. Calculate RS: from Equation (8) RS = 20mΩ. Calculate I SHORT-CIRCUIT(MAX) : from Equation (9) ISHORTCIRCUIT(MAX) = 6A. Select a MOSFET that can handle 6A at 72V: IRF530S. Calculate CT: from Equation (13) CT = 220nF. Select CT␣ =␣ 330nF, which gives the circuit breaker time-out period tMAX = 1.76ms. Consult MOSFET SOA curves: the IRF530S can handle 6A at 72V for 5ms, so it is safe to use in this application. Calculate CSS: using Equations (14) and (15) select CSS␣ =␣ 68nF. FREQUENCY COMPENSATION The LTC4253 typical frequency compensation network for the analog current limit loop is a series RC (10Ω) and CC connected from GATE to VEE. Figure 6 depicts the relationship between the compensation capacitor CC and the MOSFET’s CISS. The line in Figure 6 is used to select a starting value for CC based upon the MOSFET’s CISS specification. Optimized values for CC are shown for several popular MOSFETs. Differences in the optimized value of CC versus the starting value are small. Nevertheless, compensation values should be verified by board level short-circuit testing. As seen in Figure 5, at the onset of a short-circuit event, the input supply voltage can ring dramatically due to series inductance. If this voltage avalanches the MOSFET, current continues to flow through the MOSFET to the output. The analog current limit loop cannot control this current flow and therefore the loop undershoots. This effect cannot be eliminated by frequency compensation. A zener diode is required to clamp the input supply voltage and prevent MOSFET avalanche. SENSE RESISTOR CONSIDERATIONS For proper circuit breaker operation, Kelvin-sense PCB connections between the sense resistor and the LTC4253’s VEE and SENSE pins are strongly recommended. The drawing in Figure 7 illustrates the correct way of making connections between the LTC4253 and the sense resistor. PCB layout should be balanced and symmetrical to minimize wiring errors. In addition, the PCB layout for the sense resistor should include good thermal management techniques for optimal sense resistor power dissipation. TIMING WAVEFORMS System Power-Up Figure 8 details the timing waveforms for a typical powerup sequence in the case where a board is already installed in the backplane and system power is applied abruptly. At COMPENSATION CAPACITOR CC (nF) 60 MTY100N10E 50 40 TRACK WIDTH W: 0.03" PER AMP ON 1 OZ COPPER IRF540 IRF530 W IRF740 10 0 CURRENT FLOW TO –48V BACKPLANE SENSE RESISTOR IRF3710 30 20 CURRENT FLOW FROM LOAD 0 2000 4253 F07 6000 4000 MOSFET CISS (pF) 8000 TO SENSE TO VEE 4253 F06 Figure 6. Recommended Compensation Capacitor CC vs MOSFET CISS Figure 7. Making PCB Connections to the Sense Resistor 4253f 21 LTC4253 U W U U APPLICATIO S I FOR ATIO (Refer to Block Diagram) time point 1, the supply ramps up, together with UV/OV, VOUT and DRAIN. VIN and the PWRGD signals follow at a slower rate as set by the VIN bypass capacitor. At time point 2, VIN exceeds VLKO and the internal logic checks for UV > VUVHI, OV < VOVLO, RESET < 0.8V, GATE < VGATEL, SENSE < VCB, SS < 20 • VOS, and TIMER < VTMRL. When all conditions are met, initial timing starts and the TIMER capacitor is charged by a 5µA current source pull-up. At time point 3, TIMER reaches the VTMRH threshold and the initial timing cycle terminates. The TIMER capacitor is quickly discharged. At time point 4, the VTMRL threshold is reached and the conditions of GATE < VGATEL, SENSE␣ <␣ VCB and SS < 20 • VOS must be satisfied before the GATE startup cycle begins. SS ramps up as dictated by RSS • CSS (as in Equation 6); GATE is held low by the analog current limit (ACL) amplifier until SS crosses 20 • VOS. Upon releasing VIN CLEARS VLKO, CHECK UV > VUVHI, OV < VOVLO, RESET < 0.8V, GATE < VGATEL, SENSE < VCB, SS < 20 • VOS AND TIMER < VTMRL TIMER CLEARS VTMRL, CHECK GATE < VGATEL, SENSE < VCB AND SS < 20 • VOS 1 2 3 4 56 7 89 A B C D GND – VEE OR (–48RTN) – (–48V) UV/OV VIN VLKO VTMRH 200µA + 8 • IDRN 5µA TIMER 5µA VTMRL 50µA GATE SS 50µA VGATEL 5µA VIN – VGATEH 20 • (VACL + VOS) 20 • (VCB + VOS) 20 • VOS VACL SENSE VCB VOUT VDRNCL DRAIN VDRNL 50µA PWRGD1 PWRGD2 PWRGD3 VSQTMRH 5µA SQTIMER VSQTMRH 5µA VIH EN2 VIH EN3 INITIAL TIMING GATE START-UP 4253 F08 Figure 8. System Power-Up Timing (All Waveforms are Referenced to VEE) 4253f 22 LTC4253 U W U U APPLICATIO S I FOR ATIO (Refer to Block Diagram) GATE, 50µA sources into the external MOSFET gate and compensation network. When the GATE voltage reaches the MOSFET’s threshold, current flows into the load capacitor at time point 5. At time point 6, load current reaches SS control level and the analog current limit loop activates. Between time points 6 and 8, the GATE voltage is servoed, the SENSE voltage is regulated at VACL(t) (equation 7) and soft-start limits the slew rate of the load current. If the SENSE voltage (VSENSE – VEE) reaches the VCB threshold at time point 7, circuit breaker TIMER activates. The TIMER capacitor, CT is charged by a (200µA␣ +␣ 8␣ •␣ IDRN) current pull-up. As the load capacitor nears full charge, load current begins to decline. At time point 8, the load current falls and the SENSE voltage drops below VACL(t). The analog current limit loop shuts off and the GATE pin ramps further. At time point 9, the SENSE voltage drops below VCB, the fault TIMER ends, followed by a 5µA discharge cycle (cool-off). The duration between time points 7 and 9 must be shorter than one circuit breaker delay to avoid fault time-out during GATE rampup. When GATE ramps past the VGATEH threshold at time point␣ A, PWRGD1 pulls low. At time point B, GATE reaches its maximum voltage as determined by VIN. At time point A, SQTIMER starts its ramp-up to 4V. Having satisfied the requirement that PWRGD1 is low for more than one tSQT, PWRGD2 pulls low after EN2 pulls high above the VIH threshold at time point C. This sets off the second SQTIMER ramp-up. Having satisfied the requirement that PWRGD2 is low for more than one tSQT, PWRGD3 pulls low after EN3 pulls high at time point D. Live Insertion with Short Pin Control of UV/OV In the example shown in Figure 9, power is delivered through long connector pins whereas the UV/OV divider makes contact through a short pin. This ensures the power connections are firmly established before the LTC4253 is activated. At time point 1, the power pins make contact and VIN ramps through VLKO. At time point 2, the UV/OV divider makes contact and its voltage exceeds VUVHI. In addition, the internal logic checks for OV < VOVHI, RESET < 0.8V, GATE < VGATEL, SENSE < VCB, SS < 20 • VOS and TIMER␣ <␣ VTMRL. When all conditions are met, initial tim- ing starts and the TIMER capacitor is charged by a 5µA current source pull-up. At time point 3, TIMER reaches the VTMRH threshold and the initial timing cycle terminates. The TIMER capacitor is quickly discharged. At time point␣ 4, the VTMRL threshold is reached and the conditions of GATE␣ <␣ VGATEL, SENSE␣ <␣ VCB and SS␣ <␣ 20 • VOS must be satisfied before the GATE start-up cycle begins. SS ramps up as dictated by RSS • CSS; GATE is held low by the analog current limit amplifier until SS crosses 20 • VOS. Upon releasing GATE, 50µA sources into the external MOSFET gate and compensation network. When the GATE voltage reaches the MOSFET’s threshold, current begins flowing into the load capacitor at time point 5. At time point 6, load current reaches SS control level and the analog current limit loop activates. Between time points 6 and 8, the GATE voltage is servoed and the SENSE voltage is regulated at VACL(t) and soft-start limits the slew rate of the load current. If the SENSE voltage (VSENSE – VEE) reaches the VCB threshold at time point 7, the circuit breaker TIMER activates. The TIMER capacitor, CT is charged by a (200µA␣ +␣ 8␣ •␣ IDRN) current pull-up. As the load capacitor nears full charge, load current begins to decline. At point␣ 8, the load current falls and the SENSE voltage drops below VACL(t). The analog current limit loop shuts off and the GATE pin ramps further. At time point 9, the SENSE voltage drops below VCB and the fault TIMER ends, followed by a 5µA discharge current source (cool-off). When GATE ramps past VGATEH threshold at time point A, PWRGD1 pulls low, starting off the PWRGD sequence. PWRGD2 pulls low at time point C when EN2 is high and PWRGD1 is low for more than one tSQT. PWRGD3 pulls low at time point D when EN2 and EN3 is high and PWRGD2 is low for more than one tSQT. At time point B, GATE reaches its maximum voltage as determined by VIN. Undervoltage Timing In Figure 10 when the UV pin drops below VUVLO (time point␣ 1), the LTC4253 shuts down with TIMER, SS and GATE pulled low. If current has been flowing, the SENSE pin voltage decreases to zero as GATE collapses. When UV recovers and clears VUVHI (time point 2), an initial time cycle begins followed by a start-up cycle. 4253f 23 LTC4253 U U W U APPLICATIO S I FOR ATIO (Refer to Block Diagram) UV CLEARS VUVHI, CHECK OV < VOVHI, RESET = 0.8V, GATE < VGATEL, SENSE < VCB, SS < 20 • VOS AND TIMER < VTMRL TIMER CLEARS VTMRL, CHECK GATE < VGATEL, SENSE < VCB AND SS < 20 • VOS 1 2 3 456 7 89 A B C D GND – VEE OR (–48RTN) – (–48V) UV/OV VUVHI VIN VLKO VTMRH 200µA + 8 • IDRN 5µA TIMER 5µA VTMRL 50µA GATE 50µA VGATEL 5µA VIN – VGATEH 20 • (VACL + VOS) 20 • (VCB + VOS) 20 • VOS SS VACL VCB SENSE VOUT VDRNCL DRAIN VDRNL 50µA PWRGD1 PWRGD2 PWRGD3 VSQTMRH 5µA SQTIMER 5µA VSQTMRL VSQTMRH VSQTMRL EN2 EN3 INITIAL TIMING GATE START-UP 4253 F09 Figure 9. Power-Up Timing with a Short Pin (All Waveforms are Referenced to VEE) VIN Undervoltage Lockout Timing VIN undervoltage lockout comparator, UVLO has a similar timing behaviour as the UV pin timing except it looks at VIN for (VLKO␣ –␣ VLKH) to shut down and VLKO to revive. In VIN shutdown, both UV and OV comparators are preset off. This effectively causes the UV comparator to look for VUVHI threshold and OV comparator to look for VOVLO threshold when VIN comes out of undervoltage lockout. Undervoltage Timing with Overvoltage Glitch In Figure 11, both UV and OV pins are connected together, clears VUVHI (time point␣ 1), an initial timing cycle starts. If the system bus voltage overshoots VOVHI as shown at time point␣ 2, TIMER discharges. At time point␣ 3, the supply voltage recovers and drops below the VOVLO threshold. The initial timing cycle restarts and is followed by a GATE start-up cycle. Overvoltage Timing During normal operation, if the OV pin exceeds VOVHI as shown at time point␣ 1 of Figure 12, the TIMER and PWRGD status are unaffected; SS and GATE pull down; load disconnects. At time point 2, OV recovers and drops below the VOVLO threshold; GATE start-up begins. If the overvoltage glitch is long enough to deplete the load capacitor, time points 4 through 7 may occur. 4253f 24 LTC4253 U U W U APPLICATIO S I FOR ATIO (Refer to Block Diagram) UV DROPS BELOW VUVLO. GATE, SS AND TIMER ARE PULLED DOWN, PWRGD RELEASES UV CLEARS VUVHI, CHECK OV CONDITION, RESET < 0.8V, GATE < VGATEL, SENSE < VCB, SS < 20 • VOS AND TIMER < VTMRL TIMER CLEARS VTMRL, CHECK GATE < VGATEL, SENSE < VCB AND SS < 20 • VOS 1 UV 2 VUVLO 3 4 56 89 A B C VTMRH 200µA + 8 • IDRN 5µA VTMRL 5µA 50µA GATE SS D VUVHI 5µA TIMER 7 VIN – VGATEH 50µA VGATEL 20 • (VACL + VOS) 20 • (VCB + VOS) 20 • VOS VACL SENSE VCB VDRNCL DRAIN VDRNL 50µA PWRGD1 PWRGD2 PWRGD3 VSQTMRH 5µA SQTIMER VSQTMRL 5µA VSQTMRH VSQTMRL EN2 EN3 INITIAL TIMING GATE START-UP 4253 F10 Figure 10. Undervoltage Timing (All Waveforms are Referenced to VEE) Circuit Breaker Timing Resetting a Fault Latch In Figure 13a, the TIMER capacitor charges at 200µA if the SENSE pin exceeds VCB but VDRN is less than 6.15V. If the SENSE pin returns below VCB before TIMER reaches the VTMRH threshold, TIMER is discharged by 5µA. In Figure␣ 13b, when TIMER exceeds VTMRH, GATE pulls down immediately and the chip shuts down. In Figure␣ 13c, multiple momentary faults cause the TIMER capacitor to integrate and reach VTMRH followed by GATE pull down and the chip shuts down. During chip shutdown, LTC4253 latches TIMER high with a 5µA pull-up current source. A latched circuit breaker fault of the LTC4253 has the benefit of a long cooling time. The latched fault can be reset by pulsing the RESET pin high until the TIMER pin is pulled below VTMRL( 1V ) as shown in Figure 14. After the RESET pulse, SS and GATE ramp up without an initial timing cycle provided the interlock conditions are satisfied. Alternative methods of reset include using an external switch to pulse the UV pin below VUVLO or the VIN pin below (VLKO – VLKH). Pulling the TIMER pin below VTMRL and the SS pin to 0V then simultaneously releasing them also achieves a reset. An initial timing cycle is generated 4253f 25 LTC4253 U U W U APPLICATIO S I FOR ATIO (Refer to Block Diagram) for reset by pulsing the UV pin or VIN pin, while no initial timing cycle is generated for reset by pulsing of the TIMER and SS pins. GATE, SS, TIMER and SQTIMER low and the PWRGD signal high. The supply is fully cut off if the RESET pulse is maintained wide enough to fully discharge the GATE and SS pins. As long as RESET is high, GATE, SS, TIMER and SQTIMER are strapped to VEE and the supply is cut off. When RESET is released, if VSENSE > VCB, UV < VUVLO, OV > VOVHI or VIN is in UVLO, the chip waits for the interlock conditions before recovering as described in the Opera- Using Reset as an ON/OFF switch The asynchronous RESET pin can be used as an on/off function to cut off supply to the external power modules or loads controlled by the chip. Pulling RESET high will pull UV/OV CLEARS VUVHI, CHECK OV CONDITION, RESET< 0.8V, GATE < VGATEL, SENSE < VCB, SS < 20 • VOS AND TIMER < VTMRL UV/OV OVERSHOOTS VOVHI AND TIMER ABORTS INITIAL TIMING CYCLE UV/OV DROPS BELOW VOVLO AND TIMER RESTARTS INITIAL TIMING CYCLE TIMER CLEARS VTMRL, CHECK GATE < VGATEL, SENSE < VCB AND SS < 20 • VOS 1 2 VOVHI UV/OV 3 4 5 67 8 9A B C D VUVHI VTMRH 5µA TIMER 200µA + 8 • IDRN 5µA VTMRL 5µA 50µA GATE E VOVLO VIN – VGATEH 50µA VGATEL 20 • (VACL + VOS) 20 • (VCB + VOS) 20 • VOS SS VACL SENSE VCB VDRNCL DRAIN VDRNL 50µA PWRGD1 PWRGD2 PWRGD3 VSQTMRH 5µA SQTIMER VSQTMRL 5µA VSQTMRH VSQTMRL EN2 EN3 INITIAL TIMING GATE START-UP 4253 F11 Figure 11. Undervoltage Timing with an Overvoltage Glitch (All Waveforms are Referenced to VEE) 4253f 26 LTC4253 U U W U APPLICATIO S I FOR ATIO (Refer to Block Diagram) tion, Interlock Conditions section. If not, the GATE pin will ramp up in a soft start cycle without going through an initial cycle. Figure 15b, when a severe fault occurs, SENSE exceeds VFCL and GATE immediately pulls down until the analog current amplifier establishes control. If the severe fault causes VOUT to exceed VDRNCL, the DRAIN pin is clamped at VDRNCL. IDRN flows into the DRAIN pin and is multiplied by␣ 8. This extra current is added to the TIMER pull-up current of 200µA. This accelerated TIMER current of (200µA␣ +␣ 8␣ •␣ IDRN) produces a shorter circuit breaker fault Analog Current Limit and Fast Current Limit In Figure 15a, when SENSE exceeds VACL, GATE is regulated by the analog current limit amplifier loop. When SENSE drops below VACL, GATE is allowed to pull up. In OV OVERSHOOTS VOVHI. GATE AND SS ARE PULLED DOWN, PWRGD SIGNALS AND TIMER ARE UNAFFECTED OV DROPS BELOW VOVLO, CHECK GATE < VGATEL, SENSE < VCB AND SS < 20 • VOS 1 2 34 VOVHI OV 5 67 8 9 VOVLO VTMRH 200µA + 8 • IDRN TIMER 5µA 5µA 50µA GATE VGATEL VIN – VGATEH 50µA 20 • (VACL + VOS) 20 • (VCB + VOS) SS 20 • VOS VACL VCB SENSE GATE START-UP 4253 F12 Figure 12. Overvoltage Timing (All Waveforms are Referenced to VEE) CB TIMES-OUT 1 2 VTMRH 200µA + 8 • IDRN TIMER 5µA 1 VTMRH 200µA + 8 • IDRN TIMER CB TIMES-OUT 2 1 2 3 VTMRH 200µA + 8 • IDRN TIMER 5µA GATE GATE SS GATE SS SS VACL VCB SENSE VACL VCB SENSE VACL VCB SENSE VOUT VOUT DRAIN DRAIN VOUT DRAIN PWRGD1 PWRGD1 PWRGD1 VDRNCL CB FAULT (13a) Momentary Circuit Breaker Fault 4 CB FAULT (13b) Circuit Breaker Time-Out VDRNCL CB FAULT CB FAULT 4253 F13 (13c) Multiple Circuit Breaker Fault Figure 13. Circuit Breaker Timing Behavior (All Waveforms are Referenced to VEE) 4253f 27 LTC4253 U U W U APPLICATIO S I FOR ATIO (Refer to Block Diagram) delay. Careful selection of CT, RD and MOSFET helps prevent SOA damage in a low impedance fault condition. keeps GATE low. Above 0.2V, GATE is released and 50µA ramps up the compensation network and GATE capacitance at time point 4. Meanwhile, the SS pin voltage continues to ramp up. When GATE reaches the MOSFET’s threshold, the MOSFET begins to conduct. Due to the MOSFET’s high gm, the MOSFET current quickly reaches the soft-start control value of VACL(t) (Equation 7). At time point␣ 6, the GATE voltage is controlled by the current limit amplifier. The soft-start control voltage reaches the circuit breaker voltage, VCB at time point␣ 7 and the circuit breaker TIMER activates. As the load capacitor nears full charge, load current begins to decline below VACL(t). The current limit loop shuts off and GATE releases at time point␣ 8. At time point␣ 9, SENSE voltage falls below VCB and TIMER deactivates. Soft-Start If the SS pin is not connected, this pin defaults to a linear voltage ramp, from 0V to 2.2V in about 300µs at GATE start-up, as shown in Figure 16a. If a soft-start capacitor, CSS, is connected to this SS pin, the soft-start response is modified from a linear ramp to an RC response (Equation␣ 6), as shown in Figure 16b. This feature allows load current to slowly ramp-up at GATE start-up. Soft-start is initiated at time point 3 by a TIMER transition from VTMRH to VTMRL (time points 1 and 2) or by the OV pin falling below the VOVLO threshold after an OV condition. When the SS pin is below 0.2V, the analog current limit amplifier LATCHED TIMER RESET BY RESET PULLING HIGH RESET PULLS LOW 1 5µA 2 34 5 67 8 9 VTMRH 200µA + 8 • IDRN TIMER 5µA VTMRL 5µA 50µA GATE VGATEL VIN – VGATEH 50µA 20 • (VACL + VOS) SS 20 • (VCB + VOS) 20 • VOS VACL VCB SENSE VDRNCL DRAIN VDRNL 50µA PWRGD1 RESET VIH VIL RESET PULSE WIDTH MUST FULLY DISCHARGE TIMER 4253 F14 Figure 14. Reset of LTC4253’s Latched Fault (All Waveforms are Referenced to VEE) 4253f 28 LTC4253 U U W U APPLICATIO S I FOR ATIO (Refer to Block Diagram) Large values of CSS can cause premature circuit breaker time-out as VACL(t) may marginally exceed the VCB potential during the circuit breaker delay. The load capacitor is unable to achieve full charge in one GATE start-up cycle. A more serious side effect of a large CSS value is that SOA duration may be exceeded during soft-start into a low impedance load. A soft-start voltage below VCB will not activate the circuit breaker TIMER. Power Limit Circuit Breaker Figure 17 shows the LTC4253 in a power limit circuit breaking application. The SENSE pin is modulated by board voltage VSUPPLY. The zener voltage, VZ of D1, is set to be the same as the lowest operating voltage, VSUPPLY(MIN)␣ =␣ 36V. If the goal is to have the high supply operating voltage, VSUPPLY(MAX) = 72V give the same power as available at VSUPPLY(MIN), then resistors R3 and R7 are selected by: R7 VCB = R3 VSUPPLY(MAX) 2 VSUPPLY(MIN) + VSUPPLY(MIN) ) ( POWER(MAX) = 4 • VSUPPLY(MIN) • VSUPPLY(MAX) = 1.125 • POWER AT VSUPPLY(MIN) when VSUPPLY = 0.5 • (VSUPPLY(MIN) + VSUPPLY(MAX)) = 54V The peak power at the fault current limit occurs at the supply overvoltage threshold. The fault current limited power is: POWER(FAULT ) = (VSUPPLY ) • V RS ACL − (VSUPPLY − VZ )• R7 R3 (18) (16) If R7 is 22Ω, then R3 is 31.6k. The peak circuit breaker power limit is: 12 (17) •POWER AT VSUPPLY(MIN) CB TIMES-OUT 34 1 VTMRH 200µA + 8 • IDRN TIMER 5µA 2 VTMRH 200µA + 8 • IDRN TIMER GATE GATE SS VACL SENSE VCB VFCL SENSE VACL VCB VOUT VOUT VDRNCL DRAIN DRAIN PWRGD1 PWRGD1 4253 F15 (15a) Analog Current Limit Fault (15b) Fast Current Limit Fault Figure 15. Current Limit Behavior (All Waveforms are Referenced to VEE) 4253f 29 LTC4253 U U W U APPLICATIO S I FOR ATIO (Refer to Block Diagram) END OF INITIAL TIMING CYCLE 12 3 4 5 6 7 END OF INITIAL TIMING CYCLE 7a 8 9 10 11 12 3 4 5 6 VTMRH 7 8 9 5µA 200µA + 8 • IDRN TIMER VTMRL 50µA 50µA GATE GATE VIN – VGATEH VIN – VGATEH VGS(th) 50µA 50µA 20 • (VACL + VOS) SS 11 5µA 200µA + 8 • IDRN TIMER VTMRL VGS(th) 10 VTMRH 20 • (VACL + VOS) SS 20 • (VCB + VOS) 20 • (VCB + VOS) 20 • VOS 20 • VOS VACL SENSE VACL SENSE VCB VCB VDRNCL DRAIN VDRNCL DRAIN VDRNL VDRNL 50µA 50µA PWRGD1 PWRGD1 4253 F14 (16a) Without External CSS (16b) With External CSS Figure 16. Soft-Start Timing (All Waveforms are Referenced to VEE) GND RIN 2.8k 16k(1/4W)/6 R3 31.6k VIN C2 100µF R4 5.6k CIN 1µF R5 5.6k + C3 0.1µF R6 5.6k POWER MODULE 1 POWER MODULE 2 EN 4 VIN R1 402k 1% LTC4253 11 12 5 RESET OV PWRGD1 UV PWRGD2 RESET PWRGD3 C1 10nF CSS 68nF EN3 EN2 6 14 R2 32.4k 1% CSQ 0.1µF 13 SS DRAIN SQTIMER GATE TIMER SENSE VEE 8 CT 0.33µF EN D1 BZX84C36 GND SHORT PIN POWER MODULE 3 EN † † † 3 2 POWER MODULE 2 OUTPUT 16 15 EN3 EN2 1 10 VIN RD 1M 9 7 R7 22Ω RC 10Ω Q1 IRF530S VIN RS 0.02Ω † R8 POWER MODULE 1 OUTPUT CC 18nF † † MOC207 –VSUPPLY R9 4253 F17 Figure 17. Power Limit Circuit Breaker Application 4253f 30 LTC4253 U PACKAGE DESCRIPTIO GN Package 16-Lead Plastic SSOP (Narrow .150 Inch) (Reference LTC DWG # 05-08-1641) 0.189 – 0.196* (4.801 – 4.978) 16 15 14 13 12 11 10 9 0.229 – 0.244 (5.817 – 6.198) 0.150 – 0.157** (3.810 – 3.988) 1 0.015 ± 0.004 × 45° (0.38 ± 0.10) 0.007 – 0.0098 (0.178 – 0.249) 0.009 (0.229) REF 2 3 4 5 6 7 0.053 – 0.068 (1.351 – 1.727) 8 0.004 – 0.0098 (0.102 – 0.249) 0° – 8° TYP 0.016 – 0.050 (0.406 – 1.270) 0.008 – 0.012 (0.203 – 0.305) 0.0250 (0.635) BSC * DIMENSION DOES NOT INCLUDE MOLD FLASH. MOLD FLASH SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE ** DIMENSION DOES NOT INCLUDE INTERLEAD FLASH. INTERLEAD FLASH SHALL NOT EXCEED 0.010" (0.254mm) PER SIDE GN16 (SSOP) 1098 4253f Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights. 31 LTC4253 U TYPICAL APPLICATIO GND RIN 2.8k 16k(1/4W)/6 R3 5.6k CIN 1µF PUSH RESET R4 5.6k + C3 0.1µF R5 5.6k POWER MODULE 1 POWER MODULE 2 EN GND SHORT PIN EN POWER MODULE 3 EN 4 VIN R1 402k 1% † † † LTC4253 11 12 5 RESET OV PWRGD1 UV PWRGD2 RESET PWRGD3 C1 10nF CSS 27nF EN3 EN2 6 SS 14 R2 32.4k 1% C2 100µF VIN R8 47k 1% CSQ 0.1µF DRAIN SQTIMER 13 TIMER GATE SENSE 3 2 POWER MODULE 2 OUTPUT 16 15 EN3 EN2 1 10 9 Q1 IRF540S 7 R9 22Ω VEE CT 150nF VIN RD 1M RC 10Ω CC 22nF RS 0.01Ω VIN R6 POWER MODULE 1 OUTPUT R7 † † 4253 F18 †MOC207 –48V Figure 18. – 48V/5A Application RELATED PARTS PART NUMBER DESCRIPTION COMMENTS LT1640AH/LT1640AL Negative High Voltage Hot Swap Controller in SO-8 Negative High Voltage Supplies from -10V to -80V LT1641/LT1641-1 Positive High Voltage Hot Swap Controller in SO-8 Supplies from 9V to 80V, Autoretry/Latched Off LTC1642 Fault Protected Hot Swap Controller 3V to 16.5V, Overvoltage Protection up to 33V LT4250 – 48V Hot Swap Controller Active Current Limiting, Supplies from – 20V to – 80V LTC4251/LTC4251-1 – 48V Hot Swap Controller in SOT-23 Fast Active Current Limiting, Supplies from – 15V LTC4252-1/LTC4252-2 – 48V Hot Swap Controller in MS8/MS10 Fast Active Current Limiting, Supplies from – 15V, Drain Accelerated Response 4253f 32 Linear Technology Corporation LT/TP 0502 2K • PRINTED IN USA 1630 McCarthy Blvd., Milpitas, CA 95035-7417 (408) 432-1900 ● FAX: (408) 434-0507 ● www.linear.com LINEAR TECHNOLOGY CORPORATION 2002