™ Le79R79 Ringing Subscriber Line Interface Circuit VE580 Series APPLICATIONS Ideal for short-loop applications Ideal for ISDN-TA and fixed radio access applications Integrated Access Devices (IADs) Network Interface Units (NIUs) Cable Modems DSL Modems Set Top / House Side Boxes Intelligent PBX Pain Gain FXS Cards Voice over ISDN or T1/E1 Smart Residential Gateways WLL, APON, FITL, NGN, and all other short-loop CPE/ Enterprise telephony applications ORDERING INFORMATION Device1 Le79R79-1DJC Le79R79-2DJC Through trapezoidal ringing On-chip ring-trip detector Low standby state power Battery operation: — VBAT1: –40.5 to –75 V — VBAT2: –19 V to VBAT1 On-chip battery switching and feed selection On-hook transmission Two-wire impedance set by single external impedance Programmable constant-current feed Programmable Open Circuit voltage Programmable loop-detect threshold Current gain = 1000 Ground-key detector Polarity reversal option available Internal VEE regulator (no external –5 V power supply required) RELATED LITERATURE 080917 Ve790 Series RSLIC Device Product Brief 080158 Le79R70/79/100/101 Technical Overview 080914 Le79R79 RSLIC Device User’s Guide 080810 Le71HR0021 Reference Design User’s Guide 080255 Le71HE0040J Evaluation Board User’s Guide 080458 Le79R100/101 v. Le79R79 Comparison Brief 080753 Le58QL02/021/031 QLSLAC™ Data Sheet Packing4 32-pin PLCC (Green package) Tube 32-pin QFN (Green package) Tray Le79R79-3DJC Le79R79-1FQC Le79R79-2FQC -1: 52 dB Longitudinal Balance, Polarity Reversal -2: 63 dB Longitudinal Balance, Polarity Reversal -3: 52 dB Longitudinal Balance, No Polarity Reversal 1. Zarlink reserves the right to fulfill all orders for this device with parts marked with the "Am" part number prefix until all inventory bearing this mark has been depleted. Note that parts marked with either the "Am" or the "Le" part number prefix are equivalent devices in terms of form, fit, and function—the prefix appearing on the topside mark is the only difference. 2. Due to size constraints, QFN devices are marked by omitting the “Le” prefix and the performance grade dash character. For example, Le79R79-1FQC is marked 79R791FQC. 3. The green package meets RoHS Directive 2002/95/EC of the European Council to minimize the environmental impact of electrical equipment. 4. For delivery using a tape and reel packing system, add a "T" suffix to the OPN (Ordering Part Number) when placing an order. FEATURES Package Type2, 3 DESCRIPTION The Le79R79 Ringing SLIC device is a bipolar monolithic SLIC that offers on-chip ringing. Designers can achieve significant cost reductions at the system level for short-loop applications by integrating the ringing function on chip. Examples of such applications would be ISDN terminal adaptors, fiber-in-theloop, radio-in-the-loop, hybrid fiber/coax and video telephony (home-side) boxes. The Le79R79 Ringing SLIC device can provide sufficient voltage to meet the stringent LSSGR fiveringer equivalent specification. Using a CMOS-compatible input waveform and wave shaping R-C network, the Le79R79 Ringing SLIC device can provide trapezoidal wave ringing to meet various design requirements. See the Le79R79 Block Diagram, on page 4. Document ID#: 080152 Date: Sep 19, 2007 Rev: O Version: 2 Distribution: Public Document Le79R79 Data Sheet TABLE OF CONTENTS Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 Related Literature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 Ordering Information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 Product Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4 Connection Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5 Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7 Operating Ranges . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8 Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8 Transmission Performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8 Longitudinal Performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9 Idle Channel Noise . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9 Insertion Loss and Four-to-Four-Wire Balance Return Signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9 Line Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10 Power Supply Rejection Ratio . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10 Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10 Supply Currents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 Logic Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 Logic Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 Ring-Trip Detector Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 Ring Signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 Ground-Key Detector Thresholds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 Loop Detector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12 Relay Driver Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12 Relay Driver Schematic. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12 SLIC Device Decoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13 User-Programmable Components . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14 DC Feed Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15 Ring-Trip Components . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16 Test Circuits. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17 Le79R79 Test Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20 Application Circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21 Physical Dimensions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22 32-pin PLCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22 32-pin QFN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23 Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24 Revision B to C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24 Revision C to D . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24 Revision D to E . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24 Revision E to F . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24 Revision F to G . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24 Revision G to H . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24 Revision H to I . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24 Revision I to J1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24 Revision J1 to K1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24 Revision K1 to L1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24 Revision L1 to M1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24 Revision M1 to N1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25 2 Zarlink Semiconductor Inc. Le79R79 Data Sheet Revision N1 to N2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25 Revision N2 to O1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25 Revision O1 to O2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25 3 Zarlink Semiconductor Inc. Le79R79 Data Sheet PRODUCT DESCRIPTION The Zarlink family of subscriber line interface circuit (SLIC) products provide the telephone interface functions required throughout the worldwide market. Zarlink SLIC devices address all major telephony markets including central office (CO), private branch exchange (PBX), digital loop carrier (DLC), fiber-in-the-loop (FITL), radio-in-the-loop (RITL), hybrid fiber coax (HFC), and video telephony applications. The Zarlink SLIC devices offer support of BORSHT (battery feed, overvoltage protection, ringing, supervision, hybrid, and test) functions with features including current limiting, on-hook transmission, polarity reversal, Tip Open, and loop-current detection. These features allow reduction of linecard cost by minimizing component count, conserving board space, and supporting automated manufacturing. The Zarlink SLIC devices provide the two- to four-wire hybrid function, DC-loop feed, and two-wire supervision. Two-wire termination is programmed by a scaled impedance network. Transhybrid balance can be achieved with an external balance circuit or simply programmed using a companion Zarlink codec/filter, such as the Le58QL0xx Quad SLAC (QLSLAC™) device. The Le79R79 Ringing SLIC device is a bipolar monolithic SLIC that offers on-chip ringing. Now designers can achieve significant cost reductions at the system level for short-loop applications by integrating the ringing function on chip. Examples of such applications would be ISDN terminal adaptors, fiber-in-the-loop, radio-in-the-loop, hybrid fiber/coax and video telephony (homeside) boxes. The Le79R79 Ringing SLIC can provide sufficient voltage to meet the stringent LSSGR five-ringer equivalent specification. Using a CMOS-compatible input waveform and wave shaping R-C network, the Le79R79 Ringing SLIC can provide trapezoidal wave ringing to meet various design requirements. In order to further enhance the suitability of this device in short-loop, distributed switching applications, Zarlink has maximized power savings by incorporating battery switching on chip. The Le79R79 Ringing SLIC device switches between two battery supplies such that in the off-hook (active) state, a low battery is used to save power. In order to meet the Open Circuit voltage requirements of fax machines and maintenance termination units (MTU), the SLIC device automatically switches to a higher voltage in the On-hook (Standby) state. Like all of the Zarlink SLIC devices, the Le79R79 Ringing SLIC device supports on-hook transmission, ring-trip detection, programmable loop-detect threshold, and is available with on-chip polarity reversal. The Le79R79 Ringing SLIC device is a programmable constant-current feed device with two on-chip relay drivers to operate external relays. Several performance grades are available to meet both CCITT and LSSGR requirements, including various longitudinal balance options. Figure 1. Le79R79 Block Diagram Relay Driver RYOUT2 Relay Driver RYOUT1 RTRIP1 RTRIP2 RYE A(TIP) D1 D2 C1 Ring-Trip Detector Input Decoder and Control Ground-Key Detector HPA Two-Wire Interface C2 C3 E1 Off-Hook Detector DET Signal Transmission RD VTX RSN HPB B(RING) RINGIN RDC RDCR Power-Feed Controller VBAT2 RSGL RSGH B2EN Switch Driver VBAT1 VCC VNEG BGND AGND/DGND 4 Zarlink Semiconductor Inc. Le79R79 Data Sheet RD 1 B(RING) 2 A(TIP) 3 VBAT2 4 BGND RYOUT2 VCC CONNECTION DIAGRAMS 32 31 30 RYE 5 29 RTRIP1 RYOUT1 6 28 RTRIP2 27 HPB 8 26 HPA D1 9 25 RINGIN E1 10 24 RDCR C3 11 23 VTX C2 12 22 VNEG DET 13 21 RSN RYE 20 AGND/DGND RD NC RSGH 19 RDC D2 RSGL C1 18 AX 17 BX 16 BGND 15 VBAT2 32 1 14 VCC Top View 32-pin PLCC 31 30 29 28 27 26 RTRIP1 7 RYOUT2 B2EN VBAT1 25 24 RTRIP2 RYOUT1 2 23 HPB B2EN 3 22 HPA VBAT1 4 21 RINGIN 32-pin QFN D1 5 20 RDCR E1 6 19 VTX C3 7 18 VNEG C2 8 11 12 13 14 15 NC RSGH RSGL RDC 17 16 RSN AGND 10 D2 DET 9 C1 EXPOSED PAD Note: 1. Pin 1 is marked for orientation. 2. NC = No connect. 3. The thermally enhanced QFN package features an exposed pad on the underside which must be electrically tied to VBAT1. 5 Zarlink Semiconductor Inc. Le79R79 Data Sheet PIN DESCRIPTIONS Pin Names Type Description AGND/DGND Ground Analog and digital ground A(TIP) Output Output of A(TIP) power amplifier B2EN Input VBAT2 Enable. Logic Low enables operation from VBAT2. Logic High enables operation from VBAT1. TTL compatible. BGND Ground Battery (power) ground B(RING) Output Output of B(RING) power amplifier C3–C1 Input Decoder. SLIC control pins. C3 is MSB and C1 is LSB. TTL compatible. D1 Input Relay1 Control. TTL compatible. Logic Low activates the Relay1 relay driver. D2 Input Relay2 Control. (Option) TTL compatible. Logic Low activates the Relay2 relay driver. DET Output Hook switch detector. When enabled, a logic Low indicates that the selected detector is tripped. The logic inputs C3–C1 and E1 select the detector. The output is open collector with a built-in 15 kΩ pull-up resistor. E1 Input Ground-Key Enable. (Option) A logic High selects the off-hook detector. A logic Low selects the groundkey detector. TTL compatible. HPA Capacitor High-Pass Filter. A(TIP) side of high-pass filter capacitor. HPB Capacitor High-Pass Filter. B(RING) side of high-pass filter capacitor. NC — Not internally connected. RD Resistor Detect Resistor. Detector threshold set and filter pin. RDC Output DC Feed Resistor. Connection point for the DC-feed current programming network. The other end of the network connects to the receiver summing node (RSN). The sign of VRDC is negative for normal polarity and positive for reverse polarity. RDCR — Connection point for feedback during ringing. RINGIN Input Ring Signal. Pin for ring signal input. Square-wave shaped by external RC filter. Requires 50% duty cycle. CMOS-compatible input. RSGH Input Saturation Guard High. Pin for resistor to adjust Open Circuit voltage when operating from VBAT1. RSGL Input Saturation Guard Low. Pin for resistor to adjust the anti-saturation cut-in voltage when operating from both VBAT1 and VBAT2. RSN Input Receive Summing Node. The metallic current (both AC and DC) between A(TIP) and B(RING) is equal to 1000 x the current into this pin. The networks that program receive gain, two-wire impedance, and feed resistance all connect to this node. RTRIP1 Input Ring-Trip Detector. Ring-trip detector threshold set and filter pin. RTRIP2 Input Ring-Trip Detector. Ring-trip detector threshold offset (switch to VBAT1). For power conservation in any nonringing state, this switch is open. RYE Output Common Emitter of RYOUT1/RYOUT2. Emitter output of RYOUT1 and RYOUT2. Normally connected to relay ground. RYOUT1 Output Relay/Switch Driver. Open collector driver with emitter internally connected to RYE. RYOUT2 Output Relay/Switch Driver. (Option) Open collector driver with emitter internally connected to RYE. VBAT1 Battery Battery supply and connection to substrate. VBAT2 Battery Power supply to output amplifiers. Connect to off-hook battery through a diode. VCC Power Positive analog power supply VNEG Power Negative analog power supply. This pin is the return for the internal VEE regulator. VTX Output Transmit Audio. This output is a 0.5066 gain version of the A(TIP) and B(RING) metallic AC voltage. VTX also sources the two-wire input impedance programming network. 6 Zarlink Semiconductor Inc. Le79R79 Data Sheet ELECTRICAL CHARACTERISTICS Absolute Maximum Ratings Stresses greater than those listed under Absolute Maximum Ratings can cause permanent device failure. Functionality at or above these limits is not implied. Exposure to absolute maximum ratings for extended periods can affect device reliability. VNEG with respect to AGND/DGND –55 to +150º C 0.4 to +7 V 0.4 V to VBAT2 VBAT2 VBAT1 to GND Storage Temperature VCC with respect to AGND/DGND VBAT1 with respect to AGND/DGND: Continuous 10 ms BGND with respect to AGND/DGND: A(TIP) or B(RING) to BGND: Continuous +0.4 to –80 V +0.4 to –85 V +3 to –3 V VBAT1 –5 to +1 V 10 ms (F = 0.1 Hz) VBAT1 –10 to +5 V 1 µs (F = 0.1 Hz) VBAT1 –15 to +8 V VBAT1 –20 to +12 V 250 ns (F = 0.1 Hz) Current from A(TIP) or B(RING) RYOUT1, RYOUT2 current RYOUT1, RYOUT2 voltage RYOUT1, RYOUT2 transient RYE voltage ±150 mA 75 mA RYE to +7 V RYE to +10 V BGND to VBAT1 C3–C1, D2–D1, E1, B2EN, and RINGIN: Input voltage Maximum power dissipation, continuous, TA = 70º C, No heat sink (see note) In 32-pin PLCC package In 32-pin QFN package –0.4 V to VCC + 0.4 V 1.67 W 3.00 W θJA 45° C/W Thermal data: In 32-pin PLCC package In 32-pin QFN package 25° C/W JESD22 Class 1C compliant ESD Immunity (Human Body Model) Note: 1. Thermal limiting circuitry on the chip will shut down the circuit at a junction temperature of about 165ºC. Continuous operation above 145ºC junction temperature may degrade device reliability. 2. The thermal performance of a thermally enhanced package is assured through optimized printed circuit board layout. Specified performance requires that the exposed thermal pad be soldered to an equally sized exposed copper surface, which, in turn, conducts heat through multiple vias to a large internal copper plane. Package Assembly Green package devices are assembled with enhanced, environmental compatible lead-free, halogen-free, and antimony-free materials. The leads possess a matte-tin plating which is compatible with conventional board assembly processes or newer leadfree board assembly processes. The peak soldering temperature should not exceed 245°C during printed circuit board assembly. Refer to IPC/JEDEC J-Std-020B Table 5-2 for the recommended solder reflow temperature profile. 7 Zarlink Semiconductor Inc. Le79R79 Data Sheet OPERATING RANGES Zarlink guarantees the performance of this device over commercial (0 to 70º C) and industrial (-40 to 85ºC) temperature ranges by conducting electrical characterization over each range and by conducting a production test with single insertion coupled to periodic sampling. These characterization and test procedures comply with section 4.6.2 of Bellcore GR-357-CORE Component Reliability Assurance Requirements for Telecommunications Equipment. Environmental Ranges 0 to 70°C Commercial Ambient Temperature –40 to +85 °C extended temperature Ambient Relative Humidity 15 to 85% Electrical Ranges VCC 4.75 to 5.25 V VNEG –4.75 V to VBAT2 VBAT1 –40.5 to –75 V VBAT2 –19 V to VBAT1 AGND/DGND 0V BGND with respect to AGND/DGND –100 to +100 mV Load resistance on VTX to ground 20 kΩ minimum SPECIFICATIONS Transmission Performance Description 2-wire return loss Test Conditions (See Note 1) 200 Hz to 3.4 kHz (See Figure 6.) Min Typ ZVTX, analog output impedance 3 VVTX, analog output offset voltage Max 26 20 0 to +70° C –35 +35 −40 to +85° C –40 +40 ZRSN, analog input impedance 1 20 Unit Note dB 1, 4, 6 Ω 4 mV Ω 4 Overload level, 2-wire and 4-wire, Off hook Active state 2.5 Vpk 2a Overload level, 2-wire On hook, RLAC = 600 Ω 0.88 Vrms 2b THD (Total Harmonic Distortion) +3 dBm, BAT 2 = −24 V THD, On hook, OHT state 0dBm, RLAC = 600 Ω BAT1 = −75 V dB 5 8 Zarlink Semiconductor Inc. –64 –50 –40 Le79R79 Data Sheet Longitudinal Performance (See Figure 8.) Description Longitudinal to metallic L-T, L-4 balance Test Conditions (See Note 1) Min 200 Hz to 3.4 kHz −1, −3* 52 normal polarity −2, −4 63 reverse polarity −2 54 normal polarity, −40° C to +85 ° C −2, −4 1 kHz to 3.4 kHz −1, −3* 52 normal polarity −2, −4 58 reverse polarity −2 54 normal polarity, −40° C to +85° C Typ Max Unit 58 4 dB 54 −2, −4 Longitudinal signal generation 4-L 200 Hz to 800 Hz normal polarity 42 Longitudinal current per pin (A or B) Active or OHT state 12 Longitudinal impedance at A or B 0 to 100 Hz, TA = +25° C Note 4 28 mArms 25 Ω/pin 4 Idle Channel Noise Description Test Conditions (See Note 1) Min 0 to +70° C C-message weighted noise Typ +7 −40 to +85° C +11 +12 0 to +70° C Phosphometric weighted noise Max –83 −40 to +85° C –79 –78 Unit Note dBrnC dBmp 4 Insertion Loss and Four-to-Four-Wire Balance Return Signal (See Figure 6 and Figure 7.) Min Typ Max Gain accuracy, 4-to-2-wire Description 0 dBm, 1 kHz Test Conditions (See Note 1) –0.20 0 +0.20 Gain accuracy, 2-to-4-wire 0 dBm, 1 kHz –6.22 –6.02 –5.82 Gain accuracy, 4-to-2-wire OHT state, on hook –0.35 0 +0.35 Gain accuracy, 2-to-4-wire OHT state, on hook –6.37 –6.02 –5.77 Unit Note 4-to-4-wire 3 4-to-4-wire Gain accuracy over frequency 300 to 3400 Hz relative to 1 kHz Gain tracking +3 dBm to –55 dBm relative to 0 dBm Gain tracking 0 dBm to –37 0 to +70° C –0.10 +0.10 −40 to +85° C –0.15 +0.15 0 to +70° C –0.10 +0.10 −40 to +85° C –0.15 +0.15 0 to +70° C –0.10 +0.10 –0.15 +0.15 –0.35 +0.35 −40 to +85° C OHT state, on hook +3 dBm to 0 dBm Group delay 0 dBm, 1kHz 3 9 Zarlink Semiconductor Inc. dB 3, 4 3 µs 1, 4, 6 Le79R79 Data Sheet Line Characteristics Description IL, Loop-current accuracy IL, Long Loops, Active state Min Typ Max IL in constant-current region, B2EN=0 Test Conditions (See Note 1) 0.87IL IL 1.085IL RLDC = 600 Ω, RSGL = open 20 21.7 RLDC = 750 Ω, RSGL = short 20 V BAT1 – 10 V I L = ------------------------------------R L + 400 IL, Accuracy, Standby state ILLIM 0.8IL IL 1.2IL IL = constant-current region TA = 25° C 18 27 39 −40 to +85° C 18 27 Active, A and B to ground 55 OHT, A and B to ground 55 mA 4 4 IL, Loop current, Open Circuit state RL = 0 100 RL = 0 100 IB, Pin B current, Tip Open state B to ground VA, Standby, ground start signaling A to −48 V = 7 kΩ, B to ground = 100 Ω 34 VAB, Open Circuit voltage Note 110 IA, Pin A leakage, Tip Open state −7.5 Unit µA mA −5 V 42.8 4 8 Power Supply Rejection Ratio (VRIPPLE = 100 mVrms), Active Normal State Description Test Conditions (See Note 1) Min Typ Max VCC 50 to 3400 Hz 33 50 VNEG 50 to 3400 Hz 30 40 VBAT1 50 to 3400 Hz 30 50 VBAT2 50 to 3400 Hz 30 50 Min Typ Max 48 100 Unit Note dB 5 Unit Note Power Dissipation Description Test Conditions (See Note 1) On hook, Open Circuit state VBAT1 On hook, Standby state VBAT2 55 80 On hook, OHT state VBAT1 200 300 On hook, Active state VBAT1 220 350 Off hook, Standby state VBAT1 or VBAT2 RL = 300 Ω 2000 2800 Off hook, OHT state VBAT1 RL = 300 Ω 2000 2200 Off hook, Active state VBAT2 RL = 300 Ω 550 750 10 Zarlink Semiconductor Inc. 10 mW 10 Le79R79 Data Sheet Supply Currents Description Test Conditions (See Note 1) ICC, On-hook VCC supply current INEG, On-hook VNEG supply current IBAT, On-hook VBAT supply current Typ Max Open Circuit state Min 3.0 4.5 Standby state 3.2 5.5 OHT state 6.2 8.0 Active state-normal 6.5 9.0 Open Circuit state 0.1 0.2 Standby state 0.1 0.2 OHT state 0.7 1.1 Active state-normal 0.7 1.1 Open Circuit state 0.45 1.0 Standby state 0.6 1.5 OHT state 2.0 4.0 Active state-normal 2.7 5.0 Typ Max Unit Note mA Logic Inputs (Applies to C3–C1, D2–D1, E1, and B2EN). Description Test Conditions VIH, Input High voltage Min 2.0 VIL, Input Low voltage 0.8 IIH, Input High current –75 IIL, Input Low current –400 40 Unit Note V µA Logic Output (DET) Description Test Conditions (See Note 1) VOL, Output Low voltage IOUT = 0.8 mA, 15 kΩ to VCC VOH, Output High voltage IOUT = –0.1 mA, 15 kΩ to VCC Min Typ Max 0.40 2.4 Unit Note V Ring-Trip Detector Input Description Ring detect accuracy Test Conditions (See Note 1) Min BAT1 – 1- + 24 µA • 335 IRTD = -------------------------- RRT1 Typ Max –10 Unit +10 Note % Ring Signal Min Typ VAB, Ringing Description BAT1 = −75 V, Ringload = 1570 Ω Test Conditions (See Note 1) 66 69 VAB, Ringing offset VRINGIN = 2.5 V −10 0 10 150 180 210 Min Typ Max Unit 2 5 10 kΩ ∆V AB ⁄ ∆V RINGIN ( RINGIN gain ) Max Unit Note Vpk 7 V Ground-Key Detector Thresholds Description Test Conditions (See Note 1) Ground-key resistive threshold B to ground Ground-key current threshold B to ground 11 11 Zarlink Semiconductor Inc. mA Note Le79R79 Data Sheet Loop Detector Description Test Conditions (See Note 1) RLTH, Loop-resistance detect threshold Min Typ Max Active, VBAT1 −20 20 Active, VBAT2 −20 20 Standby −15 15 Unit Note % 9 Unit Note Relay Driver Output (Relay 1 and 2) Typ Max VOL, On voltage (each output) Description IOL = 30 mA Test Conditions (See Note 1) +0.25 +0.4 VOL, On voltage (each output) IOL = 40 mA +0.30 +0.8 IOH, Off leakage (each output) VOH = +5 V Zener breakover (each output) IZ = 100 µA Zener on voltage (each output) IZ = 30 mA Min 100 6.6 7.9 11 RELAY DRIVER SCHEMATIC RYOUT2 RYOUT1 RYE BGND BGND Note: 1. Unless otherwise noted, test conditions are BAT1 = –75 V, BAT2 = –24 V, VCC = +5 V, VNEG = –5 V, RL = 600 Ω, RDC1 = 80 kΩ, RDC2 = 20 kΩ, RD = 75 kΩ, no fuse resistors, CHP = 0.018 µF, CDC = 1.2 µF, D1 = D2 = 1N400x, two-wire AC input impedance (ZSL) is a 600 Ω resistance synthesized by the programming network shown below. RSGL = open, RSGH = open, RDCR1 = 15 kΩ, RDCR2 = 2 kΩ, CDCR = 10 nF, RRT1 = 430 kΩ, RRT2 = 12 kΩ, CRT = 1.5 µF, RSLEW = 100 kΩ, CSLEW = 0.33 µF. Figure 2. AC Input Impedance Programming Network VTX RT1 = 150 k Ω CT1 = 60 pF RT2 = 150 k Ω RSN RRX = 300 k Ω 12 Zarlink Semiconductor Inc. V RX V µA V 4 Le79R79 Data Sheet 2. a. Overload level is defined when THD = 1%. b. Overload level is defined when THD = 1.5%. 3. Balance return signal is the signal generated at VTX by VRX. This specification assumes that the two-wire AC load impedance matches the programmed impedance. 4. Not tested in production. This parameter is guaranteed by characterization or correlation to other tests. 5. This parameter is tested at 1 kHz in production. Performance at other frequencies is guaranteed by characterization. 6. Group delay can be greatly reduced by using a ZT network such as that shown in Note 1 above. The network reduces the group delay to less than 2 µs and increases 2WRL. The effect of group delay on linecard performance may also be compensated for by synthesizing complex impedance with the QSLAC or DSLAC device. 7. 70 Vpk provides 50 Vrms with a crest factor of 1.25 to a load of 1400 Ω with 2 • Rf = 100, and Rline = 70 Ω (1570 Ω). 8. Open Circuit VAB can be modified using RSGH. 9. RD must be greater than 56 kΩ. See User-Programmable Components, on page 14. for typical value of RLTH. 10. Lower power is achieved by switching into low-battery state in standby. Standby loop current is returned to VBAT1 regardless of the battery selected. SLIC Device Decoding (DET) Output State C3 C2 C1 Two-Wire Status E1 = 1 E1 = 0 Battery 0 0 0 0 Open Circuit Ring trip Ring trip 1 0 0 1 Ringing Ring trip Ring trip 2 0 1 0 Active Loop detector Ground key 3 0 1 1 On-hook TX (OHT) Loop detector Ground key 4 1 0 0 Reserved Loop detector Ground key B2EN = 1** 5 1 0 1 Standby Loop detector Ground key VBAT1 6* 1 1 0 Active Polarity Reversal Loop detector Ground key 7* 1 1 1 OHT Polarity Reversal Loop detector Ground key Note: * Only –1 and –2 performance grade device supports polarity reversal. ** For correct ground-start operation using Tip Open, VBAT1 on-hook battery must be used. 13 Zarlink Semiconductor Inc. B2EN B2EN Le79R79 Data Sheet User-Programmable Components Z T = 500 ( Z 2WIN – 2R F ) ZT is connected between the VTX and RSN pins. The fuse resistors are RF, and Z2WIN is the desired 2-wire AC input impedance. When computing ZT, the internal current amplifier pole and any external stray capacitance between VTX and RSN must be taken into account. ZL 1000 • Z T Z RX = ------------- • ---------------------------------------------------G 42L Z T + 500 ( Z L + 2R F ) ZRX is connected from VRX to RSN. ZT is defined above, and G42L is the desired receive gain. 2500 R DC1 + R DC2 = --------------I LOOP RDC1, RDC2, and CDC form the network connected to the RDC pin. ILOOP is the desired loop current in the constant-current region. 3000 R DCR1 + R DCR2 = ----------------------I RINGLIM RDCR1, RDCR2, and CDCR form the network connected to the RDCR pin. See Application Circuit, on page 21. for these components. R DC1 + R DC2 C DC = 19 ms • ----------------------------------R DC1 R DC2 R DCR1 + R DCR2 C DCR = ------------------------------------------- • 150 µs R DCR1 R DCR2 CDCR sets the ringing time constant, which can be between 15 µs and 150 µs. R D = R LTH • 12.67 for high battery state RD is the resistor connected from the RD pin to GND and RLTH is the loop-resistance threshold between on-hook and off-hook detection. RD should be greater than 56 kΩ to guarantee detection occurs in the Standby state. Choose the value of RD for high battery state; then use the equation for RLTH to find where the threshold is for low battery. Loop-Threshold Detect Equations RD - for high battery state R LTH = -------------12.67 This is the same equation as for RD above, except solved for RLTH. RD - for Active state R LTH = -------------11.37 For low battery, the detect threshold is slightly higher, which avoids oscillating between states. V BAT1 – 10 R LTH = ------------------------------ • R D – 400 – 2R F 915 RLTH Standby < RLTH Active VBAT1 < RLTH Active VBAT2, which guarantees no unstable states under all operating conditions. This equation shows at what resistance the Standby threshold is; it is actually a current threshold rather than a resistance threshold, which is shown by the VBAT dependency. 14 Zarlink Semiconductor Inc. Le79R79 Data Sheet DC FEED CHARACTERISTICS Figure 3. 50 Typical VAB vs. IL DC Feed Characteristics 5) VAPPH High Battery Anti-Sat 4) VASH 40 VAB (Volts) 30 1) Constant-Current Region 20 3) VAPPL Low Battery Anti-Sat 2) VASL 10 0 30 IL (mA) R DC = R DC1 + R DC2 = 20 kΩ + 80 kΩ = 100 kΩ ( V BAT1 = – 75 V ,V BAT2 = – 24 V ) Notes: 1. Constant-current region: 2500 V AB = I L R L = ------------- R L ; where R L = R L + 2R F , RDC 3 2. Low battery 1000 • ( 104 • 10 + R SGL ) V ASL = ------------------------------------------------------------------ ; where RSGL = resistor to GND, B2EN = logic Low. 3 6720 • 10 + ( 80 • R SGL ) 3 Anti-sat region: 3. 1000 • ( R SGL – 56 • 10 ) V ASL = --------------------------------------------------------------- ; where RSGL = resistor to VCC, B2EN = logic Low. 3 6720 • 10 + ( 80 • R SGL ) RSGL to VCC must be greater than 100 kΩ. V APPL = 4.17 + V ASL V APPL I LOOPL = -----------------------------------------------------------------------------( R DC1 + R DC2 ) -------------------------------------- + 2R F + R LOOP 600 4. High battery V ASH = V ASHH + V ASL 3 Anti-sat region: 1000 • ( 70 • 10 + R SGH ) V ASHH = ----------------------------------------------------------------------- ; where RSGH = resistor to GND, B2EN = logic High. 3 1934 • 10 + ( 31.75 • R SGH ) 3 V ASHH 5. V APPH 1000 • ( R SGH + 2.75 • 10 ) = ----------------------------------------------------------------------- ; where RSGH = resistor to VCC, B2EN = logic High. 3 1934 • 10 + ( 31.75 • R SGH ) RSGH to VCC must be greater than 100 kΩ. = 4.17 + V ASH V APPH I LOOPH = -----------------------------------------------------------------------------( R DC1 + R DC2 ) -------------------------------------- + 2R F + R LOOP 600 15 Zarlink Semiconductor Inc. Le79R79 Data Sheet RING-TRIP COMPONENTS R RT2 = 12 kΩ C RT = 1.5 µF V BAT1 R RT1 = 300 • CF • ------------------------------------------------------------------------------------------------------------------------------------------------ • ( R LRT + 150 + 2R F ) Vbat – 3.5 – ( 15 µA • 300 • CF • ( R LRT + 150 + 2R F ) ) where RLRT = Loop-detection threshold resistance for ring trip and CF = Crest factor of ringing signal (≈ 1.25) RSLEW, CSLEW Ring waveform rise time ≈ 0.214 • (RSLEW • CSLEW) ≈ tr. For a 1.25 crest factor @ 20 Hz, tr ≈ 10 mS. ∴ (RSLEW = 150 kΩ, CSLEW = 0.33 µF.) CSLEW should be changed if a different crest factor is desired. Figure 4. Ringing Waveforms Ringing Reference (Input to R SLEW ) 0 B(RING) A(TIP) Battery This is the best time for switching between Ringing and other states for minimizing detect switching transients. Figure 5. Feed Programming A (TIP) a RSN IL RL RDC1 SLIC b RDC2 B (RING) RDC Feed current programmed by R DC1 and R DC2 16 Zarlink Semiconductor Inc. CDC Le79R79 Data Sheet TEST CIRCUITS Figure 6. Two-to-Four-Wire Insertion Loss A (TIP) VTX RL SLIC 2 V AB VL RT AGND RL RRX 2 RSN B (RING) IL2-4 = 20 log(V TX / V AB ) Figure 7. Four-to-Two-Wire Insertion Loss and Four-to-Four-Wire Balance Return Signal A (TIP) VTX SLIC V AB RT RL AGND RRX B (RING) RSN V RX IL4-2 = 20 log(V AB / V RX ) BRS = 20 log(V TX / V RX ) Figure 8. 1 ωC Longitudinal Balance RL 2 S1 VTX A (TIP) << RL SLIC C RT V AB VL AGND VL RL S2 2 B (RING) RRX RSN S2 Open, S1 Closed S2 Closed, S1Open L-T Long. Bal. = - 20 log(V AB / V L) 4-L Long. Sig. Gen. = 20 log(V L / V RX ) L-4 Long. Bal. = - 20 log(V TX / V L) 17 Zarlink Semiconductor Inc. V RX Le79R79 Figure 9. Data Sheet Two-Wire Return Loss Test Circuit ZD VTX A (TIP) RT1 SLIC R VM VS AGND R CT1 RT2 ZIN B (RING) RSN ZD : The desired impedance; eg., the characteristic impedance of the line RRX Return loss = –20 log (2V M / V S) Figure 10. Loop-Detector Switching V CC 6.2 k Ω A (TIP) DET 15 pF RL = 600 Ω B (RING) Figure 11. E1 Ground-Key Switching A (TIP) B (RING) RG 18 Zarlink Semiconductor Inc. Le79R79 Figure 12. Data Sheet RFI Test Circuit L1 200Ω C1 RF 1 A (TIP) 50Ω CAX 33nF 50Ω B (RING) 200Ω HF GEN 50Ω L2 C2 RF 2 CBX 33nF VTX SLIC under test 1.5 Vrms 80% Amplitude Modulated 100 kHz to 30 MHz 19 Zarlink Semiconductor Inc. Le79R79 Data Sheet Le79R79 TEST CIRCUIT -5 V +5 V RTRIP1 CRT 1.5 µF RRT2 RRT1 12 kΩ 430 k Ω CAX 2.2 nF A (TIP) VCC VNEG RD RSGH RSGL VTX Le79R79 A (TIP) HPA CHP 18 nF CBX 2.2 nF RSGH open RRX 300 k Ω RSN B (RING) RSGL open V TX RT 300 k Ω HPB B (RING) RD 75 kΩ RTRIP2 VRX RDC1 20 kΩ RDC RDC2 80 kΩ RDCR RYOUT1 RYOUT1 RYOUT2 RYOUT2 RDCR 2.0 kΩ RYE CDC 1.2 µF RYE D1 B2EN C1 C2 C3 D1 D2 E1 DET VBAT1 BAT1 0.1 µF D2 BAT2 VBAT2 0.1 µF RINGIN BGND AGND/ DGND B2EN C1 C2 C3 D1 D2 E1 DET RSLEW 100 k Ω CSLEW See Note 2 below. 0.33 µF BATTERY GROUND ANALOG GROUND DIGITAL GROUND Note: 1. Refer to the Applications Circuit on the next page for recommended configuration. 2. The input should be 50% duty cycle CMOS-compatible input. 20 Zarlink Semiconductor Inc. Le79R79 Data Sheet APPLICATION CIRCUIT +5 V RTRIP1 CRT RRT2 RFA = 50 Ω TIP BAT1 K1 G TISP 61089 RING RFB = 50 Ω A A VCC VNEG RRT1 515 k Ω 12 kΩ CAX = 2.2 nF 1.5 µF CHP 18 nF RTRIP2 U1 Le79R79 A(TIP) HPA RD RSGH RSGL VTX RD 66 kΩ RSN RDC1 50 kΩ RDC RDCR1 RYOUT1 RYOUT2 RYOUT2 V TX V RX RDC2 50 kΩ RDCR2 15 kΩ CDC 820 nF RDCR 15 kΩ RYE RSGL open RRX RT2 CT 125 kΩ 250 k Ω CBX = 2.2 nF RYOUT1 RSGH open RT1 125 kΩ HPB B(RING) K2 -5 V CDCR 10 nF RYE B2EN C1 C2 C3 D1 D2 E1 DET D1 BAT1 VBAT1 0.1 µF D2 BAT2 VBAT2 0.1 µF RINGIN BGND AGND/ DGND B2EN C1 C2 C3 D1 D2 E1 DET RSLEW 150 k Ω CSLEW See note below. 0.33 µF BATTERY GROUND Assumptions: 1. 1.25 CF 2. 25 mA I LOOP 3. 100 mA Ringing Current Limit 4. 5.2 k Ω High Battery Loop Threshold 5. 925 Ω Ringing Loop Threshold 6. 600 Ω Two-wire Impedance, 600 Ω Z L 7. G 42L = 1 8. - 70 V V bat1, - 24 V V bat2 ANALOG GROUND DIGITAL GROUND Note: The input should be 50% duty cycle CMOS-compatible input. 21 Zarlink Semiconductor Inc. Le79R79 Data Sheet PHYSICAL DIMENSIONS 32-pin PLCC NOTES: 32-Pin PLCC JEDEC # MS-016 Min Nom Symbol A 0.125 -A1 0.075 0.090 D 0.485 0.490 D1 0.447 0.450 D2 0.205 REF E 0.585 0.590 E1 0.547 0.550 E2 0.255 REF Ԧ 0 deg -- 1 Dimensioning and tolerancing conform to ASME Y14,5M-1994. 2 To be measured at seating plan - C - contact point. 3 Dimensions “D1” and “E1” do not include mold protrusion. Allowable mold protrusion is 0.010 inch per side. Dimensions “D” and “E” include mold mismatch and determined at the parting line; that is “D1” and “E1” are measured at the extreme material condition at the upper or lower parting line. 0.595 0.553 4 Exact shape of this feature is optional. 10 deg 5 Details of pin 1 identifier are optional but must be located within the zone indicated. 6 Sum of DAM bar protrusions to be 0.007 max per lead. 7 Controlling dimension : Inch. 8 Reference document : JEDEC MS-016 Max 0.140 0.095 0.495 0.453 32-Pin PLCC Note: Packages may have mold tooling markings on the surface. These markings have no impact on the form, fit or function of the device. Markings will vary with the mold tool used in manufacturing. 22 Zarlink Semiconductor Inc. Le79R79 Data Sheet 32-pin QFN Symbol A A2 b D D2 E E2 e L N A1 A3 aaa bbb ccc Min 0.80 0.18 5.70 5.70 0.43 0.00 32 LEAD QFN Nom 0.90 0.57 REF 0.23 8.00 BSC 5.80 8.00 BSC 5.80 0.80 BSC 0.53 32 0.02 0.20 REF 0.20 0.10 0.10 Max 1.00 0.28 5.90 5.90 0.63 NOTES: 1. Dimensioning and tolerancing conform to ASME Y14.5M-1994. 2. All dimensions are in millimeters. is in degrees. 3. N is the total number of terminals. 4. The Terminal #1 identifier and terminal numbering convention shall conform to JEP 95-1 and SSP-012. Details of the Terminal #1 identifier are optional, but must be located within the zone indicated. The Terminal #1 identifier may be either a mold or marked feature. 5. Coplanarity applies to the exposed pad as well as the terminals. 6. Reference Document: JEDEC MO-220. 7. Lead width deviates from the JEDEC MO-220 standard. 0.05 32-Pin QFN Note: Packages may have mold tooling markings on the surface. These markings have no impact on the form, fit or function of the device. Markings will vary with the mold tool used in manufacturing. 23 Zarlink Semiconductor Inc. Le79R79 Data Sheet REVISION HISTORY Revision B to C • • • • Minor changes were made to the data sheet style and format to conform to Zarlink standards. Electrical Characteristics; Last row under Ring Signal, min changed from 130 to 150, typ changed from 160 to 180, and max changed from 190 to 210. SLIC Decoding Table; Added B2EN reference to the Battery Selection column and its corresponding note to the notes section. Applications Circuit; Revised Revision C to D • Minor changes were made to the data sheet style and format to conform to Zarlink standards. Revision D to E • On pages 17 and 18, RDC1 and RDC2 were switched. Revision E to F • • • The physical dimensions (PL032) were added to the Physical Dimensions section. Deleted the Ceramic DIP and Plastic DIP packages and references to them. Updated the Pin Description table to correct inconsistencies. Revision F to G • The equation on page 13 was changed: from: to: V BAT1 R RT1 = 300 • CF • ------------------------------------------------------------------------------------------------------------------------------------------ • ( R LRT + 150 + 2R F ) Vbat – 3.5 – ( 15 µA • 300 • CF • ( R LRT + 150 + 2R F ) ) V BAT1 R RT1 = 320 • CF • ------------------------------------------------------------------------------------------------------------------------------------- • ( R LRT + 150 + 2R F ) Vbat – 5 – ( 24 µA • 320 • CF • ( R LRT + 150 + 2R F ) ) Revision G to H • In “Ordering Information” section, added description for wafer foundry facility optional character. Revision H to I • • • Updated document format Added OPNs for QFN package to Ordering Information table Added physical dimensions for 8x8 QFN package Revision I to J1 • • • Added green package OPN to Ordering Information, on page 1 Added Package Assembly, on page 7 Updated document format Revision J1 to K1 • Added Note 3 to Connection Diagrams, on page 5 Revision K1 to L1 • • Added "Packing" column and Note 2 and 4 to Ordering Information, on page 1 Updated 32QFN drawing in Physical Dimensions, on page 22 Revision L1 to M1 • • • Added option for PLCC green package to Ordering Information, on page 1 Added option for QFN green package for dash grades 2 through 4 in Ordering Information, on page 1 Added note to Physical Dimensions, on page 22 24 Zarlink Semiconductor Inc. Le79R79 Revision M1 to N1 • • Removed OPNs for all non-green packaged parts from Ordering Information, on page 1 Removed 79R79-3QC, 79R79-4JC and 79R79-4QC from Ordering Information, on page 1 Revision N1 to N2 • Removed reference to Le79R79-4 option from Ordering Information, on page 1 Revision N2 to O1 • Changed IL Loop-Current Accuracy from 0.915 to 0.87 in Electrical Characteristics. Revision O1 to O2 • • Enhanced format of package drawings in Physical Dimensions, on page 22 Added new headers/footers due to Zarlink purchase of Legerity on August 3, 2007 25 Zarlink Semiconductor Inc. Data Sheet For more information about all Zarlink products visit our Web Site at www.zarlink.com Information relating to products and services furnished herein by Zarlink Semiconductor Inc. or its subsidiaries (collectively “Zarlink”) is believed to be reliable. However, Zarlink assumes no liability for errors that may appear in this publication, or for liability otherwise arising from the application or use of any such information, product or service or for any infringement of patents or other intellectual property rights owned by third parties which may result from such application or use. Neither the supply of such information or purchase of product or service conveys any license, either express or implied, under patents or other intellectual property rights owned by Zarlink or licensed from third parties by Zarlink, whatsoever. Purchasers of products are also hereby notified that the use of product in certain ways or in combination with Zarlink, or non-Zarlink furnished goods or services may infringe patents or other intellectual property rights owned by Zarlink. This publication is issued to provide information only and (unless agreed by Zarlink in writing) may not be used, applied or reproduced for any purpose nor form part of any order or contract nor to be regarded as a representation relating to the products or services concerned. The products, their specifications, services and other information appearing in this publication are subject to change by Zarlink without notice. No warranty or guarantee express or implied is made regarding the capability, performance or suitability of any product or service. Information concerning possible methods of use is provided as a guide only and does not constitute any guarantee that such methods of use will be satisfactory in a specific piece of equipment. It is the user’s responsibility to fully determine the performance and suitability of any equipment using such information and to ensure that any publication or data used is up to date and has not been superseded. Manufacturing does not necessarily include testing of all functions or parameters. These products are not suitable for use in any medical products whose failure to perform may result in significant injury or death to the user. All products and materials are sold and services provided subject to Zarlink’s conditions of sale which are available on request. Purchase of Zarlink’s I2C components conveys a license under the Philips I2C Patent rights to use these components in an I2C System, provided that the system conforms to the I2C Standard Specification as defined by Philips. Zarlink, ZL, the Zarlink Semiconductor logo and the Legerity logo and combinations thereof, VoiceEdge, VoicePort, SLAC, ISLIC, ISLAC and VoicePath are trademarks of Zarlink Semiconductor Inc. TECHNICAL DOCUMENTATION - NOT FOR RESALE