19-1853; Rev 2; 12/02 +3.3V, 10.7Gbps 1:16 Deserializer with LVDS Outputs Features ♦ Supports Serial Data Rates Up to 10.7Gbps ♦ 10Gbps/10.7Gbps Serial to 622Mbps/667Mbps Parallel Conversion ♦ Single +3.3V Supply ♦ 900mW Operating Power ♦ CML Serial Clock and Data Inputs ♦ LVDS Parallel Clock and Data Outputs ♦ -40°C to +85°C Operating Temperature Applications SONET/OC-192 SDH/STM-64 Transmission Systems Add/Drop Multiplexers Ordering Information Broadband Digital Cross-Connects PART MAX3950EGK TEMP RANGE PIN-PACKAGE -40°C to +85°C 68 QFN Pin Configuration appears at the end of data sheet. Typical Application Circuit VCC VCC 622Mbps PD15+ VCC SD+ IN+ OUT+ SDO- SD- PD15SDI+ IN+ PD0+ MAX3920* TIA MAX3940* CDR MAX3925* AGC AMP 100Ω** MAX3950 DESERIALIZER OVERHEAD PROCESSING OUT+ SDO+ 10Gbps 10Gbps 10Gbps 100Ω** 10Gbps VCC PD0- INOUT- IN- OUT- SDI- SCLKO+ SCLK+ SCLKO- SCLK- PCLK+ 100Ω** PCLK- *FUTURE PRODUCTS. **REQUIRED ONLY IF OVERHEAD CIRCUIT DOES NOT INCLUDE INTERNAL INPUT TERMINATION. THIS SYMBOL REPRESENTS A TRANSMISSION LINE OF CHARACTERISTIC IMPEDANCE Zo = 50Ω. ________________________________________________________________ Maxim Integrated Products For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at 1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com. 1 MAX3950 General Description The MAX3950 deserializer is ideal for converting 10Gbps serial data to 16-bit-wide, 622Mbps parallel data in SDH/SONET and DWDM applications. Operating from a single +3.3V supply, this device accepts CML serial clock and data inputs and delivers low-voltage differential-signal (LVDS) clock and data outputs for interfacing with high-speed digital circuitry. The MAX3950 is available in the extended temperature range (-40°C to +85°C) in a 68-pin QFN package. The typical power dissipation is 900mW. MAX3950 +3.3V, 10.7Gbps 1:16 Deserializer with LVDS Outputs ABSOLUTE MAXIMUM RATINGS Positive Supply Voltage (VCC)...............................-0.5V to +5.0V CML Input Voltage Level .................(VCC - 0.8V) to (VCC + 0.5V) LVDS Output Voltage Level........................-0.5V to (VCC + 0.5V) Continuous Power Dissipation (TA = +85°C) 68-Lead QFN (derate 43.5mW/°C above +85°C) ......2800mW Operating Temperature Range ...........................-40°C to +85°C Storage Temperature Range .............................-55°C to +150°C Lead Temperature (soldering, 10s) .................................+300°C Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. DC ELECTRICAL CHARACTERISTICS (VCC = +3.0V to +3.6V, differential loads = 100Ω ±1%, TA = -40°C to +85°C, unless otherwise noted. Typical values are at VCC = +3.3V, TA = +25°C.) PARAMETER Supply Current SYMBOL CONDITIONS MIN TYP MAX UNITS 270 350 mA 400 1200 mVP-P VCC 0.6 VCC + 0.3 V 57.5 Ω 1.375 V ICC CML INPUTS (SD±, SCLK±) Differential Input Voltage Swing VID Single-Ended Input Voltage Range VIS Input Termination to VCC RIN Figure 1 42.5 50 LVDS OUTPUT SPECIFICATION (PD[15.0] ±, PCLK±) Output High Voltage VOH Output Low Voltage VOL Differential Output Voltage Change in Magnitude of Differential Output for Complementary States |VOD| 1.025 Figure 2 ∆|VOD| Offset Output Voltage Change in Magnitude of Output Offset Voltage for Complementary States 1.15 ∆|VOS| Differential Output Impedance Output Current 2 150 80 V 250 mV 25 mV 1.25 V 25 mV 120 Ω Short together 12 Short to ground 24 _______________________________________________________________________________________ mA +3.3V, 10.7Gbps 1:16 Deserializer with LVDS Outputs (VCC = +3.0V to +3.6V, differential loads = 100Ω ±1%, TA = -40°C to +85°C, unless otherwise noted. Typical values are at VCC = +3.3V, TA = +25°C.) (Note 1) PARAMETER SYMBOL CONDITIONS MIN TYP Serial Input Data Rate MAX 10 UNITS Gbps Serial Data Setup Time tSU 25 ps Serial Data Hold Time tH 25 ps Parallel Output Data Rate 622 Parallel Output Clock Frequency 622 Parallel Clock-to-Q Delay tCLK-Q (Note 2) LVDS Output Rise/Fall Time -200 Mbps MHz +200 ps 20% to 80% 300 ps LVDS Differential Skew tSKEW1 Any differential pair 65 ps LVDS Channel-to-Channel Skew tSKEW2 PD[15..0]± 200 100kHz ≤ f ≤ 5GHz 17 5GHz ≤ f ≤ 10GHz 14 10GHz ≤ f ≤ 15GHz 11 |S11| Input Return Loss ps dB Note 1: AC specifications are guaranteed by design and characterization. Note 2: Relative to the falling edge of PCLK+. See Figure 3. VCC + 0.3V 600mV 200mV VCC VCC - 0.3V (a) AC-COUPLED CML INPUT VCC 200mV 600mV VCC - 0.6V (b) DC-COUPLED CML INPUT Figure 1. Input Amplitude _______________________________________________________________________________________ 3 MAX3950 AC ELECTRICAL CHARACTERISTICS MAX3950 +3.3V, 10.7Gbps 1:16 Deserializer with LVDS Outputs PD+ RL = 100Ω VOD V PD- VPD- VOH IVODI SINGLE-ENDED OUTPUT VOS VPD+ VOL VPD+ - VPD- DIFFERENTIAL OUTPUT 0 VODP-P = 2IVODI Figure 2. Driver Output Levels tCLK SCLK+ t SU tH SD PCLK+ tCLK-Q PD Figure 3. Timing Parameters 4 _______________________________________________________________________________________ +3.3V, 10.7Gbps 1:16 Deserializer with LVDS Outputs 230 210 200 190 180 NOTE: MEASURED 20 TO 80%. 250 RISE/FALL TIME (ps) 220 MAX3950 toc02 240 MAX3950 toc03 300 MAX3950 toc01 250 PCLK+ 200 PCLK- DATA 150 CLOCK 100 PD 170 50 160 150 0 -20 0 20 40 60 80 -40 -20 0 20 40 60 200ps/div 80 AMBIENT TEMPERATURE (°C) AMBIENT TEMPERATURE (°C) OUTPUT EYE DIAGRAM INPUT: 10.7Gbps, 213 - 1 +100 ZEROS PRBS INPUT RETURN LOSS MAX3950 toc04 0 NOTE: DATA IS FROM SIMULATION AND INCLUDES PACKAGE PARASITICS. PCLK+ -5 PCLK- MAX3950 toc05 -40 RETURN LOSS (dB) SINGLE-ENDED LVDS OUTPUT (mVP-P) OUTPUT EYE DIAGRAM INPUT: 9.953Gbps, 213 - 1 +100 ZEROS PRBS OUTPUT RISE/FALL TIME vs. TEMPERATURE LVDS OUTPUT AMPLITUDE vs. TEMPERATURE -10 -15 -20 PD -25 -30 200ps/div 0 5 10 15 20 FREQUENCY (GHz) Pin Description PIN NAME FUNCTION 1, 2, 5, 13, 16, 17, 18, 26, 33–36, 42, 51, 52, 53, 60, 68 GND Ground 6, 9, 12, 25, 31, 32, 37, 43, 50, 54, 55, 61 VCC Positive Power Supply 7 SD+ Positive Data Input. 9.953Gbps serial data stream, CML. 8 SD- Negative Data Input. 9.953Gbps serial data stream, CML. 10 SCLK+ Positive Serial Clock Input. 9.953GHz, CML. 11 SCLK- Negative Serial Clock Input. 9.953GHz, CML. 14 PCLK- Negative Parallel Clock Output, 622.08MHz, LVDS. _______________________________________________________________________________________ 5 MAX3950 Typical Operating Characteristics (TA = +25°C, unless otherwise noted.) +3.3V, 10.7Gbps 1:16 Deserializer with LVDS Outputs PIN NAME FUNCTION 15 PCLK+ Positive Parallel Clock Output, 622.08MHz, LVDS. 19, 21, 23, 27, 29, 38, 40, 44, 46, 48, 56, 58, 62, 64, 66, 3 PD0- to PD15- Negative Parallel Data Output, 622.08Mbps, LVDS. 20, 22, 24, 28, 30, 39, 41, 45, 47, 49, 57, 59, 63, 65, 67, 4 PD0+ to PD15+ Positive Parallel Data Output, 622.08Mbps, LVDS. EP Exposed Pad Ground. This must be soldered to the circuit board ground for proper thermal and electrical operation. See Layout Considerations. CP Corner Pins N.C. Not Connected. Ensure that the solder mask is located below them so that unintentional connections do not occur. 4-BIT SHIFT REGISTER MAX3950 DATA CLK CML INPUT D FLIP-FLOP DELAY 4-BIT SHIFT REGISTER CML INPUT DIVIDE BY 4 4-BIT SHIFT REGISTER 4-BIT SHIFT REGISTER OUTPUT REGISTER MAX3950 Pin Description (continued) DATA CLK DIVIDE BY 4 Figure 4. Functional Block Diagram Detailed Description The MAX3950 deserializer implements a shift-registerbased demultiplexer to convert 9.953Gbps serial data to 16-bit-wide, 622.08Mbps parallel data (Figure 4). The allocation of the serial input bits to the parallel LVDS outputs is displayed in Figure 5. Applications Information Low-Voltage Differential-Signal Outputs The MAX3950 features LVDS outputs for interfacing with high-speed digital circuitry. This LVDS implementation is based on the IEEE 1596.3 LVDS reduced-range link specification and is compatible with OIF 1999.102. 6 Note that the PCLK polarity on the MAX3950 is inverted relative to OIF 1999.102, so that PCLK+ is equivalent to RXCLK_N and PCLK- is equivalent to RXCLK_P. The MAX3950 uses 300mVP-P to 500mVP-P differential low-voltage swings to achieve fast transition times, minimize power dissipation, and improve noise immunity. The parallel clock and data LVDS outputs (PCLK+, PCLK-, PD_+, PD_-) require 100Ω differential DC termination between the inverting and noninverting outputs for proper operation. Do not terminate these outputs to ground. For more information on interfacing with the LVDS outputs, refer to Maxim Application Note HFAN1.0: Interfacing Between CML, PECL, and LVDS. _______________________________________________________________________________________ +3.3V, 10.7Gbps 1:16 Deserializer with LVDS Outputs D14 MAX3950 D15 D13 SD PCLK+ (LSB) PD0 D0 D16 D32 D48 D64 PD1 D1 D17 D33 D49 D65 D15 D31 D47 D63 D79 • • • (MSB) PD15 TRANSMITTED FIRST Figure 5. Timing Diagram VCC 250fF 50Ω 50Ω 1.1nH SD+ K = 0.4 HIGH Z SD1.1nH 250fF 70fF HIGH Z 70fF NOTE: PARASITIC VALUES SHOWN ARE TYPICAL VALUES. Figure 6. CML Input Model Current Mode Logic (CML) Inputs Layout Considerations The differential serial inputs to the MAX3950 are CML and have an input impedance of 50Ω on each of the complementary inputs. For more information on interfacing with the CML inputs, refer to Maxim Application Note HFAN-1.0: Interfacing Between CML, PECL, and LVDS. For best performance, use good high-frequency layout techniques. Filter voltage supplies, keep ground connections short, and use multiple vias where possible. Use controlled-impedance transmission lines to interface with the MAX3950’s high-speed inputs and outputs. Place power-supply decoupling as close to VCC as possible. To reduce feedthrough, isolate the input signals from the output signals. Interface Models Figures 6 and 7 show the typical input/output models for the MAX3950 deserializer. _______________________________________________________________________________________ 7 +3.3V, 10.7Gbps 1:16 Deserializer with LVDS Outputs MAX3950 Chip Information TRANSISTOR COUNT: 4800 vcc vcc PD_+ vcc PD_- MAX3950 Figure 7. LVDS Output Model Pin Configuration GND 1 51 GND GND 2 50 VCC PD15- 3 49 PD9+ PD15+ 4 48 PD9- GND 5 47 PD8+ VCC 6 46 PD8- SD+ 7 45 PD7+ SD- 8 44 PD7- VCC 9 MAX3950 43 VCC SCLK+ 10 42 GND SCLK- 11 41 PD6+ VCC 12 40 PD6- GND 13 39 PD5+ PCLK- 14 38 PD5- PCLK+ 15 37 VCC GND 16 36 GND 35 GND GND GND VCC VCC PD4+ PD4- PD3+ PD3- GND VCC PD2+ PD2- PD1- GND PD0- *EXPOSED PAD IS CONNECTED TO GND. PD1+ 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 PD0+ 18 C. N. N. C. GND 17 8 C. GND 61 60 59 58 57 56 55 54 53 52 N. GND VCC VCC PD10+ PD10- PD11- PD11+ GND VCC PD12- PD12+ PD13- 67 66 65 64 63 62 PD13+ 68 PD14- PD14+ C. N. GND TOP VIEW QFN* _______________________________________________________________________________________ +3.3V, 10.7Gbps 1:16 Deserializer with LVDS Outputs Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time. 9 _____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 © 2002 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products. MAX3950 Package Information (The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information, go to www.maxim-ic.com/packages.)