19-4567; Rev 0; 4/09 KIT ATION EVALU E L B AVAILA +3.3V, Low-Jitter, Precision Clock Generator with Multiple Outputs The MAX3627 is a low-jitter, precision clock generator optimized for network applications. The device integrates a crystal oscillator and a phase-locked loop (PLL) to generate high-frequency clock outputs for Ethernet applications. Maxim’s proprietary PLL design features ultra-low jitter (0.4psRMS) and excellent power-supply noise rejection (PSNR), minimizing design risk for network equipment. The MAX3627 contains seven LVDS outputs and one LVCMOS output. The output frequencies are selectable among 125MHz, 156.25MHz, and 312.5MHz. Applications Ethernet Networking Equipment Typical Operating Circuit Features ♦ Crystal Oscillator Interface: 25MHz ♦ OSC_IN Interface PLL Enabled: 25MHz PLL Disabled: 20MHz to 320MHz ♦ Outputs One LVDS Output at 125MHz/156.25MHz/ 312.5MHz (Selectable with FSELA) Six LVDS Outputs at 125MHz/156.25MHz/ 312.5MHz (Selectable with FSELB) One LVCMOS Output at 125MHz/156.25MHz (Selectable with FSELB) ♦ Low Phase Jitter 0.4psRMS (12kHz to 20MHz) 0.2psRMS (1.875MHz to 20MHz) ♦ Excellent PSNR: -64dBc at 156.25MHz with 40mVP-P Supply Noise at 100kHz ♦ Operating Temperature Range: 0°C to +70°C Ordering Information +3.3V ±5% 0.1μF 0.1μF 0.1μF 10.5Ω VDD 10μF VDDO_DIFF VDDO_SE Q0 125MHz/156MHz/312.5MHz Z0 = 50Ω VDDA 100Ω 0.01μF Q0 ASIC PART TEMP RANGE PIN-PACKAGE MAX3627CTJ+ 0°C to +70°C 32 TQFN-EP* +Denotes a lead(Pb)-free/RoHS-compliant package. *EP = Exposed pad. Z0 = 50Ω Pin Configuration 125MHz/156MHz/312.5MHz Z0 = 50Ω Q1 PLL_BP Z0 = 50Ω Q5 18 17 16 OE PLL_BP 26 15 FSELB VDDA 27 14 Q4 13 Q4 MAX3627 X_IN 30 X_OUT 31 *EP + GND 32 100Ω ASIC 100Ω ASIC Z0 = 50Ω FSELA 125MHz/156MHz/312.5MHz Z0 = 50Ω Q6 GND, OPEN, OR VDD 19 OSC_IN 29 ASIC 125MHz/156MHz/312.5MHz Z0 = 50Ω Q5 Q5 GND, OPEN, OR VDD 20 1 2 3 4 5 6 7 8 Q2 Q4 21 FSELA 28 125MHz/156MHz/312.5MHz Z0 = 50Ω Q4 100Ω VDD 22 Q2 X_IN ASIC Z0 = 50Ω 27pF 23 VDDO_DIFF 25MHz (CL = 18pF) 24 VDD 25 100Ω Q3 Q5 ASIC 125MHz/156MHz/312.5MHz Z0 = 50Ω Q3 X_OUT VDDO_DIFF 100Ω 33pF Q6 Z0 = 50Ω Q1 Q2 Q6 125MHz/156MHz/312.5MHz Z0 = 50Ω VDDO_SE Q2 Q1 OE TOP VIEW GND OPEN ASIC Q7 Z0 = 50Ω Q0 Q1 Q0 OSC_IN GND 100Ω MAX3627 OPEN 12 VDDO_DIFF 11 Q3 10 Q3 9 GND FSELB Q6 Z0 = 50Ω 33Ω GND Q7 125MHz/156.25MHz Z0 = 50Ω THIN QFN (5mm × 5mm) ASIC *EXPOSED PAD CONNECTED TO GROUND. ________________________________________________________________ Maxim Integrated Products For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com. 1 MAX3627 General Description MAX3627 +3.3V, Low-Jitter, Precision Clock Generator with Multiple Outputs ABSOLUTE MAXIMUM RATINGS Supply Voltage Range at VDD, VDDA, VDDO_SE, VDDO_DIFF ................................................-0.3V to +4.0V Voltage Range at Q0, Q0, Q1, Q1, Q2, Q2, Q3, Q3, Q4, Q4, Q5, Q5, Q6, Q6, Q7, PLL_BP, FSELA, FSELB, OE, OSC_IN ...-0.3V to (VDD + 0.3V) Voltage Range at X_IN ..........................................-0.3V to +1.2V Voltage Range at X_OUT .................................-0.3V to (VDD - 0.6V) Continuous Power Dissipation (TA = +70°C) 32-Pin TQFN-EP (derate 34.5mW/°C above +70°C)..2759mW Operating Junction Temperature Range ...........-55°C to +150°C Storage Temperature Range .............................-65°C to +160°C Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ELECTRICAL CHARACTERISTICS (VDD = +3.0V to +3.6V, TA = 0°C to +70°C, unless otherwise noted. Typical values are at VDD = +3.3V, TA = +25°C, unless otherwise noted. When using X_IN, X_OUT input, no signal is applied at OSC_IN. When PLL is enabled, PLL_BP = high-Z or high. When PLL is bypassed, PLL_BP = low.) (Note 1) PARAMETER Power-Supply Current (Note 2) SYMBOL IDD CONDITIONS MIN TYP MAX PLL enabled 190 256 PLL bypassed 175 UNITS mA LVDS OUTPUTS (Q0, Q0, Q1, Q1, Q2, Q2, Q3, Q3, Q4, Q4, Q5, Q5, Q6, Q6) Output High Voltage VOH Output Low Voltage VOL Differential Output Voltage Amplitude Change in Magnitude of Differential Output for Complementary States Output Offset Voltage Change in Magnitude of Output Offset Voltage for Complementary States |V OD | 1.475 0.925 Figure 1 250 1.125 |V OS | Differential Output Impedance 80 Output Current Clock Output Rise/Fall Time V |V OD | VOS tr, t f Output Duty-Cycle Distortion 105 Shorted together 5 Short to ground (Note 3) 8 20% to 80%, RL = 100 V 400 mV 25 mV 1.275 V 25 mV 140 mA 100 200 330 PLL enabled 48 50 52 PLL bypassed (Note 4) 46 50 54 2.6 ps % LVCMOS/LVTTL OUTPUT (Q7) Output Frequency Output High Voltage VOH I OH = -12mA Output Low Voltage VOL I OL = 12mA Output Rise/Fall Time tr, t f 20% to 80% at 125MHz (Note 5) Output Duty-Cycle Distortion Output Impedance 2 R OUT 160 MHz VDD V 0.4 V 0.15 0.4 0.8 ns PLL enabled 46 50 54 PLL bypassed (Note 4) 45 50 55 15 _______________________________________________________________________________________ % +3.3V, Low-Jitter, Precision Clock Generator with Multiple Outputs (VDD = +3.0V to +3.6V, TA = 0°C to +70°C, unless otherwise noted. Typical values are at VDD = +3.3V, TA = +25°C, unless otherwise noted. When using X_IN, X_OUT input, no signal is applied at OSC_IN. When PLL is enabled, PLL_BP = high-Z or high. When PLL is bypassed, PLL_BP = low.) (Note 1) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS INPUT SPECIFICATIONS (FSELA, FSELB, PLL_BP, OE) Input-Voltage High VIH 2.0 VDD V Input-Voltage Low VIL 0 0.8 V Input High Current I IH VIN = VDD 80 μA Input Low Current I IL VIN = 0 -80 μA LVCMOS/LVTTL INPUT SPECIFICATIONS (OSC_IN) (Note 6) PLL enabled Input Clock Frequency Input Amplitude Range MHz 20 320 (Note 7) 1.2 3.6 V 80 μA Input High Current I IH VIN = VDD Input Low Current I IL VIN = 0 Reference Clock Duty Cycle Input Capacitance 25 PLL bypassed -80 40 CIN μA 50 60 % 1.5 pF 625 MHz CLOCK OUTPUT AC SPECIFICATIONS VCO Center Frequency Output Frequency with PLL Enabled (Q0) FSELA = GND 125 FSELA = VDD 156.25 FSELA = high-Z Output Frequency with PLL Enabled (Q1 to Q7) FSELB = GND 125 FSELB = VDD 156.25 FSELB = high-Z (Note 8) Output Frequency with PLL Disabled Integrated Phase Jitter RJRMS Power-Supply Noise Rejection (Note 11) PSNR MHz 312.5 MHz 312.5 LVDS outputs 20 320 LVCMOS output 20 160 12kHz to 20MHz, PLL_BP = high (Note 9) 0.4 12kHz to 20MHz, PLL_BP = high-Z (Note 10) 0.4 MHz 1.0 psRMS LVDS outputs -64 LVCMOS output -49 LVDS outputs 2.5 LVCMOS output 18 Nonharmonic and Subharmonic Spurs (Note 13) -70 dBc LVDS Clock Output SSB Phase Noise at 125MHz (Note 14) f f f f f f -115 -124 -126 -130 -143 -149 dBc/Hz Deterministic Jitter Due to Supply Noise (Note 12) = = = = = > 100Hz 1kHz 10kHz 100kHz 1MHz 10MHz dBc psP-P _______________________________________________________________________________________ 3 MAX3627 ELECTRICAL CHARACTERISTICS (continued) MAX3627 +3.3V, Low-Jitter, Precision Clock Generator with Multiple Outputs ELECTRICAL CHARACTERISTICS (continued) (VDD = +3.0V to +3.6V, TA = 0°C to +70°C, unless otherwise noted. Typical values are at VDD = +3.3V, TA = +25°C, unless otherwise noted. When using X_IN, X_OUT input, no signal is applied at OSC_IN. When PLL is enabled, PLL_BP = high-Z or high. When PLL is bypassed, PLL_BP = low.) (Note 1) PARAMETER SYMBOL CONDITIONS f f f f f f LVCMOS Clock Output SSB Phase Noise at 125MHz (Note 14) Note 1: Note 2: Note 3: Note 4: Note 5: Note 6: Note 7: Note 8: Note 9: Note 10: Note 11: Note 12: Note 13: Note 14: = = = = = > MIN 100Hz 1kHz 10kHz 100kHz 1MHz 10MHz TYP -113 -123 -126 -130 -144 -151 UNITS dBc/Hz A series resistor of up to 10.5Ω is allowed between VDD and VDDA for filtering supply noise when system power-supply tolerance is VDD = 3.3V ±5%. See Figure 4. All outputs unloaded. The current when an LVDS output is shorted to ground is the steady-state current after the detection circuitry has settled. It is expected that the LVDS output short to ground condition is short-term only. Measured with OSC_IN input with 50% duty cycle. Measured with a series resistor of 33Ω to a load capacitance of 3.0pF. See Figure 2. The OSC_IN input can be DC- or AC-coupled. Must be within the absolute maximum rating of VDD + 0.3V. AC characteristics of LVCMOS output (Q7) are only guaranteed up to 160MHz. Measured with 25MHz crystal (with OSC_IN left open). Measured with 25MHz reference clock applied to OSC_IN. Measured with 40mVP-P sinusoidal signal on the supply at 100kHz. For LVDS the output frequency is 156.25MHz; for LVCMOS the output frequency is 125MHz. Measured with a 10.5Ω resistor between VDD and VDDA. Parameter calculated based on PSNR. Measurement includes XTAL oscillator feedthrough, crosstalk, intermodulation spurs, etc. Measured with 25MHz XTAL oscillator. Qx RL = 100Ω VOD V Qx Qx SINGLE-ENDED OUTPUT VOH IVODI VOS Qx VOL Qx - Qx DIFFERENTIAL OUTPUT 0 VOD P-P = 2IVODI Figure 1. Driver Output Levels 4 MAX _______________________________________________________________________________________ +3.3V, Low-Jitter, Precision Clock Generator with Multiple Outputs MAX3627 VCC 800Ω MAX3627 33Ω Z0 = 50Ω Q7 3pF 800Ω OSCILLOSCOPE 0.1μF Z0 = 50Ω 50Ω 50Ω Figure 2. LVCMOS Output Measurement Setup Typical Operating Characteristics (Typical values are at VDD = +3.3V, TA = +25°C, crystal frequency = 25MHz.) PLL_BP = HIGH 200 175 150 125 PLL_BP = LOW 100 75 50 25 -90 -100 -110 -120 -130 -140 10 20 30 40 50 AMBIENT TEMPERATURE (°C) 60 70 -100 -110 -120 -130 -140 -160 -160 0 -90 -150 -150 0 -80 MAX3627 toc03 MAX3627 toc02 -80 NOISE POWER DENSITY (dBc/Hz) SUPPLY CURRENT (mA) 275 250 NOISE POWER DENSITY (dBc/Hz) MAX3627 toc01 300 225 PHASE NOISE AT 125MHz CLOCK FREQUENCY (Q7) PHASE NOISE AT 125MHz CLOCK FREQUENCY (Q0) SUPPLY CURRENT vs. TEMPERATURE 0.1 1 10 100 1000 10,000 100,000 OFFSET FREQUENCY (kHz) 0.1 1 10 100 1000 10,000 100,000 OFFSET FREQUENCY (kHz) _______________________________________________________________________________________ 5 Typical Operating Characteristics (continued) (Typical values are at VDD = +3.3V, TA = +25°C, crystal frequency = 25MHz.) -100 -110 -120 -130 -140 -150 -90 -100 -110 -120 -130 -140 1 10 100 1000 10,000 100,000 -100 -110 -120 -130 -140 -160 -160 0.1 1 10 100 0.1 1000 10,000 100,000 1 10 100 1000 10,000 100,000 OFFSET FREQUENCY (kHz) OFFSET FREQUENCY (kHz) OFFSET FREQUENCY (kHz) DIFFERENTIAL OUTPUT WAVEFORM AT 125MHz (LVDS OUTPUT) DIFFERENTIAL OUTPUT WAVEFORM AT 156.25MHz (LVDS OUTPUT) DIFFERENTIAL OUTPUT WAVEFORM AT 312.5MHz (LVDS OUTPUT) MAX3627 toc07 MAX3627 toc09 100mV/div 100mV/div OUTPUT WAVEFORM AT 125MHz (CMOS OUTPUT) MAX3627 toc10 0 MEASURED USING SETUP IN FIGURE 2 1ns/div 500ps/div SPURS INDUCED BY POWER-SUPPLY NOISE vs. NOISE FREQUENCY SPURS INDUCED BY POWER-SUPPLY NOISE vs. NOISE FREQUENCY fC = 156.25MHz -10 SPUR AMPLITUDE (dBc) -20 15mV/div -30 VNOISE = 200mVP-P -40 -50 -60 -70 VNOISE = 100mVP-P fC = 125MHz OUTPUT = Q7 -10 -20 VNOISE = 200mVP-P -30 -40 -50 -60 VNOISE = 40mVP-P VNOISE = 100mVP-P -70 -80 VNOISE = 40mVP-P -90 -80 -100 1ns/div 0 MAX3627 toc12 1ns/div MAX3627 toc11 100mV/div MAX3627 toc08 SPUR AMPLITUDE (dBc) 0.1 -90 -150 -150 -160 -90 10 100 NOISE FREQUENCY (kHz) 6 -80 MAX3627 toc06 MAX3627 toc05 -90 -80 NOISE POWER DENSITY (dBc/Hz) MAX3627 toc04 -80 PHASE NOISE AT 312.5MHz CLOCK FREQUENCY (Q0) PHASE NOISE AT 156.25MHz CLOCK FREQUENCY (Q7) NOISE POWER DENSITY (dBc/Hz) PHASE NOISE AT 156.25MHz CLOCK FREQUENCY (Q0) NOISE POWER DENSITY (dBc/Hz) MAX3627 +3.3V, Low-Jitter, Precision Clock Generator with Multiple Outputs 1000 10 100 NOISE FREQUENCY (kHz) _______________________________________________________________________________________ 1000 +3.3V, Low-Jitter, Precision Clock Generator with Multiple Outputs PIN NAME 1 2 3, 9, 24, 32 4 5 6, 12, 19 7 8 10 11 13 14 Q0 Q0 GND Q1 Q1 15 VDDO_DIFF Q2 Q2 Q3 Q3 Q4 Q4 FSELB 16 OE 17 18 20 21 22 23 25 Q5 Q5 Q6 Q6 VDDO_SE Q7 VDD FUNCTION LVDS, Noninverting Clock Output LVDS, Inverting Clock Output Supply Ground LVDS, Noninverting Clock Output LVDS, Inverting Clock Output Power Supply for Q0, Q1, Q2, Q3, Q4, Q5, and Q6 Clock Outputs. Connect to +3.3V. LVDS, Noninverting Clock Output LVDS, Inverting Clock Output LVDS, Noninverting Clock Output LVDS, Inverting Clock Output LVDS, Noninverting Clock Output LVDS, Inverting Clock Output Three-State LVCMOS/LVTTL Input. Controls the Q1 to Q7 output divider. When connected to logiclow, the output frequency is 125MHz. When connected to logic-high, the output frequency is 156.25MHz. When left open (high-Z), the output frequency is 312.5MHz. For the Q7 LVCMOS output, the output specification is only valid up to 160MHz. LVCMOS/LVTTL Input. Enable/disable control for the Q4, Q5, and Q6 outputs. The OE pin has an internal 75k pullup resistor. When OE is connected to VDD or left open, Q4, Q5, and Q6 are enabled. When OE is connected to GND, Q4, Q5, and Q6 are disabled to reduce power consumption. When disabled, Q4, Q5, and Q6 are high impedance. LVDS, Noninverting Clock Output LVDS, Inverting Clock Output LVDS, Noninverting Clock Output LVDS, Inverting Clock Output Power Supply for Q7 Clock Output. Connect to +3.3V. LVCMOS Clock Output Core Power Supply. Connect to +3.3V. Three-State LVCMOS/LVTTL Input (Active Low). When connected to logic-high, the PLL locks to the crystal interface (25MHz typical at X_IN and X_OUT). When left open (high-Z), the PLL locks to the OSC_IN input (25MHz typical). When connected to logic-low, the PLL is bypassed and the OSC_IN input is selected. When bypass mode is selected, the VCO/PLL is disabled to save power and eliminate intermodulation spurs. 26 PLL_BP 27 VDDA Analog Power Supply for the VCO. Connect to +3.3V. For additional power-supply noise filtering, this pin can be connected to VDD through a 10.5 resistor as shown in Figure 4. 28 FSELA Three-State LVCMOS/LVTTL Input. Controls the Q0 output divider. When connected to logic-low, the output frequency is 125MHz. When connected to logic-high, the output frequency is 156.25MHz. When left open (high-Z), the output frequency is 312.5MHz. 29 OSC_IN LVCMOS Input. Self-biased to allow AC- or DC-coupling. When PLL_BP is open, the OSC_IN input frequency should be 25MHz. When the PLL is in bypass mode (PLL_BP = low), the OSC_IN input frequency can be between 20MHz and 320MHz. When PLL_BP is high, the OSC_IN should be disconnected. 30 31 — X_IN X_OUT EP Crystal Oscillator Input Crystal Oscillator Output Exposed Pad. Connect to GND for proper electrical and thermal performance. _______________________________________________________________________________________ 7 MAX3627 Pin Description MAX3627 +3.3V, Low-Jitter, Precision Clock Generator with Multiple Outputs VDD VDDA FSELA VDDO_DIFF PLL_BP PLL_BP LOGIC 125MHz/156.25MHz/ 312.5MHz 0 OSC_IN CMOS 0/OPEN PFD FILTER VCO DIVIDER 5, 4, OR 2 LVDS BUFFER LVDS BUFFER CRYSTAL OSCILLATOR X_OUT DIVIDE 25 0 DIVIDER 5, 4, OR 2 1/OPEN LVDS BUFFER LVDS BUFFER LVDS BUFFER LVDS BUFFER MAX3627 LVDS BUFFER LVCMOS BUFFER 125MHz/156.25MHz FSELB OE VDDO_SE Figure 3. Functional Diagram 8 Q0 1/OPEN 1 X_IN Q0 _______________________________________________________________________________________ Q1 Q1 Q2 Q2 Q3 Q3 Q4 Q4 Q5 Q5 Q6 Q6 Q7 +3.3V, Low-Jitter, Precision Clock Generator with Multiple Outputs The MAX3627 is a frequency generator designed to operate at Ethernet frequencies. It consists of an onchip crystal oscillator, PLL, LVCMOS output buffer, and LVDS output buffers. Using a low-frequency clock (crystal or CMOS input) as a reference, the internal PLL generates a high-frequency output clock with excellent jitter performance. The outputs can be switched among 125MHz, 156.25MHz, and 312.5MHz. Crystal Oscillator An integrated oscillator provides the low-frequency reference clock for the PLL. This oscillator requires an external crystal connected between X_IN and X_OUT. The crystal frequency is 25MHz. See the Applications Information section for more information. OSC_IN Buffer The LVCMOS OSC_IN buffer is internally biased to allow AC- or DC-coupling. This input is internally ACcoupled, and is designed to operate at 25MHz when the PLL is enabled (PLL_BP is left open). When the PLL is bypassed (PLL_BP is set low), the OSC_IN buffer can be operated from 20MHz to 320MHz. PLL The PLL takes the signal from the crystal oscillator or reference clock input and synthesizes a low-jitter, highfrequency clock. The PLL contains a phase-frequency detector (PFD), a lowpass filter, and a voltage-controlled oscillator (VCO) that operates at 625MHz. The PLL bandwidth is tuned to 150kHz typical to optimize both phase noise and power-supply noise rejection (PSNR). The VCO output is connected to the PFD input through a feedback divider that divides the VCO frequency by 25 to lock onto the 25MHz reference clock or oscillator. For output Q0, the FSELA pin is used to select among 125MHz, 156.25MHz, and 312.5MHz. For outputs Q1 to Q6, the FSELB pin is used to select among 125MHz, 156.25MHz, and 312.5MHz. For the Q7 output, the FSELB pin is used to select between 125MHz and 156.25MHz. To minimize the jitter induced by power-supply noise, the VCO supply (VDDA) is isolated from the core logic and output buffer supplies. LVDS Drivers LVCMOS Driver LVCMOS output Q7 is provided on the MAX3627. It is designed to drive single-ended high-impedance loads. The output specifications are only valid up to 160MHz. Applications Information Power-Supply Filtering The MAX3627 is a mixed analog/digital IC. The PLL contains analog circuitry susceptible to random noise. To take full advantage of on-board filtering and noise attenuation, in addition to excellent on-chip power-supply rejection, this part provides a separate power-supply pin, VDDA, for the VCO circuitry. The purpose of this design technique is to ensure clean input power supply to the VCO circuitry and to improve the overall immunity to power-supply noise. Figure 4 illustrates the recommended power-supply filter network for VDDA. This network requires that the power supply is +3.3V ±5%. Decoupling capacitors should be used on all other supply pins and placed as close as possible to the pins for best performance. Crystal Input Layout and Frequency Stability The MAX3627 features an integrated on-chip crystal oscillator to minimize system implementation cost. The integrated crystal oscillator is a Pierce-type that uses the crystal in its parallel resonance mode. It is recommended to use a 25MHz crystal with a load specification of CL = 18pF. See Table 1 for the recommended crystal specifications. The crystal, trace, and two external capacitors should be placed on the board as close as possible to the X_IN and X_OUT pins to minimize the board parasitic capacitance and prevent active signals from coupling into the oscillator. +3.3V ±5% VDD 0.1μF MAX3627 10.5Ω VDDA The high-frequency outputs—Q0, Q1, Q2, Q3, Q4, Q5, and Q6—are differential LVDS buffers designed to drive 100Ω. 0.01μF 10μF Figure 4. Analog Supply Filtering _______________________________________________________________________________________ 9 MAX3627 Detailed Description MAX3627 +3.3V, Low-Jitter, Precision Clock Generator with Multiple Outputs Table 1. Crystal Selection Parameters PARAMETER Crystal Oscillation Frequency SYMBOL f OSC Shunt Capacitance CO Load Capacitance CL Equivalent Series Resistance (ESR) RS MIN TYP MAX 25 UNITS MHz 7.0 pF 18 pF Maximum Crystal Drive Level 50 300 μW The layout shown in Figure 5 gives approximately 2pF of trace plus footprint capacitance per side of the crystal (Y1). The dielectric material is FR4, and dielectric thickness of the reference board is 15 mils. Using a 25MHz crystal and the capacitor values of C45 = 27pF and C46 = 33pF, the measured output frequency accuracy is -1ppm at +25°C ambient temperature. Crystal Selection The crystal oscillator is designed to drive a fundamental mode, AT-cut crystal resonator. See Table 1 for recommended crystal specifications. See Figure 6 for external capacitance connection. 27pF X_IN CRYSTAL (CL = 18pF) MAX3627 X_OUT 33pF Figure 6. Crystal, Capacitors Connection Figure 5. Crystal Layout 10 ______________________________________________________________________________________ +3.3V, Low-Jitter, Precision Clock Generator with Multiple Outputs Layout Considerations The inputs and outputs are the most critical paths for the MAX3627 and great care should be taken to minimize discontinuities on these transmission lines between the connector and the IC. Here are some suggestions for maximizing the performance of the MAX3627: • An uninterrupted ground plane should be positioned beneath the clock outputs. The ground plane under the crystal should be removed to minimize capacitance. 1.4V VDD 180kΩ OSC_IN ESD STRUCTURES Figure 7. Simplified OSC_IN Pin Circuit Schematic VDDO_SE • The crystal, trace, and two external capacitors should be placed on the board as close as possible to the X_IN and X_OUT pins. 10Ω Q7 10Ω ESD STRUCTURES Figure 8. Simplified LVCMOS Output Circuit Schematic VDDO_DIFF • Ground pin vias should be placed close to the IC and the input/output interfaces to allow a return current path to the MAX3627 and the receive devices. • Supply decoupling capacitors should be placed close to the supply pins, preferably on the same layer as the MAX3627. • Take care to isolate crystal input traces from the MAX3627 outputs. VDD • Maintain 100Ω differential (or 50Ω single-ended) transmission line impedance into and out of the part. • Use good high-frequency layout techniques and multilayer boards with an uninterrupted ground plane to minimize EMI and crosstalk. Refer to the MAX3627 evaluation kit for more information. Exposed-Pad Package The exposed pad on the 32-pin TQFN package provides a very low inductance path for return current traveling to the PCB ground plane. The pad is thermal and electrical ground on the MAX3627 and must be soldered to the circuit board ground for proper electrical performance. Chip Information 75kΩ PROCESS: BiCMOS OE Package Information For the latest package outline information and land patterns, go to www.maxim-ic.com/packages. ESD STRUCTURES PACKAGE TYPE PACKAGE CODE DOCUMENT NO. 32 TQFN-EP T3255+5 21-0140 Figure 9. Simplified OE Pin Circuit Schematic Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time. Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 ____________________ 11 © 2009 Maxim Integrated Products Maxim is a registered trademark of Maxim Integrated Products, Inc. MAX3627 Interface Models Figures 7, 8, and 9 show examples of interface models.