RENESAS M16C62PT

REJ09B0185-0241
16
M16C/62P Group (M16C/62P, M16C/62PT)
Hardware Manual
RENESAS 16-BIT SINGLE-CHIP MICROCOMPUTER
M16C FAMILY / M16C/60 SERIES
Before using this material, please visit our website to verify that this is the most
updated document available.
Rev.2.41
Revision Date:Jan 10, 2006
www.renesas.com
Keep safety first in your circuit designs!
1.
Renesas Technology Corp. puts the maximum effort into making semiconductor products
better and more reliable, but there is always the possibility that trouble may occur with
them. Trouble with semiconductors may lead to personal injury, fire or property damage.
Remember to give due consideration to safety when making your circuit designs, with appropriate measures such as (i) placement of substitutive, auxiliary circuits, (ii) use of nonflammable material or (iii) prevention against any malfunction or mishap.
Notes regarding these materials
1.
2.
3.
4.
5.
6.
7.
8.
These materials are intended as a reference to assist our customers in the selection of the
Renesas Technology Corp. product best suited to the customer's application; they do not
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Renesas Technology Corp. or a third party.
Renesas Technology Corp. assumes no responsibility for any damage, or infringement of
any third-party's rights, originating in the use of any product data, diagrams, charts, programs, algorithms, or circuit application examples contained in these materials.
All information contained in these materials, including product data, diagrams, charts, programs and algorithms represents information on products at the time of publication of these
materials, and are subject to change by Renesas Technology Corp. without notice due to
product improvements or other reasons. It is therefore recommended that customers contact Renesas Technology Corp. or an authorized Renesas Technology Corp. product distributor for the latest product information before purchasing a product listed herein.
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How to Use This Manual
1.
Introduction
This hardware manual provides detailed information on the M16C/62P Group (M16C/62P, M16C/62PT) of
microcomputers.
Users are expected to have basic knowledge of electric circuits, logical circuits and microcomputers.
2.
Register Diagram
The symbols, and descriptions, used for bit function in each register are shown below.
XXX Register
b7
b6
b5
b4
b3
0
*1
b2
b1
b0
Symbol
XXX
Bit Symbol
XXX0
Address
XXX
After Reset
00h
Bit Name
XXX Bit
XXX1
*5
Function
RW
1 0: XXX
0 1: XXX
1 0: Avoid this setting
1 1: XXX
RW
RW
(b2)
Nothing is assigned.
When write, should set to “0”. When read, its content is indeterminate.
(b3)
Reserved Bit
Must set to “0”
RW
XXX Bit
Function varies depending on each operation
mode
RW
XXX4
*3
XXX5
WO
XXX6
RW
XXX7
XXX Bit
*2
b1 b0
0: XXX
1: XXX
*4
RO
*1
Blank: Set to “0” or “1” according to the application
0: Set to “0”
1: Set to “1”
X: Nothing is assigned
*2
RW: Read and write
RO: Read only
WO: Write only
−: Nothing is assigned
*3
•Reserved bit
Reserved bit. Set to specified value.
*4
•Nothing is assigned
Nothing is assigned to the bit concerned. As the bit may be use for future functions,
set to “0” when writing to this bit.
•Do not set to this value
The operation is not guaranteed when a value is set.
•Function varies depending on mode of operation
Bit function varies depending on peripheral function mode.
Refer to respective register for each mode.
3.
M16C Family Documents
The following documents were prepared for the M16C family. (1)
Document
Short Sheet
Data Sheet
Hardware Manual
Contents
Hardware overview
Hardware overview and electrical characteristics
Hardware specifications (pin assignments, memory maps, peripheral
specifications, electrical characteristics, timing charts)
Software Manual
Detailed description of assembly instructions and microcomputer
performance of each instruction
Application Note
• Application examples of peripheral functions
• Sample programs
• Introduction to the basic functions in the M16C family
• Programming method with Assembly and C languages
RENESAS TECHNICAL UPDATE Preliminary report about the specification of a product, a document,
etc.
NOTES:
1. Before using this material, please visit the our website to confirm that this is the most current
document available.
Table of Contents
SFR Page Reference
1.
2.
B-1
Overview
1
1.1
Applications .................................................................................................1
1.2
Performance Outline ...................................................................................2
1.3
Block Diagram .............................................................................................5
1.4
Product List .................................................................................................7
1.5
Pin Configuration.......................................................................................14
1.6
Pin Description ..........................................................................................25
Central Processing Unit (CPU)
30
2.1
Data Registers (R0, R1, R2 and R3).........................................................30
2.2
Address Registers (A0 and A1).................................................................31
2.3
Frame Base Register (FB) ........................................................................31
2.4
Interrupt Table Register (INTB) .................................................................31
2.5
Program Counter (PC) ..............................................................................31
2.6
User Stack Pointer (USP) and Interrupt Stack Pointer (ISP).....................31
2.7
Static Base Register (SB)..........................................................................31
2.8
Flag Register (FLG)...................................................................................31
2.8.1
Carry Flag (C Flag).............................................................................31
2.8.2
Debug Flag (D Flag) ...........................................................................31
2.8.3
Zero Flag (Z Flag)...............................................................................31
2.8.4
Sign Flag (S Flag)...............................................................................31
2.8.5
Register Bank Select Flag (B Flag) ....................................................31
2.8.6
Overflow Flag (O Flag) .......................................................................31
2.8.7
Interrupt Enable Flag (I Flag)..............................................................31
2.8.8
Stack Pointer Select Flag (U Flag) .....................................................32
2.8.9
Processor Interrupt Priority Level (IPL) ..............................................32
2.8.10
Reserved Area....................................................................................32
3.
Memory
33
4.
Special Function Register (SFR)
34
5.
Reset
40
5.1
Hardware Reset 1 .....................................................................................40
5.1.1
Reset on a Stable Supply Voltage......................................................40
5.1.2
Power-on Reset..................................................................................40
A-1
6.
7.
8.
5.2
Brown-out Detection Reset (Hardware Reset 2) .......................................42
5.3
Software Reset..........................................................................................43
5.4
Watchdog Timer Reset.............................................................................43
5.5
Oscillation Stop Detection Reset...............................................................43
5.6
Internal Space ...........................................................................................44
Voltage Detection Circuit
6.1
Low Voltage Detection Interrupt ................................................................49
6.2
Limitations on Exiting Stop Mode .............................................................51
6.3
Limitations on Exiting Wait Mode ..............................................................51
6.4
Cold Start-up / Warm Start-up Determine Function ..................................52
Processor Mode
54
7.1
Types of Processor Mode .........................................................................54
7.2
Setting Processor Modes ..........................................................................55
Bus
8.1
59
Bus Mode ..................................................................................................59
8.1.1
Separate Bus......................................................................................59
8.1.2
Multiplexed Bus ..................................................................................59
8.2
9.
45
Bus Control................................................................................................60
8.2.1
Address Bus .......................................................................................60
8.2.2
Data Bus.............................................................................................60
8.2.3
Chip Select Signal ..............................................................................60
8.2.4
Read and Write Signals......................................................................63
8.2.5
ALE Signal..........................................................................................63
8.2.6
RDY Signal .........................................................................................64
8.2.7
HOLD Signal.......................................................................................65
8.2.8
8.2.8 BCLK Output .............................................................................65
8.2.9
External Bus Status When Internal Area Accessed ..........................67
8.2.10
Software Wait .....................................................................................68
Memory Space Expansion Function
72
9.1
1-Mbyte Mode ...........................................................................................72
9.2
4-Mbyte Mode ...........................................................................................72
9.2.1
9.2.1 Addresses 04000h to 3FFFFh, C0000h to FFFFFh ..................72
9.2.2
9.2.2 Addresses 40000h to BFFFFh ..................................................72
A-2
10. Clock Generation Circuit
10.1
82
Types of the Clock Generation Circuit.......................................................82
10.1.1
Main Clock..........................................................................................89
10.1.2
Sub Clock ...........................................................................................90
10.1.3
On-chip Oscillator Clock .....................................................................91
10.1.4
PLL Clock ...........................................................................................91
10.2
CPU Clock and Peripheral Function Clock................................................93
10.2.1
CPU Clock and BCLK.........................................................................93
10.2.2
Peripheral Function Clock (f1, f2, f8, f32, f1SIO, f2SIO, f8SIO,
f32SIO, fAD, fC32)..............................................................................93
10.3
Clock Output Function...............................................................................93
10.4
Power Control............................................................................................94
10.4.1
Normal Operating Mode .....................................................................94
10.4.2
Wait Mode ..........................................................................................96
10.4.3
Stop Mode ..........................................................................................98
10.5
System Clock Protection Function ..........................................................102
10.6
Oscillation Stop and Re-oscillation Detect Function................................103
10.6.1
Operation When CM27 bit = 0 (Oscillation Stop Detection Reset) ...103
10.6.2
Operation When CM27 bit = 0 (Oscillation Stop and Re-oscillation
Detect Interrupt)................................................................................103
10.6.3
How to Use Oscillation Stop and Re-oscillation Detect Function .....104
11. Protection
105
12. Interrupt
106
12.1
Type of Interrupts ....................................................................................106
12.2
Software Interrupts ..................................................................................107
12.2.1
Undefined Instruction Interrupt .........................................................107
12.2.2
Overflow Interrupt .............................................................................107
12.2.3
BRK Interrupt....................................................................................107
12.2.4
INT Instruction Interrupt....................................................................107
12.3
Hardware Interrupts.................................................................................108
12.3.1
Special Interrupts..............................................................................108
12.3.2
Peripheral Function Interrupts ..........................................................108
12.4
Interrupts and Interrupt Vector ................................................................109
12.4.1
Fixed Vector Tables..........................................................................109
12.4.2
Relocatable Vector Tables ...............................................................110
A-3
12.5
Interrupt Control ......................................................................................111
12.5.1
I Flag.................................................................................................113
12.5.2
IR Bit.................................................................................................113
12.5.3
ILVL2 to ILVL0 Bits and IPL .............................................................113
12.5.4
Interrupt Sequence ...........................................................................114
12.5.5
Interrupt Response Time ..................................................................115
12.5.6
Variation of IPL when Interrupt Request is Accepted .......................115
12.5.7
Saving Registers ..............................................................................116
12.5.8
Returning from an Interrupt Routine .................................................118
12.5.9
Interrupt Priority ................................................................................118
12.5.10 Interrupt Priority Level Select Circuit ................................................119
12.6
INT Interrupt ............................................................................................120
12.7
NMI Interrupt ...........................................................................................121
12.8
Key Input Interrupt...................................................................................121
12.9
Address Match Interrupt ..........................................................................122
13. Watchdog Timer
13.1
124
Count source protective mode ................................................................125
14. DMAC
14.1
126
Transfer Cycles .......................................................................................132
14.1.1
Effect of Source and Destination Addresses ....................................132
14.1.2
Effect of BYTE Pin Level ..................................................................132
14.1.3
Effect of Software Wait .....................................................................132
14.1.4
Effect of RDY Signal.........................................................................132
14.2
DMA Transfer Cycles ..............................................................................134
14.3
DMA Enable ............................................................................................135
14.4
DMA Request ..........................................................................................135
14.5
Channel Priority and DMA Transfer Timing.............................................136
15. Timers
15.1
137
Timer A....................................................................................................139
15.1.1
Timer Mode ......................................................................................144
15.1.2
Event Counter Mode.........................................................................146
15.1.3
One-shot Timer Mode.......................................................................151
15.1.4
Pulse Width Modulation (PWM) Mode..............................................153
A-4
15.2
Timer B....................................................................................................156
15.2.1
Timer Mode ......................................................................................159
15.2.2
Event Counter Mode.........................................................................160
15.2.3
Pulse Period and Pulse Width Measurement Mode .........................162
16. Three-Phase Motor Control Timer Function
165
17. Serial Interface
176
17.1
UARTi (i=0 to 2) ......................................................................................176
17.1.1
Clock Synchronous Serial I/O Mode.................................................189
17.1.2
Clock Asynchronous Serial I/O (UART) Mode..................................197
17.1.3
Special Mode 1 (I2C mode) ..............................................................205
17.1.4
Special Mode 2.................................................................................215
17.1.5
Special Mode 3 (IE mode) ................................................................220
17.1.6
Special Mode 4 (SIM Mode) (UART2)..............................................222
17.2
SI/O3 and SI/O4 ......................................................................................227
17.2.1
SI/Oi Operation Timing .....................................................................231
17.2.2
CLK Polarity Selection......................................................................231
17.2.3
Functions for Setting an SOUTi Initial Value ....................................232
18. A/D Converter
18.1
233
Mode Description ....................................................................................238
18.1.1
One-Shot Mode ................................................................................238
18.1.2
Repeat Mode ....................................................................................240
18.1.3
Single Sweep Mode..........................................................................242
18.1.4
Repeat Sweep Mode 0 .....................................................................244
18.1.5
Repeat Sweep Mode 1 .....................................................................246
18.2
Function...................................................................................................248
18.2.1
Resolution Select Function...............................................................248
18.2.2
Sample and Hold ..............................................................................248
18.2.3
Extended Analog Input Pins .............................................................248
18.2.4
18.2.4 External Operation Amplifier (Op-Amp) Connection Mode....248
18.2.5
18.2.5 Current Consumption Reducing Function .............................249
18.2.6
Output Impedance of Sensor under A/D Conversion .......................249
A-5
19. D/A Converter
251
20. CRC Calculation
253
21. Programmable I/O Ports
255
21.1
Port Pi Direction Register (PDi Register, i = 0 to 13) ..............................256
21.2
Port Pi Register (Pi Register, i = 0 to 13) ................................................256
21.3
Pull-up Control Register 0 to Pull-up Control Register 3
(PUR0 to PUR3 Registers).....................................................................256
21.4
Port Control Register (PCR Register) .....................................................256
22. Flash Memory Version
22.1
Memory Map ...........................................................................................272
22.1.1
22.2
270
Boot Mode ........................................................................................273
Functions To Prevent Flash Memory from Rewriting ..............................273
22.2.1
ROM Code Protect Function ............................................................273
22.2.2
ID Code Check Function ..................................................................273
22.3
CPU Rewrite Mode..................................................................................275
22.3.1
EW0 Mode........................................................................................276
22.3.2
EW1 Mode........................................................................................276
22.3.3
Flash memory Control Register (FIDR, FMR0 and FMR1 registers)276
22.3.4
Precautions on CPU Rewrite Mode..................................................284
22.3.5
Software Commands .......................................................................286
22.3.6
Data Protect Function.......................................................................291
22.3.7
Status Register .................................................................................291
22.3.8
Full Status Check .............................................................................293
22.4
Standard Serial I/O Mode........................................................................295
22.4.1
ID Code Check Function ..................................................................295
22.4.2
Example of Circuit Application in the Standard Serial I/O Mode ......301
22.5
Parallel I/O Mode.....................................................................................303
22.5.1
User ROM and Boot ROM Areas .....................................................303
22.5.2
ROM Code Protect Function ............................................................303
23. Electrical Characteristics
304
23.1
Electrical Characteristics (M16C/62P).....................................................304
23.2
Electrical Characteristics (M16C/62PT) ..................................................346
A-6
24. Precautions
24.1
359
SFR .........................................................................................................359
24.1.1
Register Settings ..............................................................................359
24.2
Reset .......................................................................................................360
24.3
Bus ..........................................................................................................361
24.4
PLL Frequency Synthesizer ....................................................................362
24.5
Power Control..........................................................................................363
24.6
Protect .....................................................................................................365
24.7
Interrupt ...................................................................................................366
24.7.1
Reading address 00000h .................................................................366
24.7.2
Setting the SP...................................................................................366
24.7.3
The NMI Interrupt .............................................................................366
24.7.4
Changing the Interrupt Generate Factor...........................................367
24.7.5
INT Interrupt .....................................................................................367
24.7.6
Rewrite the Interrupt Control Register ..............................................368
24.7.7
Watchdog Timer Interrupt.................................................................368
24.8
DMAC......................................................................................................369
24.8.1
24.9
Write to DMAE Bit in DMiCON Register ...........................................369
Timers .....................................................................................................370
24.9.1
Timer A .............................................................................................370
24.9.2
Timer B .............................................................................................372
24.10 Serial interface ........................................................................................373
24.10.1 Clock Synchronous Serial I/O...........................................................373
24.10.2 UART................................................................................................374
24.10.3 SI/O3, SI/O4 .....................................................................................374
24.11 A/D Converter..........................................................................................375
24.12 Programmable I/O Ports..........................................................................377
24.13 Electric Characteristic Differences Between Mask ROM
and Flash Memory Version Microcomputers...........................................378
24.14 Mask ROM ..............................................................................................378
24.15 Flash Memory Version ............................................................................379
24.15.1 Functions to Inhibit Rewriting Flash Memory Rewrite ......................379
24.15.2 Stop mode ........................................................................................379
24.15.3 Wait mode ........................................................................................379
24.15.4 Low power dissipation mode, on-chip oscillator low power dissipation mode ....379
24.15.5 Writing command and data...............................................................379
A-7
24.15.6 Program Command ..........................................................................379
24.15.7 Lock Bit Program Command ............................................................379
24.15.8 Operation speed ...............................................................................380
24.15.9 Instructions inhibited against use .....................................................380
24.15.10 Interrupts ..........................................................................................380
24.15.11 How to access ..................................................................................380
24.15.12 Writing in the user ROM area ...........................................................380
24.15.13 DMA transfer ....................................................................................381
24.15.14 Regarding Programming/Erasing Endurance and Execution Time ..381
24.16 Noise .......................................................................................................382
25. Differences Depending on Manufacturing Period
383
Appendix 1. Package Dimensions
385
Appendix 2. Difference between M16C/62P and M16C/30P
387
Register Index
390
A-8
SFR Page Reference
Address
0000h
0001h
0002h
0003h
0004h
0005h
0006h
0007h
0008h
0009h
000Ah
000Bh
000Ch
000Dh
000Eh
000Fh
0010h
0011h
0012h
0013h
0014h
0015h
0016h
0017h
0018h
0019h
001Ah
001Bh
001Ch
001Dh
001Eh
001Fh
0020h
0021h
0022h
0023h
0024h
0025h
0026h
0027h
0028h
0029h
002Ah
002Bh
002Ch
002Dh
002Eh
002Fh
0030h
0031h
0032h
0033h
0034h
0035h
0036h
0037h
0038h
0039h
003Ah
003Bh
003Ch
003Dh
003Eh
003Fh
Register
Symbol
Page
Processor Mode Register 0
Processor Mode Register 1
System Clock Control Register 0
System Clock Control Register 1
Chip Select Control Register
Address Match Interrupt Enable Register
Protect Register
Data Bank Register
Oscillation Stop Detection Register
PM0
PM1
CM0
CM1
CSR
AIER
PRCR
DBR
CM2
56
57
84
85
61
123
105
73
86
Watchdog Timer Start Register
Watchdog Timer Control Register
Address Match Interrupt Register 0
WDTS
WDC
RMAD0
125
53, 125
123
Address Match Interrupt Register 1
RMAD1
123
Voltage Detection Register 1
Voltage Detection Register 2
Chip Select Expansion Control Register
PLL Control Register 0
VCR1
VCR2
CSE
PLC0
46
46
68
88
Processor Mode Register 2
Low Voltage Detection Interrupt Register
DMA0 Source Pointer
PM2
D4INT
SAR0
87
47
131
DMA0 Destination Pointer
DAR0
131
DMA0 Transfer Counter
TCR0
131
DMA0 Control Register
DM0CON
130
DMA1 Source Pointer
SAR1
131
DMA1 Destination Pointer
DAR1
131
DMA1 Transfer Counter
TCR1
131
DMA1 Control Register
DM1CON
130
NOTES:
1. Blank columns are all reserved space. No access is allowed.
Address
0040h
0041h
0042h
0043h
0044h
0045h
0046h
0047h
0048h
0049h
004Ah
004Bh
004Ch
004Dh
004Eh
004Fh
0050h
0051h
0052h
0053h
0054h
0055h
0056h
0057h
0058h
0059h
005Ah
005Bh
005Ch
005Dh
005Eh
005Fh
0060h
0061h
0062h
0062h
0064h
0065h
0066h
0067h
0068h
0069h
006Ah
006Bh
006Ch
006Dh
006Eh
006Fh
0070h
0071h
0072h
0073h
0074h
0075h
0076h
0077h
0078h
0079h
007Ah
007Bh
007Ch
007Dh
007Eh
007Fh
B-1
Register
INT3 Interrupt Control Register
Timer B5 Interrupt Control Register
Timer B4 Interrupt Control Register, UART1 BUS
Collision Detection Interrupt Control Register
Timer B3 Interrupt Control Register, UART0 BUS
Collision Detection Interrupt Control Register
SI/O4 Interrupt Control Register, INT5 Interrupt
Control Register
SI/O3 Interrupt Control Register, IINT4 Interrupt
Control Register
UART2 Bus Collision Detection Interrupt Control Register
DMA0 Interrupt Control Register
DMA1 Interrupt Control Register
Key Input Interrupt Control Register
A/D Conversion Interrupt Control Register
UART2 Transmit Interrupt Control Register
UART2 Receive Interrupt Control Register
UART0 Transmit Interrupt Control Register
UART0 Receive Interrupt Control Register
UART1 Transmit Interrupt Control Register
UART1 Receive Interrupt Control Register
Timer A0 Interrupt Control Register
Timer A1 Interrupt Control Register
Timer A2 Interrupt Control Register
Timer A3 Interrupt Control Register
Timer A4 Interrupt Control Register
Timer B0 Interrupt Control Register
Timer B1 Interrupt Control Register
Timer B2 Interrupt Control Register
INT0 Interrupt Control Register
INT1 Interrupt Control Register
INT2 Interrupt Control Register
Symbol
INT3IC
TB5IC
TB4IC,
U1BCNIC
TB3IC,
U0BCNIC
S4IC,
INT5IC
S3IC,
INT4IC
BCNIC
DM0IC
DM1IC
KUPIC
ADIC
S2TIC
S2RIC
S0TIC
S0RIC
S1TIC
S1RIC
TA0IC
TA1IC
TA2IC
TA3IC
TA4IC
TB0IC
TB1IC
TB2IC
INT0IC
INT1IC
INT2IC
Page
112
111
111
111
112
112
111
111
111
111
111
111
111
111
111
111
111
111
111
111
111
111
111
111
111
112
112
112
Address
0080h
0081h
0082h
0083h
0084h
0085h
0086h
0087h
to
01AFh
01B0h
01B2h
01B3h
01B4h
01B5h
01B6h
01B7h
01B8h
01B9h
01BAh
01BBh
01BCh
01BDh
01BEh
01BFh
01C0h
to
02AFh
0250h
0251h
0252h
0253h
0254h
0255h
0256h
0257h
0258h
0259h
025Ah
025Bh
025Ch
025Dh
025Eh
025Fh
0260h
0261h
0262h
0263h
0264h
0265h
0266h
0267h
0268h
0269h
026Ah
to
0335h
0336h
0337h
0338h
0339h
033Ah
033Bh
033Ch
033Dh
033Eh
033Fh
Register
Symbol
Page
Flash Identification Register
Flash Memory Control Register 1
FIDR
FMR1
276
278
Flash Memory Control Register 0
Address Match Interrupt Register 2
FMR0
RMAD2
277
123
Address Match Interrupt Enable Register 2
Address Match Interrupt Register 3
AIER2
RMAD3
123
123
Peripheral Clock Select Register
PCLKR
87
Address
0340h
0341h
0342h
0343h
0344h
0345h
0346h
0347h
0348h
0349h
034Ah
034Bh
034Ch
034Dh
034Eh
034Fh
0350h
0351h
0352h
0353h
0354h
0355h
0356h
0357h
0358h
0359h
035Ah
035Bh
035Ch
035Dh
035Eh
035Fh
0360h
0361h
0362h
0363h
0364h
0365h
0366h
0367h
0368h
0369h
036Ah
036Bh
036Ch
036Dh
036Eh
036Fh
0370h
0371h
0372h
0373h
0374h
0375h
0376h
0377h
0378h
0379h
037Ah
037Bh
037Ch
037Dh
037Eh
037Fh
Register
Timer B3, 4, 5 Count Start Flag
Symbol
TBSR
Page
158
Timer A1-1 Register
TA11
169
Timer A2-1 Register
TA21
169
Timer A4-1 Register
TA41
169
Three-Phase PWM Control Register 0
Three-Phase PWM Control Register 1
Three-Phase Output Buffer Register 0
Three-Phase Output Buffer Register 1
Dead Time Timer
Timer B2 Interrupt Occurrence Frequency Set
Counter
INVC0
INVC1
IDB0
IDB1
DTT
ICTB2
167
168
170
170
171
169
Timer B3 Register
TB3
157
Timer B4 Register
TB4
157
Timer B5 Register
TB5
157
Timer B3 Mode Register
Timer B4 Mode Register
Timer B5 Mode Register
Interrupt Factor Select Register 2
Interrupt Factor Select Register
SI/O3 Transmit/Receive Register
TB3MR
TB4MR
TB5MR
IFSR2A
IFSR
S3TRR
157
157
157
120
120
229
SI/O3 Control Register
SI/O3 Bit Rate Generator
SI/O4 Transmit/Receive Register
S3C
S3BRG
S4TRR
228
229
229
SI/O4 Control Register
SI/O4 Bit Rate Generator
S4C
S4BRG
228
229
UART0 Special Mode Register 4
UART0 Special Mode Register 3
UART0 Special Mode Register 2
UART0 Special Mode Register
UART1 Special Mode Register 4
UART1 Special Mode Register 3
UART1 Special Mode Register 2
UART1 Special Mode Register
UART2 Special Mode Register 4
UART2 Special Mode Register 3
UART2 Special Mode Register 2
UART2 Special Mode Register
UART2 Transmit/Receive Mode Register
UART2 Bit Rate Generator
UART2 Transmit Buffer Register
U0SMR4
U0SMR3
U0SMR2
U0SMR
U1SMR4
U1SMR3
U1SMR2
U1SMR
U2SMR4
U2SMR3
U2SMR2
U2SMR
U2MR
U2BRG
U2TB
188
187
187
186
188
187
187
186
188
187
187
186
183
182
181
UART2 Transmit/Receive Control Register 0
UART2 Transmit/Receive Control Register 1
UART2 Receive Buffer Register
U2C0
U2C1
U2RB
184
185
181
NOTES:
1. Blank columns are all reserved space. No access is allowed.
B-2
Address
0380h
0381h
0382h
0383h
0384h
0385h
0386h
0387h
0388h
0389h
038Ah
038Bh
038Ch
038Dh
038Eh
038Fh
0390h
0391h
0392h
0393h
0394h
0395h
0396h
0397h
0398h
0399h
039Ah
039Bh
039Ch
039Dh
039Eh
039Fh
03A0h
03A1h
03A2h
03A3h
03A4h
03A5h
03A6h
03A7h
03A8h
03A9h
03AAh
03ABh
03ACh
03ADh
03AEh
03AFh
03B0h
03B1h
03B2h
03B3h
03B4h
03B5h
03B6h
03B7h
03B8h
03B9h
03BAh
03BBh
03BCh
03BDh
03BEh
03BFh
Register
Count Start Flag
Clock Prescaler Reset Fag
One-Shot Start Flag
Trigger Select Register
Up-Down Flag
Symbol
TABSR
CPSRF
ONSF
TRGSR
UDF
Page
141, 158
143, 158
142
142
141
Timer A0 Register
TA0
140
Timer A1 Register
TA1
140
Timer A2 Register
TA2
140
Timer A3 Register
TA3
140
Timer A4 Register
TA4
140
Timer B0 Register
TB0
157
Timer B1 Register
TB1
157
Timer B2 Register
TB2
157
Timer A0 Mode Register
Timer A1 Mode Register
Timer A2 Mode Register
Timer A3 Mode Register
Timer A4 Mode Register
Timer B0 Mode Register
Timer B1 Mode Register
Timer B2 Mode Register
Timer B2 Special Mode Register
TA0MR
TA1MR
TA2MR
TA3MR
TA4MR
TB0MR
TB1MR
TB2MR
TB2SC
140
140
140
140
140
157
157
157
170
UART0 Transmit/Receive Mode Register
UART0 Bit Rate Generator
UART0 Transmit Buffer Register
U0MR
U0BRG
U0TB
183
182
181
UART0 Transmit/Receive Control Register 0
UART0 Transmit/Receive Control Register 1
UART0 Receive Buffer Register
U0C0
U0C1
U0RB
184
185
181
UART1 Transmit/Receive Mode Register
UART1 Bit Rate Generator
UART1 Transmit Buffer Register
U1MR
U1BRG
U1TB
183
182
181
UART1 Transmit/Receive Control Register 0
UART1 Transmit/Receive Control Register 1
UART1 Receive Buffer Register
U1C0
U1C1
U1RB
184
185
181
UART Transmit/Receive Control Register 2
UCON
186
DMA0 Request Factor Select Register
DM0SL
128
DMA1 Request Factor Select Register
DM1SL
129
CRC Data Register
CRCD
253
CRC Input Register
CRCIN
253
Address
03C0h
03C1h
03C2h
03C3h
03C4h
03C5h
03C6h
03C7h
03C8h
03C9h
03CAh
03CBh
03CCh
03CDh
03CEh
03CFh
03D0h
03D1h
03D2h
03D3h
03D4h
03D5h
03D6h
03D7h
03D8h
03D9h
03DAh
03DBh
03DCh
03DDh
03DEh
03DFh
03E0h
03E1h
03E2h
03E3h
03E4h
03E5h
03E6h
03E7h
03E8h
03E9h
03EAh
03EBh
03ECh
03EDh
03EEh
03EFh
03F0h
03F1h
03F2h
03F3h
03F4h
03F5h
03F6h
03F7h
03F8h
03F9h
03FAh
03FBh
03FCh
03FDh
03FEh
03FFh
A/D Register 0
Register
Symbol
AD0
Page
237
A/D Register 1
AD1
237
A/D Register 2
AD2
237
A/D Register 3
AD3
237
A/D Register 4
AD4
237
A/D Register 5
AD5
237
A/D Register 6
AD6
237
A/D Register 7
AD7
237
A/D Control Register 2
ADCON2
236
A/D Control Register 0
A/D Control Register 1
D/A Register 0
ADCON0
ADCON1
DA0
235
235
252
D/A Register 1
DA1
252
D/A Control Register
DACON
252
Port P14 Control Register
Pull-Up Control Register 3
Port P0 Register
Port P1 Register
Port P0 Direction Register
Port P1 Direction Register
Port P2 Register
Port P3 Register
Port P2 Direction Register
Port P3 Direction Register
Port P4 Register
Port P5 Register
Port P4 Direction Register
Port P5 Direction Register
Port P6 Register
Port P7 Register
Port P6 Direction Register
Port P7 Direction Register
Port P8 Register
Port P9 Register
Port P8 Direction Register
Port P9 Direction Register
Port P10 Register
Port P11 Register
Port P10 Direction Register
Port P11 Direction Register
Port P12 Register
Port P13 Register
Port P12 Direction Register
Port P13 Direction Register
Pull-Up Control Register 0
Pull-Up Control Register 1
Pull-Up Control Register 2
Port Control Register
PC14
PUR3
P0
P1
PD0
PD1
P2
P3
PD2
PD3
P4
P5
PD4
PD5
P6
P7
PD6
PD7
P8
P9
PD8
PD9
P10
P11
PD10
PD11
P12
P13
PD12
PD13
PUR0
PUR1
PUR2
PCR
264
264
263
263
262
262
263
263
262
262
263
263
262
262
263
263
262
262
263
263
262
262
263
263
262
262
263
263
262
262
265
265
266
266
NOTES:
1. Blank columns are all reserved space. No access is allowed.
B-3
M16C/62P Group (M16C/62P, M16C/62PT)
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
1.
Overview
The M16C/62P Group (M16C/62P, M16C/62PT) of single-chip microcomputers are built using the high performance
silicon gate CMOS process using a M16C/60 Series CPU core and are packaged in a 80-pin, 100-pin and 128-pin
plastic molded QFP. These single-chip microcomputers operate using sophisticated instructions featuring a high level
of instruction efficiency. With 1M bytes of address space, they are capable of executing instructions at high speed. In
addition, this microcomputer contains a multiplier and DMAC which combined with fast instruction processing
capability, makes it suitable for control of various OA, communication, and industrial equipment which requires highspeed arithmetic/logic operations.
1.1
Applications
Audio, cameras, television, home appliance, office/communications/portable/industrial equipment, automobile,
etc.
Specifications written in this manual are believed to be accurate,
but are not guaranteed to be entirely free of error. Specifications in
this manual may be changed for functional or performance
improvements. Please make sure your manual is the latest edition.
Rev.2.41 Jan 10, 2006
REJ09B0185-0241
Page 1 of 390
M16C/62P Group (M16C/62P, M16C/62PT)
1.2
1. Overview
Performance Outline
Table 1.1 to 1.3 list Performance Outline of M16C/62P Group (M16C/62P, M16C/62PT)(128-pin version).
Table 1.1
Performance Outline of M16C/62P Group (M16C/62P, M16C/62PT)(128-pin version)
Item
CPU
Peripheral
Function
Number of Basic Instructions
Minimum Instruction Execution
Time
Operating Mode
Address Space
91 instructions
41.7ns(f(BCLK)=24MHz, VCC1=3.3 to 5.5V)
100ns(f(BCLK)=10MHz, VCC1=2.7 to 5.5V)
Single-chip, memory expansion and microprocessor mode
Memory Capacity
See Table 1.4 to 1.5 Product List
Port
Multifunction Timer
Input/Output : 113 pins, Input : 1 pin
Timer A : 16 bits x 5 channels,
Timer B : 16 bits x 6 channels,
Three phase motor control circuit
3 channels
Clock synchronous, UART, I2C bus(1), IEBus(2)
2 channels
Clock synchronous
10-bit A/D converter: 1 circuit, 26 channels
8 bits x 2 channels
2 channels
CCITT-CRC
15 bits x 1 channel (with prescaler)
Internal: 29 sources, External: 8 sources, Software: 4 sources,
Priority level: 7 levels
4 circuits
Main clock generation circuit (*),
Subclock generation circuit (*),
On-chip oscillator, PLL synthesizer
(*)Equipped with a built-in feedback resistor.
Stop detection of main clock oscillation, re-oscillation detection
function
Available (option(4))
VCC1=3.0 to 5.5 V, VCC2=2.7V to VCC1 (f(BCLK=24MHz)
VCC1=2.7 to 5.5 V, VCC2=2.7V to VCC1 (f(BCLK=10MHz)
14 mA (VCC1=VCC2=5V, f(BCLK)=24MHz)
8 mA (VCC1=VCC2=3V, f(BCLK)=10MHz)
1.8µA (VCC1=VCC2=3V, f(XCIN)=32kHz, wait mode)
0.7µA (VCC1=VCC2=3V, stop mode)
3.3±0.3 V or 5.0±0.5 V
100 times (all area)
or 1,000 times (user ROM area without block A and block 1)
/ 10,000 times (block A, block 1) (3)
-20 to 85°C,
-40 to 85°C (3)
128-pin plastic mold LQFP
Serial Interface
A/D Converter
D/A Converter
DMAC
CRC Calculation Circuit
Watchdog Timer
Interrupt
Clock Generation Circuit
Electric
Characteristics
Oscillation Stop Detection
Function
Voltage Detection Circuit
Supply Voltage
Power Consumption
Flash memory
version
Performance
M16C/62P
Program/Erase Supply Voltage
Program and Erase Endurance
Operating Ambient Temperature
Package
1 Mbyte (Available to 4 Mbytes by memory space expansion
function)
NOTES:
1. I2C bus is a registered trademark of Koninklijke Philips Electronics N. V.
2. IEBus is a registered trademark of NEC Electronics Corporation.
3. See Table 1.8 Product Code for the program and erase endurance, and operating ambient temperature.
In addition 1,000 times/10,000 times are under development as of Jul., 2005. Please inquire about a release
schedule.
4. All options are on request basis.
Rev.2.41 Jan 10, 2006
REJ09B0185-0241
Page 2 of 390
M16C/62P Group (M16C/62P, M16C/62PT)
Table 1.2
Performance Outline of M16C/62P Group (M16C/62P, M16C/62PT)(100-pin version)
Item
CPU
1. Overview
Number of Basic Instructions
Minimum Instruction
Execution Time
Operating Mode
Performance
M16C/62P
M16C/62PT(4)
91 instructions
41.7ns(f(BCLK)=24MHz, VCC1=3.3 to 5.5V) 41.7ns(f(BCLK)=24MHz, VCC1=4.0 to 5.5V)
100ns(f(BCLK)=10MHz, VCC1=2.7 to 5.5V)
Single-chip, memory expansion
Single-chip
and microprocessor mode
Address Space
1 Mbyte (Available to 4 Mbytes by 1 Mbyte
memory space expansion function)
Memory Capacity
See Table 1.4 to 1.7 Product List
Peripheral
Port
Input/Output : 87 pins, Input : 1 pin
Function
Multifunction Timer
Timer A : 16 bits x 5 channels, Timer B : 16 bits x 6 channels,
Three phase motor control circuit
Serial Interface
3 channels
Clock synchronous, UART, I2C bus(1), IEBus(2)
2 channels
Clock synchronous
A/D Converter
10-bit A/D converter: 1 circuit, 26 channels
D/A Converter
8 bits x 2 channels
DMAC
2 channels
CRC Calculation Circuit CCITT-CRC
Watchdog Timer
15 bits x 1 channel (with prescaler)
Internal: 29 sources, External: 8 sources, Software: 4 sources, Priority level: 7 levels
Interrupt
Clock Generation Circuit 4 circuits
Main clock generation circuit (*), Subclock generation circuit (*),
On-chip oscillator, PLL synthesizer
(*)Equipped with a built-in feedback resistor.
Oscillation Stop
Stop detection of main clock oscillation, re-oscillation detection function
Detection Function
Absent
Voltage Detection Circuit Available (option (5))
Electric
Supply Voltage
VCC1=3.0 to 5.5 V, VCC2=2.7V to VCC1=VCC2=4.0 to 5.5V
Characteristics
VCC1 (f(BCLK=24MHz)
(f(BCLK=24MHz)
VCC1=2.7 to 5.5 V, VCC2=2.7V to
VCC1 (f(BCLK=10MHz)
14 mA (VCC1=VCC2=5V, f(BCLK)=24MHz) 14 mA (VCC1=VCC2=5V, f(BCLK)=24MHz)
Power Consumption
8 mA (VCC1=VCC2=3V, f(BCLK)=10MHz) 2.0µA (VCC1=VCC2=5V, f(XCIN)=32kHz,
wait mode)
1.8µA (VCC1=VCC2=3V, f(XCIN)=32kHz,
wait mode)
0.8µA (VCC1=VCC2=5V, stop mode)
0.7µA (VCC1=VCC2=3V, stop mode)
Flash memory Program/Erase Supply Voltage 3.3±0.3 V or 5.0±0.5 V
5.0±0.5 V
version
Program and Erase
100 times (all area)
Endurance
or 1,000 times (user ROM area without block A and block 1)
/ 10,000 times (block A, block 1) (3)
Operating Ambient Temperature
-20 to 85°C,
T version : -40 to 85°C
V version : -40 to 125°C
-40 to 85°C (3)
Package
100-pin plastic mold QFP, LQFP
NOTES:
1. I2C bus is a registered trademark of Koninklijke Philips Electronics N. V.
2. IEBus is a registered trademark of NEC Electronics Corporation.
3. See Table 1.8 and 1.9 Product Code for the program and erase endurance, and operating ambient
temperature.
In addition 1,000 times/10,000 times are under development as of Jul., 2005. Please inquire about a release
schedule.
4. Use the M16C/62PT on VCC1=VCC2
5. All options are on request basis.
Rev.2.41 Jan 10, 2006
REJ09B0185-0241
Page 3 of 390
M16C/62P Group (M16C/62P, M16C/62PT)
Table 1.3
Performance Outline of M16C/62P Group (M16C/62P, M16C/62PT)(80-pin version)
Item
CPU
1. Overview
Number of Basic Instructions
Minimum Instruction
Execution Time
Operating Mode
Address Space
Performance
M16C/62P
M16C/62PT(4)
91 instructions
41.7ns(f(BCLK)=24MHz, VCC1=3.3 to 5.5V) 41.7ns(f(BCLK)=24MHz, VCC1=4.0 to 5.5V)
100ns(f(BCLK)=10MHz, VCC1=2.7 to 5.5V)
Single-chip mode
1 Mbyte
See Table 1.4 to 1.7 Product List
Peripheral
Port
Input/Output : 70 pins, Input : 1 pin
Function
Multifunction Timer
Timer A : 16 bits x 5 channels (Timer A1 and A2 are internal timer),
Timer B : 16 bits x 6 channels (Timer B1 is internal timer)
Serial Interface
2 channels
Clock synchronous, UART, I2C bus(1), IEBus(2)
1 channel
Clock synchronous, I2C bus(1), IEBus(2)
2 channels
Clock synchronous (1 channel is only transmission)
A/D Converter
10-bit A/D converter: 1 circuit, 26 channels
D/A Converter
8 bits x 2 channels
DMAC
2 channels
CRC Calculation Circuit CCITT-CRC
Watchdog Timer
15 bits x 1 channel (with prescaler)
Internal: 29 sources, External: 5 sources, Software: 4 sources, Priority level: 7 levels
Interrupt
Clock Generation Circuit 4 circuits
Main clock generation circuit (*), Subclock generation circuit (*),
On-chip oscillator, PLL synthesizer
(*)Equipped with a built-in feedback resistor.
Oscillation Stop
Stop detection of main clock oscillation, re-oscillation detection function
Detection Function
Absent
Voltage Detection Circuit Available (option (4))
Electric
Supply Voltage
VCC1=3.0 to 5.5 V, (f(BCLK=24MHz)
VCC1=4.0 to 5.5V, (f(BCLK=24MHz)
Characteristics
VCC1=2.7 to 5.5 V, (f(BCLK=10MHz)
Power Consumption
14 mA (VCC1=5V, f(BCLK)=24MHz)
14 mA (VCC1=5V, f(BCLK)=24MHz)
8 mA (VCC1=3V, f(BCLK)=10MHz)
2.0µA (VCC1=5V, f(XCIN)=32kHz,
wait mode)
1.8µA (VCC1=3V, f(XCIN)=32kHz,
0.8µA (VCC1=5V, stop mode)
wait mode)
0.7µA (VCC1=3V, stop mode)
5.0 ± 0.5V
Flash memory Program/Erase Supply Voltage 3.3 ± 0.3V or 5.0 ± 0.5V
version
Program and Erase
100 times (all area)
Endurance
or 1,000 times (user ROM area without block A and block 1)
/ 10,000 times (block A, block 1) (3)
Operating Ambient Temperature
-20 to 85°C,
T version : -40 to 85°C
V version : -40 to 125°C
-40 to 85°C (3)
Memory Capacity
Package
80-pin plastic mold QFP
NOTES:
1. I2C bus is a registered trademark of Koninklijke Philips Electronics N. V.
2. IEBus is a registered trademark of NEC Electronics Corporation.
3. See Table 1.8 and 1.9 Product Code for the program and erase endurance, and operating ambient
temperature.
In addition 1,000 times/10,000 times are under development as of Jul., 2005. Please inquire about a release
schedule.
4. All options are on request basis.
Rev.2.41 Jan 10, 2006
REJ09B0185-0241
Page 4 of 390
M16C/62P Group (M16C/62P, M16C/62PT)
1.3
1. Overview
Block Diagram
Figure 1.1 is a M16C/62P Group (M16C/62P, M16C/62PT) 128-pin and 100-pin version Block Diagram,
Figure 1.2 is a M16C/62P Group (M16C/62P, M16C/62PT) 80-pin version Block Diagram.
8
8
Port P0
8
Port P1
8
Port P2
8
Port P3
8
Port P5
Port P4
A/D converter
System clock
generation circuit
(10 bits X 8 channels
Output (timer A): 5
Input (timer B): 6
UART or
clock synchronous serial I/O
XIN-XOUT
XCIN-XCOUT
PLL frequency synthesizer
On-chip oscillator
Clock synchronous serial I/O
(8 bits X 2 channels)
M16C/60 series16-bit CPU core
SB
R0L
R1L
R2
R3
DMAC
ISP
INTB
D/A converter
PC
FLG
Multiplier
<VCC1 ports>(4)
8
<VCC2 ports>(4)
Port P14
(3)
Port P12
(3)
2
8
(8 bits X 2 channels)
Port P11
RAM (2)
Port P10
A0
A1
FB
(2 channels)
ROM (1)
USP
8
(15 bits)
Port P9
R0H
R1H
Watchdog timer
Memory
Port P8_5
CRC arithmetic circuit (CCITT )
(Polynomial : X16+X12+X5+1)
<VCC1 ports> (4)
(8 bits X 3 channels)
Three-phase motor
control circuit
7
Expandable up to 26 channels)
Port P8
Timer (16-bit)
8
Internal peripheral functions
Port P6
<VCC1 ports>(4)
Port P7
<VCC2 ports>(4)
8
Port P13
(3)
8
(3)
8
NOTES :
1. ROM size depends on microcomputer type.
2. RAM size depends on microcomputer type.
3. Ports P11 to P14 exist only in 128-pin version.
4. Use M16C/62PT on VCC1= VCC2.
Figure 1.1
M16C/62P Group (M16C/62P, M16C/62PT) 128-pin and 100-pin version Block Diagram
Rev.2.41 Jan 10, 2006
REJ09B0185-0241
Page 5 of 390
M16C/62P Group (M16C/62P, M16C/62PT)
1. Overview
8
8
Port P0
8
Port P2
Port P3
4
8
Port P4
Port P5
8
Port P6
Internal peripheral functions
Timer (16-bit)
Expandable up to 26 channels)
XIN-XOUT
XCIN-XCOUT
PLL frequency synthesizer
On-chip oscillator
UART or
clock synchronous serial I/O (2 channels)
UART
(1 channel)
(3)
Watchdog timer
M16C/60 series16-bit CPU core
R0H
R1H
R0L
R1L
DMAC
(2 channels)
D/A converter
(8 bits X 2 channels)
ISP
INTB
ROM (1)
RAM (2)
PC
FLG
8
Multiplier
Port P10
A0
A1
FB
USP
Memory
7
R2
R3
SB
Port P9
(15 bits)
(4)
(8 bits X 2 channels)
Port P8_5
Clock synchronous serial I/O
CRC arithmetic circuit (CCITT )
(Polynomial : X16+X12+X5+1)
7
Port P8
Output (timer A): 5
Input (timer B): 6
System clock
generation circuit
A/D converter
(10 bits X 8 channels
4
Port P7
(4)
NOTES :
1. ROM size depends on microcomputer type.
2. RAM size depends on microcomputer type.
3. To use a UART2, set the CRD bit in the U2C0 register to “1” (CTS/RTS function disabled).
4. There is no external connections for port P1, P4_4 to P4_7, P7_2 to P7_5 and P9_1 in 80-pin version.
Set the direction bits in these ports to “1” (output mode), and set the output data to “0” (“L”) using the program.
Figure 1.2
M16C/62P Group (M16C/62P, M16C/62PT) 80-pin version Block Diagram
Rev.2.41 Jan 10, 2006
REJ09B0185-0241
Page 6 of 390
M16C/62P Group (M16C/62P, M16C/62PT)
1.4
1. Overview
Product List
Table 1.4 to 1.7 list the product list, Figure 1.3 shows the Type No., Memory Size, and Package, Table 1.8 lists the
Product Code of Flash Memory version and ROMless version for M16C/62P, and Table 1.9 lists the Product Code
of Flash Memory version for M16C/62PT. Figure 1.4 shows the Marking Diagram of Flash Memory version and
ROM-less version for M16C/62P (Top View), and Figure 1.5 shows the Marking Diagram of Flash Memory
version for M16C/62PT (Top View) at the time of ROM order.
Table 1.4
Product List (1) (M16C/62P)
Type No.
M30622M6P-XXXFP
M30622M6P-XXXGP
M30622M8P-XXXFP
M30622M8P-XXXGP
M30623M8P-XXXGP
M30622MAP-XXXFP
M30622MAP-XXXGP
M30623MAP-XXXGP
M30620MCP-XXXFP
M30620MCP-XXXGP
M30621MCP-XXXGP
M30622MEP-XXXFP
M30622MEP-XXXGP
M30623MEP-XXXGP
M30622MGP-XXXFP
M30622MGP-XXXGP
M30623MGP-XXXGP
M30624MGP-XXXFP
M30624MGP-XXXGP
M30625MGP-XXXGP
M30622MWP-XXXFP
M30622MWP-XXXGP
M30623MWP-XXXGP
M30624MWP-XXXFP
M30624MWP-XXXGP
M30625MWP-XXXGP
M30626MWP-XXXFP
M30626MWP-XXXGP
M30627MWP-XXXGP
ROM Capacity RAM Capacity Package Type
48 Kbytes
4 Kbytes
PRQP0100JB-A
PLQP0100KB-A
64 Kbytes
4 Kbytes
PRQP0100JB-A
PLQP0100KB-A
PRQP0080JA-A
96 Kbytes
5 Kbytes
PRQP0100JB-A
PLQP0100KB-A
PRQP0080JA-A
128 Kbytes
10 Kbytes
PRQP0100JB-A
PLQP0100KB-A
PRQP0080JA-A
192 Kbytes
12 Kbytes
PRQP0100JB-A
PLQP0100KB-A
PLQP0128KB-A
256 Kbytes
12 Kbytes
PRQP0100JB-A
PLQP0100KB-A
PLQP0128KB-A
20 Kbytes
PRQP0100JB-A
PLQP0100KB-A
PLQP0128KB-A
320 Kbytes
16 Kbytes
PRQP0100JB-A
PLQP0100KB-A
PLQP0128KB-A
24 Kbytes
PRQP0100JB-A
PLQP0100KB-A
PLQP0128KB-A
31 Kbytes
PRQP0100JB-A
PLQP0100KB-A
PLQP0128KB-A
(D): Under development
NOTES:
1. The old package type numbers of each package type are as follows.
PLQP0128KB-A : 128P6Q-A,
PRQP0100JB-A : 100P6S-A,
PLQP0100KB-A : 100P6Q-A,
PRQP0080JA-A : 80P6S-A
Rev.2.41 Jan 10, 2006
REJ09B0185-0241
As of Dec. 2005
(1)
Page 7 of 390
Remarks
Mask ROM version
M16C/62P Group (M16C/62P, M16C/62PT)
Table 1.5
1. Overview
Product List (2) (M16C/62P)
Type No.
M30622MHP-XXXFP
M30622MHP-XXXGP
M30623MHP-XXXGP
M30624MHP-XXXFP
M30624MHP-XXXGP
M30625MHP-XXXGP
M30626MHP-XXXFP
M30626MHP-XXXGP
M30627MHP-XXXGP
M30626MJP-XXXFP
M30626MJP-XXXGP
M30627MJP-XXXGP
M30622F8PFP
M30622F8PGP
M30623F8PGP
M30620FCPFP
M30620FCPGP
M30621FCPGP
M3062LFGPFP(3)
M3062LFGPGP(3)
M30625FGPGP
M30626FHPFP
M30626FHPGP
M30627FHPGP
M30626FJPFP
M30626FJPGP
M30627FJPGP
M30622SPFP
M30622SPGP
M30620SPFP
M30620SPGP
M30624SPFP
M30624SPGP
M30626SPFP
M30626SPGP
ROM Capacity
384 Kbytes
As of Dec. 2005
RAM
Capacity
16 Kbytes
24 Kbytes
31 Kbytes
(D) 512 Kbytes
(D)
(D)
64K+4 Kbytes
31 Kbytes
4 Kbytes
128K+4 Kbytes 10 Kbytes
(D) 256K+4 Kbytes 20 Kbytes
(D)
384K+4 Kbytes 31 Kbytes
512K+4 Kbytes 31 Kbytes
−
4 Kbytes
10 Kbytes
(D) −
(D)
(D)
(D)
20 Kbytes
31 Kbytes
Package Type (1)
PRQP0100JB-A
PLQP0100KB-A
PLQP0128KB-A
PRQP0100JB-A
PLQP0100KB-A
PLQP0128KB-A
PRQP0100JB-A
PLQP0100KB-A
PLQP0128KB-A
PRQP0100JB-A
PLQP0100KB-A
PLQP0128KB-A
PRQP0100JB-A
PLQP0100KB-A
PRQP0080JA-A
PRQP0100JB-A
PLQP0100KB-A
PRQP0080JA-A
PRQP0100JB-A
PLQP0100KB-A
PLQP0128KB-A
PRQP0100JB-A
PLQP0100KB-A
PLQP0128KB-A
PRQP0100JB-A
PLQP0100KB-A
PLQP0128KB-A
PRQP0100JB-A
PLQP0100KB-A
PRQP0100JB-A
PLQP0100KB-A
PRQP0100JB-A
PLQP0100KB-A
PRQP0100JB-A
PLQP0100KB-A
Remarks
Mask ROM version
Flash memory
version (2)
ROM-less version
(D): Under development
NOTES:
1. The old package type numbers of each package type are as follows.
PLQP0128KB-A : 128P6Q-A,
PRQP0100JB-A : 100P6S-A,
PLQP0100KB-A : 100P6Q-A,
PRQP0080JA-A : 80P6S-A
2. In the flash memory version, there is 4K bytes area (block A).
3. Please use M3062LFGPFP and M3062LFGPGP for your new system instead of M30624FGPFP
and M30624FGPGP. The M16C/62P Group (M16C/62P, M16C/62PT) hardware manual is still good
for M30624FGPFP and M30624FGPGP.
M30624FGPFP
M30624FGPGP
Rev.2.41 Jan 10, 2006
REJ09B0185-0241
256K+4 Kbytes 20 Kbytes
Page 8 of 390
PRQP0100JB-A Flash memory version
PLQP0100KB-A
M16C/62P Group (M16C/62P, M16C/62PT)
Table 1.6
1. Overview
Product List (3) (T version (M16C/62PT))
Type No.
M3062CM6T-XXXFP
M3062CM6T-XXXGP
M3062EM6T-XXXGP
M3062CM8T-XXXFP
M3062CM8T-XXXGP
M3062EM8T-XXXGP
M3062CMAT-XXXFP
M3062CMAT-XXXGP
M3062EMAT-XXXGP
M3062AMCT-XXXFP
M3062AMCT-XXXGP
M3062BMCT-XXXGP
M3062CF8TFP
M3062CF8TGP
M3062AFCTFP
M3062AFCTGP
M3062BFCTGP
M3062JFHTFP
M3062JFHTGP
RAM
Package Type (1)
Capacity
(D) 48 Kbytes
4 Kbytes PRQP0100JB-A
(D)
PLQP0100KB-A
(P)
PRQP0080JA-A
(D) 64 Kbytes
4 Kbytes PRQP0100JB-A
(D)
PLQP0100KB-A
(P)
PRQP0080JA-A
(D) 96 Kbytes
5 Kbytes PRQP0100JB-A
(D)
PLQP0100KB-A
(P)
PRQP0080JA-A
(D) 128 Kbytes
10 Kbytes PRQP0100JB-A
(D)
PLQP0100KB-A
(P)
PRQP0080JA-A
(D) 64 K+4 Kbytes 4 Kbytes PRQP0100JB-A
PLQP0100KB-A
(D) 128K+4 Kbytes 10 Kbytes PRQP0100JB-A
(D)
PLQP0100KB-A
(P)
PRQP0080JA-A
(D) 384K+4 Kbytes 31 Kbytes PRQP0100JB-A
(D)
PLQP0100KB-A
ROM Capacity
(D): Under development
(P): Under planning
NOTES:
1. The old package type numbers of each package type are as follows.
PRQP0100JB-A : 100P6S-A,
PLQP0100KB-A : 100P6Q-A,
PRQP0080JA-A : 80P6S-A
2. In the flash memory version, there is 4K bytes area (block A).
Rev.2.41 Jan 10, 2006
REJ09B0185-0241
Page 9 of 390
As of Dec. 2005
Remarks
Mask ROM T Version
version
(High reliability
85°C version)
Flash
memory
version (2)
M16C/62P Group (M16C/62P, M16C/62PT)
Table 1.7
1. Overview
Product List (4) (V version (M16C/62PT))
Type No.
M3062CM6V-XXXFP
M3062CM6V-XXXGP
M3062EM6V-XXXGP
M3062CM8V-XXXFP
M3062CM8V-XXXGP
M3062EM8V-XXXGP
M3062CMAV-XXXFP
M3062CMAV-XXXGP
M3062EMAV-XXXGP
M3062AMCV-XXXFP
M3062AMCV-XXXGP
M3062BMCV-XXXGP
M3062AFCVFP
M3062AFCVGP
M3062BFCVGP
M3062JFHVFP
M3062JFHVGP
RAM
Package Type(1)
Capacity
(P) 48 Kbytes
4 Kbytes PRQP0100JB-A
(P)
PLQP0100KB-A
(P)
PRQP0080JA-A
(P) 64 Kbytes
4 Kbytes PRQP0100JB-A
(P)
PLQP0100KB-A
(P)
PRQP0080JA-A
(P) 96 Kbytes
5 Kbytes PRQP0100JB-A
(P)
PLQP0100KB-A
(P)
PRQP0080JA-A
(D) 128 Kbytes
10 Kbytes PRQP0100JB-A
(D)
PLQP0100KB-A
(P)
PRQP0080JA-A
(D) 128K+4 Kbytes 10 Kbytes PRQP0100JB-A
(D)
PLQP0100KB-A
(P)
PRQP0080JA-A
(P) 384K+4 Kbytes 31 Kbytes PRQP0100JB-A
(P)
PLQP0100KB-A
ROM Capacity
(D): Under development
(P): Under planning
NOTES:
1. The old package type numbers of each package type are as follows.
PLQP0128KB-A : 128P6Q-A,
PRQP0100JB-A : 100P6S-A,
PLQP0100KB-A : 100P6Q-A,
PRQP0080JA-A : 80P6S-A
2. In the flash memory version, there is 4K bytes area (block A).
Rev.2.41 Jan 10, 2006
REJ09B0185-0241
Page 10 of 390
As of Dec. 2005
Remarks
Mask ROM V Version
version
(High reliability
125°C version)
Flash
memory
version (2)
M16C/62P Group (M16C/62P, M16C/62PT)
Type No.
1. Overview
M3062 6 MH P - XXX FP
Package type:
FP : Package
GP : Package
PRQP0100JB-A (100P6S-A)
PRQP0080JA-A (80P6S-A),
PLQP0100KB-A (100P6Q-A),
PLQP0128KB-A (128P6Q-A),
ROM No.
Omitted for flash memory version and
ROMless version
Classification
P : M16C/62P
T : T version (M16C/62PT)
V : V version (M16C/62PT)
ROM capacity:
6: 48 Kbytes
8: 64 Kbytes
A: 96 Kbytes
C: 128 Kbytes
E: 192 Kbytes
G: 256 Kbytes
W: 320 Kbytes
H: 384 Kbytes
J: 512 Kbytes
Memory type:
M: Mask ROM version
F: Flash memory version
S: ROM-less version
Shows RAM capacity, pin count, etc
Numeric, Alphabet (L) : M16C/62P
Alphabet (L is excluded.) : M16C/62PT
M16C/62(P) Group
M16C Family
Figure 1.3
Type No., Memory Size, and Package
Rev.2.41 Jan 10, 2006
REJ09B0185-0241
Page 11 of 390
M16C/62P Group (M16C/62P, M16C/62PT)
Table 1.8
Product Code of Flash Memory version and ROMless version for M16C/62P
Product
Code
Flash memory
Version
1. Overview
D3
D5
Package
Internal ROM
(User ROM Area Without Block A,
Block 1)
Program
and Erase
Endurance
Leadincluded
Temperature
Range
100
Internal ROM
(Block A, Block 1)
Program
and Erase
Endurance
0°C to 60°C
100
0°C to 60°C
1,000
10,000
D9
Lead-free
100
100
-40°C to 85°C
-40°C to 85°C
-20°C to 85°C
-20°C to 85°C
0°C to 60°C
-40°C to 85°C
U5
-20°C to 85°C
U7
1,000
10,000
U9
ROM-less
version
D3
D5
U3
-40°C to 85°C
-20°C to 85°C
D7
U3
Temperature
Range
Operating
Ambient
Temperature
Leadincluded
−
Lead-free
−
−
−
-40°C to 85°C
-40°C to 85°C
-20°C to 85°C
-20°C to 85°C
−
-40°C to 85°C
-20°C to 85°C
−
−
−
U5
-40°C to 85°C
-20°C to 85°C
M1 6 C
M3 0 6 2 6 F H P F P
B D5
XXXXXXX
Type No. (See Figure 1.3 Type No., Memory Size, and Package)
Chip version and product code
B : Shows chip version.
Henceforth, whenever it changes a version, it continues with B, C, and D.
D5 : Shows Product code. (See table 1.8 Product Code)
Date code seven digits
The product without marking of chip version of the flash memory version and the ROMless version
corresponds to the chip version “A”.
Figure 1.4
Marking Diagram of Flash Memory version and ROM-less version for M16C/62P (Top View)
Rev.2.41 Jan 10, 2006
REJ09B0185-0241
Page 12 of 390
M16C/62P Group (M16C/62P, M16C/62PT)
Table 1.9
Product Code of Flash Memory version for M16C/62PT
Product
Code
T Version
Flash
memory
Version
1. Overview
B
V Version
T Version
Package
Leadincluded
B7
Internal ROM
(User ROM Area
Without Block A, Block 1)
Program
and Erase
Endurance
100
Temperature
Range
0°C to 60°C
Internal ROM
(Block A, Block 1)
Program
and Erase
Endurance
100
0°C to 60°C
1,000
10,000
-40°C to 85°C
U
Lead-free
100
100
0°C to 60°C
U7
1,000
10,000
-40°C to 85°C
-40°C to 85°C
-40°C to 125°C -40°C to 125°C
M1 6 C
M3 0 6 2 J F H T F P
Y YY X X X X X X X
Type No. (See Figure 1.3 Type No., Memory Size, and Package)
Date code seven digits
Product code. (See table 1.9 Product Code)
“
” : Product code “B”
“ P B F ” : Product code “U”
“ B 7
” : Product code “B”
“ U 7
” : Product code “U7”
NOTES:
1.
: Blank
Marking Diagram of Flash Memory version for M16C/62PT (Top View)
Rev.2.41 Jan 10, 2006
REJ09B0185-0241
-40°C to 85°C
-40°C to 125°C
V Version
Figure 1.5
-40°C to 85°C
-40°C to 125°C -40°C to 125°C
V Version
T Version
-40°C to 85°C
-40°C to 125°C
V Version
T Version
Temperature
Range
Operating
Ambient
Temperature
Page 13 of 390
M16C/62P Group (M16C/62P, M16C/62PT)
1.5
1. Overview
Pin Configuration
Figures 1.6 to 1.9 show the Pin Configuration (Top View).
102 101 100
P1_0/D8
P0_7/AN0_7/D7
P0_6/AN0_6/D6
P0_5/AN0_5/D5
P0_4/AN0_4/D4
P0_3/AN0_3/D3
P0_2/AN0_2/D2
P0_1/AN0_1/D1
P0_0/AN0_0/D0
P11_7
P11_6
P11_5
P11_4
P11_3
P11_2
P11_1
P11_0
P10_7/AN7/KI3
P10_6/AN6/KI2
P10_5/AN5/KI1
P10_4/AN4/KI0
P10_3/AN3
P10_2/AN2
P10_1/AN1
AVSS
P10_0/AN0
P4_4/CS0
P4_5/CS1
P4_6/CS2
P4_7/CS3
P1_3/D11
P1_4/D12
P1_5/D13/INT3
P1_6/D14/INT4
P1_7/D15/INT5
P2_0/AN2_0/A0(/D0/-)
P2_1/AN2_1/A1(/D1/D0)
P2_2/AN2_2/A2(/D2/D1)
P2_3/AN2_3/A3(/D3/D2)
P2_4/AN2_4/A4(/D4/D3)
P2_5/AN2_5/A5(/D5/D4)
P2_6/AN2_6/A6(/D6/D5)
P2_7/AN2_7/A7(/D7/D6)
VSS
P3_0/A8(/-/D7)
VCC2
P12_0
P12_1
P12_2
P12_3
P12_4
P3_1/A9
P3_2/A10
P3_3/A11
P3_4/A12
P3_5/A13
P3_6/A14
P3_7/A15
P4_0/A16
P4_1/A17
P4_2/A18
P4_3/A19
P1_1/D9
P1_2/D10
PIN CONFIGURATION (top view)
99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65
64
103
104
63
<VCC2> (2)
105
106
62
61
60
59
107
108
109
110
58
57
56
55
54
53
111
112
113
114
M16C/62P Group (M16C/62P)
115
116
52
51
50
49
48
47
117
118
119
120
121
46
45
44
122
123
43
42
41
124
125
126
127
<VCC1> (2)
40
39
128
P12_5
P12_6
P12_7
P5_0/WRL/WR
P5_1/WRH/BHE
P5_2/RD
P5_3/BCLK
P13_0
P13_1
P13_2
P13_3
P5_4/HLDA
P5_5/HOLD
P5_6/ALE
P5_7/RDY/CLKOUT
P13_4
P13_5
P13_6
P13_7
P6_0/CTS0/RTS0
P6_1/CLK0
P6_2/RXD0/SCL0
P6_3/TXD0/SDA0
P6_4/CTS1/RTS1/CTS0/CLKS1
P6_5/CLK1
VSS
NOTES:
1. P7_0 and P7_1 are N channel open-drain output pins.
2. Use the M16C/62PT on VCC1=VCC2.
P7_5/TA2IN/W
P7_4/TA2OUT/W
P7_3/CTS2/RTS2/TA1IN/V
P7_2/CLK2/TA1OUT/V
P7_1/RXD2/SCL2/TA0IN/TB5IN (1)
P7_0/TXD2/SDA2/TA0OUT (1)
P6_7/TXD1/SDA1
VCC1
P6_6/RXD1/SCL1
BYTE
CNVSS
P8_7/XCIN
P8_6/XCOUT
RESET
XOUT
VSS
XIN
VCC1
P8_5/NMI
P8_4/INT2/ZP
P8_3/INT1
P8_2/INT0
P8_1/TA4IN/U
P8_0/TA4OUT/U
P7_7/TA3IN
P7_6/TA3OUT
VREF
AVCC
P9_7/ADTRG/SIN4
P9_6/ANEX1/SOUT4
P9_5/ANEX0/CLK4
P9_4/DA1/TB4IN
P9_3/DA0/TB3IN
P9_2/TB2IN/SOUT3
P9_1/TB1IN/SIN3
P9_0/TB0IN/CLK3
P14_1
P14_0
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38
Package : PLQP0128KB-A (128P6Q-A)
Figure 1.6
Pin Configuration (Top View)
Rev.2.41 Jan 10, 2006
REJ09B0185-0241
Page 14 of 390
M16C/62P Group (M16C/62P, M16C/62PT)
Table 1.10
Pin No.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
1. Overview
Pin Characteristics for 128-Pin Package (1)
Control Pin
Port
Interrupt Pin
Timer Pin
P9_7
P9_6
P9_5
P9_4
P9_3
P9_2
P9_1
P9_0
P14_1
P14_0
BYTE
CNVSS
XCIN
XCOUT
SIN4
SOUT4
CLK4
TB4IN
TB3IN
TB2IN
TB1IN
TB0IN
P8_5
NMI
P8_4
INT2
24
P8_3
INT1
25
P8_2
INT0
26
P8_1
P8_0
P7_7
P7_6
TA4IN/U
TA4OUT/U
TA3IN
TA3OUT
P7_5
P7_4
TA2IN/W
TA2OUT/W
P7_3
P7_2
P7_1
P7_0
P6_7
TA1IN/V
TA1OUT/V
TA0IN/TB5IN
TA0OUT
27
28
29
30
31
32
ZP
CTS2/RTS2
CLK2
RXD2/SCL2
TXD2/SDA2
TXD1/SDA1
VCC1
P6_6
RXD1/SCL1
VSS
P6_5
CLK1
CTS1/RTS1/CTS0/CLKS1
TXD0/SDA0
RXD0/SCL0
CLK0
P6_0
P13_7
P13_6
P13_5
P13_4
CTS0/RTS0
46
47
48
49
50
P5_7
45
ADTRG
ANEX1
ANEX0
DA1
DA0
SOUT3
SIN3
CLK3
P6_4
P6_3
P6_2
P6_1
42
43
44
Bus Control Pin
RESET
XOUT
VSS
XIN
VCC1
23
41
Analog Pin
P8_7
P8_6
22
33
34
35
36
37
38
39
40
UART Pin
VREF
AVCC
Rev.2.41 Jan 10, 2006
REJ09B0185-0241
Page 15 of 390
RDY/CLKOUT
M16C/62P Group (M16C/62P, M16C/62PT)
Table 1.11
Pin No.
1. Overview
Pin Characteristics for 128-Pin Package (2)
Control Pin
Port
Interrupt Pin
Timer Pin
UART Pin
Analog Pin
Bus Control Pin
51
P5_6
ALE
52
P5_5
HOLD
53
HLDA
54
55
56
57
58
P5_4
P13_3
P13_2
P13_1
P13_0
P5_3
59
P5_2
RD
60
P5_1
WRH/BHE
61
WRL/WR
62
63
64
P5_0
P12_7
P12_6
P12_5
65
P4_7
CS3
66
P4_6
CS2
67
P4_5
CS1
68
P4_4
P4_3
P4_2
P4_1
P4_0
P3_7
P3_6
P3_5
P3_4
P3_3
P3_2
P3_1
P12_4
P12_3
P12_2
P12_1
P12_0
CS0
A19
A18
A17
A16
A15
A14
A13
A12
A11
A10
A9
P3_0
A8(/-/D7)
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
BCLK
VCC2
VSS
P2_7
P2_6
P2_5
P2_4
P2_3
P2_2
P2_1
P2_0
AN2_7
AN2_6
AN2_5
AN2_4
AN2_3
AN2_2
AN2_1
AN2_0
A7(/D7/D6)
A6(/D6/D5)
A5(/D5/D4)
A4(/D4/D3)
A3(/D3/D2)
A2(/D2/D1)
A1(/D1/D0)
A0(/D0/-)
96
P1_7
INT5
D15
97
P1_6
INT4
D14
98
99
100
P1_5
P1_4
P1_3
INT3
D13
D12
D11
Rev.2.41 Jan 10, 2006
REJ09B0185-0241
Page 16 of 390
M16C/62P Group (M16C/62P, M16C/62PT)
Table 1.12
Pin No.
1. Overview
Pin Characteristics for 128-Pin Package (3)
Control Pin
Port
Interrupt Pin
Timer Pin
UART Pin
Analog Pin
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
P1_2
P1_1
P1_0
P0_7
P0_6
P0_5
P0_4
P0_3
P0_2
P0_1
P0_0
P11_7
P11_6
P11_5
P11_4
P11_3
P11_2
P11_1
P11_0
120
P10_7
KI3
AN7
121
P10_6
KI2
AN6
122
P10_5
KI1
AN5
123
124
125
126
127
128
P10_4
P10_3
P10_2
P10_1
KI0
AN4
AN3
AN2
AN1
AN0_7
AN0_6
AN0_5
AN0_4
AN0_3
AN0_2
AN0_1
AN0_0
AVSS
P10_0
Rev.2.41 Jan 10, 2006
REJ09B0185-0241
Page 17 of 390
AN0
Bus Control Pin
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
M16C/62P Group (M16C/62P, M16C/62PT)
1. Overview
P1_0/D8
P1_1/D9
P1_2/D10
P1_3/D11
P1_4/D12
P1_5/D13/INT3
P1_6/D14/INT4
P1_7/D15/INT5
P2_0/AN2_0/A0(/D0/-)
P2_1/AN2_1/A1(/D1/D0)
P2_2/AN2_2/A2(/D2/D1)
P2_3/AN2_3/A3(/D3/D2)
P2_4/AN2_4/A4(/D4/D3)
P2_5/AN2_5/A5(/D5/D4)
P2_6/AN2_6/A6(/D6/D5)
P2_7/AN2_7/A7(/D7/D6)
VSS
P3_0/A8(/-/D7)
VCC2
P3_1/A9
P3_2/A10
P3_3/A11
P3_4/A12
P3_5/A13
P3_6/A14
P3_7/A15
P4_0/A16
P4_1/A17
P4_2/A18
P4_3/A19
PIN CONFIGURATION (top view)
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51
P0_7/AN0_7/D7
P0_6/AN0_6/D6
P0_5/AN0_5/D5
P0_4/AN0_4/D4
P0_3/AN0_3/D3
P0_2/AN0_2/D2
P0_1/AN0_1/D1
P0_0/AN0_0/D0
P10_7/AN7/KI3
P10_6/AN6/KI2
P10_5/AN5/KI1
P10_4/AN4/KI0
P10_3/AN3
P10_2/AN2
P10_1/AN1
AVSS
P10_0/AN0
VREF
AVCC
P9_7/ADTRG/SIN4
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
50
49
48
47
46
45
44
43
<VCC2> (2)
M16C/62P Group
(M16C/62P, M16C/62PT)
<VCC1> (2)
100
42
41
40
39
38
37
36
35
34
33
32
31
P4_4/CS0
P4_5/CS1
P4_6/CS2
P4_7/CS3
P5_0/WRL/WR
P5_1/WRH/BHE
P5_2/RD
P5_3/BCLK
P5_4/HLDA
P5_5/HOLD
P5_6/ALE
P5_7/RDY/CLKOUT
P6_0/CTS0/RTS0
P6_1/CLK0
P6_2/RXD0/SCL0
P6_3/TXD0/SDA0
P6_4/CTS1/RTS1/CTS0/CLKS1
P6_5/CLK1
P6_6/RXD1/SCL1
P6_7/TXD1/SDA1
P9_6/ANEX1/SOUT4
P9_5/ANEX0/CLK4
P9_4/DA1/TB4IN
P9_3/DA0/TB3IN
P9_2/TB2IN/SOUT3
P9_1/TB1IN/SIN3
P9_0/TB0IN/CLK3
BYTE
CNVSS
P8_7/XCIN
P8_6/XCOUT
RESET
XOUT
VSS
XIN
VCC1
P8_5/NMI
P8_4/INT2/ZP
P8_3/INT1
P8_2/INT0
P8_1/TA4IN/U
P8_0/TA4OUT/U
P7_7/TA3IN
P7_6/TA3OUT
P7_5/TA2IN/W
P7_4/TA2OUT/W
P7_3/CTS2/RTS2/TA1IN/V
P7_2/CLK2/TA1OUT/V
P7_1/RXD2/SCL2/TA0IN/TB5IN (1)
P7_0/TXD2/SDA2/TA0OUT (1)
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
NOTES:
1. P7_0 and P7_1 are N channel open-drain output pins.
2. Use the M16C/62PT on VCC1=VCC2.
Package : PRQP0100JB-A (100P6S-A)
Figure 1.7
Pin Configuration (Top View)
Rev.2.41 Jan 10, 2006
REJ09B0185-0241
Page 18 of 390
M16C/62P Group (M16C/62P, M16C/62PT)
1. Overview
P1_3/D11
P1_4/D12
P1_5/D13/INT3
P1_6/D14/INT4
P1_7/D15/INT5
P2_0/AN2_0/A0(/D0/-)
P2_1/AN2_1/A1(/D1/D0)
P2_2/AN2_2/A2(/D2/D1)
P2_3/AN2_3/A3(/D3/D2)
P2_4/AN2_4/A4(/D4/D3)
P2_5/AN2_5/A5(/D5/D4)
P2_6/AN2_6/A6(/D6/D5)
P2_7/AN2_7/A7(/D7/D6)
VSS
P3_0/A8(/-/D7)
VCC2
P3_1/A9
P3_2/A10
P3_3/A11
P3_4/A12
P3_5/A13
P3_6/A14
P3_7/A15
P4_0/A16
P4_1/A17
PIN CONFIGURATION (top view)
75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51
P1_2/D10
P1_1/D9
P1_0/D8
P0_7/AN0_7/D7
P0_6/AN0_6/D6
P0_5/AN0_5/D5
P0_4/AN0_4/D4
P0_3/AN0_3/D3
P0_2/AN0_2/D2
P0_1/AN0_1/D1
P0_0/AN0_0/D0
P10_7/AN7/KI3
P10_6/AN6/KI2
P10_5/AN5/KI1
P10_4/AN4/KI0
P10_3/AN3
P10_2/AN2
P10_1/AN1
AVSS
P10_0/AN0
VREF
AVCC
P9_7/ADTRG/SIN4
P9_6/ANEX1/SOUT4
P9_5/ANEX0/CLK4
76
77
78
50
49
48
47
<VCC2> (2)
79
80
81
46
45
44
82
83
84
85
43
42
41
40
86
87
88
89
M16C/62P Group
(M16C/62P, M16C/62PT)
39
38
92
93
37
36
35
34
33
94
95
96
32
31
30
90
91
29
97
98
99
28
27
<VCC1> (2)
26
100
P4_2/A18
P4_3/A19
P4_4/CS0
P4_5/CS1
P4_6/CS2
P4_7/CS3
P5_0/WRL/WR
P5_1/WRH/BHE
P5_2/RD
P5_3/BCLK
P5_4/HLDA
P5_5/HOLD
P5_6/ALE
P5_7/RDY/CLKOUT
P6_0/CTS0/RTS0
P6_1/CLK0
P6_2/RXD0/SCL0
P6_3/TXD0/SDA0
P6_4/CTS1/RTS1/CTS0/CLKS1
P6_5/CLK1
P6_6/RXD1/SCL1
P6_7/TXD1/SDA1
P7_0/TXD2/SDA2/TA0OUT (1)
P7_1/RXD2/SCL2/TA0IN/TB5IN (1)
P7_2/CLK2/TA1OUT/V
P7_3/CTS2/RTS2/TA1IN/V
NOTES:
1. P7_0 and P7_1 are N channel open-drain output pins.
2. Use the M16C/62PT on VCC1=VCC2.
P8_5/NMI
P8_4/INT2/ZP
P8_3/INT1
P8_2/INT0
P8_1/TA4IN/U
P8_0/TA4OUT/U
P7_7/TA3IN
P7_6/TA3OUT
P7_5/TA2IN/W
P7_4/TA2OUT/W
P9_4/DA1/TB4IN
P9_3/DA0/TB3IN
P9_2/TB2IN/SOUT3
P9_1/TB1IN/SIN3
P9_0/TB0IN/CLK3
BYTE
CNVSS
P8_7/XCIN
P8_6/XCOUT
RESET
XOUT
VSS
XIN
VCC1
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25
Package : PLQP0100KB-A (100P6Q-A)
Figure 1.8
Pin Configuration (Top View)
Rev.2.41 Jan 10, 2006
REJ09B0185-0241
Page 19 of 390
M16C/62P Group (M16C/62P, M16C/62PT)
Table 1.13
1. Overview
Pin Characteristics for 100-Pin Package (1)
Pin No.
Control Pin
FP GP
Port
Interrupt Pin
Timer Pin
1
2
99
100
P9_6
P9_5
3
4
5
6
7
8
9
10
11
1
2
3
4
5
6
7
8
9
P9_4
TB4IN
P9_3
P9_2
P9_1
P9_0
TB3IN
TB2IN
TB1IN
TB0IN
12
13
14
15
16
10 RESET
11 XOUT
12 VSS
13 XIN
14 VCC1
17
15
P8_5
NMI
18
16
P8_4
INT2
19
17
P8_3
INT1
20
18
P8_2
INT0
21
19
22
23
24
20
21
22
P8_1
P8_0
P7_7
P7_6
TA4IN/U
TA4OUT/U
TA3IN
TA3OUT
25
23
26
24
P7_5
P7_4
TA2IN/W
TA2OUT/W
27
25
28
29
30
31
32
33
26
27
28
29
30
31
P7_3
P7_2
P7_1
P7_0
P6_7
P6_6
P6_5
TA1IN/V
TA1OUT/V
TA0IN/TB5IN
TA0OUT
BYTE
CNVSS
XCIN
XCOUT
UART Pin
SOUT4
CLK4
Analog Pin
Bus Control Pin
ANEX1
ANEX0
DA1
DA0
SOUT3
SIN3
CLK3
P8_7
P8_6
ZP
CTS2/RTS2
CLK2
RXD2/SCL2
TXD2/SDA2
TXD1/SDA1
RXD1/SCL1
CLK1
34
32
35
33
P6_4
P6_3
CTS1/RTS1/CTS0/CLKS1
TXD0/SDA0
36
34
P6_2
RXD0/SCL0
37
35
P6_1
CLK0
38
36
P6_0
CTS0/RTS0
39
37
P5_7
RDY/CLKOUT
40
38
P5_6
ALE
41
39
P5_5
HOLD
42
40
43
41
P5_4
P5_3
HLAD
BCLK
44
42
P5_2
RD
45
43
P5_1
WRH/BHE
46
44
P5_0
WRL/WR
47
45
P4_7
CS3
48
46
P4_6
CS2
49
47
P4_5
CS1
50
48
P4_4
CS0
Rev.2.41 Jan 10, 2006
REJ09B0185-0241
Page 20 of 390
M16C/62P Group (M16C/62P, M16C/62PT)
Table 1.14
1. Overview
Pin Characteristics for 100-Pin Package (2)
Pin No.
Control Pin
FP GP
Port
Interrupt Pin
Timer Pin
UART Pin
Analog Pin
Bus Control Pin
51
52
49
50
P4_3
P4_2
A19
A18
53
54
51
P4_1
A17
52
P4_0
A16
P3_7
A15
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
53
54
55
56
57
58
59
60 VCC2
61
62 VSS
63
64
65
66
67
68
69
70
P3_6
P3_5
P3_4
P3_3
P3_2
P3_1
A14
A13
A12
A11
A10
A9
P3_0
A8(/-/D7)
73
71
P1_7
INT5
D15
74
72
P1_6
INT4
D14
75
73
INT3
76
77
74
75
P1_5
P1_4
P1_3
D13
D12
D11
78
76
P1_2
D10
79
77
P1_1
D9
80
78
P1_0
81
82
83
84
85
79
80
81
82
83
P0_7
P0_6
P0_5
P0_4
P0_3
AN0_7
AN0_6
AN0_5
AN0_4
AN0_3
D7
D6
D5
D4
D3
86
84
P0_2
AN0_2
D2
87
88
85
86
P0_1
P0_0
AN0_1
AN0_0
D1
D0
89
87
P10_7
KI3
AN7
90
88
P10_6
KI2
AN6
91
89
P10_5
KI1
AN5
92
90
91
92
93
94 AVSS
95
P10_4
P10_3
P10_2
P10_1
KI0
93
94
95
96
97
AN4
AN3
AN2
AN1
98
96 VREF
99
97 AVCC
100
98
55
P2_7
P2_6
P2_5
P2_4
P2_3
P2_2
P2_1
P2_0
AN2_7
AN2_6
AN2_5
AN2_4
AN2_3
AN2_2
AN2_1
AN2_0
D8
P10_0
P9_7
Rev.2.41 Jan 10, 2006
REJ09B0185-0241
A7(/D7/D6)
A6(/D6/D5)
A5(/D5/D4)
A4(/D4/D3)
A3(/D3/D2)
A2(/D2/D1)
A1(/D1/D0)
A0(/D0/-)
Page 21 of 390
AN0
SIN4
ADTRG
M16C/62P Group (M16C/62P, M16C/62PT)
1. Overview
P4_1
P4_2
P4_0
P3_7
P3_6
P3_5
P3_4
P3_3
P3_2
P3_1
P2_7/AN2_7
P3_0
P2_6/AN2_6
P2_5/AN2_5
P2_4/AN2_4
P2_3/AN2_3
P2_2/AN2_2
P2_1/AN2_1
P2_0/AN2_0
P0_7/AN0_7
PIN CONFIGURATION (top view)
60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41
P0_6/AN0_6
P0_5/AN0_5
P0_4/AN0_4
P0_3/AN0_3
P0_2/AN0_2
P0_1/AN0_1
P0_0/AN0_0
P10_7/AN7/KI3
P10_6/AN6/KI2
P10_5/AN5/KI1
P10_4/AN4/KI0
P10_3/AN3
P10_2/AN2
P10_1/AN1
AVSS
P10_0/AN0
VREF
AVCC
61
40
P4_3
62
39
63
38
64
37
65
36
66
35
67
34
68
33
72
29
73
28
74
27
75
26
76
25
77
24
78
23
P9_7/ADTRG/SIN4
79
22
P5_0
P5_1
P5_2
P5_3
P5_4
P5_5
P5_6
P5_7/CLKOUT
P6_0/CTS0/RTS0
P6_1/CLK0
P6_2/RXD0/SCL0
P6_3/TXD0/SDA0
P6_4/CTS1/RTS1/CTS0/CLKS1
P6_5/CLK1
P6_6/RXD1/SCL1
P6_7/TXD1/SDA1
P7_0/TXD2/SDA2/TA0OUT (1)
P7_1/RXD2/SCL2/TA0IN/TB5IN
P9_6/ANEX1/SOUT4
80
21
P7_6/TA3OUT
69
32
M16C/62P Group
(M16C/62P, M16C/62PT)
(1)
P7_7/TA3IN
P8_0/TA4OUT
P8_1/TA4IN
P8_2/INT0
P8_3/INT1
P9_0/TB0IN/CLK3
CNVSS(BYTE)
9 10 11 12 13 14 15 16 17 18 19 20
P8_4/INT2/ZP
P9_2/TB2IN/SOUT3
8
P8_5/NMI
P9_3/DA0/TB3IN
7
VCC1
P9_4/DA1/TB4IN
6
XIN
5
VSS
4
XOUT
3
30
RESET
2
31
P8_6/XCOUT
1
P9_5/ANEX0/CLK4
71
P8_7/XCIN
70
NOTES:
1. P7_0 and P7_1 are N channel open-drain output pins.
Package : PRQP0080JA-A (80P6S-A)
Figure 1.9
Pin Configuration (Top View)
Rev.2.41 Jan 10, 2006
REJ09B0185-0241
Page 22 of 390
M16C/62P Group (M16C/62P, M16C/62PT)
Table 1.15
Pin No.
1. Overview
Pin Characteristics for 80-Pin Package (1)
Control Pin
Port
Interrupt Pin
Timer Pin
1
2
P9_5
P9_4
3
4
5
P9_3
TB3IN
P9_2
P9_0
TB2IN
TB0IN
6
7
8
9
10
11
12
13
CNVSS
(BYTE)
XCIN
XCOUT
TB4IN
Analog Pin
Bus Control Pin
ANEX0
DA1
DA0
SOUT3
CLK3
P8_7
P8_6
RESET
XOUT
VSS
XIN
VCC1
14
P8_5
NMI
15
P8_4
INT2
16
P8_3
INT1
17
P8_2
INT0
18
P8_1
P8_0
19
UART Pin
CLK4
ZP
TA4IN
TA4OUT
20
P7_7
TA3IN
21
22
23
24
25
26
P7_6
P7_1
P7_0
P6_7
P6_6
P6_5
TA3OUT
TA0IN/TB5IN
TA0OUT
27
28
29
30
P6_4
P6_3
P6_2
P6_1
CTS1/RTS1/CTS0/CLKS1
TXD0/SDA0
RXD0/SCL0
CLK0
31
P6_0
CTS0/RTS0
32
P5_7
33
P5_6
34
P5_5
35
36
P5_4
P5_3
37
P5_2
38
P5_1
39
P5_0
40
P4_3
41
P4_2
42
P4_1
43
P4_0
44
P3_7
45
P3_6
46
P3_5
47
P3_4
48
P3_3
49
P3_2
50
P3_1
Rev.2.41 Jan 10, 2006
REJ09B0185-0241
Page 23 of 390
RXD2/SCL2
TXD2/SDA2
TXD1/SDA1
RXD1/SCL1
CLK1
CLKOUT
M16C/62P Group (M16C/62P, M16C/62PT)
Table 1.16
Pin No.
1. Overview
Pin Characteristics for 80-Pin Package (2)
Control Pin
Port
Interrupt Pin
Timer Pin
UART Pin
Analog Pin
51
52
P3_0
P2_7
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
P2_6
AN2_6
P2_5
P2_4
P2_3
P2_2
P2_1
P2_0
P0_7
P0_6
P0_5
P0_4
P0_3
P0_2
P0_1
P0_0
AN2_5
AN2_4
AN2_3
AN2_2
AN2_1
AN2_0
AN0_7
AN0_6
AN0_5
AN0_4
AN0_3
AN0_2
AN0_1
AN0_0
68
P10_7
KI3
AN7
69
P10_6
KI2
AN6
70
P10_5
KI1
AN5
71
KI0
72
P10_4
P10_3
AN4
AN3
73
P10_2
AN2
P10_1
AN1
P10_0
AN0
74
75
AN2_7
AVSS
76
77
VREF
78
AVCC
79
P9_7
SIN4
ADTRG
80
P9_6
SOUT4
ANEX1
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Bus Control Pin
M16C/62P Group (M16C/62P, M16C/62PT)
1.6
1. Overview
Pin Description
Table 1.17
Signal Name
Power supply
input
Analog power
supply input
Reset input
Pin Description (100-pin and 128-pin Version) (1)
Pin Name
VCC1,VCC2
VSS
AVCC
AVSS
I/O
Power
Description
Type Supply(3)
I
−
Apply 2.7 to 5.5 V to the VCC1 and VCC2 pins and 0 V to the VSS
pin. The VCC apply condition is that VCC1 ≥ VCC2. (1, 2)
I
VCC1 Applies the power supply for the A/D converter. Connect the AVCC
pin to VCC1. Connect the AVSS pin to VSS.
RESET
CNVSS
I
I
VCC1
VCC1
External data
bus width
select input
BYTE
I
VCC1
Bus control
pins (4)
D0 to D7
I/O
VCC2
D8 to D15
I/O
VCC2
A0 to A19
A0/D0 to
A7/D7
A1/D0 to
A8/D7
O
I/O
VCC2
VCC2
I/O
VCC2
CS0 to CS3
O
VCC2
Output CS0 to CS3 signals. CS0 to CS3 are chip-select signals to
specify an external space.
WRL/WR
WRH/BHE
RD
O
VCC2
ALE
O
VCC2
Output WRL, WRH, (WR, BHE), RD signals. WRL and WRH or
BHE and WR can be switched by program.
• WRL, WRH and RD are selected
The WRL signal becomes "L" by writing data to an even address in
an external memory space.
The WRH signal becomes "L" by writing data to an odd address in
an external memory space.
The RD pin signal becomes "L" by reading data in an external
memory space.
• WR, BHE and RD are selected
The WR signal becomes "L" by writing data in an external memory space.
The RD signal becomes "L" by reading data in an external memory space.
The BHE signal becomes "L" by accessing an odd address.
Select WR, BHE and RD for an external 8-bit data bus.
ALE is a signal to latch the address.
HOLD
I
VCC2
While the HOLD pin is held "L", the microcomputer is placed in a
hold state.
HLDA
O
VCC2
In a hold state, HLDA outputs a "L" signal.
RDY
I
VCC2
While applying a "L" signal to the RDY pin, the microcomputer is
placed in a wait state.
CNVSS
The microcomputer is in a reset state when applying “L” to the this pin.
Switches processor mode. Connect this pin to VSS to when after
a reset to start up in single-chip mode. Connect this pin to VCC1 to
start up in microprocessor mode.
Switches the data bus in external memory space. The data bus is
16 bits long when the this pin is held "L" and 8 bits long when the
this pin is held "H". Set it to either one. Connect this pin to VSS
when an single-chip mode.
Inputs and outputs data (D0 to D7) when these pins are set as the
separate bus.
Inputs and outputs data (D8 to D15) when external 16-bit data bus
is set as the separate bus.
Output address bits (A0 to A19).
Input and output data (D0 to D7) and output address bits (A0 to A7) by
timesharing when external 8-bit data bus are set as the multiplexed bus.
Input and output data (D0 to D7) and output address bits (A1 to A8)
by timesharing when external 16-bit data bus are set as the
multiplexed bus.
I : Input O : Output I/O : Input and output
Power Supply : Power supplies which relate to the external bus pins are separated as VCC2, thus they can be
interfaced using the different voltage as VCC1.
NOTES:
1. In this manual, hereafter, VCC refers to VCC1 unless otherwise noted.
2. In M16C/62PT, apply 4.0 to 5.5 V to the VCC1 and VCC2 pins. Also the apply condition is that VCC1 = VCC2.
3. When use VCC1 > VCC2, contacts due to some points or restrictions to be checked.
4. Bus control pins in M16C/62PT cannot be used.
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M16C/62P Group (M16C/62P, M16C/62PT)
Table 1.18
Signal Name
Main clock
input
Main clock
output
Sub clock input
Sub clock
output
BCLK output (2)
Clock output
1. Overview
Pin Description (100-pin and 128-pin Version) (2)
Pin Name
XIN
XOUT
I/O
Power
Description
Type Supply(1)
I
VCC1 I/O pins for the main clock generation circuit. Connect a ceramic
resonator or crystal oscillator between XIN and XOUT (3). To use
O
VCC1 the external clock, input the clock from XIN and leave XOUT open.
XCIN
XCOUT
I
O
VCC1
VCC1
I/O pins for a sub clock oscillation circuit. Connect a crystal
oscillator between XCIN and XCOUT (3). To use the external clock,
input the clock from XCIN and leave XCOUT open.
BCLK
CLKOUT
VCC2
VCC2
Outputs the BCLK signal.
The clock of the same cycle as fC, f8, or f32 is outputted.
VCC1
Input pins for the INT interrupt.
INT interrupt
input
INT0 to INT2
O
O
I
NT3 to INT5
I
VCC2
NMI interrupt
input
Key input
interrupt input
Timer A
NMI
I
VCC1
KI0 to KI3
I
VCC1
I/O
VCC1
I
VCC1
These are timer A0 to timer A4 I/O pins. (however, output of
TA0OUT for the N-channel open drain output.)
These are timer A0 to timer A4 input pins.
I
I
VCC1
VCC1
Input pin for the Z-phase.
These are timer B0 to timer B5 input pins.
O
VCC1
These are Three-phase motor control output pins.
I
VCC1
These are send control input pins.
O
VCC1
These are receive control output pins.
I/O
VCC1
These are transfer clock I/O pins.
I
VCC1
These are serial data input pins.
I
O
VCC1
VCC1
O
VCC1
These are serial data input pins.
These are serial data output pins. (however, output of TXD2 for the
N-channel open drain output.)
These are serial data output pins.
O
VCC1
I/O
VCC1
I/O
VCC1
Timer B
TA0OUT to
TA4OUT
TA0IN to
TA4IN
ZP
TB0IN to
TB5IN
Three-phase
U, U, V, V,
motor control
W, W
output
Serial interface CTS0 to
CTS2
RTS0 to
RTS2
CLK0 to
CLK4
RXD0 to
RXD2
SIN3, SIN4
TXD0 to
TXD2
SOUT3,
SOUT4
CLKS1
I2C mode
I : Input
SDA0 to
SDA2
SCL0 to
SCL2
O : Output
Input pin for the NMI interrupt. Pin states can be read by the P8_5
bit in the P8 register.
Input pins for the key input interrupt.
This is output pin for transfer clock output from multiple pins
function.
These are serial data I/O pins. (however, output of SDA2 for the Nchannel open drain output.)
These are transfer clock I/O pins. (however, output of SCL2 for the
N-channel open drain output.)
I/O : Input and output
NOTES:
1. When use VCC1 > VCC2, contacts due to some points or restrictions to be checked.
2. This pin function in M16C/62PT cannot be used.
3. Ask the oscillator maker the oscillation characteristic.
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M16C/62P Group (M16C/62P, M16C/62PT)
Table 1.19
Signal Name
Reference
voltage input
A/D converter
Pin Description (100-pin and 128-pin Version) (3)
Pin Name
VREF
AN0 to AN7,
AN0_0 to
AN0_7,
AN2_0 to
AN2_7
ADTRG
ANEX0
D/A converter
I/O port
Input port
I : Input
1. Overview
ANEX1
DA0, DA1
P0_0 to P0_7,
P1_0 to P1_7,
P2_0 to P2_7,
P3_0 to P3_7,
P4_0 to P4_7,
P5_0 to P5_7,
P12_0 to
P12_7 (2),
P13_0 to
P13_7 (2)
P6_0 to P6_7,
P7_0 to P7_7,
P9_0 to P9_7,
P10_0 to
P10_7,
P11_0 to
P11_7 (2)
P8_0 to P8_4,
P8_6, P8_7,
P14_0,
P14_1(2)
P8_5
O : Output
I/O
Power
Description
Type Supply(1)
I
VCC1 Applies the reference voltage for the A/D converter and D/A
converter.
I
VCC1 Analog input pins for the A/D converter.
I
VCC1
This is an A/D trigger input pin.
I/O
VCC1
I
O
I/O
VCC1
VCC1
VCC2
This is the extended analog input pin for the A/D converter, and is
the output in external op-amp connection mode.
This is the extended analog input pin for the A/D converter.
This is the output pin for the D/A converter.
8-bit I/O ports in CMOS, having a direction register to select an
input or output.
Each pin is set as an input port or output port. An input port can
be set for a pull-up or for no pull-up in 4-bit unit by program.
I/O
VCC1
8-bit I/O ports having equivalent functions to P0.
(however, output of P7_0 and P7_1 for the N-channel open drain
output.)
I/O
VCC1
I/O ports having equivalent functions to P0.
I
VCC1
Input pin for the NMI interrupt.
Pin states can be read by the P8_5 bit in the P8 register.
I/O : Input and output
NOTES:
1. When use VCC1 > VCC2, contacts due to some points or restrictions to be checked.
2. Ports P11 to P14 in M16C/62P (100-pin version) and M16C/62PT (100-pin version) cannot be used.
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M16C/62P Group (M16C/62P, M16C/62PT)
Table 1.20
Signal Name
Power supply
input
Analog power
supply input
Reset input
CNVSS
Main clock
input
Main clock
output
Sub clock input
Sub clock
output
Clock output
1. Overview
Pin Description (80-pin Version) (1) (1)
Pin Name
I/O
Type
I
Power
Supply
−
AVCC
AVSS
I
VCC1
Applies the power supply for the A/D converter. Connect the
AVCC pin to VCC1. Connect the AVSS pin to VSS.
RESET
CNVSS
(BYTE)
I
I
VCC1
VCC1
XIN
I
VCC1
XOUT
O
VCC1
The microcomputer is in a reset state when applying “L” to the this pin.
Switches processor mode. Connect this pin to VSS to when after a
reset to start up in single-chip mode. Connect this pin to VCC1 to
start up in microprocessor mode. As for the BYTE pin of the 80-pin
versions, pull-up processing is performed within the microcomputer.
I/O pins for the main clock generation circuit. Connect a ceramic
resonator or crystal oscillator between XIN and XOUT (3). To use
the external clock, input the clock from XIN and leave XOUT
open.
XCIN
XCOUT
I
O
VCC1
VCC1
I/O pins for a sub clock oscillation circuit. Connect a crystal
oscillator between XCIN and XCOUT (3). To use the external
clock, input the clock from XCIN and leave XCOUT open.
CLKOUT
VCC2
The clock of the same cycle as fC, f8, or f32 is outputted.
VCC1
Input pins for the INT interrupt.
VCC1, VSS
Description
Apply 2.7 to 5.5 V to the VCC1 pin and 0 V to the VSS pin. (1, 2)
INT interrupt
input
INT0 to INT2
O
I
NMI interrupt
input
Key input
interrupt input
Timer A
NMI
I
VCC1
Input pin for the NMI interrupt.
KI0 to KI3
I
VCC1
Input pins for the key input interrupt.
I/O
VCC1
These are Timer A0,Timer A3 and Timer A4 I/O pins. (however,
output of TA0OUT for the N-channel open drain output.)
I
VCC1
These are Timer A0, Timer A3 and Timer A4 input pins.
I
I
VCC1
VCC1
Input pin for the Z-phase.
These are Timer B0, Timer B2 to Timer B5 input pins.
Serial interface CTS0 to CTS1
I
VCC1
These are send control input pins.
RTS0 to RTS1
CLK0, CLK1,
CLK3, CLK4
RXD0 to RXD2
SIN4
TXD0 to TXD2
O
VCC1
These are receive control output pins.
I/O
VCC1
These are transfer clock I/O pins.
I
I
O
VCC1
VCC1
VCC1
These are serial data input pins.
This is serial data input pin.
These are serial data output pins. (however, output of TXD2 for
the N-channel open drain output.)
These are serial data output pins.
Timer B
I2C mode
I : Input
TA0OUT,
TA3OUT,
TA4OUT
TA0IN, TA3IN,
TA4IN
ZP
TB0IN, TB2IN
to TB5IN
SOUT3,
SOUT4
CLKS1
O
VCC1
O
VCC1
SDA0 to SDA2
I/O
VCC1
SCL0 to SCL2
I/O
VCC1
O : Output
This is output pin for transfer clock output from multiple pins
function.
These are serial data I/O pins. (however, output of SDA2 for the
N-channel open drain output.)
These are transfer clock I/O pins. (however, output of SCL2 for
the N-channel open drain output.)
I/O : Input and output
NOTES:
1. In this manual, hereafter, VCC refers to VCC1 unless otherwise noted.
2. In M16C/62PT, apply 4.0 to 5.5 V to the VCC1 pin.
3. Ask the oscillator maker the oscillation characteristic.
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M16C/62P Group (M16C/62P, M16C/62PT)
Table 1.21
Signal Name
Reference
voltage input
A/D converter
Pin Description (80-pin Version) (2)
Pin Name
VREF
AN0 to AN7,
AN0_0 to
AN0_7,
AN2_0 to
AN2_7
ADTRG
ANEX0
D/A converter
I/O port (1)
Input port
I : Input
1. Overview
ANEX1
DA0, DA1
P0_0 to P0_7,
P2_0 to P2_7,
P3_0 to P3_7,
P5_0 to P5_7,
P6_0 to P6_7,
P10_0 to
P10_7
P8_0 to P8_4,
P8_6, P8_7,
P9_0,
P9_2 to P9_7
P4_0 to P4_3,
P7_0, P7_1,
P7_6, P7_7
P8_5
O : Output
I/O
Power
Description
Type Supply(1)
I
VCC1 Applies the reference voltage for the A/D converter and D/A
converter.
I
VCC1 Analog input pins for the A/D converter.
I
VCC1
This is an A/D trigger input pin.
I/O
VCC1
I
O
I/O
VCC1
VCC1
VCC1
This is the extended analog input pin for the A/D converter, and is
the output in external op-amp connection mode.
This is the extended analog input pin for the A/D converter.
This is the output pin for the D/A converter.
8-bit I/O ports in CMOS, having a direction register to select an
input or output.
Each pin is set as an input port or output port. An input port can
be set for a pull-up or for no pull-up in 4-bit unit by program.
I/O
VCC1
I/O ports having equivalent functions to P0.
I/O
VCC1
I/O ports having equivalent functions to P0.
(however, output of P7_0 and P7_1 for the N-channel open drain
output.)
I
VCC1
Input pin for the NMI interrupt.
Pin states can be read by the P8_5 bit in the P8 register.
I/O : Input and output
NOTES:
1. There is no external connections for port P1, P4_4 to P4_7, P7_2 to P7_5 and P9_1 in 80-pin version. Set the
direction bits in these ports to “1” (output mode), and set the output data to “0” (“L”) using the program.
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M16C/62P Group (M16C/62P, M16C/62PT)
2.
2. Central Processing Unit (CPU)
Central Processing Unit (CPU)
Figure 2.1 shows the CPU registers. The CPU has 13 registers. Of these, R0, R1, R2, R3, A0, A1 and FB comprise a
register bank. There are two register banks.
b31
b15
b8 b7
R2
R0H
R3
R1H
b0
R0L
R1L
Data Registers (1)
R2
R3
A0
Address Registers (1)
A1
FB
b19
b15
Frame Base Registers (1)
b0
INTBH
Interrupt Table Register
INTBL
b19
b0
Program Counter
PC
b15
b0
USP
User Stack Pointer
ISP
Interrupt Stack Pointer
SB
Static Base Register
b15
b0
FLG
b15
b8
IPL
b7
U I
Flag Register
b0
O B S Z D C
Carry Flag
Debug Flag
Zero Flag
Sign Flag
Register Bank Select Flag
Overflow Flag
Interrupt Enable Flag
Stack Pointer Select Flag
Reserved Area
Processor Interrupt Priority Level
Reserved Area
NOTES:
1. These registers comprise a register bank. There are two register banks.
Figure 2.1
2.1
Central Processing Unit Register
Data Registers (R0, R1, R2 and R3)
The R0 register consists of 16 bits, and is used mainly for transfers and arithmetic/logic operations. R1 to R3 are
the same as R0.
The R0 register can be separated between high (R0H) and low (R0L) for use as two 8-bit data registers.
R1H and R1L are the same as R0H and R0L. Conversely, R2 and R0 can be combined for use as a 32-bit data
register (R2R0). R3R1 is the same as R2R0.
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M16C/62P Group (M16C/62P, M16C/62PT)
2.2
2. Central Processing Unit (CPU)
Address Registers (A0 and A1)
The register A0 consists of 16 bits, and is used for address register indirect addressing and address register relative
addressing. They also are used for transfers and logic/logic operations. A1 is the same as A0.
In some instructions, registers A1 and A0 can be combined for use as a 32-bit address register (A1A0).
2.3
Frame Base Register (FB)
FB is configured with 16 bits, and is used for FB relative addressing.
2.4
Interrupt Table Register (INTB)
INTB is configured with 20 bits, indicating the start address of an interrupt vector table.
2.5
Program Counter (PC)
PC is configured with 20 bits, indicating the address of an instruction to be executed.
2.6
User Stack Pointer (USP) and Interrupt Stack Pointer (ISP)
Stack pointer (SP) comes in two types: USP and ISP, each configured with 16 bits.
Your desired type of stack pointer (USP or ISP) can be selected by the U flag of FLG.
2.7
Static Base Register (SB)
SB is configured with 16 bits, and is used for SB relative addressing.
2.8
Flag Register (FLG)
FLG consists of 11 bits, indicating the CPU status.
2.8.1
Carry Flag (C Flag)
This flag retains a carry, borrow, or shift-out bit that has occurred in the arithmetic/logic unit.
2.8.2
Debug Flag (D Flag)
The D flag is used exclusively for debugging purpose. During normal use, it must be set to “0”.
2.8.3
Zero Flag (Z Flag)
This flag is set to “1” when an arithmetic operation resulted in 0; otherwise, it is “0”.
2.8.4
Sign Flag (S Flag)
This flag is set to “1” when an arithmetic operation resulted in a negative value; otherwise, it is “0”.
2.8.5
Register Bank Select Flag (B Flag)
Register bank 0 is selected when this flag is “0” ; register bank 1 is selected when this flag is “1”.
2.8.6
Overflow Flag (O Flag)
This flag is set to “1” when the operation resulted in an overflow; otherwise, it is “0”.
2.8.7
Interrupt Enable Flag (I Flag)
This flag enables a maskable interrupt.
Maskable interrupts are disabled when the I flag is “0”, and are enabled when the I flag is “1”. The I flag
is cleared to “0” when the interrupt request is accepted.
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M16C/62P Group (M16C/62P, M16C/62PT)
2.8.8
2. Central Processing Unit (CPU)
Stack Pointer Select Flag (U Flag)
ISP is selected when the U flag is “0”; USP is selected when the U flag is “1”.
The U flag is cleared to “0” when a hardware interrupt request is accepted or an INT instruction for software
interrupt Nos. 0 to 31 is executed.
2.8.9
Processor Interrupt Priority Level (IPL)
IPL is configured with three bits, for specification of up to eight processor interrupt priority levels from level 0
to level 7.
If a requested interrupt has priority greater than IPL, the interrupt is enabled.
2.8.10
Reserved Area
When write to this bit, write “0”. When read, its content is indeterminate.
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M16C/62P Group (M16C/62P, M16C/62PT)
3.
3. Memory
Memory
Figure 3.1 is a Memory Map of the M16C/62P group. The address space extends the 1M bytes from address 00000h to
FFFFFh.
The internal ROM is allocated in a lower address direction beginning with address FFFFFh. For example, a 64-Kbyte
internal ROM is allocated to the addresses from F0000h to FFFFFh.
As for the flash memory version, 4-Kbyte space (block A) exists in 0F000h to 0FFFFh. 4-Kbyte space is mainly for
storing data. In addition to storing data, 4-Kbyte space also can store programs.
The fixed interrupt vector table is allocated to the addresses from FFFDCh to FFFFFh. Therefore, store the start
address of each interrupt routine here.
The internal RAM is allocated in an upper address direction beginning with address 00400h. For example, a 10-Kbyte
internal RAM is allocated to the addresses from 00400h to 02BFFh. In addition to storing data, the internal RAM also
stores the stack used when calling subroutines and when interrupts are generated.
The SRF is allocated to the addresses from 00000h to 003FFh. Peripheral function control registers are located here.
Of the SFR, any area which has no functions allocated is reserved for future use and cannot be used by users.
The special page vector table is allocated to the addresses from FFE00h to FFFDBh. This vector is used by the JMPS
or JSRS instruction. For details, refer to the M16C/60 and M16C/20 Series Software Manual.
In memory expansion and microprocessor modes, some areas are reserved for future use and cannot be used by users.
Use M16C/62P (80-pin version) and M16C/62PT in single-chip mode. The memory expansion and microprocessor
modes cannot be used
.
00000h
SFR
00400h
Internal RAM
XXXXXh
Reserved area (1)
FFE00h
0F000h
Internal ROM
(data area) (3)
0FFFFh
Special page
vector table
10000h
Internal RAM
Internal ROM
(3)
Address XXXXXh
Size
Address YYYYYh
4 Kbytes
013FFh
48 Kbytes
F4000h
5 Kbytes
017FFh
64 Kbytes
F0000h
10 Kbytes
02BFFh
96 Kbytes
E8000h
12 Kbytes
033FFh
128 Kbytes
E0000h
16 Kbytes
043FFh
192 Kbytes
D0000h
20 Kbytes
053FFh
256 Kbytes
C0000h
24 Kbytes
063FFh
320 Kbytes
B0000h
31 Kbytes
07FFFh
384 Kbytes
A0000h
512 Kbytes
80000h
Size
External area
27000h
Reserved area
Memory Map
Rev.2.41 Jan 10, 2006
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Overflow
External area
80000h
Reserved area (2)
YYYYYh
Internal ROM
(program area) (5)
FFFFFh
NOTES:
1. During memory expansion and microprocessor modes, can be used.
2. In memory expansion mode, can be used.
3. As for the flash memory version, 4-Kbyte space (block A) exists.
4. Shown here is a memory map for the case where the PM10 bit in the PM1 register is “1”
and the PM13 bit in the PM1 register is “1”.
5. When using the masked ROM version, write nothing to internal ROM area.
Figure 3.1
FFFDCh Undefined instruction
28000h
FFFFFh
BRK instruction
Address match
Single step
Watchdog timer
DBC
NMI
Reset
M16C/62P Group (M16C/62P, M16C/62PT)
4.
4. Special Function Register (SFR)
Special Function Register (SFR)
SFR(Special Function Register) is the control register of peripheral functions. Tables 4.1 to 4.6 list the SFR
information.
Table 4.1
SFR Information (1) (1)
Address
0000h
0001h
0002h
0003h
0004h
0005h
0006h
0007h
0008h
0009h
000Ah
000Bh
000Ch
000Dh
000Eh
000Fh
0010h
0011h
0012h
0013h
0014h
0015h
0016h
0017h
0018h
0019h
001Ah
001Bh
001Ch
001Dh
001Eh
001Fh
0020h
0021h
0022h
0023h
0024h
0025h
0026h
0027h
0028h
0029h
002Ah
002Bh
002Ch
002Dh
002Eh
002Fh
0030h
0031h
0032h
0033h
0034h
0035h
0036h
0037h
0038h
0039h
003Ah
003Bh
003Ch
003Dh
003Eh
003Fh
NOTES:
1.
2.
3.
4.
5.
6.
Register
Symbol
After Reset
Processor Mode Register 0 (2)
PM0
00000000b(CNVSS pin is “L”)
00000011b(CNVSS pin is “H”)
Processor Mode Register 1
System Clock Control Register 0
System Clock Control Register 1
Chip Select Control Register (6)
Address Match Interrupt Enable Register
Protect Register
Data Bank Register (6)
Oscillation Stop Detection Register (3)
PM1
CM0
CM1
CSR
AIER
PRCR
DBR
CM2
00001000b
01001000b
00100000b
00000001b
XXXXXX00b
XX000000b
00h
0X000000b
Watchdog Timer Start Register
Watchdog Timer Control Register
Address Match Interrupt Register 0
WDTS
WDC
RMAD0
XXh
00XXXXXXb (4)
00h
00h
X0h
Address Match Interrupt Register 1
RMAD1
00h
00h
X0h
Voltage Detection Register 1 (5, 6)
Voltage Detection Register 2 (5, 6)
Chip Select Expansion Control Register (6)
PLL Control Register 0
VCR1
VCR2
CSE
PLC0
00001000b
00h
00h
0001X010b
Processor Mode Register 2
Low Voltage Detection Interrupt Register (6)
DMA0 Source Pointer
PM2
D4INT
SAR0
XXX00000b
00h
XXh
XXh
XXh
DMA0 Destination Pointer
DAR0
XXh
XXh
XXh
DMA0 Transfer Counter
TCR0
XXh
XXh
DMA0 Control Register
DM0CON
00000X00b
DMA1 Source Pointer
SAR1
XXh
XXh
XXh
DMA1 Destination Pointer
DAR1
XXh
XXh
XXh
DMA1 Transfer Counter
TCR1
XXh
XXh
DMA1 Control Register
DM1CON
00000X00b
The blank areas are reserved and cannot be accessed by users.
The PM00 and PM01 bits do not change at software reset, watchdog timer reset and oscillation stop detection reset.
The CM20, CM21, and CM27 bits do not change at oscillation stop detection reset.
The WDC5 bit is “0” (cold start) immediately after power-on. I t can only be set to “1” in a program.
This register does not change at software reset, watchdog timer reset and oscillation stop detection reset.
This register in M16C/62PT cannot be used.
X : Nothing is mapped to this bit
Rev.2.41 Jan 10, 2006
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M16C/62P Group (M16C/62P, M16C/62PT)
Table 4.2
Address
0040h
0041h
0042h
0043h
0044h
0045h
0046h
0047h
0048h
0049h
004Ah
004Bh
004Ch
004Dh
004Eh
004Fh
0050h
0051h
0052h
0053h
0054h
0055h
0056h
0057h
0058h
0059h
005Ah
005Bh
005Ch
005Dh
005Eh
005Fh
0060h
0061h
0062h
0063h
0064h
0065h
0066h
0067h
0068h
0069h
006Ah
006Bh
006Ch
006Dh
006Eh
006Fh
0070h
0071h
0072h
0073h
0074h
0075h
0076h
0077h
0078h
0079h
007Ah
007Bh
007Ch
007Dh
007Eh
007Fh
4. Special Function Register (SFR)
SFR Information (2) (1)
Register
INT3 Interrupt Control Register
Timer B5 Interrupt Control Register
Timer B4 Interrupt Control Register, UART1 BUS Collision Detection Interrupt Control Register
Timer B3 Interrupt Control Register, UART0 BUS Collision Detection Interrupt Control Register
SI/O4 Interrupt Control Register, INT5 Interrupt Control Register
SI/O3 Interrupt Control Register, INT4 Interrupt Control Register
UART2 Bus Collision Detection Interrupt Control Register
DMA0 Interrupt Control Register
DMA1 Interrupt Control Register
Key Input Interrupt Control Register
A/D Conversion Interrupt Control Register
UART2 Transmit Interrupt Control Register
UART2 Receive Interrupt Control Register
UART0 Transmit Interrupt Control Register
UART0 Receive Interrupt Control Register
UART1 Transmit Interrupt Control Register
UART1 Receive Interrupt Control Register
Timer A0 Interrupt Control Register
Timer A1 Interrupt Control Register
Timer A2 Interrupt Control Register
Timer A3 Interrupt Control Register
Timer A4 Interrupt Control Register
Timer B0 Interrupt Control Register
Timer B1 Interrupt Control Register
Timer B2 Interrupt Control Register
INT0 Interrupt Control Register
INT1 Interrupt Control Register
INT2 Interrupt Control Register
NOTES:
1. The blank areas are reserved and cannot be accessed by users.
X : Nothing is mapped to this bit
Rev.2.41 Jan 10, 2006
REJ09B0185-0241
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Symbol
INT3IC
TB5IC
TB4IC, U1BCNIC
TB3IC, U0BCNIC
S4IC, INT5IC
S3IC, INT4IC
BCNIC
DM0IC
DM1IC
KUPIC
ADIC
S2TIC
S2RIC
S0TIC
S0RIC
S1TIC
S1RIC
TA0IC
TA1IC
TA2IC
TA3IC
TA4IC
TB0IC
TB1IC
TB2IC
INT0IC
INT1IC
INT2IC
After Reset
XX00X000b
XXXXX000b
XXXXX000b
XXXXX000b
XX00X000b
XX00X000b
XXXXX000b
XXXXX000b
XXXXX000b
XXXXX000b
XXXXX000b
XXXXX000b
XXXXX000b
XXXXX000b
XXXXX000b
XXXXX000b
XXXXX000b
XXXXX000b
XXXXX000b
XXXXX000b
XXXXX000b
XXXXX000b
XXXXX000b
XXXXX000b
XXXXX000b
XX00X000b
XX00X000b
XX00X000b
M16C/62P Group (M16C/62P, M16C/62PT)
Table 4.3
Address
0080h
0081h
0082h
0083h
0084h
0085h
0086h
0087h
to
01AFh
01B0h
01B1h
01B2h
01B3h
01B4h
01B5h
01B6h
01B7h
01B8h
01B9h
01BAh
01BBh
01BCh
01BDh
01BEh
01C0h
to
024Fh
0250h
0251h
0252h
0253h
0254h
0255h
0256h
0257h
0258h
0259h
025Ah
025Bh
025Ch
025Dh
025Eh
025Fh
0260h
to
032Fh
0330h
0331h
0332h
0333h
0334h
0335h
0336h
0337h
0338h
0339h
033Ah
033Bh
033Ch
033Dh
033Eh
033Fh
4. Special Function Register (SFR)
SFR Information (3) (1)
Register
Symbol
After Reset
Flash Identification Register (2)
Flash Memory Control Register 1 (2)
FIDR
FMR1
XXXXXX00b
0X00XX0Xb
Flash Memory Control Register 0 (2)
Address Match Interrupt Register 2
FMR0
RMAD2
Address Match Interrupt Enable Register 2
Address Match Interrupt Register 3
AIER2
RMAD3
00000001b
00h
00h
XXh
XXXXXX00b
00h
00h
XXh
Peripheral Clock Select Register
PCLKR
NOTES:
1. The blank areas are reserved and cannot be accessed by users.
2. This register is included in the flash memory version.
X : Nothing is mapped to this bit
Rev.2.41 Jan 10, 2006
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00000011b
M16C/62P Group (M16C/62P, M16C/62PT)
Table 4.4
Address
0340h
0341h
0342h
0343h
0344h
0345h
0346h
0347h
0348h
0349h
034Ah
034Bh
034Ch
034Dh
034Eh
034Fh
0350h
0351h
0352h
0353h
0354h
0355h
0356h
0357h
0358h
0359h
035Ah
035Bh
035Ch
035Dh
035Eh
035Fh
0360h
0361h
0362h
0363h
0364h
0365h
0366h
0367h
0368h
0369h
036Ah
036Bh
036Ch
036Dh
036Eh
036Fh
0370h
0371h
0372h
0373h
0374h
0375h
0376h
0377h
0378h
0379h
037Ah
037Bh
037Ch
037Dh
037Eh
037Fh
4. Special Function Register (SFR)
SFR Information (4) (1)
Register
Symbol
After Reset
000XXXXXb
Timer B3, 4, 5 Count Start Flag
TBSR
Timer A1-1 Register
TA11
Timer A2-1 Register
TA21
Timer A4-1 Register
TA41
Three-Phase PWM Control Register 0
Three-Phase PWM Control Register 1
Three-Phase Output Buffer Register 0
Three-Phase Output Buffer Register 1
Dead Time Timer
Timer B2 Interrupt Occurrence Frequency Set Counter
INVC0
INVC1
IDB0
IDB1
DTT
ICTB2
Timer B3 Register
TB3
Timer B4 Register
TB4
Timer B5 Register
TB5
Timer B3 Mode Register
Timer B4 Mode Register
Timer B5 Mode Register
Interrupt Factor Select Register 2
Interrupt Factor Select Register
SI/O3 Transmit/Receive Register
TB3MR
TB4MR
TB5MR
IFSR2A
IFSR
S3TRR
00XX0000b
00XX0000b
00XX0000b
00XXXXXXb
00h
XXh
SI/O3 Control Register
SI/O3 Bit Rate Generator
SI/O4 Transmit/Receive Register
S3C
S3BRG
S4TRR
01000000b
XXh
XXh
SI/O4 Control Register
SI/O4 Bit Rate Generator
S4C
S4BRG
01000000b
XXh
UART0 Special Mode Register 4
UART0 Special Mode Register 3
UART0 Special Mode Register 2
UART0 Special Mode Register
UART1 Special Mode Register 4
UART1 Special Mode Register 3
UART1 Special Mode Register 2
UART1 Special Mode Register
UART2 Special Mode Register 4
UART2 Special Mode Register 3
UART2 Special Mode Register 2
UART2 Special Mode Register
UART2 Transmit/Receive Mode Register
UART2 Bit Rate Generator
UART2 Transmit Buffer Register
U0SMR4
U0SMR3
U0SMR2
U0SMR
U1SMR4
U1SMR3
U1SMR2
U1SMR
U2SMR4
U2SMR3
U2SMR2
U2SMR
U2MR
U2BRG
U2TB
UART2 Transmit/Receive Control Register 0
UART2 Transmit/Receive Control Register 1
UART2 Receive Buffer Register
U2C0
U2C1
U2RB
00h
000X0X0Xb
X0000000b
X0000000b
00h
000X0X0Xb
X0000000b
X0000000b
00h
000X0X0Xb
X0000000b
X0000000b
00h
XXh
XXh
XXh
00001000b
00000010b
XXh
XXh
NOTES:
1. The blank areas are reserved and cannot be accessed by users.
X : Nothing is mapped to this bit
Rev.2.41 Jan 10, 2006
REJ09B0185-0241
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XXh
XXh
XXh
XXh
XXh
XXh
00h
00h
00h
00h
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
M16C/62P Group (M16C/62P, M16C/62PT)
Table 4.5
Address
0380h
0381h
0382h
0383h
0384h
0385h
0386h
0387h
0388h
0389h
038Ah
038Bh
038Ch
038Dh
038Eh
038Fh
0390h
0391h
0392h
0393h
0394h
0395h
0396h
0397h
0398h
0399h
039Ah
039Bh
039Ch
039Dh
039Eh
039Fh
03A0h
03A1h
03A2h
03A3h
03A4h
03A5h
03A6h
03A7h
03A8h
03A9h
03AAh
03ABh
03ACh
03ADh
03AEh
03AFh
03B0h
03B1h
03B2h
03B3h
03B4h
03B5h
03B6h
03B7h
03B8h
03B9h
03BAh
03BBh
03BCh
03BDh
03BEh
03BFh
4. Special Function Register (SFR)
SFR Information (5) (1)
Count Start Flag
Clock Prescaler Reset Fag
One-Shot Start Flag
Trigger Select Register
Up-Down Flag
Register
Symbol
TABSR
CPSRF
ONSF
TRGSR
UDF
After Reset
00h
0XXXXXXXb
00h
00h
00h (2)
Timer A0 Register
TA0
Timer A1 Register
TA1
Timer A2 Register
TA2
Timer A3 Register
TA3
Timer A4 Register
TA4
Timer B0 Register
TB0
Timer B1 Register
TB1
Timer B2 Register
TB2
Timer A0 Mode Register
Timer A1 Mode Register
Timer A2 Mode Register
Timer A3 Mode Register
Timer A4 Mode Register
Timer B0 Mode Register
Timer B1 Mode Register
Timer B2 Mode Register
Timer B2 Special Mode Register
TA0MR
TA1MR
TA2MR
TA3MR
TA4MR
TB0MR
TB1MR
TB2MR
TB2SC
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
00h
00h
00h
00h
00h
00XX0000b
00XX0000b
00XX0000b
XXXXXX00b
UART0 Transmit/Receive Mode Register
UART0 Bit Rate Generator
UART0 Transmit Buffer Register
U0MR
U0BRG
U0TB
UART0 Transmit/Receive Control Register 0
UART0 Transmit/Receive Control Register 1
UART0 Receive Buffer Register
U0C0
U0C1
U0RB
UART1 Transmit/Receive Mode Register
UART1 Bit Rate Generator
UART1 Transmit Buffer Register
U1MR
U1BRG
U1TB
UART1 Transmit/Receive Control Register 0
UART1 Transmit/Receive Control Register 1
UART1 Receive Buffer Register
U1C0
U1C1
U1RB
UART Transmit/Receive Control Register 2
UCON
00h
XXh
XXh
XXh
00001000b
00XX0010b
XXh
XXh
00h
XXh
XXh
XXh
00001000b
00XX0010b
XXh
XXh
X0000000b
DMA0 Request Factor Select Register
DM0SL
00h
DMA1 Request Factor Select Register
DM1SL
00h
CRC Data Register
CRCD
CRC Input Register
CRCIN
XXh
XXh
XXh
NOTES:
1. The blank areas are reserved and cannot be accessed by users.
2. Bit 5 in the Up-down flag is “0” by reset. However, The values in these bits when read are indeterminate.
X : Nothing is mapped to this bit
Rev.2.41 Jan 10, 2006
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M16C/62P Group (M16C/62P, M16C/62PT)
Table 4.6
Address
03C0h
03C1h
03C2h
03C3h
03C4h
03C5h
03C6h
03C7h
03C8h
03C9h
03CAh
03CBh
03CCh
03CDh
03CEh
03CFh
03D0h
03D1h
03D2h
03D3h
03D4h
03D5h
03D6h
03D7h
03D8h
03D9h
03DAh
03DBh
03DCh
03DDh
03DEh
03DFh
03E0h
03E1h
03E2h
03E3h
03E4h
03E5h
03E6h
03E7h
03E8h
03E9h
03EAh
03EBh
03ECh
03EDh
03EEh
03EFh
03F0h
03F1h
03F2h
03F3h
03F4h
03F5h
03F6h
03F7h
03F8h
03F9h
03FAh
03FBh
03FCh
03FDh
03FEh
03FFh
4. Special Function Register (SFR)
SFR Information (6) (1)
Register
Symbol
After Reset
A/D Register 0
AD0
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
A/D Register 1
AD1
A/D Register 2
AD2
A/D Register 3
AD3
A/D Register 4
AD4
A/D Register 5
AD5
A/D Register 6
AD6
A/D Register 7
AD7
A/D Control Register 2
ADCON2
00h
A/D Control Register 0
A/D Control Register 1
D/A Register 0
ADCON0
ADCON1
DA0
00000XXXb
00h
00h
D/A Register 1
DA1
00h
D/A Control Register
DACON
00h
Port P14 Control Register (3)
Pull-Up Control Register 3 (3)
Port P0 Register
Port P1 Register
Port P0 Direction Register
Port P1 Direction Register
Port P2 Register
Port P3 Register
Port P2 Direction Register
Port P3 Direction Register
Port P4 Register
Port P5 Register
Port P4 Direction Register
Port P5 Direction Register
Port P6 Register
Port P7 Register
Port P6 Direction Register
Port P7 Direction Register
Port P8 Register
Port P9 Register
Port P8 Direction Register
Port P9 Direction Register
Port P10 Register
Port P11 Register (3)
Port P10 Direction Register
Port P11 Direction Register (3)
Port P12 Register (3)
Port P13 Register (3)
Port P12 Direction Register (3)
Port P13 Direction Register (3)
Pull-Up Control Register 0
Pull-Up Control Register 1
PC14
PUR3
P0
P1
PD0
PD1
P2
P3
PD2
PD3
P4
P5
PD4
PD5
P6
P7
PD6
PD7
P8
P9
PD8
PD9
P10
P11
PD10
PD11
P12
P13
PD12
PD13
PUR0
PUR1
Pull-Up Control Register 2
Port Control Register
PUR2
PCR
XX00XXXXb
00h
XXh
XXh
00h
00h
XXh
XXh
00h
00h
XXh
XXh
00h
00h
XXh
XXh
00h
00h
XXh
XXh
00X00000b
00h
XXh
XXh
00h
00h
XXh
XXh
00h
00h
00h
00000000b (2)
00000010b (2)
00h
00h
NOTES:
1. The blank areas are reserved and cannot be accessed by users.
2. At hardware reset 1 or hardware reset 2, the register is as follows:
• “00000000b” where “L” is inputted to the CNVSS pin
• “00000010b” where “H” is inputted to the CNVSS pin
At software reset, watchdog timer reset and oscillation stop detection reset, the register is as follows:
• “00000000b” where the PM01 to PM00 bits in the PM0 register are “00b” (single-chip mode).
• “00000010b” where the PM01 to PM00 bits in the PM0 register are “01b” (memory expansion mode) or “11b” (microprocessor mode).
3. These registers do not exist in M16C/62P (80-pin version), and M16C/62PT (80-pin version).
X : Nothing is mapped to this bit
Rev.2.41 Jan 10, 2006
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M16C/62P Group (M16C/62P, M16C/62PT)
5.
5. Reset
Reset
Hardware reset 1, brown-out detection reset (hardware reset 2), software reset, watchdog timer reset and oscillation
stop detection reset are available to reset the microcomputer.
5.1
Hardware Reset 1
The microcomputer resets pins, the CPU and SFR by setting the RESET pin. If the supply voltage meets the
recommended operating conditions, the microcomputer resets all pins when an “L” signal is applied to the RESET
pin (see Table 5.1 Pin Status When RESET Pin Level is “L”). The oscillation circuit is also reset and the main
clock starts oscillation. The microcomputer resets the CPU and SFR when the signal applied to the RESET pin
changes low (“L”) to high (“H”). The microcomputer executes the program in an address indicated by the reset
vector. The internal RAM is not reset. When an “L” signal is applied to the RESET pin while writing data to the
internal RAM, the internal RAM is in an indeterminate state.
Figure 5.1 shows an Example Reset Circuit. Figure 5.2 shows a Reset Sequence. Table 5.1 lists Pin Status When
RESET Pin Level is “L”. Figure 5.3 shows CPU Register Status After Reset. Refer to 4. Special Function
Register (SFR) for SFR states after reset.
5.1.1
Reset on a Stable Supply Voltage
(1) Apply “L” to the RESET pin
(2) Apply 20 or more clock cycles to the XIN pin
(3) Apply an “H” signal to the RESET pin
5.1.2
Power-on Reset
(1)
(2)
(3)
(4)
(5)
Apply “L” to the RESET pin
Raise the supply voltage to the recommended operating level
Insert td(P-R) ms as wait time for the internal voltage to stabilize
Apply 20 or more clock cycles to the XIN pin
Apply “H” to the RESET pin
Recommended
operation voltage
VCC1
0V
RESET
VCC1
RESET
0.2VCC1
or below
0.2VCC1 or below
0V
Supply a clock with td(P-R) + 20
or more cycles to the XIN pin
NOTES:
1. If VCC1>VCC2, the VCC2 voltage must be lower than that of VCC1 when the power
is being turned on or off.
Figure 5.1
Example Reset Circuit
Rev.2.41 Jan 10, 2006
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M16C/62P Group (M16C/62P, M16C/62PT)
5. Reset
VCC1, VCC2
XIN
td(P-R)
More than
20 cycles
are needed
Microprocessor
mode BYTE = H
RESET
BCLK
28cycles
BCLK
Content of reset vector
FFFFCh
Address
FFFFDh
FFFFEh
RD
WR
CS0
Microprocessor
mode BYTE = L
Content of reset vector
FFFFCh
Address
FFFFEh
RD
WR
CS0
Single chip
mode
FFFFCh
FFFFEh
Address
Figure 5.2
Content of reset vector
Reset Sequence
Rev.2.41 Jan 10, 2006
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M16C/62P Group (M16C/62P, M16C/62PT)
Table 5.1
5. Reset
Pin Status When RESET Pin Level is “L”
Pin Name
Status
CNVSS = VSS
CNVSS = VCC1 (1)
BYTE = VSS
BYTE = VCC1
P0
Input port
Data input
Data input
P1
Input port
Data input
Input port
P2, P3, P4_0 to P4_3
Input port
Address output (underfined)
Address output (underfined)
P4_4
Input port
CS0 output (“H” is output)
CS0 output (“H” is output)
P4_5 to P4_7
Input port
Input port (Pulled high)
Input port (Pulled high)
P5_0
Input port
WR output (“H” is output)
WR output (“H” is output)
P5_1
Input port
BHE output (undefined)
BHE output (undefined)
P5_2
Input port
RD output (“H” is output)
RD output (“H” is output)
P5_3
Input port
BCLK output
BCLK output
P5_4
Input port
HLDA output (The output
value
depends on the input to the
HOLD pin)
HLDA output (The output
value
depends on the input to the
HOLD pin)
P5_5
Input port
HOLD input
HOLD input
P5_6
Input port
ALE output (“L” is output)
ALE output (“L” is output)
P5_7
Input port
RDY input
RDY input
P6, P7, P8_0 to P8_4, Input port
P8_6, P8_7, P9, P10
Input port
Input port
P11, P12, P13, P14_0, Input port
P14_1 (2)
Input port
Input port
NOTES:
1. Shown here is the valid pin state when the internal power supply voltage has stabilized after power
on.
When CNVSS = VCC1, the pin state is indeterminate until the internal power supply voltage
stabilizes.
2. P11, P12, P13, P14_0, P14_1 pins exist in 128-pin version.
5.2
Brown-out Detection Reset (Hardware Reset 2)
The microcomputer resets pins, the CPU or SFR by setting the built-in voltage detect circuit. The voltage detect
circuit monitors the voltage applied to the VCC1 pin.
When the VC26 bit in the VCR2 register is set to “1” (reset level detect circuit enabled), the microcomputer
resets pins, the CPU and SFR as soon as the voltage that is applied to the VCC1 pin drops to Vdet3 or below.
The microcomputer resets pins and it is in a reset state when the voltage that is applied to the VCC1 pin is
Vdet3 or below. The microcomputer resets pins, CPU and SFR with Vdet3r or above and it executes the
program from the address determined by the reset vector. The microcomputer executes the program after
detecting Vdet3r and waiting td(S-R) ms. The same pins and registers are reset by the hardware reset 1 and
brown-out detection reset (hardware reset 2), and are also placed in the same reset state.
The microcomputer cannot exit stop mode by the brown-out detection reset (hardware reset 2).
Rev.2.41 Jan 10, 2006
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M16C/62P Group (M16C/62P, M16C/62PT)
5.3
5. Reset
Software Reset
The microcomputer resets pins, the CPU and SFR when the PM03 bit in the PM0 register is set to “1”
(microcomputer reset). Then the microcomputer executes the program in an address determined by the reset vector.
Set the PM03 bit to “1” while the main clock is selected as the CPU clock and the main clock oscillation is stable.
In the software reset, the microcomputer does not reset a part of the SFR. Refer to 4. Special Function Register
(SFR) for details.
Processor mode remains unchanged since the PM01 to PM00 bits in the PM0 register are not reset.
5.4
Watchdog Timer Reset
The microcomputer resets pins, the CPU and SFR when the CM06 bit in the CM0 register is set to “1” (reset) and
the watchdog timer underflows. Then the microcomputer executes the program in an address determined by the
reset vector.
In the watchdog timer reset, the microcomputer does not reset a part of the SFR. Refer to 4. Special Function
Register (SFR) for details. Processor mode remains unchanged since the PM01 to PM00 bits in the PM0 register
are not reset.
5.5
Oscillation Stop Detection Reset
The microcomputer resets and stops pins, the CPU and SFR when the CM27 bit in the CM2 register is 0, if it
detects main clock oscillation circuit stop. Refer to 10.6 Oscillation Stop and Re-oscillation Detect Function for
details.
In the oscillation stop detection reset, the microcomputer does not reset a part of the SFR. Refer to 4. Special
Function Register (SFR) for details. Processor mode remains unchanged since the PM01 to PM00 bits in the
PM0 register are not reset.
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M16C/62P Group (M16C/62P, M16C/62PT)
5.6
5. Reset
Internal Space
Figure 5.3 shows CPU Register Status After Reset. Refer to 4. Special Function Register (SFR) for SFR states
after reset.
b15
b0
0000h
Data Register(R0)
0000h
Data Register(R1)
0000h
Data Register(R2)
0000h
Data Register(R3)
0000h
Address Register(A0)
0000h
Address Register(A1)
0000h
Frame Base Register(FB)
b19
b0
00000h
Interrupt Table Register(INTB)
Content of addresses FFFFEh to FFFFCh
b15
Program Counter(PC)
b0
0000h
User Stack Pointer(USP)
0000h
Interrupt Stack Pointer(ISP)
0000h
Static Base Register(SB)
b15
b0
Flag Register(FLG)
0000h
b15
b8
IPL
Figure 5.3
b7
U I
b0
O B S Z D C
CPU Register Status After Reset
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M16C/62P Group (M16C/62P, M16C/62PT)
6.
6. Voltage Detection Circuit
Voltage Detection Circuit
Note
The M16C/62PT do not use the voltage detection circuit.
However, the cold start-up/warm start-up determine function is available.
The voltage detection circuit consists of the reset level detection circuit and the low voltage detection circuit.
The reset level detection circuit monitors the voltage applied to the VCC1 pin. The microcomputer is reset if the reset
level detection circuit detects VCC1 is Vdet3 or below. This circuit is disabled when the microcomputer is in stop
mode.
The voltage detection circuit also monitors the voltage applied to the VCC1 pin. The low voltage detection signal is
generated when the low voltage detection circuit detects VCC1 is above or below Vdet4. This signal generates the low
voltage detection interrupt. The VC13 bit in the VCR1 register determines whether VCC1 is above or below Vdet4.
The voltage detection circuit is available when VCC1=5.0V.
Figure 6.1 shows a Voltage Detection Circuit Block.
.
VCR2 Register
RESET
b7 b6
Brown-out Detection Reset
(Hardware Reset 2
Release Wait Time)
1 shot
Reset Level
Detection Circuit
td(S-R)
>T
Q
+
≥Vdet3
E
CM10 Bit=1
(Stop Mode)
Internal Reset Signal
(“L” active)
+
VCC1
≥Vdet4
E
Low Voltage
Detection Signal
Noise Rejection
VCR1 Register
Low Voltage
Detection Circuit
b3
VC13 Bit
Figure 6.1
Voltage Detection Circuit Block
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M16C/62P Group (M16C/62P, M16C/62PT)
6. Voltage Detection Circuit
Voltage Detection Register 1
b7 b6 b5 b4 b3 b2 b1 b0
0 0 0 0
0 0 0
Symbol
Address
0019h
VCR1
Bit Name
Bit Symbol
—
Reserved Bit
(b2-b0)
Low Voltage Monitor Flag (1)
VC13
—
(b7-b4)
Reserved Bit
After Reset (2)
00001000b
Function
Set to “0”
RW
RW
0 : VCC1 < Vdet4
1 : VCC1 ≥ Vdet4
Set to “0”
RO
RW
NOTES :
1. The VC13 bit is useful w hen the VC27 bit in the VCR2 register is set to “1” (low voltage detection circuit enable).
The VC13 bit is alw ays “1” (VCC1 ≥ Vdet4) w hen the VC27 bit is set to “0” (low voltage detection circuit disable).
2. This register dose not change at softw are reset, w atchdog timer reset and oscillation stop detection reset.
Voltage Detection Register 2 (1)
b7 b6 b5 b4 b3 b2 b1 b0
0 0 0 0 0 0
Address
Symbol
001Ah
VCR2
Bit Name
Bit Symbol
—
Reserved Bit
(b5-b0)
Reset Level Monitor Bit (2, 3, 6)
VC26
VC27
Low Voltage Monitor Bit (4, 6)
After Reset (5)
00h
Function
Set to “0”
RW
RW
0 : Disable reset level detection circuit
1 : Enable reset level detection circuit
RW
0 : Disable low voltage detection circuit
1 : Enable low voltage detection circuit
RW
NOTES :
1. Write to this register after setting the PRC3 bit in the PRCR register to “1” (w rite enable).
2. To use low voltage detection (hardw are reset 2), set the VC26 bit to “1” (reset level detection circuit enable).
3. VC26 bit is disabled in stop mode (the microcomputer is not reset even if the voltage input to VCC1 pin becomes
low er than Vdet3).
4. Where the VC13 bit in the VCR1 register and D42 bit in the D4INT register are used or the D40 bit is set to “1” (low
voltage detection interrupt enable), set the VC27 bit to “1” (low voltage detection circuit enable).
5. This register dose not change at softw are reset, w atchdog timer reset and oscillation stop detection reset.
6. The detection circuit dose not start operation until td(E-A) elapses after the VC26 bit, or VC27 bit is set to “1”.
Figure 6.2
VCR1 and VCR2 Registers
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M16C/62P Group (M16C/62P, M16C/62PT)
6. Voltage Detection Circuit
Low Voltage Detection Interrupt Register (1)
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
D4INT
Address
001Fh
Bit Symbol
D40
Bit Name
D43
DF0
RW
0 : Disable
1 : Enable
RW
STOP Mode Deactivation Control
Bit (4)
0 : Disable (do not use the Low voltage
detection interrupt to get out of stop
mode)
1 : Enable (use the low voltage detection
interrupt to get out of stop mode)
RW
Voltage Change Detection Flag (2)
0 : Not detected
1 : Vdet4 passing detection
RW (3)
WDT Overflow Detect Flag
0 : Not detected
1 : Detected
RW (3)
Sampling Clock Select Bit
b5 b4
0 0 : CPU clock divided by
0 1 : CPU clock divided by
1 0 : CPU clock divided by
1 1 : CPU clock divided by
DF1
—
(b7-b6)
Function
Low Voltage Detection Interrupt
Enable Bit (5)
D41
D42
After Reset
00h
8
16
32
64
Nothing is assigned. When w rite, set to “0”.
When read, their contents are “0”.
RW
RW
—
NOTES :
1. Write to this register after setting the PRC3 bit in the PRCR register to “1” (w rite enable).
2. Useful w hen the VC27 bit in the VCR2 register is set to “1” (low voltage detection circuit enabled). If the VC27 bit is
set to “0” (low voltage detection circuit disabled), the D42 bit is set to “0” (Not detect).
3. This bit is set to “0” by w riting a “0” in a program. (Writing a “1” has no effect.)
4. If the low voltage detection interrupt needs to be used to get out of stop mode again after once used for that
purpose, reset the D41 bit by w riting a “0” and then a “1”.
5. The D40 bit is effective w hen the VC27 bit = 1. To set the D40 bit to “1”, set bits in the follow ing order.
(a) Set the VC27 bit to “1”.
(b) Wait for td(E-A) until the detection circuit is actuated.
(c) Wait for the sampling time. (See Table 6.2 Sam pling Period.)
(d) Set the D40 bit to “1”.
Figure 6.3
D4INT Register
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M16C/62P Group (M16C/62P, M16C/62PT)
6. Voltage Detection Circuit
5.0V
5.0V
Vdet4
Vdet3r
Vdet3
VCC1
Vdet3s
VSS
RESET
Internal Reset Signal
VC13 bit in
VCR1 register
Indefinite
VC26 bit in
VCR2 register (1)
Indefinite
VC27 bit in
VCR2 register
Indefinite
Set to “1” by program (reset level detect circuit enable)
Set to “1” by program
(Low voltage detection circuit enable)
NOTES :
1. VC26 bit is invalid (the microcomputer is not reset even if input voltage of VCC1 pin
becomes lower than Vdet3).
Figure 6.4
Typical Operation of Brown-out Detection Reset (Hardware Reset 2)
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M16C/62P Group (M16C/62P, M16C/62PT)
6.1
6. Voltage Detection Circuit
Low Voltage Detection Interrupt
If the D40 bit in the D4INT register is set to “1” (low voltage detection interrupt enabled), the low voltage detection
interrupt request is generated when the voltage applied to the VCC1 pin is above or below Vdet4.
The low voltage detection interrupt shares the same interrupt vector with the watchdog timer interrupt and
oscillation stop, re-oscillation detection interrupt.
Set the D41 bit in the D4INT register to “1” (enabled) to use the low voltage detection interrupt to exit stop mode.
The D42 bit in the D4INT register is set to “1” as soon as the voltage applied to the VCC1 pin reaches Vdet4 due to
the voltage rise and voltage drop. When the D42 bit changes “0” to “1”, the low voltage detection interrupt request
is generated. Set the D42 bit to “0” by program. However, when the D41 bit is set to “1” and the microcomputer is
in stop mode, the low voltage detection interrupt request is generated regardless of the D42 bit state if the voltage
applied to the VCC1 pin is detected to be above Vdet4. The microcomputer then exits stop mode.
Table 6.1 shows Low Voltage Detection Interrupt Request Generation Conditions.
The DF1 to DF0 bits in the D4INT register determine the sampling period that detects the voltage applied to the
VCC1 pin reaches Vdet4. Table 6.2 shows the Sampling Periods.
Table 6.1
Low Voltage Detection Interrupt Request Generation Conditions
Operating Mode
VC27 Bit
D40 Bit
Normal Operating
Mode (1)
1
Wait Mode (2)
Stop Mode
1
(2)
D41 Bit
D42 Bit
CM02 Bit
−
0 to 1
−
−
0 to 1
0
1
−
−
1
0
VC13 Bit
0 to 1 (3)
1 to 0 (3)
0 to 1 (3)
1 to 0 (3)
0 to 1
0 to 1
− : “0”or “1”
1. The status except the wait mode and stop mode is handled as the normal mode. (Refer to 10. Clock
Generation Circuit)
2. Refer to 6.2 Limitations on Exiting Stop Mode, 6.3 Limitations on Exiting Wait Mode.
3. An interrupt request for voltage reduction is generated a sampling time after the value of the VC13
bit has changed.
See the Figure 6.6 Low Voltage Detection Interrupt Generation Circuit Operation Example for
details.
Table 6.2
Sampling Periods
Sampling Clock (µs)
DF1 to DF0=01
DF1 to DF0=10
CPU Clock
(D4INT clock)
DF1 to DF0=00
(MHz)
(CPU clock divided by 8)
(CPU clock divided by 16)
(CPU clock divided by 32)
(CPU clock divided by 64)
16
3.0
6.0
12.0
24.0
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DF1 to DF0=11
M16C/62P Group (M16C/62P, M16C/62PT)
6. Voltage Detection Circuit
Low Voltage detection interrupt generation circuit
DF1, DF0
00b
The D42 bit is set to “0” (not detected)
by program. The VC27 bit is set to “0”
(voltage down detect circuit disabled),
the D42 bit is set to “0”.
01b
Low Voltage detection Circuit
10b
D4INT clock (the
clock with which it
operates also in
wait mode)
VC27
1/8
1/2
1/2
1/2
11b
D42
VC13
VCC1
+
VREF
-
Noise
Rejection
Digital
Filter
Noise Rejection
Circuit
Low Voltage
detection signal
Watchdog
timer interrupt
signal
(Rejection Range : 200 ns)
The Low Voltage detection signal
becomes “H” when the VC27 bit is
set to “0” (disabled)
Low Voltage
detection interrupt
D41
signal
CM10
Oscillation stop,
re-oscillation
detection
interrupt signal
CM02
WAIT instruction (wait mode)
Watchdog Timer Block
D43
D40
Watchdog timer
underflow signal
Figure 6.5
This bit is set to “0” (not detected) by program.
Low Voltage detection Interrupt Generation Block
VCC1
VC13 bit in VCR1 register
sampling
sampling
sampling
sampling
No low voltage detection interrupt signals are
generated when the D42 bit is “H”.
Output of the digital filter
(2)
D42 bit in D4INT register
Set to “0” by program (not detected)
Low Voltage detection
interrupt signal
NOTES :
1. D40 bit in the D4INT register is set to “1” (low voltage detection interrupt enabled).
2. Output of the digital filter is shown in Figure 6.5.
Figure 6.6
Low Voltage Detection Interrupt Generation Circuit Operation Example
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Non-maskable
interrupt signal
M16C/62P Group (M16C/62P, M16C/62PT)
6.2
6. Voltage Detection Circuit
Limitations on Exiting Stop Mode
The low voltage detection interrupt is immediately generated and the microcomputer exits stop mode if the CM10
bit in the CM1 register is set to “1” under the conditions below.
• the VC27 bit in the VCR2 register is set to “1” (low voltage detection circuit enabled),
• the D40 bit in the D4INT register is set to “1” (low voltage detection interrupt enabled),
• the D41 bit in the D4INT register is set to “1” (low voltage detection interrupt is used to exit stop mode), and
• the voltage applied to the VCC1 pin is higher than Vdet4 (the VC13 bit in the VCR1 register is “1”)
If the microcomputer is set to enter stop mode when the voltage applied to the VCC1 pin drops below Vdet4 and to
exit stop mode when the voltage applied rises to Vdet4 or above, set the CM10 bit to “1” when VC13 bit is “0”
(VCC1 < Vdet4).
6.3
Limitations on Exiting Wait Mode
The low voltage detection interrupt is immediately generated and the microcomputer exits wait mode If WAIT
instruction is executed under the conditions below.
• the CM02 bit in the CM0 register is set to “1” (stop peripheral function clock),
• the VC27 bit in the VCR2 register is set to “1” (low voltage detection circuit enabled),
• the D40 bit in the D4INT register is set to “1” (low voltage detection interrupt enabled),
• the D41 bit in the D4INT register is set to “1” (low voltage detection interrupt is used to exit wait mode), and
• the voltage applied to the VCC1 pin is higher than Vdet4 (the VC13 bit in the VCR1 register is “1”)
If the microcomputer is set to enter wait mode when the voltage applied to the VCC1 pin drops below Vdet4 and to
exit wait mode when the voltage applied rises to Vdet4 or above, perform WAIT instruction when VC13 bit is “0”
(VCC1 < Vdet4).
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M16C/62P Group (M16C/62P, M16C/62PT)
6.4
6. Voltage Detection Circuit
Cold Start-up / Warm Start-up Determine Function
As for the cold start-up/warm start-up determine function, the WDC5 flag in the WDC register determines either
cold start-up (reset process) when power-on or warm start-up (reset process) when reset signal is applied during the
microcomputer running.
Default value of the WDC5 bit is “0” (cold start-up) when power-on. It is set to “1” (warm start-up) by writing
desired values to the WDC register. The WDC bit is not reset, regardless of a software reset or a reset operation.
Figure 6.7 shows Cold Start-up/Warm Start-up Determine Function Block Diagram. Figure 6.8 shows the Cold
Start-up/Warm Start-up Determine Function Operation Example. Figure 6.9 shows WDC Register.
WDC5 Bit
Write to WDC register
S
Internal power on reset
Figure 6.7
Q
WARM/COLD
(Cold start, warm start)
R
Cold Start-up/Warm Start-up Determine Function Block Diagram
5V
VCC
0V
5V
Pch transistor ON (about 4V)
CPU reset is deasserted
RESET
0V
T1
“1”
Set to “1” by program
T2
T > 100 µsec.
WDC5 Flag
“1” is held even if
RESET becomes 0V.
“0”
Program start
Reset Sequence (16MHz, about 20 µsec.)
Becomes “0” on the rising
edge of VCC
NOTES:
1. The timing of which WDC5 is set is affected by how the RESET signal rises (Time lag between T1 and T2).
Figure 6.8
Cold Start-up/Warm Start-up Determine Function Operation Example
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M16C/62P Group (M16C/62P, M16C/62PT)
6. Voltage Detection Circuit
Watchdog Timer Control Register
b7 b6 b5 b4 b3 b2 b1 b0
0
Symbol
Address
000Fh
WDC
Bit Symbol
Bit Name
—
High-order Bit of Watchdog Timer
(b4-b0)
WDC5
—
(b6)
WDC7
After Reset
00XXXXXXb(2)
Function
RW
RO
Cold Start / Warm Start Discrimination
Flag (1, 2)
0 : Cold Start
1 : Warm Start
Reserved Bit
Set to “0”
Prescaler Select Bit
0 : Divided by 16
1 : Divided by 128
RW
RW
RW
NOTES :
1. Writing to the WDC register factors the WDC5 bit to be set to “1” (w arm start). If the voltage applied to VCC1 is less
than 4.0 V, either w rite to this register w hen the CPU clock frequency is 2 MHz or w rite tw ice.
2. The WDC5 bit is set to “0” (cold start) w hen pow er is turned on and can be set to “1” by program only.
Figure 6.9
WDC Register
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M16C/62P Group (M16C/62P, M16C/62PT)
7.
7. Processor Mode
Processor Mode
Note
The M16C/62P (80-pin version) and M16C/62PT do not use memory expansion mode, and microprocessor
mode.
7.1
Types of Processor Mode
Three processor modes are available to choose from: single-chip mode, memory expansion mode, and
microprocessor mode. Table 7.1 shows the Features of Processor Modes.
Table 7.1
Features of Processor Modes
Processor Modes
Single-Chip Mode
Memory Expansion
Mode
Microprocessor
Mode
Access Space
Pins which are Assigned I/O Ports
SFR, Internal RAM, Internal ROM All pins are I/O ports or peripheral function I/O
pins
SFR, Internal RAM, Internal ROM, Some pins serve as bus control pins (1)
External Area (1)
SFR, Internal RAM, External Area Some pins serve as bus control pins (1)
(1)
NOTES:
1. Refer to 8. Bus.
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M16C/62P Group (M16C/62P, M16C/62PT)
7.2
7. Processor Mode
Setting Processor Modes
Processor mode is set by using the CNVSS pin and the PM01 to PM00 bits in the PM0 register.
Table 7.2 shows the Processor Mode After Hardware Reset. Table 7.3 shows the PM01 to PM00 Bits Set Values
and Processor Modes.
Table 7.2
Processor Mode After Hardware Reset
CNVSS Pin Input Level
VSS
VCC1 (1, 2)
Processor Modes
Single-Chip Mode
Microprocessor Mode
NOTES:
1. If the microcomputer is reset in hardware by applying VCC1 to the CNVSS pin (hardware reset 1 or
brown-out detection reset (hardware reset 2)), the internal ROM cannot be accessed regardless of
PM10 to PM00 bits.
2. The multiplexed bus cannot be assigned to the entire CS space.
Table 7.3
PM01 to PM00 Bits Set Values and Processor Modes
PM01 to PM00 Bits
00b
01b
10b
11b
Processor Modes
Single-Chip Mode
Memory Expansion Mode
Do not set
Microprocessor Mode
Rewriting the PM01 to PM00 bits places the microcomputer in the corresponding processor mode regardless of
whether the input level on the CNVSS pin is “H” or “L”. Note, however, that the PM01 to PM00 bits cannot be
rewritten to “01b” (memory expansion mode) or “11b” (microprocessor mode) at the same time the PM07 to PM02
bits are rewritten. Note also that these bits cannot be rewritten to enter microprocessor mode in the internal ROM,
nor can they be rewritten to exit microprocessor mode in areas overlapping the internal ROM.
If the microcomputer is reset in hardware by applying VCC1 to the CNVSS pin (hardware reset 1 or brown-out
detection reset (hardware reset 2)), the internal ROM cannot be accessed regardless of PM01 to PM00 bits.
Figures 7.1 and 7.2 show the PM0 Register and PM1 Register. Figure 7.3 show the Memory Map in Single Chip
Mode.
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M16C/62P Group (M16C/62P, M16C/62PT)
7. Processor Mode
Processor Mode Register 0 (1)
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
PM0
Bit Symbol
PM00
Address
0004h
Bit Name
Processor Mode Bit (4)
PM03
PM04
Function
b1 b0
0 0 : Single-chip mode
0 1 : Memory expansion mode
1 0 : Do not set
1 1 : Microprocessor mode
PM01
PM02
After Reset
00000000b (CNVSS pin = L)
00000011b (CNVSS pin = H)
R/W Mode Select Bit (2)
Softw are Reset Bit
RW
RW
RW
___ _____ ____
0 : RD, BHE, WR
___ ______ _____
1 : RD, WRH, WRL
Setting this bit to “1” resets the microcomputer.
When read, its content is “0”.
Multiplexed Bus Space Select b5 b4
Bit (2)
0 0 : Multiplexed bus is unused
___
(Separate bus in the entire CS space)
RW
RW
RW
_____
0 1 : Allocated to CS2 space
_____
1 0 : Allocated to CS1 space
___
1 1 : Allocated to the entire CS space (3)
PM05
PM06
PM07
RW
Port P4_0 to P4_3 Function
Select Bit (2)
0 : Address output
1 : Port function (Address is not output)
RW
BCLK Output Disable Bit (2)
0 : BCLK is output
1 : BCLK is not output (Pin is left high-impedance)
RW
NOTES :
1. Write to this register after setting the PRC1 bit in the PRCR register to “1” (w rite enable).
2. Effective w hen the PM01 to PM00 bits are set to “01b” (memory expansion mode) or “11b” (microprocessor mode).
3. To set the PM01 to PM00 bits are “01b” and the PM05 to PM04 bits are “11b” (multiplexed bus assigned to the entire
___
CS space), apply an “H” signal to the BYTE pin (external data bus is 8 bits w ide). While the CNVSS pin is held “H”
(= VCC1), do not rew rite the PM05 to PM04 bits to “11b” after reset.
If the PM05 to PM04 bits are set to “11b” during memory expansion mode, P3_1 to P3_7 and P4_0 to P4_3 become
___
I/O ports, in w hich case the accessible area for each CS is 256 bytes.
4. The PM01 to PM00 bits do not change at softw are reset, w atchdog timer reset and oscillation stop detection reset.
Figure 7.1
PM0 Register
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M16C/62P Group (M16C/62P, M16C/62PT)
7. Processor Mode
Processor Mode Register 1 (1)
b7 b6 b5 b4 b3 b2 b1 b0
0
Symbol
PM1
Address
0005h
After Reset
0X001000b
Bit Symbol
Bit Name
Function
PM10
CS2 Area Sw itch Bit
(Data Block Enable Bit)
PM11
PM12
PM13
0 : 08000h to 26FFFh (Block A disable)
1 : 10000h to 26FFFh (Block A enable)
RW
Port P3_7 to P3_4 Function Select
Bit (3)
0 : Address output
1 : Port function
RW
Watchdog Timer Function Select Bit
0 : Watchdog timer interrupt
1 : Watchdog timer reset (4)
RW
Internal Reserved Area Expansion
Bit (6)
(NOTE 7)
Memory Area Expansion Bit (3)
b5 b4
(2)
PM14
0 0 : 1-Mbyte mode (Do not expand)
0 1 : Do not set
1 0 : Do not set
1 1 : 4-Mbyte mode
PM15
—
(b6)
PM17
RW
Reserved Bit
Set to “0”.
Wait Bit (5)
0 : No w ait state
1 : With w ait state (1 w ait)
RW
RW
RW
RW
RW
NOTES :
1. Write to this register after setting the PRC1 bit in the PRCR register to “1” (w rite enable).
2. Set the PM10 bit to “0” for Mask ROM version. For flash memory version, the PM10 bit controls w hether Block A is
enabled or disabled. When the PM10 bit is set to “1”, 0F000h to 0FFFFh can be used as internal ROM area.
In addition, the PM10 bit is automatically set to “1” w hile the FMR01 bit in the FMR0 register is set to “1” (CPU
rew rite mode).
3. Effective w hen the PM01 to PM00 bits are set to “01b” (memory expansion mode) or “11b” (microprocessor
mode).
4. PM12 bit is set to “1” by w riting a “1” in a program (w riting a “0” has no effect).
5. When PM17 bit is set to “1” (w ith w ait state), one w ait state is inserted w hen accessing the internal RAM, or
internal ROM.
When PM17 bit is set to “1” and accesses an external area, set the CSiW bit in the CSR register (i=0 to 3) to “0”
(w ith w ait state).
6. The PM13 bit is automatically set to “1” w hen the FMR01 bit in the FMR0 register is “1” (CPU rew rite mode).
7. The access area is changed by the PM13 bit as listed in the table below .
Access Area
PM13=0
PM13=1
RAM Up to Addresses 00400h to 03FFFh (15 Kbytes)
The entire area is usable
Internal
ROM Up to Addresses D0000h to FFFFFh (192 Kbytes) The entire area is usable
External
Figure 7.2
Address 04000h to 07FFFh are usable
Address 80000h to CFFFFh are usable
PM1 Register
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Address 04000h to 07FFFh are reserved
Address 80000h to CFFFFh are reserved
(Memory expansion mode)
M16C/62P Group (M16C/62P, M16C/62PT)
Single-Chip Mode
00000h
SFR
00400h
Internal RAM
XXXXXh
Can not use
YYYYYh
Internal ROM
FFFFFh
7. Processor Mode
PM13=0
Internal RAM
Capacity
Address XXXXXh
Internal ROM
Capacity
Address YYYYYh
4 Kbytes
5 Kbytes
10 Kbytes
12 Kbytes
16 Kbytes
20 Kbytes
24 Kbytes
31 Kbytes
48 Kbytes
64 Kbytes
96 Kbytes
013FFh
017FFh
02BFFh
033FFh
03FFFh(2)
03FFFh(2)
03FFFh(2)
03FFFh(2)
128 Kbytes
192 Kbytes
256 Kbytes
320 Kbytes
384 Kbytes
512 Kbytes
F4000h
F0000h
E8000h
E0000h
D0000h
D0000h(2)
D0000h(2)
D0000h(2)
D0000h(2)
PM13=1
Internal RAM
Capacity
Address XXXXXh
4 Kbytes
013FFh
5 Kbytes
017FFh
10 Kbytes
02BFFh
12 Kbytes
033FFh
16 Kbytes
20 Kbytes
24 Kbytes
31 Kbytes
043FFh
053FFh
063FFh
07FFFh
Internal ROM
Capacity
Address YYYYYh
48 Kbytes
F4000h
64 Kbytes
F0000h
96 Kbytes
128 Kbytes
192 Kbytes
E8000h
E0000h
D0000h
256 Kbytes
320 Kbytes
384 Kbytes
512 Kbytes
C0000h
B0000h
A0000h
80000h
NOTES :
1. For the mask ROM version, set the PM10 bit to “0” (08000h to 26FFFh for CS2 area).
2. If PM13 bit is set to “0”, 15 Kbytes of the internal RAM and 192 Kbytes of the internal ROM can be used.
Figure 7.3
Memory Map in Single Chip Mode
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M16C/62P Group (M16C/62P, M16C/62PT)
8.
8. Bus
Bus
Note
The M16C/62P (80-pin version) and M16C/62PT do not use bus control pins.
During memory expansion or microprocessor mode, some pins serve as the bus control pins to perform data input/
output to and from external devices. These bus control pins include A0 to A19, D0 to D15, CS0 to CS3, RD, WRL/
WR, WRH/BHE, ALE, RDY, HOLD, HLDA and BCLK.
8.1
Bus Mode
The bus mode, either multiplexed or separate, can be selected using the PM05 to PM04 bits in the PM0 register.
Table 8.1 shows the Difference Between a Separate Bus and Multiplexed Bus.
8.1.1
Separate Bus
In this bus mode, data and address are separate.
8.1.2
Multiplexed Bus
In this bus mode, data and address are multiplexed.
8.1.2.1
When the input level on BYTE pin is high (8-bit data bus)
D0 to D7 and A0 to A7 are multiplexed.
8.1.2.2
When the input level on BYTE pin is low (16-bit data bus)
D0 to D7 and A1 to A8 are multiplexed. D8 to D15 are not multiplexed. Do not use D8 to D15. External devices
connecting to a multiplexed bus are allocated to only the even addresses of the microcomputer. Odd
addresses cannot be accessed.
Table 8.1
Difference Between a Separate Bus and Multiplexed Bus
Pin Name (1)
Separate Bus
P0_0 to P0_7/D0 to D7
P1_0 to P1_7/D8 to D15
BYTE = H
BYTE = L
D0 to D7
(NOTE 2)
(NOTE 2)
D8 to D15
I/O Port
P1_0 to P1_7
(NOTE 2)
P2_0/A0 (/D0/-)
P2_1 to P2_7/A1 to A7
(/D1 to D7/D0 to D6)
Multiplex Bus
A0
A0
D0
A0
A1 to A7
A1 to A7
D1 to D7
A1 to A7 D0 to D6
P3_0/A8 (/-/D7)
A8
A8
A8
D7
NOTES:
1. See Table 8.6 Pin Functions for Each Processor Mode for bus control signals other than the
above. Setting Processor Modes.
2. It changes with a setup of PM05 to PM04, and area to access.
See Table 8.6 Pin Functions for Each Processor Mode for details.
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M16C/62P Group (M16C/62P, M16C/62PT)
8.2
8. Bus
Bus Control
The following describes the signals needed for accessing external devices and the functionality of software wait.
8.2.1
Address Bus
The address bus consists of 20 lines, A0 to A19. The address bus width can be chosen to be 12, 16 or 20 bits by
using the PM06 bit in the PM0 register and the PM11 bit in the PM1 register. Table 8.2 shows the PM06 and
PM11 Bits Set Value and Address Bus Width.
Table 8.2
PM06 and PM11 Bits Set Value and Address Bus Width
Set Value (1)
Pin Function
Address Bus Width
PM11=1
P3_4 to P3_7
12 bits
PM06=1
P4_0 to P4_3
PM11=0
A12 to A15
PM06=1
P4_0 to P4_3
PM11=0
A12 to A15
PM06=0
A16 to A19
16 bits
20 bits
NOTES:
1. No values other than those shown above can be set.
When processor mode is changed from single-chip mode to memory extension mode, the address bus is
indeterminate until any external area is accessed.
8.2.2
Data Bus
When input on the BYTE pin is high (data bus is 8 bits wide), 8 lines D0 to D7 comprise the data bus; when
input on the BYTE pin is low(data bus is 16 bits wide), 16 lines D0 to D15 comprise the data bus.
Do not change the input level on the BYTE pin while in operation.
8.2.3
Chip Select Signal
The chip select (hereafter referred to as the CSi) signals are output from the CSi (i = 0 to 3) pins. These pins
can be chosen to function as I/O ports or as CS by using the CSi bit in the CSR register.
Figure 8.1 shows the CSR Register.
During 1-Mbyte mode, the external area can be separated into up to 4 by the CSi signal which is output from the
CSi pin. During 4-Mbyte mode, CSi signal or bank number is output from the CSi pin. Refer to 9. Memory
Space Expansion Function. Figure 8.2 shows the Example of Address Bus and CSi Signal Output in 1-Mbyte
mode.
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M16C/62P Group (M16C/62P, M16C/62PT)
8. Bus
Chip Select Control Register
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
Address
0008h
CSR
Bit Name
Bit Symbol ____
CS0 Output Enable Bit
CS0
____
CS1
CS1 Output Enable Bit
After Reset
00000001b
Function
0 : Chip select output disabled
(functions as I/O port)
1 : Chip select output enabled
RW
RW
RW
____
CS2
CS2 Output Enable Bit
RW
____
CS3
CS3 Output Enable Bit
RW
____
CS0W
0 : With w ait state
1 : Without w ait state (1, 2, 3)
CS0 Wait Bit
RW
____
CS1W
CS1 Wait Bit
RW
____
CS2W
CS2 Wait Bit
RW
____
CS3W
CS3 Wait Bit
RW
NOTES :
_____
____
1. Where the RDY signal is used in the area indicated by CSi (i = 0 to 3) or the multiplex bus is used, set the CSiW bit to
(w ith w ait state).
2. If the PM17 bit in the PM1 register is set to “1” (w ith w ait state), set the CSiW bit to “0” (w ith w ait state).
3. When the CSiW bit = 0 (w ith w ait state), the number of w ait states can be selected using the CSEi1W to CSEi0W bits
in the CSE register.
Figure 8.1
CSR Register
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M16C/62P Group (M16C/62P, M16C/62PT)
Example 1
8. Bus
Example 2
To access the external area indicated by CSj in the next cycle after
accessing the external area indicated by CSi
To access the internal ROM or internal RAM in the next cycle after
accessing the external area indicated by CSi
The address bus and the chip select signal both change state between
these two cycles.
The chip select signal changes state but the address bus does not
change state
Access to the external
area indicated by CSi
Access to the external
area indicated by CSj
Access to the external Access to the internal
area indicated by CSi ROM or internal RAM
BCLK
BCLK
Read signal
Read signal
Data
Data bus
Address Address
Address bus
Data bus
Address bus
Data
CSi
Data
Address
CSi
CSj
Example 3
Example 4
To access the external area indicated by CSi in the next cycle after
accessing the external area indicated by the same CSi
Not to access any area (nor instruction prefetch generated) in the next cycle after
accessing the external area indicated by CSi
The address bus changes state but the chip select signal does not
change state
Neither the address bus nor the chip select signal changes state between
these two cycles
Access to the external
area indicated by CSi
Access to the same
external area
Access to the external
area indicated by CSi
BCLK
BCLK
Read signal
Read signal
Data
Data bus
Address bus
Data
Address Address
CSi
Data bus
Address bus
No access
Data
Address
CSi
NOTES :
1. These examples show the address bus and chip select signal when accessing areas in two successive cycles. The chip select bus cycle
may be extended more than two cycles depending on a combination of these examples.
Shown above is the case where separate bus is selected and the area is accessed for read without wait states. i = 0 to 3, j = 0 to 3
(not including i, however)
Figure 8.2
Example of Address Bus and CSi Signal Output in 1-Mbyte mode
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M16C/62P Group (M16C/62P, M16C/62PT)
8.2.4
8. Bus
Read and Write Signals
When the data bus is 16 bits wide, the read and write signals can be chosen to be a combination of RD, BHE
and WR or a combination of RD, WRL and WRH by using the PM02 bit in the PM0 register. When the data
bus is 8 bits wide, use a combination of RD, WR and BHE.
Table 8.3 shows the Operation of RD, WRL, and WRH Signals. Table 8.4 shows the Operation of RD, WRL,
and BHE Signals.
Table 8.3
Operation of RD, WRL and WRH Signals
Data Bus Width
16-bit
(BYTE pin input = L)
Table 8.4
WRL
H
L
H
L
WRH
H
H
L
L
Status of External Data Bus
Read data
Write 1 byte of data to an even address
Write 1 byte of data to an odd address
Write data to both even and odd addresses
Operation of RD, WRL and BHE Signals
Data Bus Width
16-bit
(BYTE pin input = L)
8-bit
(BYTE pin input = H)
8.2.5
RD
L
H
H
H
RD
H
L
H
L
H
L
H
L
WRL
L
H
L
H
L
H
L
H
BHE
L
L
H
H
L
L
Not used
Not used
A0
H
H
L
L
L
L
H or L
H or L
Status of External Data Bus
Write 1 byte of data to an odd address
Read 1 byte of data from an odd address
Write 1 byte of data to an even address
Read 1 byte of data from an even address
Write data to both even and odd addresses
Read data from both even and odd addresses
Write 1 byte of data
Read 1 byte of data
ALE Signal
The ALE signal latches the address when accessing the multiplex bus space. Latch the address when the ALE
signal falls.
When BYTE Pin Input = H
When BYTE Pin Input = L
ALE
A0/D0 to A7/D7
ALE
Address
Data
A0
A1/D0 to A8/D7
A8 to A19
Address
Address
A9 to A19
NOTES :
1. If the entire CS space is assigned a multiplexed bus, these pins function as I/O ports.
Figure 8.3
Data
Address (1)
ALE Signal, Address Bus, Data Bus
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Address
M16C/62P Group (M16C/62P, M16C/62PT)
8.2.6
8. Bus
RDY Signal
This signal is provided for accessing external devices which need to be accessed at low speed. If input on the
RDY pin is asserted low at the last falling edge of BCLK of the bus cycle, one wait state is inserted in the bus
cycle. While in a wait state, the following signals retain the state in which they were when the RDY signal was
acknowledged.
A0 to A19, D0 to D15, CS0 to CS3, RD, WRL, WRH, WR, BHE, ALE, HLDA
Then, when the input on the RDY pin is detected high at the falling edge of BCLK, the remaining bus cycle is
executed. Figure 8.4 shows Example in which the Wait State was Inserted into Read Cycle by RDY Signal. To
use the RDY signal, set the corresponding bit (CS3W to CS0W bits) in the CSR register to “0” (with wait state).
When not using the RDY signal, the RDY pin must be pulled-up.
In an instance of separate bus
BCLK
RD
CSi
(i=0 to 3)
RDY
tsu(RDY - BCLK)
Accept timing of RDY signal
In an instance of multiplexed bus
BCLK
RD
CSi
(i=0 to 3)
RDY
tsu(RDY - BCLK)
: Wait using RDY signal
Accept timing of RDY signal
: Wait using software
Shown above is the case where CSEi1W to CSEi0W (i = 0 to 3) bits in the CSE register are “ 00b” (one wait state).
Figure 8.4
Example in which Wait State was Inserted into Read Cycle by RDY Signal
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M16C/62P Group (M16C/62P, M16C/62PT)
8.2.7
8. Bus
HOLD Signal
This signal is used to transfer control of the bus from the CPU or DMAC to an external circuit. When the input
on HOLD pin is pulled low, the microcomputer is placed in a hold state after the bus access then in process
finishes. The microcomputer remains in the hold state while the HOLD pin is held low, during which time the
HLDA pin outputs a low-level signal.
Table 8.5 shows the Microcomputer Status in Hold State.
Bus-using priorities are given to HOLD, DMAC, and CPU in order of decreasing precedence. However, if the
CPU is accessing an odd address in word units, the DMAC cannot gain control of the bus during two separate
accesses.
HOLD > DMAC > CPU
Figure 8.5
Table 8.5
Bus-Using Priorities
Microcomputer Status in Hold State
Item
Status
BCLK
Output
A0 to A19, D0 to D15, CS0 to CS3, RD, WRL,WRH,
WR, BHE
High-impedance
P0, P1, P3, P4 (2) High-impedance
I/O ports
P6 to P14 (1)
HLDA
Internal Peripheral Circuits
ALE Signal
Maintains status when HOLD signal is received
Output “L”
ON (but watchdog timer stops)(3)
Undefined
NOTES:
1. P11 to P14 are included in the 128-pin version.
2. When I/O port function is selected.
3. The watchdog timer dose not stop when the PM22 bit in the PM2 register is set to “1” (the count
source for the watchdog timer is the on-chip oscillator clock).
8.2.8
8.2.8 BCLK Output
If the PM07 bit in the PM0 register is set to “0” (output enable), a clock with the same frequency as that of the
CPU clock is output as BCLK from the BCLK pin. Refer to 10.2 CPU Clock and Peripheral Function Clock.
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M16C/62P Group (M16C/62P, M16C/62PT)
Table 8.6
8. Bus
Pin Functions for Each Processor Mode
Processor Mode
PM05 to PM04 bits
00b(separate bus) bits
Data Bus Width BYTE
Pin
P0_0 to P0_7
P1_0 to P1_7
P2_0
P2_1 to P2_7
8 bits
“H”
D0 to D7
I/O ports
A0
A1 to A7
16 bits
“L”
D0 to D7
D8 to D15
A0
A1 to A7
P3_0
P3_1 to P3_3
P3_4 to
PM11=0
P3_7
PM11=1
P4_0 to
PM06=0
P4_3
PM06=1
P4_4
CS0=0
CS0=1
A8
A9 to A11
A12 to A15
I/O ports
A16 to A19
I/O ports
I/O ports
A8
CS0
P4_5
CS1=0
I/O ports
CS1=1
CS1
CS2=0
I/O ports
CS2=1
CS2
CS3=0
I/O ports
CS3=1
CS3
PM02=0
WR
PM02=1
− (3)
PM02=0
BHE
PM02=1
− (3)
P4_6
P4_7
P5_0
P5_1
P5_2
RD
P5_3
BCLK
P5_4
HLDA
P5_5
HOLD
P5_6
ALE
RDY
P5_7
Memory
Expansion Mode
01b(CS2 is for multiplexed bus and 11b (multiplexed
bus for the entire
others are for separate bus)
10b(CS1 is for multiplexed bus and space) (1)
others are for separate bus)
8 bits
16 bits
8 bits
“H”
“L”
“H”
(4)
(4)
D0 to D7
I/O ports
D0 to D7
I/O ports
I/O ports
D8 to D15 (4)
A0
A0/D0
A0/D0 (2)
A1 to A7
A1 to A7
A1 to A7
/D1 to D7 (2)
/D0 to D6 (2)
/D1 to D7
A8
A8
A8/D7 (2)
I/O ports
I/O ports
Memory Expansion Mode or Microprocessor Mode
I/O ports
WRL
− (3)
WRL
− (3)
WRH
− (3)
WRH
− (3)
I/O ports : Function as I/O ports or peripheral function I/O pins.
NOTES:
1. To set the PM01 to PM00 bits are set to “01b” and the PM05 to PM04 bits are set to “11b” (multiplexed bus
assigned to the entire CS space), apply “H” to the BYTE pin (external data bus 8 bits wide). While the CNVSS
pin is held “H” (= VCC1), do not rewrite the PM05 to PM04 bits to “11b” after reset. If the PM05 to PM04 bits are
set to “11b” during memory expansion mode, P3_1 to P3_7 and P4_0 to P4_3 become I/O ports, in which case
the accessible area for each CS is 256 bytes.
2. In separate bus mode, these pins serve as the address bus.
3. If the data bus is 8 bits wide, make sure the PM02 bit is set to “0” (RD, BHE, WR).
4. When accessing the area that uses a multiplexed bus, these pins output an indeterminate value during a write.
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M16C/62P Group (M16C/62P, M16C/62PT)
8.2.9
8. Bus
External Bus Status When Internal Area Accessed
Table 8.7 shows the External Bus Status When Internal Area Accessed.
Table 8.7
External Bus Status When Internal Area Accessed
Item
SFR Accessed
Address output
A0 to A19
D0 to D15
When Read
When Write
High-impedance
Output data
RD, WR, WRL, WRH
RD, WR, WRL, WRH output
BHE
BHE output
CS0 to CS3
ALE
Output “H”
Output “L”
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Internal ROM, RAM Accessed
Maintain status before accessed
address of external area or SFR
High-impedance
Undefined
Output “H”
Maintain status before accessed status
of external area or SFR
Output “H”
Output “L”
M16C/62P Group (M16C/62P, M16C/62PT)
8.2.10
8. Bus
Software Wait
Software wait states can be inserted by using the PM17 bit in the PM1 register, the CS0W to CS3W bits in the
CSR register, and the CSE register. The SFR area is unaffected by these control bits. This area is always
accessed in 2 BCLK or 3 BCLK cycles as determined by the PM20 bit in the PM2 register. See Table 8.8 Bit
and Bus Cycle Related to Software Wait for details.
To use the RDY signal, set the corresponding CS3W to CS0W bit to “0” (with wait state). Figure 8.6 shows the
CSE Register. Table 8.8 shows the Bit and Bus Cycle Related to Software Wait. Figure 8.7 and 8.8 show the
Typical Bus Timings Using Software Wait.
Chip Select Expansion Control Register
b7 b6 b5 b4 b3 b2 b1 b0
Address
Symbol
001Bh
CSE
Bit Name
Bit Symbol _____
CS0 Wait Expansion Bit (1)
CSE00W
CSE01W
After Reset
00h
Function
b1 b0
0 0 : 1 w ait
0 1 : 2 w aits
1 0 : 3 w aits
1 1 : Do not set
RW
RW
RW
_____
CSE10W
CS1 Wait Expansion Bit (1)
b3 b2
0 0 : 1 w ait
0 1 : 2 w aits
1 0 : 3 w aits
1 1 : Do not set
CSE11W
RW
RW
_____
CSE20W
CS2 Wait Expansion Bit (1)
b5 b4
0 0 : 1 w ait
0 1 : 2 w aits
1 0 : 3 w aits
1 1 : Do not set
CSE21W
RW
RW
_____
CSE30W
CS3 Wait Expansion Bit (1)
CSE31W
b7 b6
0 0 : 1 w ait
0 1 : 2 w aits
1 0 : 3 w aits
1 1 : Do not set
RW
RW
NOTES :
1. Set the CSiW bit (i = 0 to 3) in the CSR register to “0” (w ith w ait state) before w riting to the CSEi1W to CSEi0W bits.
If the CSiW bit needs to be set to “1” (w ithout w ait state), set the CSEi1W to CSEi0W bits to “00b” before setting it.
Figure 8.6
CSE Register
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M16C/62P Group (M16C/62P, M16C/62PT)
Table 8.8
Area
SFR
Bit and Bus Cycle Related to Software Wait
Bus Mode
1
0
−
−
−
0
1
CSR Register
CS3W Bit (1)
CS2W Bit (1)
CS1W Bit (1)
CS0W Bit (1)
−
−
−
−
−
0
1
PM2
PM1
Register
Register
PM20 Bit PM17 Bit (5)
−
−
Internal
RAM,
ROM
External
Area
8. Bus
−
−
Separate
Bus
−
−
−
−
−
−
1
−
−
−
1
−
Multiplexed
Bus (2)
−
−
−
−
−
0
0
0
0
0
0
0
0
CSE Register
CSE31W to CSE30W Bit
CSE21W to CSE20W Bit
CSE11W to CSE10W Bit
CSE01W to CSE00W Bit
−
−
−
−
00b
00b
01b
10b
00b
00b
01b
10b
00b
Software
Wait
−
−
No wait
1 wait
No wait
1 wait
2 waits
3 waits
1 wait
1 wait
2 waits
3 waits
1 wait
Bus Cycle
2 BCLK cycles (3)
3 BCLK cycles (3)
1 BCLK cycle (4)
2 BCLK cycles
1 BCLK cycle
(read)
2 BCLK cycles
(write)
2 BCLK cycle (4)
3 BCLK cycles
4 BCLK cycle
2 BCLK cycle
3 BCLK cycles
3 BCLK cycles
4 BCLK cycles
3 BCLK cycles
NOTES:
1. To use the RDY signal, set this bit to “0”.
2. To access in multiplexed bus mode, set the corresponding bit of CS0W to CS3W to “0” (with wait
state).
3. When the selected CPU clock source is the PLL clock, the number of wait cycles can be altered by
the PM20 bit in the PM2 register. When using a 16 MHz or higher PLL clock, be sure to set the
PM20 bit to “0” (2 wait cycles).
4. After reset, the PM17 bit is set to “0” (without wait state), all of the CS0W to CS3W bits are set to “0”
(with wait state), and the CSE register is set to “00h” (one wait state for CS0 to CS3). Therefore, the
internal RAM and internal ROM are accessed with no wait states, and all external areas are
accessed with one wait state.
5. When PM17 bit is set to “1” and accesses an external area, set the CSiW (i=0 to 3) bits to “0” (with
wait state).
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M16C/62P Group (M16C/62P, M16C/62PT)
8. Bus
(1) Separate Bus, No Wait Setting
Bus cycle (1)
Bus cycle (1)
BCLK
Write signal
Read signal
Data bus
Address bus
Output
Address
Input
Address
CS
(2) Separate Bus, 1-Wait Setting
Bus cycle (1)
Bus cycle (1)
BCLK
Write signal
Read signal
Data bus
Address bus
Output
Input
Address
Address
CS
(3) Separate Bus, 2-Wait Setting
Bus cycle (1)
Bus cycle (1)
BCLK
Write signal
Read signal
Data bus
Address bus
Output
Address
Input
Address
CS
NOTES :
1. These example timing charts indicate bus cycle length. After this bus cycle sometimes come read and write cycles in
succession.
Figure 8.7
Typical Bus Timings Using Software Wait (1)
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M16C/62P Group (M16C/62P, M16C/62PT)
8. Bus
(1) Separate Bus, 3-Wait Setting
Bus cycle (1)
Bus cycle (1)
BCLK
Write signal
Read signal
Data bus
Input
Output
Address
Address bus
Address
CS
(2) Multiplexed Bus, 1- or 2-Wait Setting
Bus cycle (1)
Bus cycle (1)
Address
Address
BCLK
Write signal
Read signal
ALE
Address bus
Address bus/ Address
Data bus
Data output
Address
Input
CS
(3) Multiplexed Bus, 3-Wait Setting
Bus cycle (1)
Bus cycle (1)
BCLK
Write signal
Read signal
ALE
Address bus
Address bus/ Address
Data bus
Address
Address
Data output
Address
Input
CS
NOTES :
1. These example timing charts indicate bus cycle length. After this bus cycle sometimes come read and write cycles in
succession.
Figure 8.8
Typical Bus Timings Using Software Wait (2)
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M16C/62P Group (M16C/62P, M16C/62PT)
9.
9. Memory Space Expansion Function
Memory Space Expansion Function
Note
The M16C/62P (80-pin version) and M16C/62PT do not use the memory space expansion function.
The following describes a memory space extension function.
During memory expansion or microprocessor mode, the memory space expansion function allows the access space to
be expanded using the appropriate register bits.
Table 9.1 shows The Way of Setting Memory Space Expansion Function, Memory Space.
Table 9.1
The Way of Setting Memory Space Expansion Function, Memory Space
Memory Space Expansion Function
1-Mbyte Mode
4-Mbyte Mode
9.1
How to Set (PM15 to PM14)
00b
11b
Memory Space
1 Mbyte (no expansion)
4 Mbytes
1-Mbyte Mode
In this mode, the memory space is 1 Mbytes. In 1-Mbyte mode, the external area to be accessed is specified using
the CSi (i = 0 to 3) signals (hereafter referred to as the CSi area). Figures 9.2 to 9.3 show the Memory Mapping and
CS Area in 1-Mbyte mode.
9.2
4-Mbyte Mode
In this mode, the memory space is 4 Mbytes. Figure 9.1 shows the DBR Register. The BSR2 to BSR0 bits in the
DBR register select a bank number which is to be accessed to read or write data. Setting the OFS bit to “1” (with
offset) allows the accessed address to be offset by 40000h.
In 4-Mbyte mode, the CSi (i=0 to 3) pin functions differently for each area to be accessed.
9.2.1
9.2.1 Addresses 04000h to 3FFFFh, C0000h to FFFFFh
• The CSi signal is output from the CSi pin (same operation as 1-Mbyte mode. However, the last address of
CS1 area is 3FFFFh).
9.2.2
9.2.2 Addresses 40000h to BFFFFh
• The CS0 pin outputs “L”
• The CS1 to CS3 pins output the value of setting as the BSR2 to BSR0 bits (bank number)
Figures 9.4 to 9.5 show the Memory Mapping and CS Area in 4-Mbyte mode. Note that banks 0 to 6 are data-only
areas. Locate the program in bank 7 or the CSi area.
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M16C/62P Group (M16C/62P, M16C/62PT)
9. Memory Space Expansion Function
Data Bank Register (1)
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
DBR
Address
000Bh
Bit Symbol
Bit Name
—
(b1-b0)
OFS
BSR0
Function
Nothing is assigned. When w rite, set to “0”.
When read, their contents are “0”.
0 : Not offset
1 : Offset
Bank Selection Bits
b5 b4 b3
b5 b4 b3
0 0 0 : Bank 0
0 1 0 : Bank 2
1 0 0 : Bank 4
1 1 0 : Bank 6
0 0 1 : Bank 1
0 1 1 : Bank 3
1 0 1 : Bank 5
1 1 1 : Bank 7
BSR2
RW
Nothing is assigned. When w rite, set to “0”.
When read, their contents are “0”.
NOTES :
1. Effective w hen the PM01 to PM00 bits in the PM0 register are set to “01b” (memory expansion mode) or “11b”
(microprocessor mode).
Figure 9.1
DBR Register
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RW
—
Offset Bit
BSR1
—
(b7-b6)
After Reset
00h
RW
RW
RW
—
M16C/62P Group (M16C/62P, M16C/62PT)
Memory expansion mode
00000h
00400h
9. Memory Space Expansion Function
Microprocessor mode
SFR
SFR
Internal RAM
Internal RAM
Reserved area
Reserved area
XXXXXh
04000h
CS3 (16 Kbytes)
08000h Reserved, external area(2)
10000h
27000h
28000h
30000h
Reserved, external area(2)
Reserved area
CS2 (PM10=0: 124 Kbytes)
CS2 (PM10=1: 92 Kbytes)
Reserved area
CS1 (32 Kbytes)
External area
External area
CS0 (Memory expansion mode:640 Kbytes )
D0000h
Reserved area
CS0 (Microprocessor mode:832 Kbytes)
YYYYYh
Internal ROM
FFFFFh
PM13=0
Internal RAM
Capacity Address XXXXXh
4 Kbytes 013FFh
5 Kbytes 017FFh
10 Kbytes
12 Kbytes
16 Kbytes
20 Kbytes
24 Kbytes
31 Kbytes
02BFFh
033FFh
03FFFh(1)
03FFFh(1)
03FFFh(1)
03FFFh(1)
Internal ROM
Capacity Address YYYYYh
48 Kbytes F4000h
64 Kbytes F0000h
96 Kbytes E8000h
128 Kbytes
192 Kbytes
256 Kbytes
320 Kbytes
384 Kbytes
512 Kbytes
E0000h
D0000h
CS0
Memory expansion mode
30000h to CFFFFh
Microprocessor mode
30000h to FFFFFh
External Area
CS1
CS2
28000h to
When PM10=0
2FFFFh
08000h to 26FFFh
CS3
04000h to
07FFFh
When PM10=1
10000h to 26FFFh
D0000h(1)
D0000h(1)
D0000h(1)
D0000h(1)
NOTES :
1. If PM13 bit in the PM1 register is set to “0”, 15 Kbytes of the internal RAM and 192 Kbytes of the internal ROM can be used.
2. For flash memory version, when the PM10 bit in the PM1 register is set to “1”, 0F000h to 0FFFFh can be used as internal ROM area.
Figure 9.2
Memory Mapping and CS Area in 1-Mbyte mode (PM13=0)
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M16C/62P Group (M16C/62P, M16C/62PT)
Memory expansion mode
00000h
00400h
9. Memory Space Expansion Function
Microprocessor mode
SFR
SFR
Internal RAM
Internal RAM
XXXXXh
Reserved area
08000h Reserved, external area(1)
Reserved, external area(1)
CS2 (PM10=0: 124 Kbytes)
10000h
27000h
28000h
30000h
CS2 (PM10=1: 92 Kbytes)
Reserved area
Reserved area
CS1 (32 Kbytes)
External area
CS0 (Memory expansion mode : 320 Kbytes )
External area
80000h
Reserved area
CS0 (Microprocessor mode : 832 Kbytes)
YYYYYh
Internal ROM
FFFFFh
PM13=1
Internal RAM
Capacity
Address XXXXXh
Internal ROM
Address YYYYYh
Capacity
4 Kbytes
5 Kbytes
10 Kbytes
12 Kbytes
013FFh
017FFh
02BFFh
033FFh
48 Kbytes
64 Kbytes
F4000h
F0000h
Memory expansion mode
30000h to 7FFFFh
Microprocessor mode
30000h to FFFFFh
16 Kbytes
20 Kbytes
24 Kbytes
31 Kbytes
043FFh
053FFh
063FFh
07FFFh
96 Kbytes
E8000h
128 Kbytes
192 Kbytes
E0000h
D0000h
256 Kbytes
320 Kbytes
384 Kbytes
512 Kbytes
C0000h
B0000h
A0000h
80000h
CS0
External area
CS1
28000h to
2FFFFh
CS2
When PM10=0
08000h to 26FFFh
CS3
No area
When PM10=1
10000h to 26FFFh
NOTES :
1. For flash memory version, when the PM10 bit in the PM1 register is set to “1”, 0F000h to 0FFFFh can be used as internal ROM area.
Figure 9.3
Memory Mapping and CS Area in 1-Mbyte mode (PM13=1)
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M16C/62P Group (M16C/62P, M16C/62PT)
Memory expansion mode
00000h
00400h
9. Memory Space Expansion Function
Microprocessor mode
SFR
SFR
Internal RAM
Internal RAM
Reserved area
Reserved area
XXXXXh
04000h
CS3 (16 Kbytes)
08000h Reserved, external area(3)
10000h
27000h
28000h
Reserved, external area(3)
Reserved area
Reserved area
External area
External area
CS1 (96 Kbytes)
40000h
C0000h
D0000h
CS2 (PM10=0 : 124 Kbytes)
CS2 (PM10=1 : 92 Kbytes)
Other than the CS area (512 Kbytes X 8 banks)
CS0 (Memory expansion mode : 64 Kbytes )
Reserved area
CS0 (Microprocessor mode : 256 Kbytes)
YYYYYh
Internal ROM
FFFFFh
PM13=0
Internal RAM
Capacity Address XXXXXh
4 Kbytes 013FFh
5 Kbytes 017FFh
10 Kbytes 02BFFh
12 Kbytes 033FFh
16 Kbytes 03FFFh(2)
20 Kbytes 03FFFh(2)
24 Kbytes 03FFFh(2)
31 Kbytes 03FFFh(2)
Internal ROM
Address YYYYYh
Capacity
CS0
48 Kbytes F4000h
Memory expansion mode
C0000h
to
CFFFFh
64 Kbytes F0000h
96 Kbytes E8000h
Microprocessor mode
C0000h to FFFFFh
128 Kbytes E0000h
192 Kbytes
256 Kbytes
320 Kbytes
384 Kbytes
512 Kbytes
External area
CS1
28000h to
3FFFFh
CS2
When PM10=0
08000h to 26FFFh
When PM10=1
10000h to 26FFFh
CS3
04000h to
07FFFh
D0000h
D0000h(2)
D0000h(2)
D0000h(2)
D0000h(2)
NOTES :
1. The CS0 pin outputs a low signal, and the CS1 to CS3 pins output a bank number.
2. If PM13 bit in the PM1 register is set to “0”, 15 Kbytes of the internal RAM and 192 Kbytes of the internal ROM can be used.
3. For flash memory version, when the PM10 bit in the PM1 register is set to “1”, 0F000h to 0FFFFh can be used as internal ROM area.
Figure 9.4
Memory Mapping and CS Area in 4-Mbyte mode (PM13=0)
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Other than the CS area(1)
40000h to BFFFFh
M16C/62P Group (M16C/62P, M16C/62PT)
Memory expansion mode
00000h
9. Memory Space Expansion Function
Microprocessor mode
SFR
SFR
00400h
Internal RAM
Internal RAM
Reserved area
Reserved area
XXXXXh
08000h Reserved, external area(2)
Reserved, external area(2)
CS2 (PM10=0: 124 Kbytes)
10000h
27000h
28000h
CS2 (PM10=1: 92 Kbytes)
Reserved area
Reserved area
External area
External area
CS1 (96 Kbytes)
40000h
Other than the CS area (Memory expansion mode:256 Kbytes X 8 banks)*
*Two 256 Kbytes X 8 banks can be used by changing the offset.
80000h
C0000h
Other than the CS area(Microprocessor mode : 512 Kbytes X 8 banks)
Reserved area
CS0 (Microprocessor mode : 256 Kbytes)
YYYYYh
Internal ROM
FFFFFh
PM13=1
Internal RAM
Capacity Address XXXXXh
4 Kbytes
013FFh
5 Kbytes
017FFh
10 Kbytes
02BFFh
12 Kbytes
033FFh
16 Kbytes
20 Kbytes
24 Kbytes
31 Kbytes
043FFh
053FFh
063FFh
07FFFh
Internal ROM
Capacity Address YYYYYh
CS0
48 Kbytes
F4000h
Microprocessor mode
64 Kbytes
F0000h
C0000h to FFFFFh
96 Kbytes
E8000h
128 Kbytes
192 Kbytes
E0000h
D0000h
256 Kbytes
320 Kbytes
384 Kbytes
512 Kbytes
C0000h
B0000h
A0000h
80000h
CS1
28000h to
3FFFFh
External area
CS2
When PM10=0
08000h to 26FFFh
CS3
No area
When PM10=1
10000h to 26FFFh
NOTES :
1. The CS0 pin outputs a low signal, and the CS1 to CS3 pins output a bank number.
2. For flash memory version, when the PM10 bit in the PM1 register is set to “1”, 0F000h to 0FFFFh can be used as internal ROM area.
Figure 9.5
Memory Mapping and CS Area in 4-Mbyte mode (PM13=1)
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Other than the CS area (1)
Memory expansion mode
40000h to 7FFFFh
Microprocessor mode
40000h to BFFFFh
M16C/62P Group (M16C/62P, M16C/62PT)
9. Memory Space Expansion Function
Figure 9.6 shows the External Memory Connect Example in 4-Mbyte Mode.
In this example, the CS pin of 4-Mbyte ROM is connected to the CS0 pin of microcomputer. The 4 Mbyte ROM
address input AD21, AD20 and AD19 pins are connected to the CS3, CS2 and CS1 pins of microcomputer,
respectively. The address input AD18 pin is connected to the A19 pin of microcomputer. Figures Figure 9.7 to 9.9
show the Relationship of Addresses Between the 4-Mbyte ROM and the Microcomputer for the Case of a
Connection Example in Figure 9.6.
In microprocessor mode, or in memory expansion mode where the PM13 bit in the PM1 register is “0”, banks are
located every 512 Kbytes. Setting the OFS bit in the DBR register to “1” (offset) allows the accessed address to be
offset by 40000h, so that even the data overlapping a bank boundary can be accessed in succession.
In memory expansion mode where the PM13 bit is “1,” each 512-Kbyte bank can be accessed in 256 Kbyte units
by switching them over with the OFS bit.
Because the SRAM can be accessed on condition that the chip select signals S2 = H and S1 =L, CS0 and CS2 can
be connected to S2 and S1, respectively. If the SRAM does not have the input pins to accept “H” active and “L”
active chip select signals(S1, S2), CS0 and CS2 should be decoded external to the chip.
8
AD0 to AD16
A17
AD17
A19
AD18
CS1
AD19
CS2
AD20
CS3
AD21
OE
RD
CS0
CS
WR
DQ0 to DQ7
AD0 to AD16
OE
S2
S1 (1)
W
4M bytes ROM
Microcomputer
A0 to A16
DQ0 to DQ7
17
128K bytes SRAM
D0 to D7
NOTES:
1. If only one chip select pin (S1 or S2) is present,
decoding by use of an external circuit is required.
Figure 9.6
External Memory Connect Example in 4-Mbyte Mode
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M16C/62P Group (M16C/62P, M16C/62PT)
9. Memory Space Expansion Function
Memory expansion mode where PM13 =0
ROM address
Microcomputer address
OFS bit in DBR
register = 0
000000h
OFS bit in DBR
register = 1
Output from the Microcomputer Pins
Bank
Number
OFS
40000h
Access
Area
CS Output
Address Output
CS3
CS2
CS1
A19
A18
A17
40000h
0
0
0
0
1
0
A16 A15 to A0
0
0000h
000000h
BFFFFh
0
0
0
1
0
1
1
FFFFh
07FFFFh
40000h
0
0
0
1
0
0
0
0000h
040000h
BFFFFh
0
0
1
0
1
1
1
FFFFh
0BFFFFh
0
040000h
bank 0
(512 Kbytes)
0
40000h
1
BFFFFh
080000h
0C0000h
bank 0
(512 Kbytes)
40000h
bank 1
(512 Kbytes)
0
BFFFFh
40000h
0
0
1
0
1
0
0
0000h
080000h
BFFFFh
0
0
1
1
0
1
1
FFFFh
0FFFFFh
1
40000h
40000h
0
0
1
1
0
0
0
0000h
0C0000h
BFFFFh
0
1
0
0
1
1
1
FFFFh
13FFFFh
1
BFFFFh
100000h
40000h
bank 1
(512 Kbytes)
40000h
0
1
0
0
1
0
0
0000h
100000h
BFFFFh
0
1
0
1
0
1
1
FFFFh
17FFFFh
0
140000h
bank 2
(512 Kbytes)
BFFFFh
2
40000h
40000h
0
1
0
1
0
0
0
0000h
140000h
BFFFFh
0
1
1
0
1
1
1
FFFFh
1BFFFFh
1
BFFFFh
180000h
40000h
bank 2
(512 Kbytes)
40000h
0
1
1
0
1
0
0
0000h
180000h
BFFFFh
0
1
1
1
0
1
1
FFFFh
1FFFFFh
40000h
0
1
1
1
0
0
0
0000h
1C0000h
BFFFFh
1
0
0
0
1
1
1
FFFFh
23FFFFh
0
Data
1C0000h
bank 3
(512 Kbytes)
BFFFFh
3
40000h
1
BFFFFh
200000h
40000h
bank 3
(512 Kbytes)
40000h
1
0
0
0
1
0
0
0000h
200000h
BFFFFh
1
0
0
1
0
1
1
FFFFh
27FFFFh
0
240000h
bank 4
(512 Kbytes)
BFFFFh
4
40000h
40000h
1
0
0
1
0
0
0
0000h
240000h
BFFFFh
1
0
1
0
1
1
1
FFFFh
2BFFFFh
1
BFFFFh
280000h
40000h
bank 4
(512 Kbytes)
40000h
1
0
1
0
1
0
0
0000h
280000h
BFFFFh
1
0
1
1
0
1
1
FFFFh
2FFFFFh
0
2C0000h
bank 5
(512 Kbytes)
BFFFFh
5
40000h
1
0
1
1
0
0
0
0000h
2C0000h
BFFFFh
1
1
0
0
1
1
1
FFFFh
33FFFFh
40000h
1
1
0
0
1
0
0
0000h
300000h
BFFFFh
1
1
0
1
0
1
1
FFFFh
37FFFFh
40000h
1
1
0
1
0
0
0
0000h
340000h
BFFFFh
1
1
1
0
1
1
1
FFFFh
3BFFFFh
bank 6
(512 Kbytes)
40000h
1
1
1
0
1
0
0
0000h
380000h
BFFFFh
7FFFFh
1
1
1
0
1
1
1
FFFFh
3BFFFFh
80000h
1
1
1
1
0
0
0
0000h
3C0000h
BFFFFh
1
1
1
1
0
1
1
FFFFh
3FFFFFh
C0000h
1
1
1
1
1
0
0
0000h
3C0000h
CFFFFh
1
1
1
1
1
0
0
FFFFh
40000h
1
BFFFFh
300000h
40000h
bank 5
(512 Kbytes)
0
340000h
bank 6
(512 Kbytes)
BFFFFh
6
40000h
1
BFFFFh
Program
or data
Program
or data
380000h
3C0000h
3FFFFFh
40000h
bank 7
(512 Kbytes)
BFFFFh
7
0
3CFFFFh
D0000h
Internal ROM access
DFFFFh
Internal ROM access
D0000h
Internal ROM access
DFFFFh
Internal ROM access
A21
A20
A19
A18
N.C.
A17
A16 A15 to A0
Address input for
4-Mbyte ROM
Address Input for 4-Mbyte ROM
N.C.: No connected
Figure 9.7
Relationship Between Addresses on 4-Mbyte ROM and Those on Microcomputer (1)
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M16C/62P Group (M16C/62P, M16C/62PT)
9. Memory Space Expansion Function
Memory expansion mode where PM13 =1
ROM address
Microcomputer address
OFS bit in DBR
register = 0
000000h
Output from the Microcomputer Pins
Bank
Number
OFS
40000h
0
bank 0
(256 Kbytes)
7FFFFh
bank 1
(256 Kbytes)
0
40000h
40000h
bank 2
(256 Kbytes)
40000h
bank 2
(256 Kbytes)
7FFFFh
40000h
bank 3
(256 Kbytes)
7FFFFh
40000h
bank 4
(256 Kbytes)
7FFFFh
280000h
1
40000h
bank 5
(256 Kbytes)
0
0000h
000000h
7FFFFh
0
0
0
0
1
1
1
FFFFh
03FFFFh
40000h
0
0
0
1
0
0
0
0000h
040000h
7FFFFh
0
0
0
1
0
1
1
FFFFh
07FFFFh
40000h
0
0
1
0
1
0
0
0000h
080000h
7FFFFh
0
0
1
0
1
1
1
FFFFh
0BFFFFh
40000h
0
0
1
1
0
0
0
0000h
0C0000h
7FFFFh
0
0
1
1
0
1
1
FFFFh
0FFFFFh
40000h
0
1
0
0
1
0
0
0000h
100000h
7FFFFh
0
1
0
0
1
1
1
FFFFh
13FFFFh
40000h
0
1
0
1
0
0
0
0000h
140000h
7FFFFh
0
1
0
1
0
1
1
FFFFh
17FFFFh
40000h
0
1
1
0
1
0
0
0000h
180000h
7FFFFh
0
1
1
0
1
1
1
FFFFh
1BFFFFh
40000h
0
1
1
1
0
0
0
0000h
1C0000h
7FFFFh
0
1
1
1
0
1
1
FFFFh
1FFFFFh
40000h
1
0
0
0
1
0
0
0000h
200000h
7FFFFh
1
0
0
0
1
1
1
FFFFh
23FFFFh
40000h
1
0
0
1
0
0
0
0000h
240000h
7FFFFh
1
0
0
1
0
1
1
FFFFh
27FFFFh
1
40000h
1
0
1
0
1
0
0
0000h
280000h
7FFFFh
1
0
1
0
1
1
1
FFFFh
2BFFFFh
5
40000h
1
0
1
1
0
0
0
0000h
2C0000h
7FFFFh
1
0
1
1
0
1
1
FFFFh
2FFFFFh
1
40000h
bank 6
(256 Kbytes)
40000h
1
1
0
0
1
0
0
0000h
300000h
7FFFFh
1
1
0
0
1
1
1
FFFFh
33FFFFh
6
40000h
bank 7
(256 Kbytes)
7FFFFh
3C0000h
40000h
bank 7
(256 Kbytes)
3FFFFFh
7FFFFh
40000h
1
1
0
1
0
0
0
0000h
340000h
7FFFFh
1
1
0
1
0
1
1
FFFFh
37FFFFh
40000h
1
1
1
0
1
0
0
0000h
380000h
7FFFFh
1
1
1
0
1
1
1
FFFFh
3BFFFFh
1
7FFFFh
Program
only
A16 A15 to A0
0
7FFFFh
Program
or data
0
4
7FFFFh
380000h
1
1
40000h
bank 6
(256 Kbytes)
340000h
0
0
7FFFFh
300000h
0
3
40000h
bank 5
(256 Kbytes)
2C0000h
0
0
40000h
bank 4
(256 Kbytes)
7FFFFh
240000h
A17
0
2
7FFFFh
200000h
A18
0
40000h
bank 3
(256 Kbytes)
1C0000h
A19
0
7FFFFh
Data
CS1
1
7FFFFh
180000h
CS2
1
bank 1
(256 Kbytes)
140000h
Address Output
CS3
1
40000h
7FFFFh
100000h
CS Output
0
40000h
0C0000h
Access
Area
40000h
bank 0
(256 Kbytes)
7FFFFh
040000h
080000h
OFS bit in DBR
register = 1
7
7
0
80000h
Internal ROM access
FFFFFh
Internal ROM access
40000h
1
1
1
1
0
0
0
0000h
7FFFFh
1
1
1
1
0
1
1
FFFFh
3C0000h
3FFFFFh
1
80000h
Internal ROM access
FFFFFh
Internal ROM access
A21
A20
A19
A18
N.C. A17
A16 A15 to A0
Address input for
4-Mbyte ROM
Address Input for 4-Mbyte ROM
N.C.: No connected
Figure 9.8
Relationship Between Addresses on 4-Mbyte ROM and Those on Microcomputer (2)
Rev.2.41 Jan 10, 2006
REJ09B0185-0241
Page 80 of 390
M16C/62P Group (M16C/62P, M16C/62PT)
9. Memory Space Expansion Function
Microprocessor mode
Microcomputer address
ROM address
Output from the Microcomputer Pins
OFS bit in DBR
register = 0
000000h
OFS bit in DBR
register = 1
Bank
Number
OFS
40000h
Access
Area
CS Output
Address Output
CS3
CS2
CS1
A19
A18
A17
40000h
0
0
0
0
1
0
A16 A15 to A0
0
0000h
000000h
BFFFFh
0
0
0
1
0
1
1
FFFFh
07FFFFh
40000h
0
0
0
1
0
0
0
0000h
040000h
BFFFFh
0
0
1
0
1
1
1
FFFFh
0BFFFFh
40000h
0
0
1
0
1
0
0
0000h
080000h
0
040000h
bank 0
(512 Kbytes)
0
40000h
1
BFFFFh
080000h
40000h
bank 0
(512 Kbytes)
0
0C0000h
bank 1
(512 Kbytes)
BFFFFh
BFFFFh
0
0
1
1
0
1
1
FFFFh
0FFFFFh
40000h
0
0
1
1
0
0
0
0000h
0C0000h
1
40000h
1
BFFFFh
100000h
40000h
BFFFFh
0
1
0
0
1
1
1
FFFFh
13FFFFh
40000h
0
1
0
0
1
0
0
0000h
100000h
BFFFFh
0
1
0
1
0
1
1
FFFFh
17FFFFh
40000h
0
1
0
1
0
0
0
0000h
140000h
BFFFFh
0
1
1
0
1
1
1
FFFFh
1BFFFFh
40000h
0
1
1
0
1
0
0
0000h
180000h
BFFFFh
0
1
1
1
0
1
1
FFFFh
1FFFFFh
40000h
0
1
1
1
0
0
0
0000h
1C0000h
BFFFFh
1
0
0
0
1
1
1
FFFFh
23FFFFh
40000h
1
0
0
0
1
0
0
0000h
200000h
BFFFFh
1
0
0
1
0
1
1
FFFFh
27FFFFh
40000h
1
0
0
1
0
0
0
0000h
240000h
BFFFFh
1
0
1
0
1
1
1
FFFFh
2BFFFFh
40000h
1
0
1
0
1
0
0
0000h
280000h
BFFFFh
1
0
1
1
0
1
1
FFFFh
2FFFFFh
40000h
1
0
1
1
0
0
0
0000h
2C0000h
BFFFFh
1
1
0
0
1
1
1
FFFFh
33FFFFh
40000h
1
1
0
0
1
0
0
0000h
300000h
BFFFFh
1
1
0
1
0
1
1
FFFFh
37FFFFh
40000h
1
1
0
1
0
0
0
0000h
340000h
BFFFFh
1
1
1
0
1
1
1
FFFFh
3BFFFFh
bank 6
(512 Kbytes)
40000h
1
1
1
0
1
0
0
0000h
380000h
BFFFFh
7FFFFh
1
1
1
0
1
1
1
FFFFh
3BFFFFh
bank 1
(512 Kbytes)
0
140000h
bank 2
(512 Kbytes)
BFFFFh
2
40000h
1
BFFFFh
180000h
40000h
bank 2
(512 Kbytes)
0
Data
1C0000h
bank 3
(512 Kbytes)
BFFFFh
3
40000h
1
BFFFFh
200000h
40000h
bank 3
(512 Kbytes)
0
240000h
bank 4
(512 Kbytes)
BFFFFh
4
40000h
1
BFFFFh
280000h
40000h
bank 4
(512 Kbytes)
0
2C0000h
bank 5
(512 Kbytes)
BFFFFh
5
40000h
1
BFFFFh
300000h
40000h
bank 5
(512 Kbytes)
0
340000h
bank 6
(512 Kbytes)
BFFFFh
6
40000h
1
BFFFFh
Program
or data
Program
or data
380000h
40000h
bank 7
(512 Kbytes)
3C0000h
7FFFFh
C0000h
7
3FFFFFh
FFFFFh
80000h
1
1
1
1
0
0
0
0000h
3C0000h
BFFFFh
1
1
1
1
0
1
1
FFFFh
3FFFFFh
C0000h
1
1
1
1
1
0
0
0000h
3C0000h
FFFFFh
1
1
1
1
1
1
1
FFFFh
3FFFFFh
A21
A20
A19
A18
N.C.
A17
0
A16 A15 to A0
Address Input for
4-Mbyte ROM
Address Input for 4-Mbyte ROM
N.C.: No connected
Figure 9.9
Relationship Between Addresses on 4-Mbyte ROM and Those on Microcomputer (3)
Rev.2.41 Jan 10, 2006
REJ09B0185-0241
Page 81 of 390
M16C/62P Group (M16C/62P, M16C/62PT)
10. Clock Generation Circuit
10. Clock Generation Circuit
10.1
Types of the Clock Generation Circuit
4 circuits are incorporated to generate the system clock signal :
• Main clock oscillation circuit
• Sub clock oscillation circuit
• On-chip oscillator
• PLL frequency synthesizer
Table 10.1 lists the Clock Generation Circuit Specifications. Figure 10.1 shows the Clock Generation Circuit.
Figures 10.2 to 10.6 show the clock-related registers.
Table 10.1
Clock Generation Circuit Specifications
Item
Use of Clock
Clock Frequency
Usable Oscillator
Pins to Connect
Oscillator
Oscillation Stop,
Restart Function
Oscillator Status
After Reset
Other
Main Clock
Oscillation Circuit
• CPU clock source
• Peripheral function
clock source
Sub Clock
Oscillation Circuit
• CPU clock source
• Timer A, B's clock
source
0 to 16 MHz
• Ceramic oscillator
• Crystal oscillator
XIN, XOUT
On-chip oscillator
PLL frequency
synthesizer
• CPU clock source
• Peripheral function
clock source
32.768 kHz
• Crystal oscillator
• CPU clock source
• Peripheral function clock
source
• CPU and peripheral
function
clock sources when the
main clock stops
oscillating
About 1 MHz
−
10 to 24MHz
−
XCIN, XCOUT
−
−
Presence
Presence
Presence
Presence
Oscillating
Stopped
Stopped
Stopped
−
−
Externally derived clock can be input
Rev.2.41 Jan 10, 2006
REJ09B0185-0241
Page 82 of 390
M16C/62P Group (M16C/62P, M16C/62PT)
10. Clock Generation Circuit
Sub-clock
generating circuit
XCIN
CM01 to CM00=00b
I/O ports
PM01 to PM00=00b, CM01 to CM00=01b
PM01 to PM00=00b, CM01 to CM00=10b
XCOUT
fC32
1/32
CM04
CLKOUT
PM01 to PM00=00b,
CM01 to CM00=11b
f1
PCLK0=1
Sub-clock
f2
PCLK0=0
fC
On-chip
oscillator
CM21
f8
On-chip
oscillator
clock
f32
fAD
Oscillation
stop,
re-oscillation
detection
circuit
f1SIO
PCLK1=1
f2SIO
PCLK1=0
f8SIO
CM10=1(stop mode)
S Q
XIN
PLL
frequency
synthesizer
XOUT
R
CM05
Main
clock
Main clock
generating circuit
1
PLL
clock
0
f32SIO
e b c
a
CM21=1
D4INT clock
CM07=0
d
Divider
CPU clock
fC
CM21=0
CM11
BCLK
CM07=1
CM02
S Q
WAIT instruction
R
e
a
c
b
1/2
1/2
1/2
1/2
1/2
1/32
RESET
1/2
1/4
1/8
Software reset
1/16
CM06=0
CM17 to CM16=11b
NMI
CM06=1
CM06=0
CM17 to CM16=10b
Interrupt request level judgment output
CM02, CM04, CM05, CM06, CM07: Bits in CM0 register
CM10, CM11, CM16, CM17: Bits in CM1 register
PCLK0, PCLK1: Bits in PCLKR register
CM21, CM27 : Bits in CM2 register
d
CM06=0
CM17 to CM16=01b
CM06=0
CM17 to CM16=00b
Details of divider
Oscillation Stop, Re-Oscillation Detection Circuit
Main
clock
Pulse generation
circuit for clock
edge detection
and charge,
discharge control
CM27=0
Charge,
discharge
circuit
CM27=1
Reset
generating
circuit
Oscillation stop,
re-oscillation
detection interrupt
generating circuit
Oscillation stop
detection reset
Oscillation stop
detection reset
CM21 switch signal
PLL Frequency Synthesizer
Programmable
counter
Main clock
Phase
compar
ator
Charge
pump
Voltage
control
oscillator
(VCO)
Internal lowpass
filter
Figure 10.1
Clock Generation Circuit
Rev.2.41 Jan 10, 2006
REJ09B0185-0241
Page 83 of 390
1/2
PLL Clock
M16C/62P Group (M16C/62P, M16C/62PT)
10. Clock Generation Circuit
System Clock Control Register 0 (1)
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
CM0
Address
0006h
Bit Symbol
CM00
CM01
CM02
CM03
CM04
CM05
CM06
CM07
After Reset
01001000b
Bit Name
Function
RW
Clock Output Function
Select Bit
(Valid only in single-chip
mode)
b1 b0
WAIT Mode Peripheral
Function Clock Stop Bit (10)
0 : Peripheral function clock does not stop in
w ait mode
1 : Peripheral function clock stops in w ait
mode(8)
RW
XCIN-XCOUT Drive
Capacity Select Bit (2)
0 : LOW
1 : HIGH
RW
0 : I/O ports P8_6, P8_7
1 : XCIN-XCOUT oscillation function (9)
RW
0 : On
1 : Off
RW
Port XC Select Bit
(2)
Main Clock Stop Bit
(3, 10, 12, 13)
0 0 : I/O port P5_7
0 1 : Output fC
1 0 : Output f8
1 1 : Output f32
(4, 5)
RW
RW
Main Clock Division
Select Bit 0 (7, 13, 14)
0 : CM16 and CM17 enabled
1 : Division-by-8 mode
RW
System Clock Select Bit
0 : Main clock, PLL clock, or on-chip oscillator clock
1 : Sub clock
RW
(6, 10, 11, 12)
NOTES :
1. Rew rite this register after setting the PRC0 bit in the PRCR register to “1” (w rite enable).
2. The CM03 bit is set to “1” (high) w hile the CM04 bit is set to “0” (I/O port) or w hen entering stop mode.
3. This bit is provided to stop the main clock w hen the low pow er consumption mode or on-chip oscillator low pow er
dissipation mode is selected. This bit cannot be used for detection as to w hether the main clock stops or not. To
stop the main clock, set bits as follow s:
(a) Set the CM07 bit to “1” (sub clock selected) or the CM21 bit in the CM2 register to “1” (On-chip oscillator
selected)
w ith the sub-clock stably oscillates.
(b) Set the CM20 bit in the CM2 register to “0” (Oscillation stop, re-oscillation detection function disabled).
(c) Set the CM05 bit to “1” (Stop).
4. During external clock input, Set the CM05 bit to “0” (oscillate).
5. When CM05 bit is set to “1”, the XOUT pin is held “H”. Because the internal feedback resistor remains connected, the
XIN pin is pulled “H” to the same level as XOUT via the feedback resistor.
6. After setting the CM04 bit to “1” (XCIN-XCOUT oscillator function), w ait until the sub-clock oscillates stably before
sw itching the CM07 bit from “0” to “1” (sub-clock).
7. When entering stop mode from high-speed or middle-speed mode, on-chip oscillator mode or on-chip oscillator low
pow er mode, the CM06 bit is set to “1” (divide-by-8 mode).
8. The fC32 clock does not stop. In low -speed mode or low pow er consumption mode, do not set this bit to “1”
(peripheral clock stops in w ait mode).
9. To use a sub-clock, set this bit to “1”. Also make sure ports P8_6 and P8_7 are directed for input, w ith no pull-ups.
10. When the PM21 bit in the PM2 register is set to “1” (disable clock modification), this bit remains unchanged even if
w riting to the CM02, CM05, and CM07 bits.
11. When setting the PM21 bit to “1”, set the CM07 bit to “0” (main clock) before setting the PM21 bit to “1”.
12. To use the main clock as the clock source for the CPU clock, set bits as follow s.
(a) Set the CM05 bit to “0” (oscillate).
(b) Wait the main clock oscillation stabilizes.
(c) Set the CM11, CM21 and CM07 bits to “0”.
13. When the CM21 bit is set to “0” (on-chip oscillator stops) and the CM05 bit is set to “1” (main clock stops), the CM06
bit is fixed to “1” (divide-by-8 mode) and the CM15 bit is fixed to “1” (drive capacity High).
14. To return from on-chip oscillator mode to high-speed or middle-speed mode, set the CM06 and CM15 bits to “1”.
Figure 10.2
CM0 Register
Rev.2.41 Jan 10, 2006
REJ09B0185-0241
Page 84 of 390
M16C/62P Group (M16C/62P, M16C/62PT)
10. Clock Generation Circuit
System Clock Control Register 1(1)
b7 b6 b5 b4 b3 b2 b1 b0
0 0 0
Symbol
CM1
Bit Symbol
CM10
CM11
—
(b4-b2)
CM15
CM16
Address
0007h
After Reset
00100000b
Bit Name
All Clock Stop Control Bit
Function
(4, 6)
RW
0 : Clock on
1 : All clocks off (stop mode)
RW
System Clock Select Bit 1 (6, 7)
0 : Main clock
1 : PLL clock (5)
RW
Reserved Bit
Set to “0”
XIN-XOUT Drive Capacity
Select Bit (2)
0 : LOW
1 : HIGH
Main Clock Division Select Bit 1 (3)
b7 b6
CM17
0 0 : No division mode
0 1 : Divide-by-2 mode
1 0 : Divide-by-4 mode
1 1 : Divide-by-16 mode
RW
RW
RW
RW
NOTES :
1. Rew rite this register after setting the PRC0 bit in the PRCR register to “1” (w rite enable).
2. When entering stop mode from high-speed or middle-speed mode, or the CM05 bit is set to “1” (main clock stops) in
low speed mode, the CM15 bit is set to “1” (drive capacity high).
3. This bit is valid w hen the CM06 bit is set to “0” (CM16 and CM17 bits enabled).
4. If the CM10 bit is set to “1” (stop mode), XOUT is held “H” and the internal feedback resistor is disconnected. The
XCIN and XCOUT pins are in high-impedance state. When the CM11 bit is set to “1” (PLL clock), or the CM20 bit in the
CM2 register is set to “1” (oscillation stop, re-oscillation detection function enabled), do not set the CM10 bit to “1”.
5. After setting the PLC07 bit in the PLC0 register to “1” (PLL operation), w ait tsu (PLL) elapses before setting the CM11
bit to “1” (PLL clock).
6. When the PM21 bit in the PM2 register is set to “1” (disable clock modification), this bit remains unchanged even if
w riting to the CM10, CM11 bits.
When the PM22 bit in the PM2 register is set to “1” (on-chip oscillator clock is selected as w atchdog timer count
source), this bit remains unchanged even if w riting to the CM10 bit.
7. This bit is valid w hen the CM07 bit is set to “0” and the CM21 bit is set to “0”.
Figure 10.3
CM1 Register
Rev.2.41 Jan 10, 2006
REJ09B0185-0241
Page 85 of 390
M16C/62P Group (M16C/62P, M16C/62PT)
10. Clock Generation Circuit
Oscillation Stop Detection Register (1)
b7 b6 b5 b4 b3 b2 b1 b0
0 0
Symbol
CM2
Address
000Ch
After Reset
0X000000b (11)
Bit Symbol
Bit Name
Function
CM20
CM21
CM22
CM23
—
(b5-b4)
RW
Oscillation Stop,
Re-Oscillation Detection
Enable Bit (7, 9, 10,11)
0: Oscillation stop, re-oscillation detection
function disabled
1: Oscillation stop, re-oscillation detection
function enabled
RW
System Clock Select Bit 2
(2, 3, 6, 8, 11, 12)
0: Main clock or PLL clock
1: On-chip oscillator clock
(On-chip oscillator oscillates)
RW
Oscillation Stop,
Re-Oscillation Detection
Flag (4)
0: Main clock stops, re-oscillation not
detected
1: Main clock stops, re-oscillation detected
RW
XIN Monitor Flag (5)
0: Main clock oscillates
1: Main clock stops
RO
Reserved Bit
Set to “0”
—
(b6)
Nothing is assigned. When w rite, set to “0”.
When read, its content is “0”.
CM27
Operation Select Bit
(w hen an oscillation stop,
re-oscillation is detected) (11)
0: Oscillation stop detection reset
1: Oscillation stop, re-oscillation detection
interrupt
RW
—
RW
NOTES :
1. Rew rite this register after setting the PRC0 bit in the PRCR register to “1” (w rite enable).
2. When the CM20 bit is set to “1” (oscillation stop, re-oscillation detection function enabled), the CM27 bit is set to “1”
(oscillation stop, re-oscillation detection interrupt), and the CPU clock source is the main clock, the CM21 bit is set to
“1” (on-chip oscillator clock) if the main clock stop is detected.
3. If the CM20 bit is set to “1” and the CM23 bit is set to “1” (main clock stops), do not set the CM21 bit to “0”.
4. This bit is set to “1” w hen the main clock stop is detected and the main clock re-oscillation is detected. When this
flag changes state from “0” to “1”, an oscillation stop or a re-oscillation detection interrupt is generated. Use this bit in
an interrupt routine to determine the factors of interrupts betw een the oscillation stop and re-oscillation detection
interrupt and the w atchdog timer interrupt. This bit is set to “0” by w riting “0” in a program. (This bit remains
unchanged even if w riting “1”. Nor is it set to “0” w hen an oscillation stop or a re-oscillation detection interrupt
request is acknow ledged.)
When the CM22 bit is set to “1” and an oscillation stop or a re-oscillation is detected, an oscillation stop or a reoscillation detection interrupt is not generated.
5. Determine the main clock status by reading the CM23 bit several times in an oscillation stop or a re-oscillation
detection interrupt routine
6. This bit is valid w hen the CM07 bit in the CM0 register is set to “0”.
7. When the PM21 bit in the PM2 register is set to “1” (disable clock modification), this bit remains unchanged even if
w riting to the CM20 bit.
8. Where the CM20 bit is set to “1” (oscillation stop, re-oscillation detection function enabled), the CM27 bit is “1”
(oscillation stop, re-oscillation detection interrupt), and the CM11 bit is set to “1” (PLL clock is selected as the CPU
clock source), the CM21 bit remains unchanged even if a main clock stop is detected. When the CM22 bit is set to
“0” under these conditions, an oscillation stop, a re-oscillation detection interrupt request is generated at main clock
stop detection. Set the CM21 bit to “1” (on-chip oscillator clock) in the interrupt routine.
9. Set the CM20 bit to “0” (disabled) before entering stop mode. Exit stop mode before setting the CM20 bit back to “1”
(enabled).
10. Set the CM20 bit in the CM2 register to “0” (disabled) before setting the CM05 bit in the CM0 register to “1” (main clock
stops).
11. The CM20, CM21 and CM27 bits remain unchanged at the oscillation stop detection reset.
12. When the CM21 bit is set to “0” (on-chip oscillator stops) and the CM05 bit is set to “1” (main clock stops), the CM06
bit is fixed to “1” (divide-by-8 mode) and the CM15 bit is fixed to “1” (drive capacity High).
Figure 10.4
CM2 Register
Rev.2.41 Jan 10, 2006
REJ09B0185-0241
Page 86 of 390
M16C/62P Group (M16C/62P, M16C/62PT)
10. Clock Generation Circuit
Peripheral Clock Select Register (1)
b7 b6 b5 b4 b3 b2 b1 b0
0 0 0 0 0 0
Symbol
PCLKR
Address
025Eh
Bit Symbol
After Reset
00000011b
Bit Name
Function
PCLK0
Timers A, B Clock Select Bit
(Clock source for Timers A , B, and the dead timer)
0 : f2
1 : f1
PCLK1
SI/O Clock Select Bit
(Clock source for UART0 to UART2, SI/O3, and
SI/O4)
0 : f2SIO
1 : f1SIO
Reserved bit
Set to “0”
—
(b7-b2)
RW
RW
RW
RW
NOTES :
1. Write to this register after setting the PRC0 bit in the PRCR register to “1” (w rite enable).
Processor Mode Register 2 (1)
b7 b6 b5 b4 b3 b2 b1 b0
0 0
Symbol
PM2
Address
001Eh
Bit Symbol
After Reset
XXX00000b
Bit Name
Function
RW
Specifying Wait w hen Accessing
SFR at PLL Operation (2)
0 : 2 w aits
1 : 1 w aits
RW
System Clock Protective Bit (3, 4)
0 : Clock is protected by PRCR register
1 : Clock modification disabled
RW
WDT Count Source
Protective Bit (3, 5)
0 : CPU clock is used for the w atchdog timer
count source
1 : On-chip oscillator clock is used for the
w atchdog timer count source
RW
—
(b4-b3)
Reserved Bit
Set to “0”
—
(b7-b5)
Nothing is assigned. When w rite, set to “0”.
When read, their contents are indeterminate.
PM20
PM21
PM22
RW
—
NOTES :
1. Write to this register after setting the PRC1 bit in the PRCR register to “1” (w rite enable).
2. The PM20 bit become effective w hen PLC07 bit in the PLC0 register is set to “1” (PLL on). Change the PM20 bit
w hen the PLC07 bit is set to “0” (PLL off). Set the PM20 bit to “0” (2 w aits) w hen PLL clock > 16MHz.
3. Once this bit is set to “1”, it cannot be cleared to “0” in a program.
4. If the PM21 bit is set to “1”, w riting to the follow ing bits has no effect:
CM02 bit in CM0 register
CM05 bit in CM0 register (main clock does not stop)
CM07 bit in CM0 register (clock source for the CPU clock does not change)
CM10 bit in CM1 register (stop mode is not entered)
CM11 bit in CM1 register (clock source for the CPU clock does not change)
CM20 bit in CM2 register (oscillation stop, re-oscillation detection function settings do not change)
All bits in PLC0 register (PLL frequency synthesizer settings do not change)
Be aw are that the WAIT instruction cannot be executed w hen the PM21 bit = 1.
5. Setting the PM22 bit to “1” results in the follow ing conditions:
• The on-chip oscillator starts oscillating, and the on-chip oscillator clock becomes the w atchdog timer count source.
• The CM10 bit is disabled against w rite. (Writing a “1” has no effect, nor is stop mode entered.)
• The w atchdog timer does not stop w hen in w ait mode or hold state.
Figure 10.5
PCLKR Register and PM2 Register
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M16C/62P Group (M16C/62P, M16C/62PT)
10. Clock Generation Circuit
PLL Control Register 0 (1, 2)
b7 b6 b5 b4 b3 b2 b1 b0
0 0 1
Symbol
PLC0
Address
001Ch
Bit Symbol
PLC00
Bit Name
PLL Multiplying Factor
Select Bit (3)
PLC01
PLC02
—
(b3)
—
(b4)
—
(b6-b5)
PLC07
After Reset
0001X010b
Function
RW
b2 b1 b0
0 0 0 : Do not set
0 0 1 : Multiply by 2
0 1 0 : Multiply by 4
0 1 1 : Multiply by 6
1 0 0 : Multiply by 8
101:
110:
Do not set
111:
Nothing is assigned. When w rite, set to “0”.
When read, its content is indeterminate.
Reserved Bit
Set to “1”
Reserved Bit
Set to “0”
Operation Enable Bit (4)
0: PLL Off
1: PLL On
RW
RW
RW
—
RW
RW
RW
NOTES :
1. Write to this register after setting the PRC0 bit in the PRCR register to “1” (w rite enable).
2. When the PM21 bit in the PM2 register is “1” (clock modification disable), w riting to this register has no effect.
3. These three bits can only be modified w hen the PLC07 bit = 0 (PLL turned off). The value once w ritten to this bit
cannot be modified.
4. Before setting this bit to “1”, set the CM07 bit in the CM0 register to “0” (main clock), set the CM17 to CM16 bits in the
CM1 register to “00b” (main clock undivided mode), and set the CM06 bit in the CM0 register to “0” (CM16 and CM17
bits enable).
Figure 10.6
PLC0 Register
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M16C/62P Group (M16C/62P, M16C/62PT)
10. Clock Generation Circuit
The following describes the clocks generated by the clock generation circuit.
10.1.1
Main Clock
This clock is used as the clock source for the CPU and peripheral function clocks. This clock is used as the
clock source for the CPU and peripheral function clocks. The main clock oscillator circuit is configured by
connecting a resonator between the XIN and XOUT pins. The main clock oscillator circuit contains a feedback
resistor, which is disconnected from the oscillator circuit during stop mode in order to reduce the amount of
power consumed in the chip. The main clock oscillator circuit may also be configured by feeding an externally
generated clock to the XIN pin. Figure 10.7 shows the Examples of Main Clock Connection Circuit.
After reset, the main clock divided by 8 is selected for the CPU clock.
The power consumption in the chip can be reduced by setting the CM05 bit in the CM0 register to “1” (main
clock oscillator circuit turned off) after switching the clock source for the CPU clock to a sub clock or on-chip
oscillator clock. In this case, XOUT goes “H”. Furthermore, because the internal feedback resistor remains on,
XIN is pulled “H” to XOUT via the feedback resistor. Note that if an externally generated clock is fed into the
XIN pin, the main clock cannot be turned off by setting the CM05 bit to “1,” unless the sub clock is chosen as a
CPU clock. If necessary, use an external circuit to turn off the clock.
During stop mode, all clocks including the main clock are turned off. Refer to 10.4 Power Control.
Microcomputer
Microcomputer
(Built-in Feedback Resistor)
(Built-in Feedback Resistor)
CIN
XIN
External clock
XIN
Oscillator
VCC1
VSS
XOUT
Rd(1)
COUT
XOUT Open
VSS
NOTES :
1. Place a damping resistor if required. The resistance will vary depending on the oscillator and the oscillation drive
capacity setting. Use the value recommended by each oscillator the oscillator manufacturer.
When the oscillation drive capacity is set to low, check that oscillation is stable. Also, place a feedback resistor
between XIN and XOUT if the oscillator manufacturer recommends placing the resistor externally.
Figure 10.7
Examples of Main Clock Connection Circuit
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M16C/62P Group (M16C/62P, M16C/62PT)
10.1.2
10. Clock Generation Circuit
Sub Clock
The sub clock is generated by the sub clock oscillation circuit. This clock is used as the clock source for the
CPU clock, as well as the timer A and timer B count sources. In addition, an fc clock with the same frequency
as that of the sub clock can be output from the CLKOUT pin.
The sub clock oscillator circuit is configured by connecting a crystal resonator between the XCIN and XCOUT
pins. The sub clock oscillator circuit contains a feedback resistor, which is disconnected from the oscillator
circuit during stop mode in order to reduce the amount of power consumed in the chip. The sub clock oscillator
circuit may also be configured by feeding an externally generated clock to the XCIN pin.
Figure 10.8 shows the Examples of Sub Clock Connection Circuit.
After reset, the sub clock is turned off. At this time, the feedback resistor is disconnected from the oscillator
circuit.
To use the sub clock for the CPU clock, set the CM07 bit in the CM0 register to “1” (sub clock) after the sub
clock becomes oscillating stably.
During stop mode, all clocks including the sub clock are turned off. Refer to 10.4 Power Control.
Microcomputer
Microcomputer
(Built-in Feedback Resistor)
(Built-in Feedback Resistor)
CCIN
XCIN
External clock
XCIN
Oscillator
VCC1
VSS
XCOUT
(1)
RCd
CCOUT
XCOUT Open
VSS
NOTES :
1. Place a damping resistor if required. The resistance will vary depending on the oscillator and the oscillation drive
capacity setting. Use the value recommended by each oscillator the oscillator manufacturer.
When the oscillation drive capacity is set to low, check that oscillation is stable. Also, place a feedback resistor
between XCIN and XCOUT if the oscillator manufacturer recommends placing the resistor externally.
Figure 10.8
Examples of Sub Clock Connection Circuit
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M16C/62P Group (M16C/62P, M16C/62PT)
10.1.3
10. Clock Generation Circuit
On-chip Oscillator Clock
This clock, approximately 1MHz, is supplied by a on-chip oscillator. This clock is used as the clock source for
the CPU and peripheral function clocks. In addition, if the PM22 bit in the PM2 register is “1” (on-chip
oscillator clock for the watchdog timer count source), this clock is used as the count source for the watchdog
timer (Refer to 13.1 Count source protective mode).
After reset, the on-chip oscillator is turned off. It is turned on by setting the CM21 bit in the CM2 register to
“1” (on-chip oscillator clock), and is used as the clock source for the CPU and peripheral function clocks, in
place of the main clock. If the main clock stops oscillating when the CM20 bit in the CM2 register is “1”
(oscillation stop, re-oscillation detection function enabled) and the CM27 bit is “1” (oscillation stop, reoscillation detection interrupt), the on-chip oscillator automatically starts operating, supplying the necessary
clock for the microcomputer.
10.1.4
PLL Clock
The PLL clock is generated PLL frequency synthesizer. This clock is used as the clock source for the CPU and
peripheral function clocks. After reset, the PLL clock is turned off. The PLL frequency synthesizer is activated
by setting the PLC07 bit to “1” (PLL operation). When the PLL clock is used as the clock source for the CPU
clock, wait tsu(PLL) for the PLL clock to be stable, and then set the CM11 bit in the CM1 register to “1”.
Before entering wait mode or stop mode, be sure to set the CM11 bit to “0” (CPU clock source is the main
clock). Furthermore, before entering stop mode, be sure to set the PLC07 bit in the PLC0 register to “0” (PLL
stops). Figure 10.9 shows the Procedure to Use PLL Clock as CPU Clock Source.
The PLL clock frequency is determined by the equation below. When the PLL clock frequency is 16 MHz or
more, set the PM20 bit in the PM2 register to “0” (2 waits).
PLL clock frequency=f(XIN) X (multiplying factor set by the PLC02 to PLC00 bits in the PLC0 register
(However, 10 MHz PLL clock frequency 24 MHz)
The PLC02 to PLC00 bits can be set only once after reset. Table 10.2 shows the Example for Setting PLL
Clock Frequencies.
Table 10.2
XIN (MHz)
10
5
3.33
2.5
12
6
4
3
Example for Setting PLL Clock Frequencies
PLC02
0
0
0
1
0
0
0
1
PLC01
0
1
1
0
0
1
1
0
PLC00
1
0
1
0
1
0
1
0
NOTES:
1. 10MHz ≤ PLL clock frequency ≤ 24MHz.
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Multiplying Factor
2
4
6
8
2
4
6
8
PLL Clock (MHz) (1)
20
24
M16C/62P Group (M16C/62P, M16C/62PT)
10. Clock Generation Circuit
Using the PLL clock as the clock source for the CPU
Set the CM07 bit to “0” (main clock), the CM17 to CM16 bits
to “00b” (main clock undivided), and the CM06 bit to “0”
(CM16 and CM17 bits enabled). (1)
Set the PLC02 to PLC00 bits (multiplying factor).
(When PLL clock > 16MHz)
Set the PM20 bit to “0” (2 wait states).
Set the PLC07 bit to “1” (PLL operation).
Wait until the PLL clock becomes stable (tsu(PLL)).
Set the CM11 bit to “1” (PLL clock for the CPU clock source).
END
NOTES :
1. PLL operation mode can be entered from high speed mode.
Figure 10.9
Procedure to Use PLL Clock as CPU Clock Source
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M16C/62P Group (M16C/62P, M16C/62PT)
10.2
10. Clock Generation Circuit
CPU Clock and Peripheral Function Clock
Two type clocks: CPU clock to operate the CPU and peripheral function clocks to operate the peripheral functions.
10.2.1
CPU Clock and BCLK
These are operating clocks for the CPU and watchdog timer.
The clock source for the CPU clock can be chosen to be the main clock, sub clock, on-chip oscillator clock or
the PLL clock.
If the main clock or on-chip oscillator clock is selected as the clock source for the CPU clock, the selected clock
source can be divided by 1 (undivided), 2, 4, 8 or 16 to produce the CPU clock. Use the CM06 bit in CM0
register and the CM17 to CM16 bits in the CM1 register to select the divide-by-n value.
When the PLL clock is selected as the clock source for the CPU clock, the CM06 bit should be set to “0” and
the CM17 to CM16 bits to “00b” (undivided).
After reset, the main clock divided by 8 provides the CPU clock.
During memory expansion or microprocessor mode, a BCLK signal with the same frequency as the CPU clock
can be output from the BCLK pin by setting the PM07 bit in the PM0 register to “0” (output enabled).
Note that when entering stop mode from high or middle speed mode, on-chip oscillator mode or on-chip
oscillator low power dissipation mode, or when the CM05 bit in the CM0 register is set to “1” (main clock
turned off) in low-speed mode, the CM06 bit in the CM0 register is set to “1” (divide-by-8 mode).
10.2.2
Peripheral Function Clock (f1, f2, f8, f32, f1SIO, f2SIO, f8SIO, f32SIO, fAD,
fC32)
These are operating clocks for the peripheral functions.
Of these, fi (i = 1, 2, 8, 32) and fiSIO are derived from the main clock, PLL clock or on-chip oscillator clock by
dividing them by i. The clock fi is used for timers A and B, and fiSIO is used for serial I/O. The f8 and f32
clocks can be output from the CLKOUT pin.
The fAD clock is produced from the main clock, PLL clock or on-chip oscillator clock, and is used for the A/D
converter.
When the WAIT instruction is executed after setting the CM02 bit in the CM0 register to “1” (peripheral
function clock turned off during wait mode), or when the microcomputer is in low power dissipation mode, the
fi, fiSIO and fAD clocks are turned off.
The fC32 clock is produced from the sub clock, and is used for timers A and B. This clock can be used when
the sub clock is on.
10.3
Clock Output Function
During single-chip mode, the f8, f32 or fC clock can be output from the CLKOUT pin. Use the CM01 to CM00
bits in the CM0 register to select.
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M16C/62P Group (M16C/62P, M16C/62PT)
10.4
10. Clock Generation Circuit
Power Control
Normal operating mode, wait mode and stop mode are provided as the power consumption control. All mode
states, except wait mode and stop mode, are called normal operating mode in this document.
10.4.1
Normal Operating Mode
Normal operating mode is further classified into seven modes.
In normal operating mode, because the CPU clock and the peripheral function clocks both are on, the CPU and
the peripheral functions are operating. Power control is exercised by controlling the CPU clock frequency. The
higher the CPU clock frequency, the greater the processing capability. The lower the CPU clock frequency, the
smaller the power consumption in the chip. If the unnecessary oscillator circuits are turned off, the power
consumption is further reduced.
Before the clock sources for the CPU clock can be switched over, the new clock source to which switched must
be oscillating stably. If the new clock source is the main clock, sub clock or PLL clock, allow a sufficient wait
time in a program until it becomes oscillating stably.
Note that operating modes cannot be changed directly from low speed or low power dissipation mode to onchip oscillator or on-chip oscillator low power dissipation mode. Nor can operating modes be changed directly
from on-chip oscillator or on-chip oscillator low power dissipation mode to low speed or low power dissipation
mode. Where the CPU clock source is changed from the on-chip oscillator to the main clock, change the
operating mode to the medium speed mode (divided by 8 mode) after the clock was divided by 8 (the CM06 bit
in the CM0 register was set to “1”) in the on-chip oscillator mode.
10.4.1.1
High-speed Mode
The main clock divided by 1 provides the CPU clock. If the sub clock is on, fC32 can be used as the count
source for Timers A and B.
10.4.1.2
PLL Operating Mode
The main clock multiplied by 2, 4, 6 or 8 provides the PLL clock, and this PLL clock serves as the CPU clock.
If the sub clock is on, fC32 can be used as the count source for Timers A and B. PLL operating mode can be
entered from high speed mode. If PLL operating mode is to be changed to wait or stop mode, first go to high
speed mode before changing.
10.4.1.3
Medium-Speed Mode
The main clock divided by 2, 4, 8 or 16 provides the CPU clock. If the sub clock is on, fC32 can be used as the
count source for Timers A and B.
10.4.1.4
Low-Speed Mode
The sub clock provides the CPU clock. The main clock is used as the clock source for the peripheral function
clock when the CM21 bit in the CM2 register is set to “0” (on-chip oscillator turned off), and the on-chip
oscillator clock is used when the CM21 bit is set to “1” (on-chip oscillator oscillating).
The fC32 clock can be used as the count source for Timers A and B.
10.4.1.5
Low Power Dissipation Mode
In this mode, the main clock is turned off after being placed in low speed mode. The sub clock provides the
CPU clock. The fC32 clock can be used as the count source for Timers A and B.
Simultaneously when this mode is selected, the CM06 bit becomes “1” (divided by 8 mode). In the low power
dissipation mode, do not change the CM06 bit. Consequently, the medium speed (divided by 8) mode is to be
selected when the main clock is operated next
10.4.1.6
On-chip Oscillator Mode
The on-chip oscillator clock divided by 1 (undivided), 2, 4, 8 or 16 provides the CPU clock. The on-chip
oscillator clock is also the clock source for the peripheral function clocks. If the sub clock is on, fC32 can be
used as the count source for Timers A and B. When the operating mode is returned to the high and medium
speed modes, set the CM06 bit in the CM0 register to “1” (divided by 8 mode).
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10.4.1.7
10. Clock Generation Circuit
On-chip Oscillator Low Power Dissipation Mode
The main clock is turned off after being placed in on-chip oscillator mode. The CPU clock can be selected as in
the on-chip oscillator mode. The on-chip oscillator clock is the clock source for the peripheral function clocks.
If the sub clock is on, fC32 can be used as the count source for Timers A and B.
Table 10.3
Setting Clock Related Bit and Modes
Modes
PLL Operating Mode
High-Speed Mode
Mediumdivided by 2
Speed Mode divided by 4
divided by 8
divided by 16
Low-Speed Mode
Low Power Dissipation Mode
On-chip
divided by 1
Oscillator
divided by 2
Mode
divided by 4
divided by 8
divided by 16
On-chip Oscillator Low Power
Dissipation Mode
CM2
Register
CM21
0
0
0
0
0
0
−
0
1
1
1
1
1
CM11
1
0
0
0
0
0
0
0
0
0
0
0
0
CM17, CM16
00b
00b
01b
10b
11b
−
−
00b
01b
10b
−
11b
CM07
0
0
0
0
0
0
1
1
0
0
0
0
0
CM06
0
0
0
0
1
0
−
1(1)
0
0
0
1
0
CM05
0
0
0
0
0
0
0
1(1)
0
0
0
0
0
CM04
−
−
−
−
−
−
1
1
−
−
−
−
−
1
0
(NOTE 2)
0
(NOTE 2)
1
−
CM1 Register
CM0 Register
− : “0” or ”1”
NOTES:
1. When the CM05 bit is set to “1” (main clock turned off) in low-speed mode, the mode goes to low
power dissipation mode and CM06 bit is set to “1” (divided by 8 mode) simultaneously.
2. The divide-by-n value can be selected the same way as in on-chip oscillator mode.
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M16C/62P Group (M16C/62P, M16C/62PT)
10.4.2
10. Clock Generation Circuit
Wait Mode
In wait mode, the CPU clock is turned off, so are the CPU (because operated by the CPU clock) and the
watchdog timer. However, if the PM22 bit in the PM2 register is “1” (on-chip oscillator clock for the watchdog
timer count source), the watchdog timer remains active. Because the main clock, sub clock and on-chip
oscillator clock all are on, the peripheral functions using these clocks keep operating.
10.4.2.1
Peripheral Function Clock Stop Function
If the CM02 bit in the CM0 register is “1” (peripheral function clocks turned off during wait mode), the f1, f2,
f8, f32, f1SIO, f8SIO, f32SIO and fAD clocks are turned off when in wait mode, with the power consumption
reduced that much. However, fC32 remains on.
10.4.2.2
Entering Wait Mode
The microcomputer is placed into wait mode by executing the WAIT instruction.
When the CM11 bit = 1 (CPU clock source is the PLL clock), be sure to clear the CM11 bit in the CM1 register
to “0” (CPU clock source is the main clock) before going to wait mode. The power consumption of the chip can
be reduced by clearing the PLC07 bit in the PLC0 register to “0” (PLL stops).
10.4.2.3
Pin Status During Wait Mode
Table 10.4 lists Pin Status During Wait Mode.
Table 10.4
Pin Status During Wait Mode
Pin
A0 to A19, D0 to D15, CS0 to CS3,
BHE
“H”
RD, WR, WRL, WRH
HLDA, BCLK
ALE
I/O ports
CLKOUT
“H”
“L”
When fC selected
When f8, f32 selected
Rev.2.41 Jan 10, 2006
REJ09B0185-0241
Memory Expansion Mode
Single-Chip Mode
Microprocessor Mode
Retains status before wait mode Does not become a bus control
pin
Retains status before wait mode Retains status before wait mode
Does not become a CLKOUT pin Does not stop
Does not stop when the CM02 bit
is “0”.
When the CM02 bit is “1”, the
status immediately prior to
entering wait mode is
maintained.
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M16C/62P Group (M16C/62P, M16C/62PT)
10.4.2.4
10. Clock Generation Circuit
Exiting Wait Mode
The microcomputer is moved out of wait mode by a hardware reset, NMI interrupt, low voltage detection
interrupt or peripheral function interrupt.
If the microcomputer is to be moved out of exit wait mode by a hardware reset, NMI interrupt or low voltage
detection interrupt, set the peripheral function interrupt priority ILVL2 to ILVL0 bits to “000b” (interrupts
disabled) before executing the WAIT instruction.
The peripheral function interrupts are affected by the CM02 bit. If CM02 bit is “0” (peripheral function clocks
not turned off during wait mode), peripheral function interrupts can be used to exit wait mode. If CM02 bit is
“1” (peripheral function clocks turned off during wait mode), the peripheral functions using the peripheral
function clocks stop operating, so that only the peripheral functions clocked by external signals can be used to
exit wait mode.
Table 10.5
Interrupts to Exit Wait Mode and Use Conditions
Interrupt
CM02=0
CM02=1
NMI Interrupt
Serial Interface
Interrupt
Key Input Interrupt
A/D Conversion
Interrupt
Timer A Interrupt
Timer B Interrupt
Can be used
Can be used
Can be used when operating with
internal or external clock
Can be used
Can be used in one-shot mode or
single sweep mode
Can be used in all modes
Can be used when operating with
external clock
Can be used
−(Do not use)
INT Interrupt
Can be used
Low Voltage Detection Can be used
Interrupt
Can be used in event counter mode or
when the count source is fC32
Can be used
Can be used
Table 10.5 lists the Interrupts to Exit Wait Mode and Use Conditions.
If the microcomputer is to be moved out of wait mode by a peripheral function interrupt, set up the following
before executing the WAIT instruction.
(1) Set the ILVL2 to ILVL0 bits in the interrupt control register, for peripheral function interrupts used to
exit wait mode.
The ILVL2 to ILVL0 bits in all other interrupt control registers, for peripheral function interrupts not
used to exit wait mode, are set to “000b” (interrupt disable).
(2) Set the I flag to “1”.
(3) Start operating the peripheral functions used to exit wait mode.
When the peripheral function interrupt is used, an interrupt routine is performed as soon as an interrupt
request is acknowledged and the CPU clock is supplied again.
When the microcomputer exits wait mode by the peripheral function interrupt, the CPU clock is the same clock
as the CPU clock executing the WAIT instruction.
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10.4.3
10. Clock Generation Circuit
Stop Mode
In stop mode, all oscillator circuits are turned off, so are the CPU clock and the peripheral function clocks.
Therefore, the CPU and the peripheral functions clocked by these clocks stop operating. The least amount of
power is consumed in this mode. If the voltage applied to VCC1 and VCC2 pins is VRAM or more, the internal
RAM is retained. When applying 2.7 or less voltage to VCC1 and VCC2 pins, make sure VCC1 ≥ VCC2 ≥
VRAM.
However, the peripheral functions clocked by external signals keep operating. The following interrupts can be
used to exit stop mode. Table 10.6 lists Interrupts to Stop Mode and Use Conditions
Table 10.6
Interrupts to Stop Mode and Use Conditions
Interrupt
Condition
Can be used
NMI Interrupt
Key Input Interrupt
INT Interrupt
Timer A Interrupt
Timer B Interrupt
Serial Interface Interrupt
Low Voltage Detection
Interrupt
10.4.3.1
Can be used
Can be used
Can be used
(when counting external pulses in event counter mode)
Can be used
(when external clock is selected)
Can be used
(Refer to 6.1 Low Voltage Detection Interrupt for an Operating Condition)
Entering Stop Mode
The microcomputer is placed into stop mode by setting the CM10 bit in the CM1 register to “1” (all clocks
turned off). At the same time, the CM06 bit in the CM0 register is set to “1” (divide-by-8 mode) and the CM15
bit in the CM1 register is set to “1” (main clock oscillator circuit drive capability high).
Before entering stop mode, set the CM20 bit in the CM2 register to “0” (oscillation stop, re-oscillation detection
function disable).
Also, if the CM11 bit in the CM1 register is “1” (PLL clock for the CPU clock source), set the CM11 bit to “0”
(main clock for the CPU clock source) and the PLC07 bit in the PLC0 register to “0” (PLL turned off) before
entering stop mode.
10.4.3.2
Pin Status in Stop Mode
Table 10.7 lists Pin Status in Stop Mode.
Table 10.7
Pin Status in Stop Mode
A0 to A19, D0 to D15, CS0 to CS3,
BHE
Memory Expansion Mode
Single-Chip Mode
Microprocessor Mode
Retains status before stop mode Does not become a bus control
pin
RD, WR, WRL, WRH
“H”
HLDA, BCLK
ALE
I/O ports
CLKOUT
When fC selected
When f8, f32 selected
“H”
Pin
Rev.2.41 Jan 10, 2006
REJ09B0185-0241
indeterminate
Retains status before stop mode Retains status before stop mode
Does not become a CLKOUT pin “H”
Retains status before stop mode
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10.4.3.3
10. Clock Generation Circuit
Exiting Stop Mode
Stop mode is exited by a hardware reset, NMI interrupt, low voltage detection interrupt or peripheral function
interrupt.
When the hardware reset, NMI interrupt or low voltage detection interrupt is used to exit stop mode, set all
ILVL2 to ILVL0 bits in the interrupt control registers for the peripheral function interrupt to “000b” (interrupt
disabled) before setting the CM10 bit to “1”.
When the peripheral function interrupt is used to exit stop mode, set the CM10 bit to “1” after the following
settings are completed.
(1) Set the ILVL2 to ILVL0 bits in the interrupt control registers to decide the peripheral priority level of
the peripheral function interrupt.
Set the interrupt priority levels of the interrupts, not being used to exit stop mode, to “0” by setting the
all ILVL2 to ILVL0 bits to “000b”.
(2) Set the I flag to “1”.
(3) Start operation of peripheral function being used to exit wait mode.
When exiting stop mode by the peripheral function interrupt, the interrupt routine is performed when an
interrupt request is generated and the CPU clock is supplied again.
When stop mode is exited by the peripheral function interrupt or NMI interrupt, the CPU clock source is as
follows, in accordance with the CPU clock source setting before the microcomputer had entered stop mode.
• When the sub clock is the CPU clock before entering stop mode : Sub clock
• When the main clock is the CPU clock source before entering stop mode : Main clock divided by 8
• When the on-chip oscillator clock is the CPU clock source before entering stop mode
: On-chip oscillator clock divided by 8
Figure 10.10 shows the State Transition from Normal Operating Mode to Stop Mode and Wait Mode. Figure
10.11 shows the State Transition in Normal Operating Mode.
Table 10.8 shows a state transition matrix describing Allowed Transition and Setting. The vertical line shows
current state and horizontal line shows state after transition.
Reset
All oscillators stopped
Stop mode
WAIT
instruction
CM10=1(6)
Wait mode
Medium-speed mode
(divided-by-8 mode)
Interrupt
CPU operation stopped
Interrupt
Interrupt
CM07=0
CM06=1
CM05=0
CM11=0
CM10=1(5)
WAIT
instruction
High-speed, mediumspeed mode
Stop mode
CM10=1(6)
When
low power
dissipation
mode
(NOTES 1, 2)
When
lowspeed
mode
PLL operation
mode
CM10=1(6)
Low-speed, low power
dissipation mode
Stop mode
Interrupt
CM10=1(6)
Stop mode
Wait mode
Interrupt
On-chip oscillator, On-chip
oscillator dissipation mode
WAIT
instruction
Interrupt
Wait mode
WAIT
instruction
Interrupt
Wait mode
Interrupt(4)
Normal mode
NOTES :
1. Do not go directly from PLL operation mode to wait or stop mode.
2. PLL operation mode can be entered from high speed mode. Similarly, PLL operation mode can be changed back to high speed mode.
3. Shown above is the case where the PM21 bit in the PM2 register = 0 (system clock protective function unused).
4. The on-chip oscillator clock divided by 8 provides the CPU clock.
5. Write to the CM0 and CM1 registers per 16 bit with CM21=0 (on-chip oscillator stops).
Since the operation starts from the main clock after exiting stop mode, the time until the CPU operates can be reduced.
6. Before entering stop mode, be sure to clear the CM20 bit in the CM2 register to “ 0” (oscillation stop and oscillation restart detection function disabled).
Figure 10.10
State Transition to Stop Mode and Wait Mode
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M16C/62P Group (M16C/62P, M16C/62PT)
10. Clock Generation Circuit
Main clock oscillation
On-chip oscillator clock oscillation
PLL operation mode
CPU clock : f(PLL)
CM07=0
CM06=0
CM17=0
CM16=0
CM04=1
PLL operation
mode
CPU clock : f(PLL)
CM07=0
CM06=0
CM17=0
CM16=0
PLC07=1
CM11=1(6)
PLC07=0
CM11=0
High-speed mode
CPU clock : f(XIN)
CM07=0
CM06=0
CM17=0
CM16=0
CM04=0
Middle-speed mode
(divide by 2)
CPU clock : f(XIN)/2
CM07=0
CM06=0
CM17=0
CM16=1
Middle-speed mode
(divide by 4)
CPU clock : f(XIN)/4
CM07=0
CM06=0
CM17=1
CM16=0
CM04=1
Middle-speed mode
(divide by 8)
CPU clock : f(XIN)/8
CM07=0
CM06=1
CPU clock : f(XIN)/16
CM07=0
CM06=0
CM17=1
CM16=1
On-chip oscillator low power
dissipation mode
On-chip oscillator mode
Middle-speed mode
(divide by 16)
CM21=0(7)
CM21=1
CPU clock
f(Ring)
f(Ring)/2
f(Ring)/4
f(Ring)/8
f(Ring)/16
CM04=1
CM04=0
CM05=0
CM05=1(1)
CM04=0
PLC07=0
CM11=0
High-speed mode
Middle-speed mode
(divide by 2)
Middle-speed mode
(divide by 4)
Middle-speed mode
(divide by 8)
Middle-speed mode
(divide by 16)
CPU clock : f(XIN)
CM07=0
CM06=0
CM17=0
CM16=0
CPU clock : f(XIN)/2
CM07=0
CM06=0
CM17=0
CM16=1
CPU clock : f(XIN)/4
CM07=0
CM06=0
CM17=1
CM16=0
CPU clock : f(XIN)/8
CPU clock : f(XIN)/16
CM07=0
CM06=0
CM17=1
CM16=1
CM07=1(3)
CM07=0
CM06=1
CM21=0(7)
CM21=1
CPU clock
f(Ring)
f(Ring)/2
f(Ring)/4
f(Ring)/8
f(Ring)/16
CM04=1
On-chip oscillator
low power
dissipation mode
On-chip oscillator
mode
PLC07=1
CM11=1(6)
CPU clock
f(Ring)
f(Ring)/2
f(Ring)/4
f(Ring)/8
f(Ring)/16
CM05=0
CM05=1(1)
CPU clock
f(Ring)
f(Ring)/2
f(Ring)/4
f(Ring)/8
f(Ring)/16
CM07=0(2, 4)
Low-speed mode
CM21=0
CPU clock : f(XCIN)
CM07=0
Low-speed mode
CPU clock : f(XCIN)
CM07=0
CM21=1
CM05=0
CM05=1(1, 8)
Low power dissipation mode
CPU clock : (XCIN)
CM07=0
CM06=1
CM15=1
Sub clock oscillation
NOTES:
1. Avoid making a transition when the CM20 bit in the CM2 register is set to “1” (oscillation stop, re-oscillation detection function enabled).
Set the CM20 bit to “0” (oscillation stop, re-oscillation detection function disabled) before transiting.
2. Wait the main clock oscillation stabilizes.
3. Switch clock after oscillation of sub-clock is sufficiently stable.
4. Change CM17 and CM16 bits in the CM1 register before changing CM06 bit in the CM0 register.
5. Transit in accordance with arrow.
6. The PM20 bit in the PM2 register become effective when the PLC07 bit in the PLC0 register is set to “1” (PLL on). Change the PM20 bit when the PLC07 bit is set to “0” (PLL off).
Set the PM20 bit to “0” (2 waits) when PLL clock >16MHz.
7. Set the CM06 bit to “1” (division by 8 mode) before changing back the operation mode from on-chip oscillator mode to high- or middle-speed mode.
8. When the CM21 bit in the CM2 register = 0 (on-chip oscillator turned off) and the CM05 bit in the CM0 register = 1 (main clock turned off), the CM06 bit is fixed to 1 (divide-by-8 mode)
and the CM15 bit in the CM1 register is fixed to “1” (drive capability High).
Figure 10.11
State Transition in Normal Operating Mode
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CM04=0
M16C/62P Group (M16C/62P, M16C/62PT)
10. Clock Generation Circuit
Allowed Transition and Setting(9)
Table 10.8
State After Transition
High-Speed Mode, Low-Speed
Middle-Speed
Mode(2)
Mode
Current
State
High-Speed Mode,
Middle-Speed Mode
Low-Speed
(9)(NOTE 7)
(NOTE 8)
Mode(2)
Low Power
Dissipation
Mode
(13)
(11)
(8)
Low Power
Dissipation Mode
PLL
Operating
Mode(2)
(NOTE 1, 6)
On-chip
Oscillator
Mode
On-chip Oscillator
Low Power
Dissipation Mode
Stop
Mode
Wait
Mode
(16)
(NOTE 3)
(15)
−
(NOTE 1)
−
−
−
(NOTE 1)
−
−
−
(NOTE 1)
(17)
−
−
−
−
(16)
(10)
PLL Operating
Mode(2)
(12)(NOTE 3)
−
−
On-chip Oscillator
Mode
(14)(NOTE 4)
−
−
−
(NOTE 8)
(11)(NOTE 1)
(NOTE 1)
On-chip Oscillator
Low Power
Dissipation Mode
−
−
−
−
(10)
(NOTE 8)
(NOTE 1)
(18)(NOTE 5)
(18)
(18)
−
(18)
(NOTE 5)
(18)(NOTE 5)
(18)
(18)
(18)
−
(18)
(18)
Wait Mode
(17)
(16)
−
Stop Mode
(17)
(16)
(17)
(16)
(17)
−
−
−: Cannot transit
NOTES:
1. Avoid making a transition when the CM20 bit is set in to “1” (oscillation stop, re-oscillation detection function enabled).
Set the CM20 bit to “0” (oscillation stop, re-oscillation detection function disabled) before transiting.
2. On-chip oscillator clock oscillates and stops in low-speed mode. In this mode, the on-chip oscillator can be used as peripheral function clock.
Sub clock oscillates and stops in PLL operating mode. In this mode, sub clock can be used as peripheral function clock.
3. PLL operating mode can only be entered from and changed to high-speed mode.
4. Set the CM06 bit to “1” (division by 8 mode) before transiting from on-chip oscillator mode to high- or middle-speed mode.
5. When exiting stop mode, the CM0S6 bit is set to “1” (division by 8 mode).
6. If the CM05 bit set to “1” (main clock stop), then the CM06 bit is set to “1” (division by 8 mode).
7. A transition can be made only when sub clock is oscillating.
8. State transitions within the same mode (divide-by-n values changed or subclock oscillation turned on or off) are shown in the table below.
Sub Clock Oscillating
No
Division
Sub clock
Turned Off
Sub clock
Oscillating
No Division
Sub Clock Turned Off
Divided by
2
Divided by
4
Divided by
8
Divided by
16
(4)
(5)
(7)
(6)
(5)
(7)
(7)
Divided by 2
(3)
Divided by 4
(3)
(4)
Divided by 8
(3)
(4)
(5)
Divided by 16
(3)
(4)
(5)
(7)
No Division
(2)
−
−
−
No
Division
Divided by
2
Divided by
4
Divided by
8
Divided by
16
(1)
−
−
−
−
(6)
−
(1)
−
−
−
(6)
−
−
(1)
−
−
(6)
−
−
−
(1)
−
−
−
−
−
−
(1)
(4)
(5)
(7)
(6)
(5)
(7)
(6)
(7)
(6)
Divided by 2
−
(2)
−
−
−
(3)
Divided by 4
−
−
(2)
−
−
(3)
(4)
Divided by 8
−
−
−
(2)
−
(3)
(4)
(5)
Divided by 16
−
−
−
−
(2)
(3)
(4)
(5)
(6)
(7)
−: Cannot transit
9.
( ) : setting method. See the following table.
Setting
Operation
Setting
Operation
(1)
CM04 = 0
Sub clock turned off
(10)
CM05 = 0
Main clock oscillating
(2)
CM04 = 1
Sub clock oscillating
(11)
CM05 = 1
Main clock turned off
(3)
CM06 = 0, CM17 = 0, CM16 = 0
CPU clock no division mode
(12)
PLC07=0, CM11=0
Main clock selected
(4)
CM06 = 0, CM17 = 0, CM16 = 1
CPU clock division by 2 mode
(13)
PLC07=1, CM11=1
PLL clock selected
(5)
CM06 = 0, CM17 = 1, CM16 = 0
CPU clock division by 4 mode
(14)
CM21=0
Main clock or PLL clock selected
(6)
CM06 = 0, CM17 = 1, CM16 = 1
CPU clock division by 16 mode
(15)
CM21=1
On-chip oscillator clock selected
(7)
CM06 = 1
CPU clock division by 8 mode
(16)
CM10=1
Transition to stop mode
(8)
CM07 = 0
Main clock, PLL clock, or on-chip
oscillator clock selected
(17)
Wait Instruction
Transition to wait mode
(9)
CM07 = 1
Sub clock selected
(18)
Hardware Interrupt
Exit stop mode or wait mode
CM04, CM05, CM06, CM07
CM10, CM11, CM16, CM17
CM20, CM21
PLC07
Rev.2.41 Jan 10, 2006
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: Bits in CM0 register
: Bits in CM1 register
: Bits in CM2 register
: Bits in PLC0 register
Page 101 of 390
M16C/62P Group (M16C/62P, M16C/62PT)
10.5
10. Clock Generation Circuit
System Clock Protection Function
The system clock protection function prohibits the CPU clock from changing clock sources when the main clock is
selected the CPU clock source. This prevents the CPU clock from stopping should the program crash. This
function is available when the main clock is selected as the CPU clock source.
When the PM21 bit in the PM2 register is set to “1” (clock change disabled), the following bits cannot be written
to:
• The CM02 bit, CM05 bit and CM07 bit in the CM0 register
• The CM10 bit and CM11 bit in the CM1 register
• The CM20 bit in the CM2 register
• All bits in the PLC0 register
When using the system clock protection function, set the CM05 bit in the CM0 register to “0” (main clock
oscillation) and CM07 bit to “0” (main clock as CPU clock source) and follow the procedure below.
(1) Set the PRC1 bit in the PRCR register to “1” (write enable).
(2) Set the PM21 bit in the PM2 register to “1” (protects the clock).
(3) Set the PRC1 bit in the PRCR register to “0” (write disable).
When the PM21 bit is set to “1,” do not execute the WAIT instruction.
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M16C/62P Group (M16C/62P, M16C/62PT)
10.6
10. Clock Generation Circuit
Oscillation Stop and Re-oscillation Detect Function
The oscillation stop and re-oscillation detect function is such that main clock oscillation circuit stop and reoscillation are detected. At oscillation stop, re-oscillation detection, reset or oscillation stop, re-oscillation
detection interrupt are generated. Which is to be generated can be selected using the CM27 bit in the CM2 register.
The oscillation stop detection function can be enabled and disabled by the CM20 bit in the CM2 register. Table
10.9 lists a Specification Overview of Oscillation Stop and Re-Oscillation Detect Function.
Table 10.9
Specification Overview of Oscillation Stop and Re-Oscillation Detect Function
Item
Oscillation Stop Detectable Clock and
Frequency Bandwidth
Enabling Condition for Oscillation Stop,
Re-Oscillation Detection Function
Operation at Oscillation Stop,
Re-Oscillation Detection
10.6.1
Specification
f(XIN)≥2 MHz
Set CM20 bit to “1” (enable)
• Reset occurs (when CM27 bit =0)
• Oscillation stop, re-oscillation detection interrupt
generated (when CM27 bit =1)
Operation When CM27 bit = 0 (Oscillation Stop Detection Reset)
Where main clock stop is detected when the CM20 bit is “1” (oscillation stop, re-oscillation detection function
enabled), the microcomputer is initialized, coming to a halt (oscillation stop reset; refer to 4. Special Function
Register (SFR), 5. Reset).
This status is reset with hardware reset 1 or hardware reset 2. Also, even when re-oscillation is detected, the
microcomputer can be initialized and stopped; it is, however, necessary to avoid such usage (During main clock
stop, do not set the CM20 bit to “1” and the CM27 bit to “0”).
10.6.2
Operation When CM27 bit = 0 (Oscillation Stop and Re-oscillation Detect
Interrupt)
Where the main clock corresponds to the CPU clock source and the CM20 bit is “1” (oscillation stop and reoscillation detect function enabled), the system is placed in the following state if the main clock comes to a halt:
• Oscillation stop and re-oscillation detect interrupt request occurs.
• The on-chip oscillator starts oscillation, and the on-chip oscillator clock becomes the clock source
for CPU clock and peripheral functions in place of the main clock.
• CM21 bit = 1 (on-chip oscillator clock for CPU clock source and clock source of peripheral function.)
• CM22 bit = 1 (main clock stop detected)
• CM23 bit = 1 (main clock stopped)
Where the PLL clock corresponds to the CPU clock source and the CM20 bit is “1,” the system is placed in the
following state if the main clock comes to a halt: Since the CM21 bit remains unchanged, set it to “1” (on-chip
oscillator clock) inside the interrupt routine.
• Oscillation stop and re-oscillation detect interrupt request occurs.
• CM22 bit = 1 (main clock stop detected)
• CM23 bit = 1 (main clock stopped)
• CM21 bit remains unchanged
Where the CM20 bit is “1”, the system is placed in the following state if the main clock re-oscillates from the
stop condition:
• Oscillation stop and re-oscillation detect interrupt request occurs.
• CM22 bit = 1 (main clock re-oscillation detected)
• CM23 bit = 0 (main clock oscillation)
• CM21 bit remains unchanged
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M16C/62P Group (M16C/62P, M16C/62PT)
10.6.3
10. Clock Generation Circuit
How to Use Oscillation Stop and Re-oscillation Detect Function
• The oscillation stop and re-oscillation detect interrupt shares the vector with the watchdog timer interrupt
and low voltage detection interrupt. If the oscillation stop, re-oscillation detection and watchdog timer
interrupts both are used, read the CM22 bit in an interrupt routine to determine which interrupt source is
requesting the interrupt.
• Where the main clock re-oscillated after oscillation stop, the clock source for the CPU clock and peripheral
functions must be switched to the main clock in the program. Figure 10.12 shows the Procedure to Switch
Clock Source From On-chip Oscillator to Main Clock.
• Simultaneously with oscillation stop, re-oscillation detection interrupt occurrence, the CM22 bit becomes
“1”. When the CM22 bit is set at “1,” oscillation stop, re-oscillation detection interrupt are disabled. By
setting the CM22 bit to “0” in the program, oscillation stop, re-oscillation detection interrupt are enabled.
• If the main clock stops during low speed mode where the CM20 bit is “1”, an oscillation stop, re-oscillation
detection interrupt request is generated. At the same time, the on-chip oscillator starts oscillating. In this
case, although the CPU clock is derived from the sub clock as it was before the interrupt occurred, the
peripheral function clocks now are derived from the on-chip oscillator clock.
• To enter wait mode while using the oscillation stop, re-oscillation detection function, set the CM02 bit to
“0” (peripheral function clocks not turned off during wait mode).
• Since the oscillation stop, re-oscillation detection function is provided in preparation for main clock stop
due to external factors, set the CM20 bit to “0” (Oscillation stop, re-oscillation detection function disabled)
where the main clock is stopped or oscillated in the program, that is where the stop mode is selected or the
CM05 bit is altered.
• This function cannot be used if the main clock frequency is 2 MHz or less. In that case, set the CM20 bit to
“0”.
Switch the main clock
NO
Determine several times whether
the CM23 bit is set to “0”
(main clock oscillates)
YES
Set the CM06 bit to “1”
(divide-by-8)
Set the CM22 bit to “0”
(main clock does not stop)
Set the CM21 bit to “0”
(main clock as CPU clock source) (1)
End
CM06 bit : Bit in CM0 register
CM21 to CM23 bits : Bits in CM2 register
NOTES:
1. If the clock source for CPU clock is to be changed to PLL clock, set to PLL operation mode
after set to high-speed mode.
Figure 10.12
Procedure to Switch Clock Source From On-chip Oscillator to Main Clock
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M16C/62P Group (M16C/62P, M16C/62PT)
11. Protection
11. Protection
Note
The M16C/62PT do not use the PRC3 bit in the PRCR register.
In the event that a program runs out of control, this function protects the important registers so that they will not be
rewritten easily. Figure 11.1 shows the PRCR Register. The following lists the registers protected by the PRCR
register.
• The PRC0 bit protects the CM0, CM1, CM2, PLC0 and PCLKR registers;
• The PRC1 bit protects the PM0, PM1, PM2, TB2SC, INVC0 and INVC1 registers;
• The PRC2 bit protects the PD9, S3C and S4C registers;
• The PRC3 bit protects the VCR2 and D4INT registers.
Set the PRC2 bit to “1” (write enabled) and then write to any address, and the PRC2 bit will be cleared to “0” (write
protected). The registers protected by the PRC2 bit should be changed in the next instruction after setting the PRC2 bit
to “1”. Make sure no interrupts or DMA transfers will occur between the instruction in which the PRC2 bit is set to
“1” and the next instruction. The PRC0, PRC1 and PRC3 bits are not automatically cleared to “0” by writing to any
address. They can only be cleared in a program.
Protect Register
b7 b6 b5 b4 b3 b2 b1 b0
0 0
Symbol
PRCR
Bit Symbol
Address
000Ah
After Reset
XX000000b
Bit Name
Protect Bit 0
PRC0
Protect Bit 1
PRC1
Protect Bit 2
PRC2
Protect Bit 3
PRC3
Function
RW
Enable w rite to CM0, CM1, CM2, PLC0 and PCLKR
registers
0 : Write protected
1 : Write enabled
RW
Enable w rite to PM0, PM1, PM2, TB2SC, INVC0 and
INVC1 registers
0 : Write protected
1 : Write enabled
RW
Enable w rite to PD9, S3C and S4C registers
0 : Write protected
1 : Write enabled (1)
RW
Enable w rite to VCR2 and D4INT registers
0 : Write protected
1 : Write enabled
RW
—
(b5-b4)
Reserved Bit
—
(b7-b6)
Nothing is assigned. When w rite, set to “0”.
When read, their contents are indeterminate.
Set to “0”
RW
—
NOTES :
1. The PRC2 bit is set to “0” by w riting to any address after setting it to “1”. Other bits are not set to “0” by w riting to
any address, and must therefore be set in a program.
Figure 11.1
PRCR Register
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M16C/62P Group (M16C/62P, M16C/62PT)
12. Interrupt
12. Interrupt
Note
The M16C/62P (80-pin version) do not use INT3 to INT5 interrupt of peripheral function.
The M16C/62PT (100-pin version) do not use low voltage detection interrupt.
The M16C/62PT (80-pin version) do not use low voltage detection interrupt and INT3 to INT5 interrupt of peripheral
function.
12.1
Type of Interrupts
Figure 12.1 shows Type of Interrupts.
Software
(Non-maskable interrupt)
Interrupt
Special
(Non-maskable interrupt)
Hardware
Undefined instruction (UND instruction)
Overflow (INTO instruction)
BRK instruction
INT instruction
NMI
DBC (2)
Watchdog timer
Oscillation stop and re-oscillation
detection
Low voltage detection
Single step (2)
Address match
Peripheral function (1)
(Maskable interrupt)
NOTES:
1. The peripheral functions in the microcomputer are used to generate the peripheral interrupt.
2. Do not normally use this interrupt because it is provided exclusively for use by development tools.
Figure 12.1
Type of Interrupts
• Maskable Interrupt
: An interrupt which can be enabled (disabled) by the interrupt enable flag (I flag) or
whose interrupt priority can be changed by priority level.
• Non-Maskable Interrupt : An interrupt which cannot be enabled (disabled) by the interrupt enable flag (I flag)
or whose interrupt priority cannot be changed by priority level.
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M16C/62P Group (M16C/62P, M16C/62PT)
12.2
12. Interrupt
Software Interrupts
A software interrupt occurs when executing certain instructions. Software interrupts are non-maskable interrupts.
12.2.1
Undefined Instruction Interrupt
An undefined instruction interrupt occurs when executing the UND instruction.
12.2.2
Overflow Interrupt
An overflow interrupt occurs when executing the INTO instruction with the O flag in the FLG register set to “1”
(the operation resulted in an overflow). The following are instructions whose O flag changes by arithmetic:
ABS, ADC, ADCF, ADD, CMP, DIV, DIVU, DIVX, NEG, RMPA, SBB, SHA, SUB
12.2.3
BRK Interrupt
A BRK interrupt occurs when executing the BRK instruction.
12.2.4
INT Instruction Interrupt
An INT instruction interrupt occurs when executing the INT instruction. Software interrupt Nos. 0 to 63 can be
specified for the INT instruction. Because software interrupt Nos. 4 to 31 are assigned to peripheral function
interrupts, the same interrupt routine as for peripheral function interrupts can be executed by executing the INT
instruction.
In software interrupt Nos. 0 to 31, the U flag is saved to the stack during instruction execution and is cleared to
“0” (ISP selected) before executing an interrupt sequence. The U flag is restored from the stack when returning
from the interrupt routine. In software interrupt Nos. 32 to 63, the U flag does not change state during
instruction execution, and the SP then selected is used.
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M16C/62P Group (M16C/62P, M16C/62PT)
12.3
12. Interrupt
Hardware Interrupts
Hardware interrupts are classified into two types − special interrupts and peripheral function interrupts.
12.3.1
Special Interrupts
Special interrupts are non-maskable interrupts.
12.3.1.1
NMI Interrupt
An NMI interrupt is generated when input on the NMI pin changes state from high to low. For details about the
NMI interrupt, refer to the 12.7 NMI Interrupt.
12.3.1.2
DBC Interrupt
Do not normally use this interrupt because it is provided exclusively for use by development tools.
12.3.1.3
Watchdog Timer Interrupt
Generated by the watchdog timer. Once a watchdog timer interrupt is generated, be sure to initialize the
watchdog timer. For details about the watchdog timer, refer to the 13. Watchdog Timer.
12.3.1.4
Oscillation Stop and Re-oscillation Detection Interrupt
Generated by the oscillation stop and re-oscillation detection function. For details about the oscillation stop and
re-oscillation detection function, refer to the 10. Clock Generation Circuit.
12.3.1.5
12.3.1.5 Low Voltage Detection Interrupt
Generated by the voltage detection circuit. For details about the voltage detection circuit, refer to the 6. Voltage
Detection Circuit.
12.3.1.6
Single-Step Interrupt
Do not normally use this interrupt because it is provided exclusively for use by development tools.
12.3.1.7
Address Match Interrupt
An address match interrupt is generated immediately before executing the instruction at the address indicated
by the RMAD0 to RMAD3 register that corresponds to one of the AIER0 or AIER1 bit in the AIER register or
the AIER20 or AIER21 bit in the AIER2 register which is “1” (address match interrupt enabled). For details
about the address match interrupt, refer to the 12.9 Address Match Interrupt.
12.3.2
Peripheral Function Interrupts
The peripheral function interrupt occurs when a request from the peripheral functions in the microcomputer is
acknowledged. The peripheral function interrupt is a maskable interrupt. See Table 12.2 Relocatable Vector
Tables about how the peripheral function interrupt occurs. Refer to the descriptions of each function for details.
Rev.2.41 Jan 10, 2006
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M16C/62P Group (M16C/62P, M16C/62PT)
12.4
12. Interrupt
Interrupts and Interrupt Vector
One interrupt vector consists of 4 bytes. Set the start address of each interrupt routine in the respective interrupt
vectors. When an interrupt request is accepted, the CPU branches to the address set in the corresponding interrupt
vector. Figure 12.2 shows the Interrupt Vector.
MSB
Vector address (L)
LSB
Low-order address
Middle-order address
Vector address (H)
Figure 12.2
12.4.1
0000
High-order
address
0000
0000
Interrupt Vector
Fixed Vector Tables
The fixed vector tables are allocated to the addresses from FFFDCh to FFFFFh. Table 12.1 lists the Fixed
Vector Tables. In the flash memory version of microcomputer, the vector addresses (H) of fixed vectors are used
by the ID code check function. For details, refer to the 22.2 Functions To Prevent Flash Memory from
Rewriting.
Table 12.1
Fixed Vector Tables
Interrupt Source
Undefined Instruction (UND instruction)
Overflow (INTO instruction)
BRK Instruction (2)
Address Match
Single Step (1)
Watchdog Timer,
Oscillation Stop and Re-Oscillation
Detection,
Low Voltage Detection
Vector Table Addresses
Address (L) to Address (H)
FFFDCh to FFFDFh
FFFE0h to FFFE3h
FFFE4h to FFFE7h
FFFE8h to FFFEBh
FFFECh to FFFEFh
FFFF0h to FFFF3h
DBC (1)
FFFF4h to FFFF7h
NMI
Reset
FFFF8h to FFFFBh
FFFFCh to FFFFFh
Reference
M16C/60, M16C/20 Series
software manual
12.9 Address Match Interrupt
13. Watchdog Timer
10. Clock Generation Circuit
6. Voltage Detection Circuit
12.7 NMI interrupt
5. Reset
NOTES:
1. Do not normally use this interrupt because it is provided exclusively for use by development tools.
2. If the contents of address FFFE7h is FFh, program execution starts from the address shown by the
vector in the relocatable vector table.
Rev.2.41 Jan 10, 2006
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M16C/62P Group (M16C/62P, M16C/62PT)
12.4.2
12. Interrupt
Relocatable Vector Tables
The 256 bytes beginning with the start address set in the INTB register comprise a reloacatable vector table
area. Table 12.2 lists the Relocatable Vector Tables. Setting an even address in the INTB register results in the
interrupt sequence being executed faster than in the case of odd addresses.
Table 12.2
Relocatable Vector Tables
+16 to +19 (0010h to 0013h)
Software
Interrupt
Number
0
1 to 3
4
+20 to +23 (0014h to 0017h)
+24 to +27 (0018h to 001Bh)
+28 to +31 (001Ch to 001Fh)
+32 to +35 (0020h to 0023h)
5
6
7
8
+36 to +39 (0024h to 0027h)
9
INT0
+40 to +43 (0028h to 002Bh)
+44 to +47 (002Ch to 002Fh)
+48 to +51 (0030h to 0033h)
+52 to +55 (0034h to 0037h)
+56 to +59 (0038h to 003Bh)
+60 to +63 (003Ch to 003Fh)
+64 to +67 (0040h to 0043h)
+68 to +71 (0044h to 0047h)
+72 to +75 (0048h to 004Bh)
+76 to +79 (004Ch to 004Fh)
+80 to +83 (0050h to 0053h)
+84 to +87 (0054h to 0057h)
+88 to +91 (0058h to 005Bh)
+92 to +95 (005Ch to 005Fh)
+96 to +99 (0060h to 0063h)
+100 to +103 (0064h to 0067h)
+104 to +107 (0068h to 006Bh)
+108 to +111 (006Ch to 006Fh)
+112 to +115 (0070h to 0073h)
+116 to +119 (0074h to 0077h)
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
INT1
+120 to +123 (0078h to 007Bh)
30
INT2
Software Interrupt (5)
+124 to +127 (007Ch to 007Fh)
31
+128 to +131 (0080h to 0083h)
to
+252 to +255 (00FCh to 00FFh)
32
to
63
Interrupt Source
BRK Instruction (5)
−(Reserved)
Vector Address (1)
Address (L) to Address (H)
+0 to +3 (0000h to 0003h)
INT3
Timer B5
Timer B4, UART1 Bus Collision Detect (4, 6)
Timer B3, UART0 Bus Collision Detect (4, 6)
SI/O4, INT5 (2)
SI/O3, INT4 (2)
UART 2 Bus Collision Detection (6)
DMA0
DMA1
Key Input Interrupt
A/D
UART2 Transmit, NACK2 (3)
UART2 Receive, ACK2 (3)
UART0 Transmit, NACK0 (3)
UART0 Receive, ACK0 (3)
UART1 Transmit, NACK1 (3)
UART1 Receive, ACK1 (3)
Timer A0
Timer A1
Timer A2
Timer A3
Timer A4
Timer B0
Timer B1
Timer B2
Reference
M16C/60, M16C/20
Series software manual
12.6 INT interrupt
15. Timers
15. Timers
17. Serial Interface
12.6 INT interrupt
17. Serial Interface
17. Serial Interface
14. DMAC
12.8 Key Input Interrupt
18. A/D Converter
17. Serial Interface
15. Timers
12.6 INT interrupt
M16C/60, M16C/20
Series software manual
NOTES:
1. Address relative to address in INTB.
2. Use the IFSR6 and IFSR7 bits in the IFSR register to select.
3. During I2C mode, NACK and ACK interrupts comprise the interrupt source.
4. Use the IFSR26 and IFSR27 bits in the IFSR2A register to select.
5. These interrupts cannot be disabled using the I flag.
6. Bus collision detection : During IE mode, this bus collision detection constitutes the factor of an interrupt.
During I2C mode, however, a start condition or a stop condition detection constitutes
the factor of an interrupt.
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M16C/62P Group (M16C/62P, M16C/62PT)
12.5
12. Interrupt
Interrupt Control
The following describes how to enable/disable the maskable interrupts, and how to set the priority in which order
they are accepted. What is explained here does not apply to nonmaskable interrupts.
Use the I flag in the FLG register, IPL, and ILVL2 to ILVL0 bits in the each interrupt control register to enable/
disable the maskable interrupts. Whether an interrupt is requested is indicated by the IR bit in the each interrupt
control register.
Figure 12.3 and Figure 12.4 show the Interrupt Control Registers.
Interrupt Control Register (2)
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
TB5IC
TB4IC/U1BCNIC(3)
TB3IC/U0BCNIC(3)
BCNIC
DM0IC, DM1IC
KUPIC
ADIC
S0TIC to S2TIC
S0RIC to S2RIC
TA0IC to TA4IC
TB0IC to TB2IC
Address
0045h
0046h
0047h
004Ah
004Bh, 004Ch
004Dh
004Eh
0051h, 0053h, 004Fh
0052h, 0054h, 0050h
0055h to 0059h
005Ah to 005Ch
Bit Name
Bit Symbol
Interrupt Priority Level Select Bit
ILVL1
ILVL2
—
(b7-b4)
Function
Interrupt Request Bit
RW
b2 b1 b0
0 0 0 : Level 0 (interrupt disabled)
0 0 1 : Level 1
0 1 0 : Level 2
0 1 1 : Level 3
1 0 0 : Level 4
1 0 1 : Level 5
1 1 0 : Level 6
1 1 1 : Level 7
ILVL0
IR
After Reset
XXXXX000b
XXXXX000b
XXXXX000b
XXXXX000b
XXXXX000b
XXXXX000b
XXXXX000b
XXXXX000b
XXXXX000b
XXXXX000b
XXXXX000b
0 : Interrupt not requested
1 : Interrupt requested
Nothing is assigned. When w rite, set to “0”.
When read, their contents are indeterminate.
RW
RW
RW
RW(1)
—
NOTES :
1. This bit can only be reset by w riting “0” (Do not w rite “1”).
2. To rew rite the interrupt control registers, do so at a point that does not generate the interrupt request for that register.
For details, refer to 24.6 Interrupt.
3. Use the IFSR2A register to select.
Figure 12.3
Interrupt Control Registers (1)
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M16C/62P Group (M16C/62P, M16C/62PT)
12. Interrupt
INTi (0 to 5) Interrupt Control Register (2)
b7 b6 b5 b4 b3 b2 b1 b0
0
Symbol
INT3IC (4)
S4IC/INT5IC
S3IC/INT4IC
INT0IC to INT2IC
Address
0044h
0048h
0049h
005Dh to 005Fh
Bit Name
Bit Symbol
Interrupt Priority Level Select Bit
ILVL1
ILVL2
POL
—
(b5)
—
(b7-b6)
Function
RW
b2 b1 b0
0 0 0 : Level 0 (interrupt disabled)
0 0 1 : Level 1
0 1 0 : Level 2
0 1 1 : Level 3
1 0 0 : Level 4
1 0 1 : Level 5
1 1 0 : Level 6
1 1 1 : Level 7
ILVL0
IR
After Reset
XX00X000b
XX00X000b
XX00X000b
XX00X000b
RW
RW
RW
Interrupt Request Bit
0: Interrupt not requested
1: Interrupt requested
RW(1)
Polarity Select Bit
0 : Selects falling edge (3, 5)
1 : Selects rising edge
RW
Reserved Bit
Set to “0”
Nothing is assigned. When w rite, set to “0”.
When read, their contents are indeterminate.
RW
—
NOTES :
1. This bit can only be reset by w riting “0” (Do not w rite “1”).
2. To rew rite the interrupt control register, do so at a point that does not generate the interrupt request for that register.
For details, refer to 24.6 Interrupt.
3. If the IFSRi bit (i = 0 to 5) in the IFSR register are “1” (both edges), set the POL bit in the INTiIC register to “0” (falling
edge).
4. When the BYTE pin is low and the processor mode is memory expansion or microprocessor mode, set the LVL2 to
ILVL0
5. Set the POL bit in the S3IC or S4IC register to “0” (falling edge) w hen the IFSR6 bit in the IFSR register = 0 (SI/O3
selected) or IFSR7 bit = 0 (SI/O4 selected), respectively.
Figure 12.4
Interrupt Control Registers (2)
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M16C/62P Group (M16C/62P, M16C/62PT)
12.5.1
12. Interrupt
I Flag
The I flag enables or disables the maskable interrupt. Setting the I flag to “1” (= enabled) enables the maskable
interrupt. Setting the I flag to “0” (= disabled) disables all maskable interrupts.
12.5.2
IR Bit
The IR bit is set to “1” (= interrupt requested) when an interrupt request is generated. Then, when the interrupt
request is accepted and the CPU branches to the corresponding interrupt vector, the IR bit is cleared to “0” (=
interrupt not requested).
The IR bit can be cleared to “0” in a program. Note that do not write “1” to this bit.
12.5.3
ILVL2 to ILVL0 Bits and IPL
Interrupt priority levels can be set using the ILVL2 to ILVL0 bits.
Table 12.3 shows the Settings of Interrupt Priority Levels and Table 12.4 shows the Interrupt Priority Levels
Enabled by IPL.
The following are conditions under which an interrupt is accepted:
• I flag = 1
• IR bit = 1
• interrupt priority level > IPL
The I flag, IR bit, ILVL2 to ILVL0 bits and IPL are independent of each other. In no case do they affect one
another.
Table 12.3 Settings of Interrupt Priority Levels
Table 12.4Interrupt Priority Levels Enabled by IPL
000b
Interrupt Priority
Level
Level 0 (interrupt disabled)
001b
Level 1
001b
Interrupt levels 2 and above are enabled
010b
Level 2
010b
Interrupt levels 3 and above are enabled
011b
Level 3
011b
Interrupt levels 4 and above are enabled
100b
Level 4
100b
Interrupt levels 5 and above are enabled
101b
Level 5
101b
Interrupt levels 6 and above are enabled
110b
Level 6
110b
Interrupt levels 7 and above are enabled
111b
Level 7
111b
All maskable interrupts are disabled
ILVL2 to ILVL0 Bits
Rev.2.41 Jan 10, 2006
REJ09B0185-0241
Priority
Order
−
000b
Interrupt levels 1 and above are enabled
Low
High
Page 113 of 390
IPL
Enabled Interrupt Priority Levels
M16C/62P Group (M16C/62P, M16C/62PT)
12.5.4
12. Interrupt
Interrupt Sequence
An interrupt sequence − what are performed over a period from the instant an interrupt is accepted to the instant
the interrupt routine is executed − is described here.
If an interrupt occurs during execution of an instruction, the processor determines its priority when the
execution of the instruction is completed, and transfers control to the interrupt sequence from the next cycle. If
an interrupt occurs during execution of either the SMOVB, SMOVF, SSTR or RMPA instruction, the processor
temporarily suspends the instruction being executed, and transfers control to the interrupt sequence.
The CPU behavior during the interrupt sequence is described below. Figure 12.5 shows Time Required for
Executing Interrupt Sequence.
(1) The CPU obtains interrupt information (interrupt number and interrupt request level) by reading address
000000h. Then, the IR bit applicable to the interrupt information is set to “0” (interrupt requested).
(2) The FLG register, prior to an interrupt sequence, is saved to a temporary register (1) within the CPU.
(3) The I, D and U flags in the FLG register become as follows:
• The I flag is set to “0” (interrupt disabled)
• The D flag is set to “0” (single-step interrupt disabled)
• The U flag is set to “0” (ISP selected)
However, the U flag does not change state if an INT instruction for software interrupt Nos. 32 to 63 is
executed.
(4) The temporary register (1) within the CPU is saved to the stack.
(5) The PC is saved to the stack.
(6) The interrupt priority level of the acknowledged interrupt in IPL is set.
(7) The start address of the relevant interrupt routine set in the interrupt vector is stored in the PC.
After the interrupt sequence is completed, an instruction is executed from the starting address of the interrupt
routine.
NOTES:
1.Temporary register cannot be modified by users.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
CPU clock
Address bus
Address
0000h
Interrupt
information
Data bus
RD
Indeterminate(1)
Indeterminate(1)
SP-2
SP-4
SP-2
contents
SP-4
contents
vec
vec
contents
vec+2
vec+2
contents
Indeterminate(1)
WR(2)
NOTES :
1. The indeterminate state depends on the instruction queue buffer. A read cycle occurs when
the instruction queue buffer is ready to accept instructions.
2. The WR signal timing shown here is for the case where the stack is located in the internal RAM.
Figure 12.5
Time Required for Executing Interrupt Sequence
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PC
18
M16C/62P Group (M16C/62P, M16C/62PT)
12.5.5
12. Interrupt
Interrupt Response Time
Figure 12.6 shows the Interrupt Response Time. The interrupt response or interrupt acknowledge time denotes a
time from when an interrupt request is generated till when the first instruction in the interrupt routine is
executed. Specifically, it consists of a time from when an interrupt request is generated till when the instruction
then executing is completed ((a) on Figure 12.6) and a time during which the interrupt sequence is executed ((b)
on Figure 12.6).
Interrupt request generated
Interrupt request acknowledged
Time
Instruction
Interrupt sequence
(a)
Instruction in
interrupt routine
(b)
Interrupt response time
(a) A time from when an interrupt request is generated till when the instruction then
executing is completed. The length of this time varies with the instruction being
executed. The DIVX instruction requires the longest time, which is equal to 30 cycles
(without wait state, the divisor being a register).
(b) A time during which the interrupt sequence is executed. For details, see the table
below. Note, however, that the values in this table must be increased 2 cycles for the
DBC interrupt and 1 cycle for the address match and single-step interrupts.
Interrupt Vector Address SP Value 16-Bit Bus, Without Wait 8-Bit Bus, Without Wait
Figure 12.6
12.5.6
Even
Even
18 cycles
20 cycles
Even
Odd
19 cycles
20 cycles
Odd
Even
19 cycles
20 cycles
Odd
Odd
20 cycles
20 cycles
Interrupt Response Time
Variation of IPL when Interrupt Request is Accepted
When a maskable interrupt request is accepted, the interrupt priority level of the accepted interrupt is set in the
IPL.
When a software interrupt or special interrupt request is accepted, one of the interrupt priority levels listed in
Table 12.5 is set in the IPL. Table 12.5 lists the IPL Level That is Set to IPL When a Software or Special
Interrupt is Accepted.
Table 12.5
IPL Level That is Set to IPL When a Software or Special Interrupt is Accepted
Interrupt Sources
Level that is Set to IPL
7
Watchdog Timer, NMI, Oscillation Stop and Re-Oscillation Detection,
Low Voltage Detection
Not changed
Software, Address Match, DBC, Single-Step
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M16C/62P Group (M16C/62P, M16C/62PT)
12.5.7
12. Interrupt
Saving Registers
In the interrupt sequence, the FLG register and PC are saved to the stack.
At this time, the 4 high-order bits of the PC and the 4 high-order (IPL) and 8 low-order bits in the FLG register,
16 bits in total, are saved to the stack first. Next, the 16 low-order bits of the PC are saved.
Figure 12.7 shows the Stack Status Before and After Acceptance of Interrupt Request.
The other necessary registers must be saved in a program at the beginning of the interrupt routine. Use the
PUSHM instruction, and all registers except SP can be saved with a single instruction.
Address
MSB
Stack
m−4
m−4
PCL
m−3
m−3
PCM
m−2
m−2
FLGL
Address
MSB
Stack
LSB
m−1
m−1
m
Content of previous stack
m+1
Content of previous stack
[SP]
SP value before
interrupt request is
accepted.
Stack status before interrupt request
is acknowledged
PCH : 4 high-order bits of PC
PCM : 8 middle-order bits of PC
PCL : 8 low-order bits of PC
Figure 12.7
LSB
FLGH
[SP]
New SP value
PCH
m
Content of previous stack
m+1
Content of previous stack
Stack status after interrupt request
is acknowledged
FLGH : 4 high-order bits of FLG
FLGL : 8 low-order bits of FLG
Stack Status Before and After Acceptance of Interrupt Request
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M16C/62P Group (M16C/62P, M16C/62PT)
12. Interrupt
The operation of saving registers carried out in the interrupt sequence is dependent on whether the SP (1), at the
time of acceptance of an interrupt request, is even or odd. If the stack pointer (1) is even, the FLG register and
the PC are saved,16 bits at a time. If odd, they are saved in two steps, 8 bits at a time. Figure 12.8 shows the
Operation of Saving Register.
NOTES:
1.When any INT instruction in software numbers 32 to 63 has been executed, this is the SP indicated by the
U flag. Otherwise, it is the ISP.
(1) SP contains even number
Address
Sequence in which order
registers are saved
Stack
[SP] − 5 (Odd)
[SP] − 4 (Even)
PCL
[SP] − 3(Odd)
PCM
[SP] − 2 (Even)
FLGL
[SP] − 1(Odd)
[SP]
(2) Saved simultaneously,
all 16 bits
PCH
FLGH
(1) Saved simultaneously,
all 16 bits
(Even)
Finished saving registers
in two operations.
(2) SP contains odd number
Address
Stack
Sequence in which order
registers are saved
[SP] − 5 (Even)
[SP] − 4(Odd)
PCL
[SP] − 3 (Even)
PCM
[SP] − 2(Odd)
FLGL
(3)
(4)
Saved, 8 bits at a time
[SP] − 1 (Even)
[SP]
FLGH
(1)
PCH
(2)
(Odd)
Finished saving registers
in four operations.
PCH : 4 high-order bits of PC
PCM : 8 middle-order bits of PC
PCL : 8 low-order bits of PC
FLGH : 4 high-order bits of FLG
FLGL : 8 low-order bits of FLG
NOTES :
1. [SP] denotes the initial value of the SP when interrupt request is acknowledged.
After registers are saved, the SP content is [SP] minus 4.
Figure 12.8
Operation of Saving Register
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M16C/62P Group (M16C/62P, M16C/62PT)
12.5.8
12. Interrupt
Returning from an Interrupt Routine
The FLG register and PC in the state in which they were immediately before entering the interrupt sequence are
restored from the stack by executing the REIT instruction at the end of the interrupt routine.
Thereafter the CPU returns to the program which was being executed before accepting the interrupt request.
Return the other registers saved by a program within the interrupt routine using the POPM or similar instruction
before executing the REIT instruction.
Register bank is switched back to the bank used prior to the interrupt sequence by the REIT instruction.
12.5.9
Interrupt Priority
If two or more interrupt requests are sampled at the same sampling points (a timing to detect whether an
interrupt request is generated or not), the interrupt with the highest priority is acknowledged.
For maskable interrupts (peripheral functions interrupt), any desired priority level can be selected using the
ILVL2 to ILVL0 bits. However, if two or more maskable interrupts have the same priority level, their interrupt
priority is resolved by hardware, with the highest priority interrupt accepted.
The watchdog timer and other special interrupts have their priority levels set in hardware. Figure 12.9 shows the
Hardware Interrupt Priority.
Software interrupts are not affected by the interrupt priority. If an instruction is executed, control branches
invariably to the interrupt routine.
Reset
High
NMI
DBC
Watchdog Timer
Oscillation Stop and Re-Oscillation
Detection,
Low Voltage Detection
Peripheral Function
Single Step
Address Match
Figure 12.9
Hardware Interrupt Priority
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Low
M16C/62P Group (M16C/62P, M16C/62PT)
12. Interrupt
12.5.10 Interrupt Priority Level Select Circuit
The interrupt priority level select circuit selects the highest priority interrupt when two or more interrupt
requests are sampled at the same sampling point.
Figure 12.10 shows the Interrupts Priority Select Circuit.
Priority level of each interrupt
Level 0 (initial value)
Highest
INT1
Timer B2
Timer B0
Timer A3
Timer A1
Timer B4, UART1 bus collision
INT3
INT2
INT0
Timer B1
Timer A4
Timer A2
Timer B3, UART0 bus collision
Timer B5
UART1 reception, ACK1
UART0 reception, ACK0
Priority of peripheral function interrupts
(if priority levels are same)
UART2 reception, ACK2
A/D conversion
DMA1
UART 2 bus collision
SI/O4, INT5
Timer A0
UART1 transmission, NACK1
UART0 transmission, NACK0
UART2 transmission, NACK2
Key input interrupt
DMA0
Lowest
SI/O, INT4
Interrupt request level resolution output to clock
generating circuit (Figure 10.1 Clock Generation Circuit)
IPL
I flag
Interrupt request
accepted
Address match
Watchdog timer
Oscillation stop and
re-oscillation detection
Low voltage detection
DBC
NMI
Figure 12.10
Interrupts Priority Select Circuit
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M16C/62P Group (M16C/62P, M16C/62PT)
12.6
12. Interrupt
INT Interrupt
INTi interrupt (i=0 to 5) is triggered by the edges of external inputs. The edge polarity is selected using the IFSRi
bit in the IFSR register.
INT4 and INT5 share the interrupt vector and interrupt control register with SI/O3 and SI/O4, respectively. To use
the INT4 interrupt, set the IFSR6 bit in the IFSR register to “1” (= INT4). To use the INT5 interrupt, set the IFSR7
bit in the IFSR register to “1” (= INT5).
After modifying the IFSR6 or IFSR7 bit, clear the corresponding IR bit to “0” (= interrupt not requested) before
enabling the interrupt.
Figure 12.11 shows the IFSR and IFSR2A Registers.
Interrupt Factor Select Register
b7 b6 b5 b4 b3 b2 b1 b0
Address
Symbol
IFSR
Bit Symbol
IFSR0
IFSR1
IFSR2
IFSR3
IFSR4
IFSR5
IFSR6
IFSR7
After Reset
00h
035Fh
Bit Name
INT0 Interrupt Polarity Sw itching Bit
INT1 Interrupt Polarity Sw itching Bit
INT2 Interrupt Polarity Sw itching Bit
INT3 Interrupt Polarity Sw itching Bit
INT4 Interrupt Polarity Sw itching Bit
INT5 Interrupt Polarity Sw itching Bit
Function
0 : One edge
1 : Both edges
0 : One edge
1 : Both edges
0 : One edge
1 : Both edges
0 : One edge
1 : Both edges
0 : One edge
1 : Both edges
0 : One edge
1 : Both edges
(1)
RW
(1)
RW
(1)
RW
(1)
RW
(1)
RW
(1)
RW
Interrupt Request Factor Select Bit (2) 0 : SI/O3 (3)
RW
_____
Interrupt Request Factor Select Bit (2)
RW
1 : INT4
0 : SI/O4 (3)
RW
_____
1 : INT5
NOTES :
1. When setting this bit to “1” (= both edges), make sure the POL bit in the INT0IC to INT5IC register are set to “0”
(= falling edge).
2. During memory expansion and microprocessor modes, w hen the data bus is 16 bits w ide (BYTE pin is "L"), set
this bit to “0” (= SI/O3, SI/O4).
3. When setting this bit to “0” (= SI/O3, SI/O4), make sure the POL bit in the S3IC and S4IC registers are set to “0”
(= falling edge).
Interrupt Factor Select Register 2
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
IFSR2A
Bit Symbol
Address
035Eh
After Reset
00XXXXXXb
Bit Name
Function
RW
—
(b5-b0)
Nothing is assigned. When w rite, set to “0”.
When read, their contents are indeterminate.
—
IFSR26
Interrupt Request Factor Select Bit (1) 0 : Timer B3
1 : UART0 bus collision detection
RW
IFSR27
Interrupt Request Factor Select Bit (2) 0 : Timer B4
1 : UART1 bus collision detection
RW
NOTES :
1. Timer B3 and UART0 bus collision detection share the vector and interrupt control register. When using Timer B3
interrupt, clear the IFSR26 bit to “0” (Timer B3). When using UART0 bus collision detection, set the IFSR26 bit to “1”.
2. Timer B4 and UART1 bus collision detection share the vector and interrupt control register. When using Timer B4
interrupt, clear the IFSR27 bit to “0” (Timer B4). When using UART1 bus collision detection, set the IFSR27 bit to “1”.
Figure 12.11
IFSR and IFSR2A Registers
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M16C/62P Group (M16C/62P, M16C/62PT)
12.7
12. Interrupt
NMI Interrupt
An NMI interrupt is generated when input on the NMI pin changes state from high to low. The NMI interrupt is a
non-maskable interrupt.
The input level of this NMI interrupt input pin can be read by accessing the P8_5 bit in the P8 register.
This pin cannot be used as an input port.
12.8
Key Input Interrupt
Of P10_4 to P10_7, a key input interrupt is generated when input on any of the P10_4 to P10_7 pins which has had
the PD10_4 to PD10_7 bits in the PD10 register set to “0” (= input) goes low. Key input interrupts can be used as a
key-on wake up function, the function which gets the microcomputer out of wait or stop mode. However, if you
intend to use the key input interrupt, do not use P10_4 to P10_7 as analog input ports. Figure 12.12 shows the block
diagram of the Key Input Interrupt. Note, however, that while input on any pin which has had the PD10_4 to
PD10_7 bits set to “0” (= input mode) is pulled low, inputs on all other pins of the port are not detected as
interrupts.
PU25 bit in
PUR2 register
Pull-up
transistor
PD10_7 bit in
PD10 register
KUPIC register
PD10_7 bit in PD10 register
KI3
Pull-up
transistor
PD10_6 bit in
PD10 register
Interrupt control circuit
KI2
Pull-up
transistor
PD10_5 bit in
PD10 register
KI1
Pull-up
transistor
PD10_4 bit in
PD10 register
KI0
Figure 12.12
Key Input Interrupt
Rev.2.41 Jan 10, 2006
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Key input interrupt
request
M16C/62P Group (M16C/62P, M16C/62PT)
12.9
12. Interrupt
Address Match Interrupt
An address match interrupt is generated immediately before executing the instruction at the address indicated by
the RMADi register (i=0 to 3). Set the start address of any instruction in the RMADi register. Use the AIER0 and
AIER1 bits in the AIER register and AIER20 and AIER21 bits in the AIER2 register to enable or disable the
interrupt. Note that the address match interrupt is unaffected by the I flag and IPL. For address match interrupts, the
value of the PC that is saved to the stack area varies depending on the instruction being executed (refer to 12.5.7
Saving Registers).
(The value of the PC that is saved to the stack area is not the correct return address.) Therefore, follow one of the
methods described below to return from the address match interrupt.
• Rewrite the content of the stack and then use the REIT instruction to return.
• Restore the stack to its previous state before the interrupt request was accepted by using the POP or similar
other instruction and then use a jump instruction to return.
Table 12.6 shows the Value of the PC that is Saved to the Stack Area when an Address Match Interrupt Request is
Accepted
Figure 12.13 shows the AIER, AIER2 and RMAD0 to RMAD3 Registers.
Table 12.6
Value of the PC that is Saved to the Stack Area when an Address Match Interrupt
Request is Accepted
Value of the PC that is
saved to the stack area
Instruction at the Address Indicated by the RMADi Register
• 16-bit op-code instruction
• Instruction shown below among 8-bit operation code instructions
ADD.B:S
#IMM8,dest
SUB.B:S
#IMM8,dest
AND.B:S
OR.B:S
#IMM8,dest
MOV.B:S
#IMM8,dest
STZ.B:S
STNZ.B:S #IMM8,dest
STZX.B:S
#IMM81,#IMM82,dest
CMP.B:S
#IMM8,dest
PUSHM
src
POPM dest
JMPS
#IMM8
JSRS
#IMM8
MOV.B:S
#IMM,dest (However, dest=A0 or A1)
Instructions other than the above
#IMM8,dest
#IMM8,dest
The address
indicated by the
RMADi register +2
The address
indicated by the
RMADi register +1
Value of the PC that is saved to the stack area : Refer to 12.5.7 Saving Registers.
Table 12.7
Relationship Between Address Match Interrupt Sources and Associated Registers
Address Match Interrupt sources
Address Match Interrupt 0
Address Match Interrupt 1
Address Match Interrupt 2
Address Match Interrupt 13
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Address Match Interrupt Enable Bit
AIER0
AIER1
AIER20
AIER21
Page 122 of 390
Address Match Interrupt Register
RMAD0
RMAD1
RMAD2
RMAD3
M16C/62P Group (M16C/62P, M16C/62PT)
12. Interrupt
Address Match Interrupt Enable Register
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
AIER
Address
0009h
Bit Symbol
After Reset
XXXXXX00b
Bit Name
Function
RW
AIER0
Address Match Interrupt 0
Enable Bit
0 : Interrupt disabled
1 : Interrupt enabled
RW
AIER1
Address Match Interrupt 1
Enable Bit
0 : Interrupt disabled
1 : Interrupt enabled
RW
—
(b7-b2)
Nothing is assigned. When w rite, set to “0”.
When read, their contents are indeterminate.
—
Address Match Interrupt Enable Register 2
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
AIER2
Address
01BBh
Bit Symbol
After Reset
XXXXXX00b
Bit Name
Function
RW
AIER20
Address Match Interrupt 2
Enable Bit
0 : Interrupt disabled
1 : Interrupt enabled
RW
AIER21
Address Match Interrupt 3
Enable Bit
0 : Interrupt disabled
1 : Interrupt enabled
RW
—
(b7-b2)
Nothing is assigned. When w rite, set to “0”.
When read, their contents are indeterminate.
—
Address Match Interrupt Register i (i = 0 to 3)
(b23)
b7
(b19)
b3
(b16) (b15)
b0 b7
(b8)
b0 b7
b0
Symbol
RMAD0
RMAD1
RMAD2
RMAD3
Function
Address setting register for address match interrupt
Nothing is assigned. When w rite, set to “0”.
When read, their contents are indeterminate.
Figure 12.13
AIER, AIER2 and RMAD0 to RMAD3 Registers
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Address
0012h to 0010h
0016h to 0014h
01BAh to 01B8h
01BEh to 01BCh
After Reset
X00000h
X00000h
X00000h
X00000h
Setting Range
RW
00000h to FFFFFh
RW
—
M16C/62P Group (M16C/62P, M16C/62PT)
13. Watchdog Timer
13. Watchdog Timer
The watchdog timer is the function of detecting when the program is out of control. Therefore, we recommend using
the watchdog timer to improve reliability of a system. The watchdog timer contains a 15-bit counter which counts
down the clock derived by dividing the CPU clock using the prescaler. Whether to generate a watchdog timer interrupt
request or apply a watchdog timer reset as an operation to be performed when the watchdog timer underflows after
reaching the terminal count can be selected using the PM12 bit of PM1 register. The PM12 bit can only be set to “1”
(reset). Once this bit is set to “1,” it cannot be set to “0” (watchdog timer interrupt) in a program. Refer to 5.4
Watchdog Timer Reset for the details of watchdog timer reset.
When the main clock source is selected for CPU clock, on-chip oscillator clock, PLL clock, the divide-by-N value for
the prescaler can be chosen to be 16 or 128. If a sub-clock is selected for CPU clock, the divide by- N value for the
prescaler is always 2 no matter how the WDC7 bit is set. The period of watchdog timer can be calculated as given
below. The period of watchdog timer is, however, subject to an error due to the prescaler.
With main clock chosen for CPU clock, on-chip oscillator clock, PLL clock
Watchdog timer period
Prescaler dividing (16 or 128) × Watchdog timer count (32768)
CPU clock
=
With sub-clock chosen for CPU clock
Watchdog timer period
Prescaler dividing (2) × Watchdog timer count (32768)
CPU clock
=
For example, when CPU clock = 16 MHz and the divide-by-N value for the prescaler= 16, the watchdog timer period
is approx. 32.8 ms.
The watchdog timer is initialized by writing to the WDTS register. The prescaler is initialized after reset. Note that the
watchdog timer and the prescaler both are inactive after reset, so that the watchdog timer is activated to start counting
by writing to the WDTS register.
In stop mode, wait mode and hold state, the watchdog timer and prescaler are stopped. Counting is resumed from the
held value when the modes or state are released.
Figure 13.1 shows the Watchdog Timer Block Diagram. Figure 13.2 shows the WDC and WDTS Register.
Prescaler
CM07 = 0
WDC7 = 0
1/16
CPU
clock
1/128
CM07 = 0
WDC7 = 1
PM22 = 0
PM12 = 0 Watchdog timer
HOLD
interrupt request
CM07 = 1
1/2
Watchdog timer
PM12 = 1
On-chip oscillator clock
PM22 = 1
Write to WDTS register
Internal RESET signal
(“L” active)
CM07: Bit in CM0 register
WDC7: Bit in WDC register
PM12: Bit in PM1 register
PM22: Bit in PM2 register
Figure 13.1
Watchdog Timer Block Diagram
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Reset
Set to
“7FFFh”
M16C/62P Group (M16C/62P, M16C/62PT)
13. Watchdog Timer
Watchdog Timer Control Register
b7 b6 b5 b4 b3 b2 b1 b0
0
Symbol
Address
000Fh
WDC
Bit Symbol
Bit Name
—
High-order Bit of Watchdog Timer
(b4-b0)
WDC5
—
(b6)
WDC7
After Reset
00XXXXXXb(2)
Function
RW
RO
Cold Start / Warm Start Discrimination
Flag (1, 2)
0 : Cold Start
1 : Warm Start
Reserved Bit
Set to “0”
Prescaler Select Bit
0 : Divided by 16
1 : Divided by 128
RW
RW
RW
NOTES :
1. Writing to the WDC register factors the WDC5 bit to be set to “1” (w arm start). If the voltage applied to VCC1 is less
than 4.0 V, either w rite to this register w hen the CPU clock frequency is 2 MHz or w rite tw ice.
2. The WDC5 bit is set to “0” (cold start) w hen pow er is turned on and can be set to “1” by program only.
Watchdog Timer Start Register (1)
b7
b0
Symbol
WDTS
Address
000Eh
After Reset
Indeterminate
Function
The w atchdog timer is initialized and starts counting after a w rite instruction to this register.
The w atchdog timer value is alw ays initialized to “7FFFh” regardless of w hatever value is
w ritten.
RW
WO
NOTES :
1. Write to the WDTS register after the w atchdog timer interrupt occurs.
Figure 13.2
13.1
WDC and WDTS Register
Count source protective mode
In this mode, a on-chip oscillator clock is used for the watchdog timer count source. The watchdog timer can be
kept being clocked even when CPU clock stops as a result of run-away.
Before this mode can be used, the following register settings are required:
(1) Set the PRC1 bit in the PRCR register to “1” (enable writes to PM1 and PM2 registers).
(2) Set the PM12 bit in the PM1 register to “1” (reset when the watchdog timer underflows).
(3) Set the PM22 bit in the PM2 register to “1” (on-chip oscillator clock used for the watchdog timer count
source).
(4) Set the PRC1 bit in the PRCR register to “0” (disable writes to PM1 and PM2 registers).
(5) Write to the WDTS register (watchdog timer starts counting).
Setting the PM22 bit in the PM register to “1” results in the following conditions.
• The on-chip oscillator starts oscillating, and the on-chip oscillator clock becomes the watchdog timer count
source.
Watchdog timer period
=
Watchdog timer count (32768)
On-chip oscillator clock
• The CM10 bit in the CM1 register is disabled against write (Writing a “1” has no effect, nor is stop mode
entered).
• The watchdog timer does not stop when in wait mode or hold state.
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M16C/62P Group (M16C/62P, M16C/62PT)
14. DMAC
14. DMAC
The DMAC (Direct Memory Access Controller) allows data to be transferred without the CPU intervention.
Two DMAC channels are included. Each time a DMA request occurs, the DMAC transfers one (8 or 16-bit) data from
the source address to the destination address. The DMAC uses the same data bus as used by the CPU. Because the
DMAC has higher priority of bus control than the CPU and because it makes use of a cycle steal method, it can transfer
one word (16 bits) or one byte (8 bits) of data within a very short time after a DMA request is generated. Figure 14.1
shows the DMAC Block Diagram. Table 14.1 lists the DMAC Specifications. Figures 14.2 to 14.4 shows the DMACrelated registers.
Address bus
DMA0 source pointer SAR0(20)
(addresses 0022h to 0020h)
DMA0 destination pointer DAR0 (20)
(addresses 0026h to 0024h)
DMA0 forward address pointer (20) (1)
DMA0 transfer counter reload register TCR0 (16)
(addresses 0029h, 0028h)
DMA1 source pointer SAR1 (20)
(addresses 0032h to 0030h)
DMA0 transfer counter TCR0 (16)
DMA1 destination pointer DAR1 (20)
DMA1 transfer counter reload register TCR1 (16)
DMA1 forward address pointer (20) (1)
(addresses 0036h to 0034h)
(addresses 0039h, 0038h)
DMA1 transfer counter TCR1 (16)
DMA latch high-order bits
DMA latch low-order bits
Data bus low-order bits
Data bus high-order bits
NOTES :
1. Pointer is incremented by a DMA request.
Figure 14.1
DMAC Block Diagram
A DMA request is generated by a write to the DSR bit in the DMiSL register (i = 0 to 1), as well as by an interrupt
request which is generated by any function specified by the DMS and DSEL3 to DSEL0 bits in the DMiSL register.
However, unlike in the case of interrupt requests, DMA requests are not affected by the I flag and the interrupt control
register, so that even when interrupt requests are disabled and no interrupt request can be accepted, DMA requests are
always accepted. Furthermore, because the DMAC does not affect interrupts, the IR bit in the interrupt control register
does not change state due to a DMA transfer.
A data transfer is initiated each time a DMA request is generated when the DMAE bit in the DMiCON register = 1
(DMA enabled). However, if the cycle in which a DMA request is generated is faster than the DMA transfer cycle, the
number of transfer requests generated and the number of times data is transferred may not match. Refer to 14.4 DMA
Request for details.
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M16C/62P Group (M16C/62P, M16C/62PT)
Table 14.1
14. DMAC
DMAC Specifications
Item
No. of Channels
Transfer Memory Space
Maximum No. of Bytes Transferred
DMA Request Factors (1, 2)
Specification
2 (cycle steal method)
• From any address in the 1-Mbyte space to a fixed address
• From a fixed address to any address in the 1-Mbyte space
• From a fixed address to a fixed address
128 Kbytes (with 16-bit transfers) or 64 Kbytes (with 8-bit transfers)
Falling edge of INT0 or INT1
Both edge of INT0 or INT1
Timer A0 to timer A4 interrupt requests
Timer B0 to timer B5 interrupt requests
UART0 transfer, UART0 reception interrupt requests
UART1 transfer, UART1 reception interrupt requests
UART2 transfer, UART2 reception interrupt requests
SI/O3, SI/O4 interrupt requests
A/D conversion interrupt requests
Software triggers
Channel Priority
DMA0 > DMA1 (DMA0 takes precedence)
Transfer Unit
8 bits or 16 bits
Transfer Address Direction
forward or fixed (The source and destination addresses cannot both be
in the forward direction.)
Transfer Mode
Single Transfer
Transfer is completed when the DMAi transfer counter (i = 0 to 1)
underflows after reaching the terminal count.
Repeat Transfer
When the DMAi transfer counter underflows, it is reloaded with the value
of the DMAi transfer counter reload register and a DMA transfer is
continued with it.
DMA Interrupt Request Generation Timing When the DMAi transfer counter underflowed
DMA Start up
Data transfer is initiated each time a DMA request is generated when the
DMAE bit in the DMAiCON register = 1 (enabled).
DMA Shutdown
Single Transfer
• When the DMAE bit is set to “0” (disabled)
• After the DMAi transfer counter underflows
Repeat Transfer
When the DMAE bit is set to “0” (disabled)
Reload Timing for Forward Address Pointer When a data transfer is started after setting the DMAE bit to “1”
and Transfer Counter
(enabled), the forward address pointer is reloaded with the value of the
SARi or the DARi pointer whichever is specified to be in the forward
direction and the DMAi transfer counter is reloaded with the value of the
DMAi transfer counter reload register.
DMA Transfer Cycles
Minimum 3 cycles between SFR and internal RAM
NOTES:
1. DMA transfer is not effective to any interrupt. DMA transfer is affected neither by the I flag nor by the interrupt
control register.
2. The selectable factors of DMA requests differ with each channel.
3. Make sure that no DMAC-related registers (addresses 0020h to 003Fh) are accessed by the DMAC.
Rev.2.41 Jan 10, 2006
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Page 127 of 390
M16C/62P Group (M16C/62P, M16C/62PT)
14. DMAC
DMA0 Request Factor Select Register
b7 b6 b5 b4 b3 b2 b1 b0
Address
Symbol
03B8h
DM0SL
Bit Name
Bit Symbol
DSEL0
DMA Request Factor Select Bit
(NOTE 1)
DSEL1
DSEL2
DSEL3
—
Nothing is assigned. When w rite, set to “0”.
(b5-b4)
When read, their content are “0”.
DMS
After Reset
00h
Function
RW
RW
RW
RW
RW
—
DMA Request Factor Expansion
Select Bit
0: Basic factor of request
1: Extended factor of request
RW
Softw are DMA Request Bit
A DMA request is generated by setting this bit
to “1” w hen the DMS bit is “0” (basic factor)
and the DSEL3 to DSEL0 bits are “0001b”
(softw are trigger).
The value of this bit w hen read is “0”.
RW
DSR
NOTES :
1. The factors of DMA0 requests can be selected by a combination of DMS bit and DSEL3 to DSEL0 bits in the manner
described below .
DSEL3 to DSEL0
DMS=0(Basic Factor of Request)
DMS=1(Extended Factor of Request)
_____
0000b
—
Falling Edge of INT0 Pin
Softw are Trigger
0001b
—
0010b
Timer A0
—
0011b
Timer A1
—
0100b
Timer A2
—
0101b
Timer A3
—
_____
0110b
Timer A4
Tw o Edges of INT0 Pin
0111b
Timer B0
Timer B3
1000b
Timer B1
Timer B4
1001b
Timer B2
Timer B5
1010b
UART0 Transmit
—
1011b
—
UART0 Receive
—
1100b
UART2 Transmit
—
1101b
UART2 Receive
—
1110b
A/D Conversion
—
1111b
UART1 Transmit
Figure 14.2
DM0SL Register
Rev.2.41 Jan 10, 2006
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M16C/62P Group (M16C/62P, M16C/62PT)
14. DMAC
DMA1 Request Factor Select Register
b7 b6 b5 b4 b3 b2 b1 b0
Address
Symbol
03BAh
DM1SL
Bit Name
Bit Symbol
DSEL0
DMA Request factor Select Bit
(NOTE 1)
DSEL1
DSEL2
DSEL3
—
Nothing is assigned. When w rite, set to “0”.
(b5-b4)
When read, their contents are “0”.
DMS
After Reset
00h
Function
RW
RW
RW
RW
RW
—
DMA Request Factor Expansion
Select Bit
0: Basic factor of request
1: Extended factor of request
RW
Softw are DMA Request Bit
A DMA request is generated by setting this bit
to “1” w hen the DMS bit is “0” (basic factor)
and the DSEL3 to DSEL0 bits are “0001b”
(softw are trigger).
The value of this bit w hen read is “0”.
RW
DSR
NOTES :
1. The factors of DMA1 requests can be selected by a combination of DMS bit and DSEL3 to DSEL0 bits in the manner
described below .
DSEL3 to DSEL0
DMS=0(Basic Factor of Request)
DMS=1(Extended Factor of Request)
_____
—
0000b
Falling Edge of INT1 Pin
0001b
Softw are Trigger
—
0010b
Timer A0
—
0011b
Timer A1
—
0100b
Timer A2
—
0101b
Timer A3
SI/O3
0110b
Timer A4
SI/O4
_____
Tw o Edges of INT1 Pin
0111b
Timer B0
1000b
Timer B1
—
1001b
Timer B2
—
1010b
UART0 Transmit
—
1011b
UART0 Receive/ACK0
—
1100b
UART2 Transmit
—
1101b
UART2 Receive/ACK2
—
1110b
A/D Conversion
—
1111b
UART1 Receive/ACK1
—
Figure 14.3
DM1SL Register
Rev.2.41 Jan 10, 2006
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M16C/62P Group (M16C/62P, M16C/62PT)
14. DMAC
DMAi Control Register (i=0,1)
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
DM0CON
DM1CON
Bit Symbol
Address
002Ch
003Ch
Bit Name
Transfer Unit Bit Select Bit
After Reset
00000X00b
00000X00b
Function
RW
Repeat Transfer Mode Select Bit
0 : Single transfer
1 : Repeat transfer
RW
DMA Request Bit
0 : DMA not requested
1 : DMA requested
DMA Enable Bit
0 : Disabled
1 : Enabled
RW
DSD
Source Address Direction Select
Bit (2)
0 : Fixed
1 : Forw ard
RW
DAD
Destination Address Direction Select
Bit (2)
0 : Fixed
1 : Forw ard
RW
DMBIT
DMASL
DMAS
DMAE
—
(b7-b6)
Nothing is assigned. When w rite, set to “0”.
When read, their contents are “0”.
NOTES :
1. The DMAS bit can be set to “0” by w riting “0” in a program (This bit remains unchanged even if “1” is w ritten).
2. At least one of the DAD and DSD bits must be “0” (address direction fixed).
Figure 14.4
DM0CON and DM1CON Register
Rev.2.41 Jan 10, 2006
REJ09B0185-0241
RW
0 : 16 bits
1 : 8 bits
Page 130 of 390
RW(1)
—
M16C/62P Group (M16C/62P, M16C/62PT)
14. DMAC
DMAi Source Pointer (i = 0, 1) (1)
(b23)
b7
(b19)
b3
(b16) (b15)
b0 b7
(b8)
b0 b7
b0
Symbol
SAR0
SAR1
Address
0022h to 0020h
0032h to 0030h
Function
Set the source address of transfer
Nothing is assigned. When w rite, set “0”.
When read, their contents are “0”.
After Reset
Indeterminate
Indeterminate
Setting Range
RW
00000h to FFFFFh
RW
—
NOTES :
1. If the DSD bit in the DMiCON register is “0” (fixed), this register can only be w ritten to w hen the DMAE bit in the
DMiCON register is “0” (DMA disabled).
If the DSD bit is “1” (forw ard direction), this register can be w ritten to at any time.
If the DSD bit is “1” and the DMAE bit is “1” (DMA enabled), the DMAi forw ard address pointer can be read from this
register. Otherw ise, the value w ritten to it can be read.
DMAi Destination Pointer (i = 0, 1) (1)
(b23)
b7
(b19)
b3
(b16) (b15)
b0 b7
(b8)
b0 b7
b0
Symbol
DAR0
DAR1
Address
0026h to 0024h
0036h to 0034h
Function
Set the destination address of transfer
Nothing is assigned. When w rite, set “0”.
When read, their contents are “0”.
After Reset
Indeterminate
Indeterminate
Setting Range
RW
00000h to FFFFFh
RW
—
NOTES :
1. If the DAD bit in the DMiCON register is “0” (fixed), this register can only be w ritten to w hen the DMAE bit in the
DMiCON register is “0”(DMA disabled).
If the DAD bit is “1” (forw ard direction), this register can be w ritten to at any time.
If the DAD bit is “1” and the DMAE bit is “1” (DMA enabled), the DMAi forw ard address pointer can be read from this
register. Otherw ise, the value w ritten to it can be read.
DMAi Transfer Counter (i = 0, 1)
(b15)
b7
(b8)
b0 b7
b0
Symbol
TCR0
TCR1
Address
0029h to 0028h
0039h to 0038h
Function
Set the transfer count minus 1. The w ritten value is stored in the DMAi
transfer counter reload register, and w hen the DMAE bit in the DMiCON
register is set to “1” (DMA enabled) or the DMAi transfer counter
underflow s w hen the DMASL bit in the DMiCON register is “1” (repeat
transfer), the value of the DMAi transfer counter reload register is
transferred to the DMAi transfer counter.
When read, the DMAi transfer counter is read.
Figure 14.5
SAR0, SAR1, DAR0, DAR1, TCR0 and TCR1 Registers
Rev.2.41 Jan 10, 2006
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After Reset
Indeterminate
Indeterminate
Setting Range
RW
0000h to FFFFh
RW
M16C/62P Group (M16C/62P, M16C/62PT)
14.1
14. DMAC
Transfer Cycles
The transfer cycle consists of a memory or SFR read (source read) bus cycle and a write (destination write) bus
cycle. The number of read and write bus cycles is affected by the source and destination addresses of transfer.
During memory extension and microprocessor modes, it is also affected by the BYTE pin level. Furthermore, the
bus cycle itself is extended by a software wait or RDY signal.
14.1.1
Effect of Source and Destination Addresses
If the transfer unit and data bus both are 16 bits and the source address of transfer begins with an odd address,
the source read cycle consists of one more bus cycle than when the source address of transfer begins with an
even address.
Similarly, if the transfer unit and data bus both are 16 bits and the destination address of transfer begins with an
odd address, the destination write cycle consists of one more bus cycle than when the destination address of
transfer begins with an even address.
14.1.2
Effect of BYTE Pin Level
During memory extension and microprocessor modes, if 16 bits of data are to be transferred on an 8-bit data bus
(input on the BYTE pin = high), the operation is accomplished by transferring 8 bits of data twice. Therefore,
this operation requires two bus cycles to read data and two bus cycles to write data. Furthermore, if the DMAC
is to access the internal area (internal ROM, internal RAM, or SFR), unlike in the case of the CPU, the DMAC
does it through the data bus width selected by the BYTE pin.
14.1.3
Effect of Software Wait
For memory or SFR accesses in which one or more software wait states are inserted, the number of bus cycles
required for that access increases by an amount equal to software wait states.
14.1.4
Effect of RDY Signal
During memory extension and microprocessor modes, DMA transfers to and from an external area are affected
by the RDY signal. Refer to 8.2.6 RDY Signal.
Figure 14.6 shows the example of the Transfer Cycles for Source Read. For convenience, the destination write
cycle is shown as one cycle and the source read cycles for the different conditions are shown. In reality, the
destination write cycle is subject to the same conditions as the source read cycle, with the transfer cycle changing
accordingly. When calculating transfer cycles, take into consideration each condition for the source read and the
destination write cycle, respectively. For example, when data is transferred in 16 bit units using an 8-bit bus ((2) on
Figure 14.6), two source read bus cycles and two destination write bus cycles are required.
Rev.2.41 Jan 10, 2006
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Page 132 of 390
M16C/62P Group (M16C/62P, M16C/62PT)
14. DMAC
(1) When the transfer unit is 8 or 16 bits and the source of transfer is an even address
BCLK
Address
bus
CPU use
Source
Dummy
cycle
Destination
CPU use
RD signal
WR signal
Data bus
CPU use
Dummy
cycle
Destination
Source
CPU use
(2) When the transfer unit is 16 bits and the source address of transfer is an odd address, or when the
transfer unit is 16 bits and an 8-bit bus is used
BCLK
Address
bus
CPU use
Source
Source + 1
Destination
Dummy
cycle
CPU use
RD signal
WR signal
Data bus
CPU use
Source + 1
Source
Destination
Dummy
cycle
CPU use
(3) When the source read cycle under condition (1) has one wait state inserted
BCLK
Address
bus
Destination
Source
CPU use
Dummy
cycle
CPU use
RD signal
WR signal
Data bus
CPU use
Source
Destination
Dummy
cycle
CPU use
(4) When the source read cycle under condition (2) has one wait state inserted
BCLK
Address
bus
CPU use
Source
Source + 1
Destination
Dummy
cycle
CPU use
RD signal
WR signal
Data bus
CPU use
Source
Source + 1
Destination
Dummy
cycle
CPU use
NOTES :
1. The same timing changes occur with the respective conditions at the destination as at the source.
Figure 14.6
Transfer Cycles for Source Read
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Page 133 of 390
M16C/62P Group (M16C/62P, M16C/62PT)
14.2
14. DMAC
DMA Transfer Cycles
Any combination of even or odd transfer read and write addresses is possible. Table 14.2 lists the DMA Transfer
Cycles. Table 14.3 lists the Coefficient j, k.
The number of DMAC transfer cycles can be calculated as follows:
No. of transfer cycles per transfer unit = No. of read cycles × j + No. of write cycles × k
Table 14.2
DMA Transfer Cycles
Transfer Unit
Bus Width
8-bit Transfers
(DMBIT= 1)
16-bit
(BYTE= L)
8-bit
(BYTE = H)
16-bit Transfers 16-bit
(DMBIT= 0)
(BYTE = L)
8-bit
(BYTE = H)
Access
Address
Even
Odd
Even
Odd
Even
Odd
Even
Odd
Single-Chip Mode
No. of Read
Cycles
1
1
—
—
1
2
—
—
No. of Write
Cycles
1
1
—
—
1
2
—
—
Memory Expansion Mode
Microprocessor Mode
No. of Read
No. of Write
Cycles
Cycles
1
1
1
1
1
1
1
1
1
1
2
2
2
2
2
2
— : This condition does not exist.
Table 14.3
Coefficient j, k
Internal Area
Internal ROM,
SFR
RAM
j
k
External Area
Separate Bus
No Wait
With
Wait
1-Wait
2-Wait
(2)
(2)
No
Wait
1
1
2
2
2
2
3
3
1
2
With Wait (1)
1-Wait 2-Wait 3-Wait
2
3
4
2
3
4
NOTES:
1. Depends on the set value of CSE register.
2. Depends on the set value of PM20 bit in the PM2 register.
Rev.2.41 Jan 10, 2006
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Page 134 of 390
Multiplex Bus
With Wait (1)
1-Wait 2-Wait 3-Wait
3
3
4
3
3
4
M16C/62P Group (M16C/62P, M16C/62PT)
14.3
14. DMAC
DMA Enable
When a data transfer starts after setting the DMAE bit in the DMiCON register (i = 0, 1) to “1” (enabled), the
DMAC operates as follows:
(1) Reload the forward address pointer with the SARi register value when the DSD bit in the DMiCON register
is “1” (forward) or the DARi register value when the DAD bit in the DMiCON register is “1” (forward).
(2) Reload the DMAi transfer counter with the DMAi transfer counter reload register value.
If the DMAE bit is set to “1” again while it remains set, the DMAC performs the above operation. However, if a
DMA request may occur simultaneously when the DMAE bit is being written, follow the steps below.
Step 1: Write “1” to the DMAE bit and DMAS bit in the DMiCON register simultaneously.
Step 2: Make sure that the DMAi is in an initial state as described above (1) and (2) in a program.
If the DMAi is not in an initial state, the above steps should be repeated.
14.4
DMA Request
The DMAC can generate a DMA request as triggered by the factor of request that is selected with the DMS and
DSEL3 to DSEL0 bits in the DMiSL register (i = 0, 1) on either channel. Table 14.4 lists the Timing at Which the
DMAS Bit Changes State.
Whenever a DMA request is generated, the DMAS bit is set to “1” (DMA requested) regardless of whether or not
the DMAE bit is set. If the DMAE bit was set to “1” (enabled) when this occurred, the DMAS bit is set to “0”
(DMA not requested) immediately before a data transfer starts. This bit cannot be set to “1” in a program (it can
only be set to “0”).
The DMAS bit may be set to “1” when the DMS or the DSEL3 to DSEL0 bits change state. Therefore, always be
sure to set the DMAS bit to “0” after changing the DMS or the DSEL3 to DSEL0 bits.
Because if the DMAE bit is “1”, a data transfer starts immediately after a DMA request is generated, the DMAS bit
in almost all cases is “0” when read in a program. Read the DMAE bit to determine whether the DMAC is enabled.
Table 14.4
Timing at Which the DMAS Bit Changes State
DMA Factor
Software Trigger
Peripheral Function
Rev.2.41 Jan 10, 2006
REJ09B0185-0241
DMAS Bit of the DMiCON Register
Timing at which the bit is set to “1”
Timing at which the bit is set to “0”
When the DSR bit in the DMiSL register • Immediately before a data transfer starts
is set to “1”
• When set by writing “0” in a program
When the interrupt control register for
the peripheral function that is selected
by the DSEL3 to DSEL0 and DMS bits
in the DMiSL register has its IR bit set
to “1”
Page 135 of 390
M16C/62P Group (M16C/62P, M16C/62PT)
14.5
14. DMAC
Channel Priority and DMA Transfer Timing
If both DMA0 and DMA1 are enabled and DMA transfer request signals from DMA0 and DMA1 are detected
active in the same sampling period (one period from a falling edge to the next falling edge of BCLK), the DMAS
bit on each channel is set to “1” (DMA requested) at the same time. In this case, the DMA requests are arbitrated
according to the channel priority, DMA0 > DMA1. The following describes DMAC operation when DMA0 and
DMA1 requests are detected active in the same sampling period. Figure 14.7 shows an example of DMA Transfer
by External Factors.
DMA0 request having priority is received first to start a transfer when a DMA0 request and DMA1 request are
generated simultaneously. After one DMA0 transfer is completed, a bus arbitration is returned to the CPU. When
the CPU has completed one bus access, a DMA1 transfer starts. After one DMA1 transfer is completed, the bus
arbitration is again returned to the CPU.
In addition, DMA requests cannot be counted up since each channel has one DMAS bit. Therefore, when DMA
requests, as DMA1 in Figure 14.7, occurs more than one time, the DMAS bit is set to “0” as soon as getting the bus
arbitration. The bus arbitration is returned to the CPU when one transfer is completed.
Refer to 8.2.7 Hold Signal for details about bus arbitration between the CPU and DMA.
An example where DMA requests for external factors are detected active at the same
BCLK
DMA0
Bus
arbitration
DMA1
CPU
INT0
DMA0
request bit
INT1
DMA1
request bit
Figure 14.7
DMA Transfer by External Factors
Rev.2.41 Jan 10, 2006
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M16C/62P Group (M16C/62P, M16C/62PT)
15. Timers
15. Timers
Note
The M16C/62P (80-pin version) and M16C/62PT (80-pin version) do not include TA1IN, TA1OUT,
TA2IN, TA2OUT and TB pins. Do not use the function which needs these pins.
Eleven 16-bit timers, each capable of operating independently of the others, can be classified by function as either
Timer A (five) and Timer B (six). The count source for each timer acts as a clock, to control such timer operations as
counting, reloading, etc. Figures 15.1 and 15.2 show block diagrams of Timer A and Timer B configuration,
respectively.
f2 PCLK0 bit = 0
1/2
Clock prescaler
f1 or f2
· Main clock
f1
· PLL clock
· On-chip oscillator
clock
1/32
XCIN
PCLK0 bit = 1
f8
1/8
1/4
f32
Set the CPSR bit in the
CPSRF register to “1”
(= prescaler reset)
fC32
Reset
f1 or f2 f8 f32 fC32
00
01
10
11
TMOD1 to TMOD0
10
Noise
filter
TA0IN
00: Timer mode
10: One-shot timer mode
11: PWM mode
TCK1 to TCK0
01
00
Timer A0 interrupt
Timer A0
01: Event counter mode
11 TA0TGH to TA0TGL
TCK1 to TCK0
00
01
10
11
TMOD1 to TMOD0
10
Noise
filter
TA1IN
00: Timer mode
10: One-shot tiemr mode
11: PWM mode
01
00
Timer A1 interrupt
Timer A1
01: Event counter mode
11 TA1TGH to TA1TGL
00: Timer mode
10: One-shot timer mode
11: PWM mode
TCK1 to TCK0
00
01
10
11
Noise
filter
TA2IN
TMOD1 to TMOD0
10
01
00
Timer A2 interrupt
Timer A2
01: Event counter mode
11 TA2TGH to TA2TGL
TCK1 to TCK0
00
01
10
11
10
Noise
filter
01
00
TA3IN
00: Timer mode
10: One-shot timer mode
11: PWM mode
TMOD1 to TMOD0
Timer A3 interrupt
Timer A3
01: Event counter mode
11 TA3TGH to TA3TGL
00
01
10
11
TCK1 to TCK0
TMOD1 to TMOD0
10
Noise
filter
TA4IN
00: Timer mode
10: One-shot timer mode
11: PWM mode
01
00
Timer A4 interrupt
Timer A4
01: Event counter mode
11 TA4TGH to TA4TGL
Timer B2 overflow
or underflow
TCK1 to TCK0, TMOD1 to TMOD0 : Bits in TAiMR register (i=0 to 4)
TAiGH to TAiGL: Bits in ONSF register and TRGSR register
NOTES :
1. Be aware that TA0IN shares the pin with RXD2 and TB5IN.
Figure 15.1
Timer A Configuration
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Page 137 of 390
M16C/62P Group (M16C/62P, M16C/62PT)
f2
15. Timers
PCLK0 bit = 0
1/2
· Main clock
f1
· PLL clock
· On-chip oscillator
clock
Clock prescaler
f1 or f2
1/8
00
01
10
11
TCK1 to TCK0
00: Timer mode
10: Pulse period / pulse width measurement mode
TMOD1 to TMOD0
TB0IN
00
01
10
11
00
01
10
11
TCK1
01: Event counter mode
00: Timer mode
10: Pulse period / pulse width measurement mode
TMOD1 to TMOD0
1
Timer B1 interrupt
Timer B1
0
TCK1
01: Event counter mode
TCK1 to TCK0
00: Timer mode
10: Pulse period / pulse width measurement mode
TMOD1 to TMOD0
1
Timer B2 interrupt
Timer B2
0
TCK1
01: Event counter mode
TCK1 to TCK0
00: Timer mode
10: Pulse period / pulse width measurement mode
TMOD1 to TMOD0
1
Noise
filter
TB3IN
Timer B3
0
TCK1
00
01
10
11
1
TMOD1 to TMOD0
Timer B4
01: Event counter mode
TCK1 to TCK0
00: Timer mode
10: Pulse period / pulse width measurement mode
TMOD1 to TMOD0
1
Timer B5
0
TCK1
01: Event counter mode
TCK1 to TCK0, TMOD1 to TMOD0 : Bits in TBiMR register (i=0 to 5)
NOTES :
1. Be aware that TB5IN shares the pin with RXD2 and TA0IN.
Figure 15.2
Timer B Configuration
Rev.2.41 Jan 10, 2006
REJ09B0185-0241
Timer B4 interrupt
0
Noise
filter
TB5IN
01: Event counter mode
00: Timer mode
10: Pulse period / pulse width measurement mode
TCK1
00
01
10
11
Timer B3 interrupt
TCK1 to TCK0
Noise
filter
TB4IN
Timer B0 interrupt
0
Noise
filter
TB2IN
Timer B0
1
TCK1 to TCK0
Noise
filter
00
01
10
11
Reset
Timer B2 overflow or underflow
(to a count source of Timer A)
Noise
filter
TB1IN
Set the CPSR bit in the
CPSRF register to “1”
(= prescaler reset)
f32
1/4
f1 or f2 f8 f32 fC32
f8
fC32
1/32
XCIN
PCLK0 bit = 1
Page 138 of 390
Timer B5 interrupt
M16C/62P Group (M16C/62P, M16C/62PT)
15.1
15. Timers
Timer A
Note
The M16C/62P (80-pin version) and M16C/62PT (80-pin version) do not include TA1IN and TA1OUT pins
of Timer A1, and TA2IN and TA2OUT pins of Timer A2.
[Precautions when using Timer A1 and Timer A2]
• Timer Mode
The Gate Function and the Pulse Output Function cannot be used. Set the MR2 to
MR0 bits in the TA1MR and TA2MR registers to “000b” when using Timer
Mode.
• Event Counter Mode
The Pulse Output Function cannot be used and external input signals cannot be counted.
Two-phase Pulse Signal of Timer A2 cannot be used. Set the MR2 to MR0 bits in the
TA1MR and TA2MR registers to “000b” when using the Event Counter Mode.
• One-shot Timer Mode The Pulse Output Function cannot be used and count start by the external trigger cannot
be counted. Set the MR1 to MR0 bits in the TA1MR and TA2MR registers to “00b”
when using the One-shot Timer Mode.
• Pulse Width
PWM pulse cannot be outputted.
Modulation Mode
Figure 15.3 shows a Timer A Block Diagram. Figures 15.4 to 15.7 show registers related to Timer A. Timer A
supports the following four modes. Except in event counter mode, Timers A0 to A4 all have the same function. Use
the TMOD1 to TMOD0 bits in the TAiMR register (i = 0 to 4) to select the desired mode.
• Timer Mode:
The timer counts an internal count source.
• Event Counter Mode:
The timer counts pulses from an external device or overflows and
underflows of other timers.
• One-shot Timer Mode:
The timer outputs a pulse only once before it reaches the minimum
count “0000h”.
• Pulse Width Modulation (PWM) Mode: The timer outputs pulses in a given width successively.
Select clock
High-Order Bits of Data Bus
· Timer
:TMOD1 to TMOD0=00, MR2=0
:TMOD1 to TMOD0=10
· Pulse Width Modulation :TMOD1 to TMOD0=11
TMOD1 to TMOD0,
MR2
Select Count Source · One-Shot Timer
f1 or f2
f8
f32
fC32
00
01
10
11
Low-Order Bits of Data Bus
8 low-order
bits
· Timer (gate function): TMOD1 to TMOD0=00,
MR2=1
8 highorder bits
Reload Register
TCK1 to TCK0
· Event counter :TMOD1 to TMOD0=01
Polarity
Selector
TAiIN
TAiS
TB2 Overflow (1)
TAj Overflow (1)
TAk Overflow (1)
00
01
10
11
To external
trigger circuit
TAiTGH to TAiTGL
TAiUD
Decrement
00
01
11
Counter
Increment / decrement
Always decrement except
in event counter mode
01
TMOD1 to TMOD0
0
1
Pulse Output
MR2
TAiOUT
Toggle Flip Flop
i=0 to 4
j=i-1, however, j=4 if i=0
k=i+1, however, k=0 if i=4
NOTES:
1. Overflow or underflow
TCK1 to TCK0, TMOD1 to TMOC0, MR2 to MR1 : Bits in TAiMR register
TAiTGH to TAiTGL : Bits in ONSF register if i=0 or bits in TRGSR register if i=1 to 4
TAiS : Bits in the TABSR register
TAiUD : Bits in the UDF register
Figure 15.3
Timer A Block Diagram
Rev.2.41 Jan 10, 2006
REJ09B0185-0241
Page 139 of 390
TAi
Timer A0
Timer A1
Timer A2
Timer A3
Timer A4
Addresses
0387h - 0386h
0389h - 0388h
038Bh - 038Ah
038Dh - 038Ch
038Fh - 038Eh
TAj
Timer A4
Timer A0
Timer A1
Timer A2
Timer A3
TAk
Timer A1
Timer A2
Timer A3
Timer A4
Timer A0
M16C/62P Group (M16C/62P, M16C/62PT)
15. Timers
Timer Ai Mode Register (i=0 to 4)
b7 b6 b5 b4 b3 b2 b1 b0
Address
Symbol
0396h to 039Ah
TA0MR to TA4MR
Bit Name
Bit Symbol
Operation Mode Select Bit
TMOD0
TMOD1
MR0
MR1
MR2
MR3
TCK0
TCK1
b1 b0
0 0 : Timer mode
0 1 : Event counter mode
1 0 : One-shot timer mode
1 1 : Pulse w idth modulation (PWM) mode
—
Function varies w ith each operation mode
Count Source Select Bit
Timer Ai Register (i= 0 to 4) (1)
(b15)
b7
After Reset
00h
Function
(b8)
b0 b7
b0
Function varies w ith each operation mode
Symbol
Address
After Reset
TA0
TA1
TA2
TA3
TA4
0387h, 0386h
Indeterminate
0389h, 0388h
038Bh, 038Ah
038Dh, 038Ch
038Fh, 038Eh
Indeterminate
Indeterminate
Indeterminate
Indeterminate
Mode
Setting Range
Function
0000h to FFFFh
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
Timer Mode
Divide the count source by n + 1 w here n = set
value
Event Counter
Mode
Divide the count source by FFFFh – n + 1 w here 0000h to FFFFh
n = set value w hen counting up or by n + 1 w hen
counting dow n (5)
RW
One-Shot Timer
Mode
Divide the count source by n w here n = set value 0000h to FFFFh(2, 4)
and factor the timer to stop
WO
Pulse Width
Modulation Mode
(16-Bit PWM)
0000h to FFFEh(3, 4)
Modify the pulse w idth as follow s:
PWM period: (216 – 1) / fj
High level PWM pulse w idth: n / fj
w here n = set value, fj = count source frequency
WO
Pulse Width
Modulation Mode
(8-Bit PWM)
Modify the pulse w idth as follow s:
PWM period: (28 – 1) × (m + 1)/ fj
High level PWM pulse w idth: (m + 1)n / fj
w here n = high-order address set value,
m = low -order address set value, fj = count
source frequency
00h to FEh
(High-order address)
00h to FFh
(Low -order address)
RW
WO
(3, 4)
NOTES :
1. The register must be accessed in 16-bit units.
2. If the TAi register is set to “0000h”, the counter does not w ork and timer Ai interrupt requests are not generated
either. Furthermore, if “pulse output” is selected, no pulses are output from the TAiOUT pin.
3. If the TAi register is set to “0000h”, the pulse w idth modulator does not w ork, the output level on the TAiOUT pin
remains low , and timer Ai interrupt requests are not generated either. The same applies w hen the 8 high-order bits
of the timer TAi register are set to “00h” w hile operating as an 8-bit pulse w idth modulator.
4. Use the MOV instruction to w rite to the TAi register.
5. The timer counts pulses from an external device or overflow s or underflow s in other timers.
Figure 15.4
TAiMR and TAi Registers
Rev.2.41 Jan 10, 2006
REJ09B0185-0241
Page 140 of 390
M16C/62P Group (M16C/62P, M16C/62PT)
15. Timers
Count Start Flag
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
TABSR
Bit Symbol
Timer
TA0S
Timer
TA1S
TA2S
Timer
Timer
TA3S
TA4S
Timer
Timer
TB0S
TB1S
Timer
TB2S
Timer
Address
0380h
Bit Name
A0 Count Start Flag
A1 Count Start Flag
A2 Count Start Flag
A3 Count Start Flag
A4 Count Start Flag
B0 Count Start Flag
B1 Count Start Flag
B2 Count Start Flag
After Reset
00h
Function
0 : Stops counting
1 : Starts counting
RW
RW
RW
RW
RW
RW
RW
RW
RW
Up/Down Flag (1)
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
Address
0384h
UDF
Bit Name
Bit Symbol
Timer A0 Up/Dow n Flag
TA0UD
Timer A1 Up/Dow n Flag
TA1UD
Timer A2 Up/Dow n Flag
TA2UD
TA3UD
Timer A3 Up/Dow n Flag
TA4UD
Timer A4 Up/Dow n Flag
Timer A2 Tw o-Phase Pulse
TA2P
Signal Processing Select Bit
TA3P
Timer A3 Tw o-Phase Pulse
Signal Processing Select Bit
TA4P
Timer A4 Tw o-Phase Pulse
Signal Processing Select Bit
After Reset
00h
Function
0 : Dow n count
1 : Up count
Enabled by setting the MR2 bit in the TAiMR
register to “0” (=sw itching source in UDF
register) during event counter mode.
0 : tw o-phase pulse signal processing
disabled
1 : tw o-phase pulse signal processing
enabled (2, 3)
RW
RW
RW
RW
RW
RW
WO
WO
WO
NOTES :
1. Use MOV instruction to w rite to this register.
2. Make sure the port direction bits for the TA2IN to TA4IN and TA2OUT to TA4OUT pins are set to “0” (input mode).
3. When not using the tw o-phase pulse signal processing function, set the bit corresponding to Timer A2 to Timer A4 to
“0”.
Figure 15.5
TABSR and UDF Registers
Rev.2.41 Jan 10, 2006
REJ09B0185-0241
Page 141 of 390
M16C/62P Group (M16C/62P, M16C/62PT)
15. Timers
One-Shot Start Flag
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
ONSF
Bit Symbol
TA0OS
TA1OS
TA2OS
TA3OS
TA4OS
TAZIE
TA0TGL
TA0TGH
Address
0382h
After Reset
00h
Bit Name
Timer A0 One-Shot Start Flag
Timer A1 One-Shot Start Flag
Timer A2 One-Shot Start Flag
Timer A3 One-Shot Start Flag
Timer A4 One-Shot Start Flag
Z-Phase Input Enable Bit
Function
RW
The timer starts counting by setting this bit to “1”
w hile the TMOD1 to TMOD0 bits in the TAiMR
register i = 0 to 4) = 10b (= one-shot timer mode)
and the MR2 bit in the TAiMR register = 0 (=TAiOS
bit enabled). When read, its content is 0”.
RW
RW
RW
RW
RW
0 : Z-phase input disabled
1 : Z-phase input enabled
RW
Timer A0 Event/Trigger Select b7 b6
0 0 : Input on TA0IN is selected (1)
Bit
0 1 : TB2 is selected (2)
1 0 : TA4 is selected (2)
1 1 : TA1 is selected (2)
RW
RW
NOTES :
1. Make sure the PD7_1 bit in the PD7 register is set to “0” (= input mode).
2. Overflow or underflow .
Trigger Select Register
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
TRGSR
Address
0383h
Bit Symbol
TA1TGL
Bit Name
Timer A1 Event/Trigger Select Bit
Timer A2 Event/Trigger Select Bit
Timer A3 Event/Trigger Select Bit
b5 b4
0 0 : Input on TA3IN is selected (1)
0 1 : TB2 is selected (2)
1 0 : TA2 is selected (2)
1 1 : TA4 is selected (2)
TA3TGH
TA4TGL
b3 b2
0 0 : Input on TA2IN is selected (1)
0 1 : TB2 is selected (2)
1 0 : TA1 is selected (2)
1 1 : TA3 is selected (2)
TA2TGH
TA3TGL
Function
b1 b0
0 0 : Input on TA1IN is selected (1)
0 1 : TB2 is selected (2)
1 0 : TA0 is selected (2)
1 1 : TA2 is selected (2)
TA1TGH
TA2TGL
After Reset
00h
Timer A4 Event/Trigger Select Bit
TA4TGH
b7 b6
0 0 : Input on TA4IN is selected (1)
0 1 : TB2 is selected (2)
1 0 : TA3 is selected (2)
1 1 : TA0 is selected (2)
NOTES :
1. Make sure the port direction bits for the TA1IN to TA4IN pins are set to “0” (= input mode).
2. Overflow or underflow .
Figure 15.6
ONSF, RGSR Registers
Rev.2.41 Jan 10, 2006
REJ09B0185-0241
Page 142 of 390
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M16C/62P Group (M16C/62P, M16C/62PT)
15. Timers
Clock Prescaler Reset Flag
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
CPSRF
Bit Symbol
—
(b6-b0)
Address
0381h
After Reset
0XXXXXXXb
Bit Name
Function
Nothing is assigned. When w rite, set to “0”.
When read, their contents are indeterminate.
Clock Prescaler Reset Flag
CPSR
Figure 15.7
CPSRF Register
Rev.2.41 Jan 10, 2006
REJ09B0185-0241
Page 143 of 390
Setting this bit to “1” initializes the
prescaler for the timekeeping clock.
(When read, its content is “0”.)
RW
—
RW
M16C/62P Group (M16C/62P, M16C/62PT)
15.1.1
15. Timers
Timer Mode
In timer mode, the timer counts a count source generated internally (see Table 15.1). Figure 15.8 shows TAiMR
Register in Timer Mode.
Table 15.1
Specifications in Timer Mode
Item
Count source
Count Operation
Divide Ratio
Count Start Condition
Count Stop Condition
Interrupt Request
Generation Timing
TAiIN Pin Function
TAiOUT Pin Function
Read from Timer
Write to Timer
Select Function
Rev.2.41 Jan 10, 2006
REJ09B0185-0241
Specification
f1, f2, f8, f32, fC32
• Down-count
• When the timer underflows, it reloads the reload register contents and
continues counting
1/(n+1) n: set value of TAi register (i= 0 to 4) 0000h to FFFFh
Set TAiS bit in TABSR register to “1” (= start counting)
Set TAiS bit to “0” (= stop counting)
Timer underflow
I/O port or gate input
I/O port or pulse output
Count value can be read by reading TAi register
• When not counting and until the 1st count source is input after counting start
Value written to TAi register is written to both reload register and counter
• When counting (after 1st count source input)
Value written to TAi register is written to only reload register
(Transferred to counter when reloaded next)
• Gate function
Counting can be started and stopped by an input signal to TAiIN pin
• Pulse output function
Whenever the timer underflows, the output polarity of TAiOUT pin is inverted.
When TAiS bit is set to “0” (stop counting), the pin outputs a low.
Page 144 of 390
M16C/62P Group (M16C/62P, M16C/62PT)
15. Timers
Timer Ai Mode Register (i=0 to 4)
b7 b6 b5 b4 b3 b2 b1 b0
0
0 0
Symbol
Address
0396h to 039Ah
TA0MR to TA4MR
Bit Name
Bit Symbol
TMOD0
Operation Mode Select Bit
TMOD1
Pulse Output Function Select Bit
MR0
Gate Function Select Bit
MR2
TCK0
Set to “0” in timer mode
Count Source Select Bit
TCK1
NOTES :
1. TA0OUT pin is N-channel open drain output.
2. The port direction bit for the TAiIN pin is set to “0” (= input mode).
3. Selected by PCLK0 bit in the PCLKR register.
Figure 15.8
TAiMR Register in Timer Mode
Rev.2.41 Jan 10, 2006
REJ09B0185-0241
b1 b0
0 0 : Timer mode
0 : Pulse is not output
(TAiOUT pin is a normal port pin)
1 : Pulse is output (1)
(TAiOUT pin is a pulse output pin)
Page 145 of 390
RW
RW
RW
RW
b4 b3
0 0 : Gate function not available
0 1 : (TAiIN pin functions as I/O port)
1 0 : Counts w hile input on the TAiIN
pin is low (2)
1 1 : Counts w hile input on the TAiIN
pin is high (2)
MR1
MR3
After Reset
00h
Function
RW
RW
RW
b7 b6
0 0 : f1 or f2 (3)
0 1 : f8
1 0 : f32
1 1 : fC32
RW
RW
M16C/62P Group (M16C/62P, M16C/62PT)
15.1.2
15. Timers
Event Counter Mode
In event counter mode, the timer counts pulses from an external device or overflows and underflows of other
timers. Timer A2, A3 and A4 can count two-phase external signals. Table 15.2 lists Specifications in Event Counter
Mode (when not processing two-phase pulse signal). Table 15.3 lists Specifications in Event Counter Mode (when
processing two-phase pulse signal with Timer A2, A3 and A4). Figure 15.9 shows TAiMR Register in Event
Counter Mode (when not using two-phase pulse signal processing). Figure 15.10 shows TA2MR to TA4MR
Registers in Event Counter Mode (when using two-phase pulse signal processing with Timer A2, A3 and A4).
Table 15.2
Specifications in Event Counter Mode (when not processing two-phase pulse signal)
Item
Count Source
Count Operation
Divided Ratio
Count Start Condition
Count Stop Condition
Interrupt Request
Generation Timing
TAiIN Pin Function
TAiOUT Pin Function
Read from Timer
Write to Timer
Select Function
Rev.2.41 Jan 10, 2006
REJ09B0185-0241
Specification
• External signals input to TAiIN pin (i=0 to 4) (effective edge can be selected in
program)
• Timer B2 overflows or underflows,
Timer Aj (j=i-1, except j=4 if i=0) overflows or underflows,
Timer Ak (k=i+1, except k=0 if i=4) overflows or underflows
• Up-count or down-count can be selected by external signal or program
• When the timer overflows or underflows, it reloads the reload register contents
and continues counting. When operating in free-running mode, the timer
continues counting without reloading.
1/ (FFFFh - n + 1) for up-count
1/ (n + 1) for down-count n : set value of TAi register 0000h to FFFFh
Set TAiS bit in the TABSR register to “1” (= start counting)
Set TAiS bit to “0” (= stop counting)
Timer overflow or underflow
I/O port or count source input
I/O port, pulse output, or up/down-count select input
Count value can be read by reading TAi register
• When not counting and until the 1st count source is input after counting start
Value written to TAi register is written to both reload register and counter
• When counting (after 1st count source input)
Value written to TAi register is written to only reload register
(Transferred to counter when reloaded next)
• Free-run count function
Even when the timer overflows or underflows, the reload register content is
not reloaded to it
• Pulse output function
Whenever the timer underflows or underflows, the output polarity of TAiOUT
pin is inverted. When TAiS bit is set to “0” (stop counting), the pin outputs a
low.
Page 146 of 390
M16C/62P Group (M16C/62P, M16C/62PT)
15. Timers
Timer Ai Mode Register (i=0 to 4)
(when not using two-phase pulse signal processing)
b7 b6 b5 b4 b3 b2 b1 b0
0
0 1
Address
Symbol
0396h to 039Ah
TA0MR to TA4MR
Bit Name
Bit Symbol
TMOD0
Operation Mode Select Bit
TMOD1
Pulse Output Function Select Bit
MR2
MR3
TCK0
b1 b0
0 1 : Event counter mode (1)
RW
RW
RW
0 : Pulse is not output
(TAiOUT pin functions as I/O port)
1 : Pulse is output (2)
(TAiOUT pin functions as pulse output pin)
RW
Count Polarity Select Bit (3)
0 : Counts falling edge of external signal
1 : Counts rising edge of external signal
RW
Up/Dow n Sw itching Factor
Select Bit
0 : UDF register
1 : Input signal to TAiOUT pin (4)
RW
MR0
MR1
After Reset
00h
Function
Set to “0” in event counter mode
Count Operation Type Select Bit 0 : Reload type
1 : Free-run type
RW
RW
Can be “0” or “1” w hen not using tw o-phase pulse signal processing
TCK1
RW
NOTES :
1. During event counter mode, the count source can be selected using the ONSF and TRGSR registers.
2. TA0OUT pin is N-channel open drain output.
3. Effective w hen the TAiTGH and TAiTGL bits in the ONSF or TRGSR register are “00b” (TAiIN pin input).
4. Count dow n w hen input on TAiOUT pin is low or count up w hen input on that pin is high. The port direction bit for
TAiOUT pin is set to “0” (= input mode).
Figure 15.9
TAiMR Register in Event Counter Mode (when not using two-phase pulse signal
processing)
Rev.2.41 Jan 10, 2006
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M16C/62P Group (M16C/62P, M16C/62PT)
Table 15.3
15. Timers
Specifications in Event Counter Mode (when processing two-phase pulse signal with
Timer A2, A3 and A4)
Item
Count Source
Count Operation
Divide Ratio
Count Start Condition
Count Stop Condition
Interrupt Request
Generation Timing
TA2IN Pin Function
TA2OUT Pin Function
Read from Timer
Write to Timer
Select Function (1)
Specification
• Two-phase pulse signals input to TAiIN or TAiOUT pins (i=2 to 4)
• Up-count or down-count can be selected by two-phase pulse signal
• When the timer overflows or underflows, it reloads the reload register contents
and continues counting. When operating in free-running mode, the timer
continues counting without reloading.
1/ (FFFFh - n + 1) for up-count
1/ (n + 1) for down-count n : set value of TAi register 0000h to FFFFh
Set TAiS bit of TABSR register to “1” (= start counting)
Set TAiS bit to “0” (= stop counting)
Timer overflow or underflow
Two-phase pulse input
Two-phase pulse input
Count value can be read by reading Timer A2, A3 or A4 register
• When not counting and until the 1st count source is input after counting start
Value written to TAi register is written to both reload register and counter
• When counting (after 1st count source input)
Value written to TAi register is written to reload register
(Transferred to counter when reloaded next)
• Normal processing operation (Timer A2 and Timer A3)
The timer counts up rising edges or counts down falling edges on TAjIN pin
when input signals on TAjOUT pin is “H”.
TAjOUT
TAjIN
(j=2, 3)
Upcount
Upcount
Upcount
Downcount
Downcount
Downcount
• Multiply-by-4 processing operation (Timer A3 and Timer A4)
If the phase relationship is such that TAkIN(k=3, 4) pin goes “H” when the
input signal on TAkOUT pin is “H,” the timer counts up rising and falling edges
on TAkOUT and TAkIN pins. If the phase relationship is such that TAkIN pin
goes “L” when the input signal on TAkOUT pin is “H,” the timer counts down
rising and falling edges on TAkOUT and TAkIN pins.
TAkOUT
Count up all edges
Count down all edges
TAkIN
(k=3, 4)
Count up all edges
Count down all edges
• Counter initialization by Z-phase input (Timer A3)
The timer count value is initialized to 0 by Z-phase input.
NOTES:
1. Only Timer A3 is selectable. Timer A2 is fixed to normal processing operation, and Timer A4 is fixed
to multiply-by-4 processing operation.
Rev.2.41 Jan 10, 2006
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M16C/62P Group (M16C/62P, M16C/62PT)
15. Timers
Timer A2 Mode Register (i=2 to 4)
(when using two-phase pulse signal processing)
b7 b6 b5 b4 b3 b2 b1 b0
0 1 0 0 0 1
Symbol
Address
0398h to 039Ah
TA2MR to TA4MR
Bit Name
Bit Symbol
Operation Mode Select Bit
TMOD0
After Reset
00h
Function
b1 b0
0 1 : Event counter mode
TMOD1
MR0
MR1
MR2
MR3
TCK0
TCK1
RW
RW
RW
To use tw o-phase pulse signal processing, set this bit to “0”.
To use tw o-phase pulse signal processing, set this bit to “0”.
To use tw o-phase pulse signal processing, set this bit to “1”.
To use tw o-phase pulse signal processing, set this bit to “0”.
Count Operation Type Select Bit
0 : Reload type
1 : Free-run type
Tw o-phase pulse signal processing 0 : Normal processing operation
1 : Multiply-by-4 processing operation
Operation Type Select Bit (1, 2)
RW
RW
RW
RW
RW
RW
NOTES :
1. TCK1 bit is valid for Timer A3 mode register. No matter how this bit is set, Timer A2 and A4 alw ays operate in normal
processing mode and x4 processing mode, respectively.
2. If tw o-phase pulse signal processing is desired, follow ing register settings are required:
• Set the TAiP bit in the UDF register to “1” (tw o-phase pulse signal processing function enabled).
• Set the TAiTGH and TAiTGL bits in the TRGSR register to “00b” (TAiIN pin input).
• Set the port direction bits for TAiIN and TAiOUT to “0” (input mode).
Figure 15.10
TA2MR to TA4MR Registers in Event Counter Mode (when using two-phase pulse
signal processing with Timer A2, A3 and A4)
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M16C/62P Group (M16C/62P, M16C/62PT)
15.1.2.1
15. Timers
Counter Initialization by Two-Phase Pulse Signal Processing
This function initializes the timer count value to “0” by Z-phase (counter initialization) input during two-phase
pulse signal processing.
This function can only be used in Timer A3 event counter mode during two-phase pulse signal processing, freerunning type, x4 processing, with Z-phase entered from the ZP pin.
Counter initialization by Z-phase input is enabled by writing “0000h” to the TA3 register and setting the TAZIE
bit in the ONSF register to “1” (= Z-phase input enabled).
Counter initialization is accomplished by detecting Z-phase input edge. The active edge can be chosen to be the
rising or falling edge by using the POL bit in the INT2IC register. The Z-phase pulse width applied to the INT2
pin must be equal to or greater than one clock cycle of Timer A3 count source.
The counter is initialized at the next count timing after recognizing Z-phase input. Figure 15.11 shows the
Relationship Between the Two-Phase Pulse (A phase and B phase) and the Z-Phase.
If Timer A3 overflow or underflow coincides with the counter initialization by Z-phase input, a Timer A3
interrupt request is generated twice in succession. Do not use Timer A3 interrupt when using this function.
TA3OUT
(A phase)
TA3IN
(B phase)
Count source
ZP (1)
Input equal to or greater than one clock cycle
of count source
m
Timer A3
m+1
1
2
3
4
5
NOTES :
1. This timing diagram is for the case where the POL bit in the INT2IC register = 1 (= rising edge).
Figure 15.11
Two-Phase Pulse (A phase and B phase) and the Z-Phase
Rev.2.41 Jan 10, 2006
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M16C/62P Group (M16C/62P, M16C/62PT)
15.1.3
15. Timers
One-shot Timer Mode
In one-shot timer mode, the timer is activated only once by one trigger (see Table 15.4). When the trigger
occurs, the timer starts up and continues operating for a given period. Figure 15.12 shows the TAiMR Register
in One-Shot Timer Mode.
Table 15.4
Specifications in One-shot Timer Mode
Item
Count Source
Count Operation
Divide Ratio
Count start Condition
Count Stop Condition
Interrupt Request
Generation Timing
TAiIN Pin Function
TAiOUT Pin Function
Read from Timer
Write to Timer
Select Function
Rev.2.41 Jan 10, 2006
REJ09B0185-0241
Specification
f1, f2, f8, f32, fC32
• Down-count
• When the counter reaches “0000h,” it stops counting after reloading a new
value
• If a trigger occurs when counting, the timer reloads a new count and restarts
counting
1/n n : set value of TAi register (i=0 to 4) 0000h to FFFFh
However, the counter does not work if the divide-by-n value is set to “0000h”.
TAiS bit in the TABSR register = 1 (start counting) and one of the following
triggers occurs.
• External trigger input from the TAiIN pin
• Timer B2 overflow or underflow,
Timer Aj (j=i-1, except j=4 if i=0) overflow or underflow,
Timer Ak (k=i+1, except k=0 if i=4) overflow or underflow
• The TAiOS bit in the ONSF register is set to “1”(= timer starts)
• When the counter is reloaded after reaching “0000h”
• TAiS bit is set to “0” (= stop counting)
When the counter reaches “0000h”
I/O port or trigger input
I/O port or pulse output
An indeterminate value is read by reading TAi register
• When not counting and until the 1st count source is input after counting start
Value written to TAi register is written to both reload register and counter
• When counting (after 1st count source input)
Value written to TAi register is written to only reload register
(Transferred to counter when reloaded next)
• Pulse output function
The timer outputs a low when not counting and a high when counting.
Page 151 of 390
M16C/62P Group (M16C/62P, M16C/62PT)
15. Timers
Timer Ai Mode Register (i=0 to 4)
b7 b6 b5 b4 b3 b2 b1 b0
0
1 0
Symbol
Address
After Reset
0396h to 039Ah
00h
TA0MR to TA4MR
Bit Name
Bit Symbol
Function
TMOD0
Operation Mode Select Bit
b1 b0
1 0 : One-shot timer mode
TMOD1
Pulse Output Function Select 0 : Pulse is not output
Bit
(TAiOUT pin functions as I/O port)
MR0
1 : Pulse is output (1)
(TAiOUT pin functions as a pulse output pin)
MR1
MR2
MR3
TCK0
TCK1
External Trigger Select
Bit (2)
0 : Falling edge of input signal to TAiIN pin (3)
1 : Rising edge of input signal to TAiIN pin (3)
Trigger Select Bit
0 : TAiOS bit is enabled
1 : Selected by TAiTGH to TAiTGL bits
Set to “0” in one-shot timer mode
Count Source Select Bit
b7 b6
0 0 : f1 or f2 (4)
0 1 : f8
1 0 : f32
1 1 : fC32
NOTES :
1. TA0OUT pin is N-channel open drain output.
2. Effective w hen the TAiTGH and TAiTGL bits in the ONSF or TRGSR register are “00b” (TAiIN pin input).
3. The port direction bit for the TAiIN pin is set to “0” (= input mode).
4. Selected by PCLK0 bit in the PCLKR register.
Figure 15.12
TAiMR Register in One-Shot Timer Mode
Rev.2.41 Jan 10, 2006
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M16C/62P Group (M16C/62P, M16C/62PT)
15.1.4
15. Timers
Pulse Width Modulation (PWM) Mode
In PWM mode, the timer outputs pulses of a given width in succession (see Table 15.5). The counter functions
as either 16-bit pulse width modulator or 8-bit pulse width modulator. Figure 15.13 shows TAiMR Register in
PWM Mode. Figures 15.14 and 15.15 show Example of 16-bit Pulse Width Modulator Operation and Example
of 8-bit Pulse Width Modulator Operation.
Table 15.5
Specifications in PWM Mode
Item
Count Source
Count Operation
16-bit PWM
8-bit PWM
Count Start Condition
Count Stop Condition
Interrupt Request
Generation Timing
TAiIN Pin Function
TAiOUT Pin Function
Read from Timer
Write to Timer
Rev.2.41 Jan 10, 2006
REJ09B0185-0241
Specification
f1, f2, f8, f32, fC32
• Down-count (operating as an 8-bit or a 16-bit pulse width modulator)
• The timer reloads a new value at a rising edge of PWM pulse and continues
counting
• The timer is not affected by a trigger that occurs during counting
• High level width n / fj
n : set value of TAi register (i=o to 4)
16
fj: count source frequency (f1, f2, f8, f32, fC32)
• Cycle time (2 -1) / fj fixed
• High level width n × (m+1) / fj n : set value of TAi register high-order address
• Cycle time (28-1) × (m+1) / fj m : set value of TAi register low-order address
• TAiS bit of TABSR register is set to “1” (= start counting)
• The TAiS bit = 1 and external trigger input from the TAiIN pin
• The TAiS bit = 1 and one of the following external triggers occurs
• Timer B2 overflow or underflow,
Timer Aj (j=i-1, except j=4 if i=0) overflow or underflow,
Timer Ak (k=i+1, except k=0 if i=4) overflow or underflow
TAiS bit is set to “0” (= stop counting)
On the falling edge of PWM pulse
I/O port or trigger input
Pulse output
An indeterminate value is read by reading TAi register
• When not counting and until the 1st count source is input after counting start
Value written to TAi register is written to both reload register and counter
• When counting (after 1st count source input)
Value written to TAi register is written to only reload register
(Transferred to counter when reloaded next)
Page 153 of 390
M16C/62P Group (M16C/62P, M16C/62PT)
15. Timers
Timer Ai Mode Register (i= 0 to 4)
b7 b6 b5 b4 b3 b2 b1 b0
1 1
Address
Symbol
0396h to 039Ah
TA0MR to TA4MR
Bit Name
Bit Symbol
TMOD0
Operation Mode Select Bit
TMOD1
Pulse Output Function
Select Bit (4)
MR0
MR1
b1 b0
1 1 : PWM mode (1)
RW
External Trigger Select
Bit (2)
0 : Falling edge of input signal to TAiIN pin (3)
1 : Rising edge of input signal to TAiIN pin (3)
RW
Trigger Select Bit
0 : Write “1” to TAiS bit in the TASF register
1 : Selected by TAiTGH to TAiTGL bits
16/8-Bit PWM Mode Select
Bit
0 : Functions as a 16-bit pulse w idth modulator
1 : Functions as an 8-bit pulse w idth modulator
Count Source Select Bit
b7 b6
TCK0
TCK1
0 0 : f1 or f2 (5)
0 1 : f8
1 0 : f32
1 1 : fC32
NOTES :
1. TA0OUT pin is N-channel open drain output.
2. Effective w hen the TAiTGH and TAiTGL bits in the ONSF or TRGSR register are “00b” (TAiIN pin input).
3. The port direction bit for the TAiIN pin is set to “0” (= input mode).
4. Set this bit to “1” (Pulse is output) to output PWM pulse.
5. Selected by PCLK0 bit in the PCLKR register.
Figure 15.13
TAiMR Register in PWM Mode
Rev.2.41 Jan 10, 2006
REJ09B0185-0241
RW
RW
RW
0 : Pulse is not output
(TAiOUT pin functions as I/O port)
1 : Pulse is output (1)
(TAiOUT pin functions as a pulse output pin)
MR2
MR3
After Reset
00h
Function
Page 154 of 390
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M16C/62P Group (M16C/62P, M16C/62PT)
15. Timers
1 / fi × (216 − 1)
Count source
“H”
Input signal to
TAiIN pin
“L”
Trigger is not generated by this signal
1 / fj × n
PWM pulse output
from TAiOUT pin
“H”
IR bit in TAiIC
register
“1”
“L”
“0”
fj : Frequency of count source
(f1, f2, f8, f32, fC32)
i = 0 to 4
Set to “0” upon accepting an interrupt request or by writing in program
NOTES :
1. n = 0000h to FFFEh.
2. This timing diagram is for the case where the TAi register is “0003h”, the TAiTGH and TAiTGL bits in the ONSF or TRGSR
register = 00b (TAiIN pin input), the MR1 bit of TAiMR register = 1 (rising edge), and the MR2 bit in the TAiMR register = 1
(trigger selected by TAiTGH and TAiTGL bits).
Figure 15.14
Example of 16-bit Pulse Width Modulator Operation
1 / fj × (m + 1) × (28 - 1)
Count source (1)
“H”
Input signal to
TAiIN pin
“L”
1 / fj × (m + 1)
Underflow signal of
8-bit prescaler (2)
“H”
“L”
1 / fj × (m + 1) × n
PWM pulse output
from TAiOUT pin
IR bit in TAiIC
register
“H”
“L”
“1”
“0”
fj : Frequency of count source
(f1, f2, f8, f32, fC32)
i = 0 to 4
Set to “0” upon accepting an interrupt request or by writing in program
NOTES :
1. The 8-bit prescaler counts the count source.
2. The 8-bit pulse width modulator counts the output from the 8-bit prescaler underflow signal.
3. m = 00h to FFh; n = 00h to FEh.
4. This timing diagram is for the case where the TAi register is “0202h”, the TAiTGH and TAiTGL bits in the ONSF or TRGSR
register = 00b (TAiIN pin input), the MR1 bit in the TAiMR register = 0 (falling edge), and the MR2 bit in the TAiMR register
= 1 (trigger selected by TAiTGH and TAiTGL bits).
Figure 15.15
Example of 8-bit Pulse Width Modulator Operation
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M16C/62P Group (M16C/62P, M16C/62PT)
15.2
15. Timers
Timer B
Note
The M16C/62P (80-pin version) and M16C/62PT (80-pin version) do not include TB1IN pin of Timer B1.
[Precautions when using TimerB2]
• Event Counter Mode
The external input signals cannot be counted. Set the TCK1 bit in the TB1MR
register to “1” when using the Event Counter Mode.
This mode cannot be used.
• Pulse Period/Pulse Width
Measurement Mode
Figure 15.16 shows a Timer B Block Diagram. Figures 15.17 and 15.18 show registers related to the Timer B.
Timer B supports the following three modes. Use the TMOD1 and TMOD0 bits in the TBiMR register (i = 0 to 5)
to select the desired mode.
• Timer Mode:
The timer counts an internal count source.
• Event Counter Mode:
The timer counts pulses from an external device or overflows or
underflows of other timers.
• Pulse Period/Pulse Width Measurement Mode:
The timer measures pulse period or pulse width of an external signal.
High-order Bits of Data Bus
Select Clock Source
Low-order Bits of Data Bus
TCK1 to TCK0
f1 or f2
f8
f32
fC32
00
00: Timer
10: Pulse Period and Pulse
Width Measurement
01
10
Counter
TCK1
1
(Note 1, 2)
Polarity Switching
and Edge Pulse
8 highorder bits
Reload Register
TMOD1 to TMOD0
11
TBj Overflow
TBiIN
8 low-order bits
01:
Event Counter
TBiS
0
Counter Reset Circuit
i=0 to 5
NOTES :
1. Overflows or underflows.
2. j=i-1, however, j=2 when i=0 j=5 when i=3
TCK1 to TCK0, TMOD1 to TMOD0 : Bits in TAiMR register
TBiS : Bits in the TABSR and the TBSR register
Figure 15.16
Timer B Block Diagram
Rev.2.41 Jan 10, 2006
REJ09B0185-0241
Page 156 of 390
TBi
Timer B0
Timer B1
Timer B2
Timer B3
Timer B4
Timer B5
Address
0391h - 0390h
0393h - 0392h
0395h - 0394h
0351h - 0350h
0353h - 0352h
0355h - 0354h
TBj
Timer B2
Timer B0
Timer B1
Timer B5
Timer B3
Timer B4
M16C/62P Group (M16C/62P, M16C/62PT)
15. Timers
Timer Bi Mode Register (i=0 to 5)
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
Address
After Reset
TB0MR to TB2MR
039Bh to 039Dh
00XX0000b
035Bh to 035Dh
TB3MR to TB5MR
Bit Name
Bit Symbol
Operation Mode Select Bit
TMOD0
00XX0000b
Function
TMOD1
MR0
MR1
—
RW
b1 b0
0 0 : Timer mode
0 1 : Event counter mode
1 0 : Pulse period measurement mode,
pulse w idth measurement mode
1 1 : Do not set to this value
RW
Function varies w ith each operation mode
RW
RW
RW
RW(1)
MR2
—(2)
MR3
TCK0
TCK1
Count Source Select Bit
Function varies w ith each operation mode
RO
RW
RW
NOTES :
1. Timer B0, Timer B3.
2. Timer B1, Timer B2, Timer B4, Timer B5.
Timer Bi Register (i=0 to 5)(1)
(b15)
b7
(b8)
b0 b7
b0
Symbol
TB0
TB1
TB2
TB3
TB4
TB5
Mode
Address
0391h, 0390h
0393h, 0392h
0395h, 0394h
0351h, 0350h
0353h, 0352h
0355h, 0354h
After Reset
Indeterminate
Indeterminate
Indeterminate
Indeterminate
Indeterminate
Indeterminate
Function
Setting Range
Timer Mode
Divide the count source by n + 1
w here n = set value
0000h to FFFFh
Event Counter Mode
Divide the count source by n + 1
w here n = set value (2)
0000h to FFFFh
Pulse Period Measurement Mode,
Pulse Width Measurement Mode
Measures a pulse period or w idth
—
NOTES :
1. The register must be accessed in 16-bit units.
2. The timer counts pulses from an external device or overflow s or underflow s of other timers.
Figure 15.17
TBiMR and TBi Registers
Rev.2.41 Jan 10, 2006
REJ09B0185-0241
Page 157 of 390
RW
RW
RW
RO
M16C/62P Group (M16C/62P, M16C/62PT)
15. Timers
Count Start Flag
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
TABSR
Bit Symbol
Timer
TA0S
Timer
TA1S
TA2S
Timer
TA3S
Timer
TA4S
Timer
Timer
TB0S
TB1S
Timer
TB2S
Timer
Address
0380h
Bit Name
A0 Count Start Flag
A1 Count Start Flag
A2 Count Start Flag
A3 Count Start Flag
A4 Count Start Flag
B0 Count Start Flag
B1 Count Start Flag
B2 Count Start Flag
After Reset
00h
Function
0 : Stops counting
1 : Starts counting
RW
RW
RW
RW
RW
RW
RW
RW
RW
Timer B3, B4, B5 Count Start Flag
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
Address
0340h
TBSR
Bit Name
Bit Symbol
—
Nothing is assigned. When w rite, set to “0”.
(b4-b0)
When read, their contents are indeterminate.
TB3S
TB4S
TB5S
Timer B3 Count Start Flag
Timer B4 Count Start Flag
Timer B5 Count Start Flag
After Reset
000XXXXXb
Function
RW
—
RW
RW
RW
0 : Stops counting
1 : Starts counting
Clock Prescaler Reset Flag
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
CPSRF
Bit Symbol
—
(b6-b0)
Address
0381h
After Reset
0XXXXXXXb
Bit Name
Function
Nothing is assigned. When w rite, set to “0”.
When read, their contents are indeterminate.
Clock Prescaler Reset Flag
CPSR
Figure 15.18
TABSR, TBSR and CPSRF Registers
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REJ09B0185-0241
Page 158 of 390
Setting this bit to “1” initializes the
prescaler for the timekeeping clock.
(When read, its content is “0”.)
RW
—
RW
M16C/62P Group (M16C/62P, M16C/62PT)
15.2.1
15. Timers
Timer Mode
In timer mode, the timer counts a count source generated internally (see Table 15.6). Figure 15.19 shows
TBiMR Register in Timer Mode.
Table 15.6
Specifications in Timer Mode
Item
Count Source
Count Operation
Divide Ratio
Count Start Condition
Count Stop Condition
Interrupt Request
Generation Timing
TBiIN Pin Function
Read from Timer
Write to Timer
Specification
f1, f2, f8, f32, fC32
• Down-count
• When the timer underflows, it reloads the reload register contents and
continues counting
1/(n+1) n: set value of TBi register (i= 0 to 5) 0000h to FFFFh
Set TBiS bit(1) to “1” (= start counting)
Set TBiS bit to “0” (= stop counting)
Timer underflow
I/O port
Count value can be read by reading TBi register
• When not counting and until the 1st count source is input after counting start
Value written to TBi register is written to both reload register and counter
• When counting (after 1st count source input)
Value written to TBi register is written to only reload register
(Transferred to counter when reloaded next)
NOTES:
1. The TB0S to TB2S bits are assigned to the bit 5 to bit 7 in the TABSR register, and the TB3S to
TB5S bits are assigned to the bit 5 to bit 7 in the TBSR register.
Timer Bi Mode Register (i= 0 to 5)
b7 b6 b5 b4 b3 b2 b1 b0
0 0
Symbol
Address
039Bh to 039Dh
TB0MR to TB2MR
035Bh to 035Dh
TB3MR to TB5MR
Bit Name
Bit Symbol
TMOD0
Operation Mode Select Bit
TMOD1
MR0
Has no effect in timer mode
Can be set to “0” or “1”
MR1
After Reset
00XX0000b
00XX0000b
Function
b1 b0
0 0 : Timer mode
TB0MR, TB3MR registers
Set to “0” in timer mode
MR2
MR3
TCK0
—
When w rite in timer mode, set to “0”.
When read in timer mode, its content is indeterminate.
RO
Count Source Select Bit
NOTES :
1. Selected by PCLK0 bit in the PCLKR register.
TBiMR Register in Timer Mode
Rev.2.41 Jan 10, 2006
REJ09B0185-0241
RW
TB1MR, TB2MR, TB4MR, TB5MR registers
Nothing is assigned. When w rite, set to “0”.
When read, its content is indeterminate
TCK1
Figure 15.19
RW
RW
RW
RW
RW
Page 159 of 390
b7 b6
0 0 : f1 or f2 (1)
0 1 : f8
1 0 : f32
1 1 : fC32
RW
RW
M16C/62P Group (M16C/62P, M16C/62PT)
15.2.2
15. Timers
Event Counter Mode
In event counter mode, the timer counts pulses from an external device or overflows and underflows of other
timers (see Table 15.7). Figure 15.20 shows TBiMR Register in Event Counter Mode.
Table 15.7
Specifications in Event Counter Mode
Item
Count Source
Count Operation
Divide Ratio
Specification
• External signals input to TBiIN pin (i=0 to 5) (effective edge can be selected in
program)
• Timer Bj overflow or underflow (j=i-1, except j=2 if i=0, j=5 if i=3)
• Down-count
• When the timer underflows, it reloads the reload register contents and
continues counting
1/(n+1) n: set value of TBi register
0000h to FFFFh
Count Start Condition
Set TBiS
Count Stop Condition
Set TBiS bit to “0” (= stop counting)
Interrupt Request
Generation Timing
TBiIN Pin Function
Timer underflow
Read from Timer
Count value can be read by reading TBi register
• When not counting and until the 1st count source is input after counting start
Value written to TBi register is written to both reload register and counter
• When counting (after 1st count source input)
Value written to TBi register is written to only reload register
(Transferred to counter when reloaded next)
Write to Timer
bit(1)
to “1” (= start counting)
Count source input
NOTES:
1. The TB0S to TB2S bits are assigned to the bit 5 to bit 7 in the TABSR register, and the TB3S to
TB5S bits are assigned to the bit 5 to bit 7 in the TBSR register.
Rev.2.41 Jan 10, 2006
REJ09B0185-0241
Page 160 of 390
M16C/62P Group (M16C/62P, M16C/62PT)
15. Timers
.
Timer Bi Mode Register (i=0 to 5)
b7 b6 b5 b4 b3 b2 b1 b0
0 1
Address
Symbol
039Bh to 039Dh
TB0MR to TB2MR
035Bh to 035Dh
TB3MR to TB5MR
Bit Name
Bit Symbol
TMOD0
Operation Mode Select Bit
TMOD1
Count Polarity Select Bit (1)
MR0
MR1
After Reset
00XX0000b
00XX0000b
Function
b1 b0
0 1 : Event counter mode
b3 b2
0 0 : Counts falling edges of external signal
0 1 : Counts rising edges of external signal
1 0 : Counts falling and rising edges
external signal
1 1 : Do not set to this value
TB0MR, TB3MR registers
Set to “0” in event counter mode
MR2
RW
RW
RW
RW
RW
RW
TB1MR, TB2MR, TB4MR, TB5MR registers
Nothing is assigned. When w rite, set to “0”.
When read, its content is indeterminate.
—
MR3
When w rite in event counter mode, set to “0”.
When read in event counter mode, its content is indeterminate.
RO
TCK0
Has no effect in event counter mode.
Can be set to “0” or “1”.
RW
Event Clock Select
TCK1
0 : Input from TBiIN pin (2)
1 : TBj overflow or underflow
(j = i – 1, how ever, j = 2 if i = 0,
j = 5 if i = 3)
RW
NOTES :
1. Effective w hen the TCK1 bit = 0 (input from TBiIN pin). If the TCK1 bit = 1 (TBj overflow or underflow ), these bits can
be set to “0” or “1”.
2. The port direction bit for the TBiIN pin must be set to “0” (= input mode).
Figure 15.20
TBiMR Register in Event Counter Mode
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Page 161 of 390
M16C/62P Group (M16C/62P, M16C/62PT)
15.2.3
15. Timers
Pulse Period and Pulse Width Measurement Mode
In pulse period and pulse width measurement mode, the timer measures pulse period or pulse width of an
external signal (see Table 15.8). Figure 15.21 shows TBiMR Register in Pulse Period and Pulse Width
Measurement Mode. Figure 15.22 shows the Operation Timing when Measuring a Pulse Period. Figure 15.23
shows the Operation Timing when Measuring a Pulse Width.
Table 15.8
Specifications in Pulse Period and Pulse Width Measurement Mode
Item
Count Source
Count Operation
Count Start Condition
Count Stop Condition
Interrupt Request
Generation Timing
TBiIN Pin Function
Read from Timer
Write to Timer
Specification
f1, f2, f8, f32, fC32
• Up-count
• Counter value is transferred to reload register at an effective edge of
measurement pulse. The counter value is set to “0000h” to continue counting.
Set TBiS (i=0 to 5) bit (3) to “1” (= start counting)
Set TBiS bit to “0” (= stop counting)
• When an effective edge of measurement pulse is input (1)
• Timer overflow. When an overflow occurs, MR3 bit in the TBiMR register is set
to “1” (overflowed) simultaneously. MR3 bit is set to “0” (no overflow) by
writing to TBiMR register at the next count timing or later after MR3 bit was set
to “1”. At this time, make sure TBiS bit is set to “1” (start counting).
Measurement pulse input
Contents of the reload register (measurement result) can be read by reading TBi
register (2)
Value written to TBi register is written to neither reload register nor counter
NOTES:
1. Interrupt request is not generated when the first effective edge is input after the timer started
counting.
2. Value read from TBi register is indeterminate until the second valid edge is input after the timer
starts counting.
3. The TB0S to TB2S bits are assigned to the bit 5 to bit 7 in the TABSR register, and the TB3S to
TB5S bits are assigned to the bit 5 to bit 7 in the TBSR register.
Rev.2.41 Jan 10, 2006
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Page 162 of 390
M16C/62P Group (M16C/62P, M16C/62PT)
15. Timers
Timer Bi Mode Register (i=0 to 5)
b7 b6 b5 b4 b3 b2 b1 b0
1 0
Symbol
Address
TB0MR to TB2MR
039Bh to 039Dh
035Bh to 035Dh
TB3MR to TB5MR
Bit Name
Bit Symbol
Operation Mode Select Bit
TMOD0
After Reset
00XX0000b
00XX0000b
Function
b1 b0
1 0 : Pulse period / pulse w idth measurement
mode
TMOD1
Measurement Mode Select
Bit
MR0
MR1
MR3
TCK0
0 0 : Pulse period measurement
(Measurement betw een a falling edge and
the next falling edge of measured pulse)
0 1 : Pulse period measurement
(Measurement betw een a rising edge and
the next rising edge of measured pulse)
1 0 : Pulse w idth measurement
(Measurement betw een a falling edge and
the next rising edge of measured pulse
and betw een a rising edge and the next
falling edge)
1 1 : Do not set to this value
TB1MR, TB2MR, TB4MR, TB5MR registers
Nothing is assigned. When w rite, set to “0”.
When read, its content is indeterminate.
Timer Bi Overflow Flag (1)
0 : Timer did not overflow
1 : Timer has overflow ed
Count Source Select Bit
b7 b6
TCK1
RW
b3 b2
TB0MR, TB3MR registers
Set to “0” in pulse period and pulse w idth measurement mode
MR2
RW
RW
0 0 : f1 or f2 (2)
0 1 : f8
1 0 : f32
1 1 : fC32
RW
RW
RW
—
RO
RW
RW
NOTES :
1. This flag is indeterminate after reset. When the TBiS bit = 1 (start counting), the MR3 bit is cleared to “0” (no overflow )
by w riting to the TBiMR register at the next count timing or later after the MR3 bit w as set to “1” (overflow ed). The
MR3 bit cannot be set to “1” in a program. The TB0S to TB2S bits are assigned to the bit 5 to bit 7 in the TABSR
register, and the TB3S to TB5S bits are assigned to the bit 5 to bit 7 in the TBSR register.
2. Selected by PCLK0 bit in the PCLKR register.
Figure 15.21
TBiMR Register in Pulse Period and Pulse Width Measurement Mode
Rev.2.41 Jan 10, 2006
REJ09B0185-0241
Page 163 of 390
M16C/62P Group (M16C/62P, M16C/62PT)
15. Timers
Count source
“H”
Measurement pulse
Reload register
transfer timing
“L”
Transfer
(indeterminate value)
Transfer
(measured value)
counter
(NOTE 1)
(NOTE 1)
(NOTE 2)
Timing at which counter
reaches “0000h”
“1”
TBiS bit
“0”
“1”
IR bit in TBiIC
register
“0”
“1”
MR3 bit in TBiMR
register
Set to “0” upon accepting an interrupt request or by writing in
program
“0”
The TB0S to TB2S bits are assigned to the bit 5 to bit 7 in the TABSR register, and the TB3S to TB5S bits
are assigned to the bit 5 to bit 7 in the TABSR register.
i = 0 to 5
NOTES :
1. Counter is initialized at completion of measurement.
2. Timer has overflowed.
3. This timing diagram is for the case where the MR1 to MR0 bits in the TBiMR register are “00b” (measure the
interval from falling edge to falling edge of the measurement pulse).
Figure 15.22
Operation Timing when Measuring a Pulse Period
Count source
Measurement pulse
Reload register
transfer timing
“H”
“L”
counter
Transfer
(indeterminate
value)
(NOTE 1)
Transfer
(measured value)
(NOTE 1)
Transfer
(measured
value)
(NOTE 1)
Transfer
(measured value)
(NOTE 1)
(NOTE 2)
Timing at which counter
reaches “0000h”
“1”
TBiS bit
“0”
“1”
IR bit in TBiIC
register
“0”
“1”
MR3 bit in TBiMR
register
Set to “0” upon accepting an interrupt request or by
writing in program
“0”
The TB0S to TB2S bits are assigned to the bit 5 to bit 7 in the TABSR register, and the TB3S to TB5S
bits are assigned to the bit 5 to bit 7 in the TABSR register.
i = 0 to 5
NOTES :
1. Counter is initialized at completion of measurement.
2. Timer has overflowed.
3. This timing diagram is for the case where the MR1 to MR0 bits in the TBiMR register are “10b” (measure the
interval from a falling edge to the next rising edge and the interval from a rising edge to the next falling edge of the
measurement pulse).
Figure 15.23
Operation Timing when Measuring a Pulse Width
Rev.2.41 Jan 10, 2006
REJ09B0185-0241
Page 164 of 390
M16C/62P Group (M16C/62P, M16C/62PT)
16. Three-Phase Motor Control Timer Function
16. Three-Phase Motor Control Timer Function
Note
The M16C/62P (80-pin version) and M16C/62PT (80-pin version) do not use this function.
Timers A1, A2, A4 and B2 can be used to output three-phase motor drive waveforms. Table 16.1 lists the Three-phase
Motor Control Timer Functions Specifications. Figure 16.1 shows the Three-phase Motor Control Timer Functions
Block Diagram. Also, the related registers are shown on Figure 16.2 to Figure 16.8.
Table 16.1
Three-phase Motor Control Timer Functions Specifications
Item
Three-Phase Waveform Output Pin
Forced Cutoff Input(1)
Used Timers
Output Waveform
Carrier Wave Cycle
Three-Phase PWM Output Width
Dead Time
Active Level
Positive and Negative-Phase
Concurrent Active Disable Function
Interrupt Frequency
Specification
Six pins (U, U, V, V, W, W)
Input “L” to NMI pin
Timer A4, A1, A2 (used in the one-shot timer mode)
Timer A4: U- and U-phase waveform control
Timer A1: V- and V-phase waveform control
Timer A2: W- and W-phase waveform control
Timer B2 (used in the timer mode)
Carrier wave cycle control
Dead time timer (3 eight-bit timer and shared reload register)
Dead time control
Triangular wave modulation, Sawtooth wave modification
Enable to output “H” or “L” for one cycle
Enable to set positive-phase level and negative-phase level
respectively
Triangular wave modulation: count source x (m+1) x 2
Sawtooth wave modulation: count source x (m+1)
m: Setting value of TB2 register, 0000h to FFFFh
Count source: f1, f2, f8, f32, fC32
Triangular wave modulation: count source x n x 2
Sawtooth wave modulation: count source x n
n: Setting value of TA4, TA1 and TA2 register (of TA4, TA41,
TA1, TA11, TA2 and TA21 registers when setting the INV11 bit
to “1”), 0001h to FFFFh
Count source: f1, f2, f8, f32, fC32
Count source x p, or no dead time
p: Setting value of DTT register, 01h to FFh
Count source: f1, f2, f1 divided by 2, f2 divided by 2
Enable to select “H” or “L”
Positive and negative-phases concurrent active disable function
Positive and negative-phases concurrent active detect function
For Timer B2 interrupt, select a carrier wave cycle-to-cycle basis
through 15 times carrier wave cycle-to-cycle basis
NOTES:
1. Forced cutoff with NMI input is effective when the IVPCR1 bit in the TB2SC register is set to “1”
(three-phase output forcible cutoff by NMI input enabled). If an “L” signal is applied to the NMI pin
when the IVPCR1 bit is “1,” the related pins go to a high-impedance state regardless of which
functions of those pins are being used.
Related pins
Rev.2.41 Jan 10, 2006
REJ09B0185-0241
P7_2/CLK2/TA1OUT/V, P7_3/CTS2/RTS2/TA1IN/V, P7_4/TA2OUT/W,
P7_5/TA2IN/W, P8_0/TA4OUT/U, P8_1/TA4IN/U
Page 165 of 390
M16C/62P Group (M16C/62P, M16C/62PT)
16. Three-Phase Motor Control Timer Function
INV00 to INV07: Bits in INVC0 Register
INV10 to INV15: Bits in INVC1 Register
DUi, DUBi: Bits in IDBi Register (i=0,1)
TA1S to TA4S: Bits in TABSR Register
PWCOM: Bits in TB2SC Register
INV13
ICTB2 Register n=1 to 15
Value to be written to
INV03 bit
INV00
Reload Control Signal for Timer A1
1
ICTB2 Counter
n=1 to 15
0
PWCON
Timer B2 Underflow
f1 or f2
1/2
Timer B2
(Timer Mode)
Dead Time
Timer
n = 1 to 255
Transfer Trigger(1)
Trigger
DU1
bit
TA41 Register
Reload
Trigger
INV11
Timer A4
One-Shot
Pulse
When setting the TA4S bit to “0”,
signal is set to “0”
TA1 Register
Reload Control
Signal for Timer A1
DQ
T
DQ
T
DUB1
bit
DUB0
bit
INV11
DQ
T
DQ
T
Timer A1
One-Shot
Pulse
Trigger
Reload Control
Signal for Timer A2
INV11
Timer A2
One-Shot
Pulse
V-Phase
Output Signal
V-Phase
Output Signal
Inverse
Control
U
Inverse
Control
V
DQ
T
Inverse
Control
V
Inverse
Control
W
Inverse
Control
W
Dead Time
Timer
n = 1 to 255
Trigger
W-Phase Output
Control Circuit
When setting the TA1S bit to “0”,
signal is set to “0”
DQ
T
Trigger
Timer A2 Counter
(One-Shot Timer Mode)
TQ
U-Phase
Output Signal
DQ
T
Dead Time
Timer
n = 1 to 255
V-Phase Output
Control Circuit
INV06
TA21 Register
Reload
U
Trigger
Trigger
When setting the TA1S bit to “0”,
signal is set to “0”
TA2 Register
Inverse
Control
Three-Phase
Output
Shift Register
(U Phase)
Timer A1 Counter
(One-Shot Timer Mode)
TQ
INV06
TA11 Register
Reload
Trigger
DQ
T
DU0
bit
Timer A4 Counter
TQ
INV14
U-Phase
Output Signal
Reload Control
Signal for Timer A4
(One-Shot Timer Mode)
INV02
U-phase Output
Control Circuit
Start Trigger Signal for Timers A1, A2, A4
TA4 Register
R
RESET
Timer B2
NMI
Interrupt INV05
Request Bit
Reload Register
n = 1 to 255
Trigger
INV06
Write Signal to
Timer B2
INV10
T
INV04
0
1
INV12
INV07
Write signal to INV03 bit
Circuit to set Interrupt
Generation Frequency
INV01
INV11
INV03
DQ
W-Phase
Output Signal
W-Phase
Output Signal
DQ
T
DQ
T
Switching to P8_0, P8_1 and P7_2 to P7_5 is not shown in this diagram.
NOTES:
1. Transfer trigger is generated only when the IDB0 and IDB1 registers are set and the first timer B2 underflows,
if the INV06 bit is set to “0” (triangular wave modulation).
Figure 16.1
Three-phase Motor Control Timer Functions Block Diagram
Rev.2.41 Jan 10, 2006
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M16C/62P Group (M16C/62P, M16C/62PT)
16. Three-Phase Motor Control Timer Function
Three-Phase Control Register 0 (1)
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
INVC0
Address
0348h
Bit Symbol
Bit Name
INV00
INV01
INV02
INV03
After Reset
00h
Function
RW
Interrupt Enable Output
Polarity Select Bit (3)
0 : The ICTB2 counter is incremented by one on the
rising edge of Timer A1 reload control signal
1 : The ICTB2 counter is incremented by one on the
f alling edge of Timer A1 reload control signal
RW
Interrupt Enable Output
Specification Bit (2, 3)
0 : ICTB2 counter is incremented by one when Timer B2
underf lows
1 : Selected by the INV00 bit
RW
Mode Select Bit (4, 5)
0 : No three-phase control timer functions
1 : Three-phase control timer function
RW
0 : Disables three-phase control timer output
1 : Enables three-phase control timer output
RW
Output Control Bit
(5, 6)
INV04
Positiv e and Negativ e-Phases
Concurrent Activ e Disable
Function Enable Bit
0 : Enables concurrent active output
1 : Disables concurrent active output
RW
INV05
Positiv e and Negativ e-Phases
Concurrent Activ e Output Detect
Flag (7)
0 : Not detected
1 : Detected
RW
INV06
Modulation Mode
Select (8, 9)
0 : Triangular w ave modulation mode
1 : Saw tooth w ave modulation mode
RW
Softw are Trigger Select
Transf er trigger is generated when the INV07 bit is set to “1”.
Trigger to the dead time timer is also generated when setting
the INV06 bit to “1”. Its v alue is “0” when read.
RW
INV07
NOTES :
1.
Set the INVC0 register af ter the PRC1 bit in the PRCR register is set to “1” (write enable).
Rewrite the INV00 to INV02 and INV06 bits when Timers A1, A2, A4 and B2 stop.
2.
Set the INV01 bit to “1” af ter setting the ICTB2 register.
3.
The INV00 and INV01 bits are enabled only when the INV11 bit is set to “1” (three-phase mode 1). The ICTB2 counter is incremented by
one ev ery time Timer B2 underf lows, regardless of INV00 and INV01 bit settings, when the INV11 bit is set to “0” (three-phase mode).
When setting the INV01 bit to “1”, set Timer A1 count start f lag bef ore the f irst Timer B2 underf low.
When the INV00 bit is set to “1”, the f irst interrupt is generated when Timer B2 underf lows n -1 times, if n is the v alue set in the ICTB2
counter. Subsequent interrupts are generated ev ery n times Timer B2 underf lows.
4.
Set the INV02 bit to “1” to operate the dead time timer, U-, V-and W-phase output control circuits and ICTB2 counter.
5.
When the
INVC03
bit is___
set to “1”, the pins applied to U/V/W output three-phase PWM.
__
__
The U, U , V, V, W and W pins, including pins shared with other output f unctions, are all placed in high-impedance states
when the f ollowing conditions are all met.
• The INV02 bit is set to “1” (three-phase control timer f unction)
• The INV03 bit is set to “0” (three-phase control timer output disabled)
• Direction registers of each port are set to “0” (input mode)
6.
The INV03 bit is set to “0” when the f ollowings conditions are all met.
• Reset
• A concurrent activ e state occurs while INV04 bit is set to “1”
• The INV03 bit is set to _____
“0” by program
• A signal applied to the NMI pin changes “H” to “L”
When both the INVC04 and INVC05 bits are set to “1”, the INVC03 bit is set to “0”.
7.
The INV05 bit can not be set to “1” by program. Set the INV04 bit to “0”, as well, when setting the INV05 bit to “0”.
8.
The f ollowing table describes how the INV06 bit works.
Item
INV06=0
Mode
Triangular wav e modulation mode
INV06=1
Sawtooth wav e modulation mode
Timing to Transf er f rom the IDB0
Transf erred once by generating a transf er trigger
and IDB1 Registers to Three Phase af ter setting the IDB0 and IDB1 registers
Output Shif t Register
Transf erred ev ery time a transf er trigger
is generated
Timing to Trigger the Dead Time
Timer when the INV16 Bit=0
INV13 Bit
On the f alling edge of a one-shot pulse of the timer
A1, A2 or A4
By a transf er trigger, or the f alling edge of
a one-shot pulse of the timer A1, A2 or A4
Enabled when the INV11 bit=1 and the INV06 bit=0
Disabled
Transf er trigger : Timer B2 underf lows and write to the INV07 bit, or write to the TB2 register when INV10 = 1
9.
When the INV06 bit is set to “1”, set the INV11 bit to “0” (three-phase mode 0) and the PWCON bit in the TB2SC register to “0” (reload
Timer B2 with Timer B2 underf low).
Figure 16.2
INVC0 Register
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M16C/62P Group (M16C/62P, M16C/62PT)
16. Three-Phase Motor Control Timer Function
Three-Phase Control Register 1 (1)
b7 b6 b5 b4 b3 b2 b1 b0
0
Symbol
INVC1
Address
0349h
Bit Symbol
Bit Name
After Reset
00h
Function
RW
INV10
Timer A1, A2 and A4 Start 0 : Timer B2 underflow
1 : Timer B2 underflow and w rite to Timer B2
Trigger Select Bit
RW
INV11
Timer A1-1, A2-1 and A4-1 0 : Three-phase mode 0
1 : Three-phase mode 1
Control Bit (2, 3)
RW
INV12
Dead Time Timer Count
Source Select Bit
INV13
INV14
INV15
INV16
—
(b7)
0 : f1 or f2
1 : f1 divided-by-2 or f2 divided-by-2
RW
0 : Timer A1 reload control signal is “0”
1 : Timer A1 reload control signal is “1”
RO
Output Polarity Control Bit
0 : Active “L” of an output w aveform
1 : Active “H” of an output w aveform
RW
Dead Time Disable Bit
0 : Enables dead time
1 : Disables dead time
RW
Dead Time Timer Trigger
Select Bit
0 : Falling edge of a one-shot pulse of Timer A1,
A2, A4 (5)
1 : Rising edge of the three-phase output shift
register (U-, V-, W-phase)
RW
Reserved Bit
Set to “0”
Carrier Wave Detect Bit
(4)
RW
NOTES :
1. Rew rite the INVC1 register after the PRC1 bit in the PRCR register is set to “1” (w rite enable).
The timers A1, A2, A4, and B2 must be stopped during rew rite.
2. The follow ing table lists how the INV11 bit w orks.
INV11=1
Item
INV11=0
Three-phase mode 1
Mode
Three-phase mode 0
TA11, TA21 and TA41
Registers
Not used
Used
INV00 and INV01 Bit
Disabled.
The ICTB2 counter is incremented
w henever Timer B2 underflow s
Enabled
Enabled w hen INV11=1 and INV06=0
INV13 Bit
Disabled
3. When the INV06 bit is set to “1” (saw tooth w ave modulation mode), set the INV11 bit to “0” (three-phase mode 0).
Also, w hen the INV11 bit is set to “0”, set the PWCON bit in the TB2SC register to “0” (Timer B2 is reloaded w hen
Timer B2 underflow s).
4. The INV13 bit is enabled only w hen the INV06 bit is set to “0” (Triangular w ave modulation mode) and the INV11 bit to
“1” (three-phase mode 1).
5. If the follow ing conditions are all met, set the INV16 bit to “1” (rising edge of the three-phase output shift register).
• The INV15 bit is set to “0” (dead time timer enabled)
• The Dij bit (i=U, V or W, j=0, 1) and DiBj bit alw ays have different values w hen the INV03 bit is set to “1”.
(The positive-phase and negative-phase alw ays output opposite level signals.)
If above conditions are not met, set the INV16 bit to “0” (falling edge of a one-shot pulse of Timer A1, A2, A4).
Figure 16.3
INVC1 Register
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M16C/62P Group (M16C/62P, M16C/62PT)
16. Three-Phase Motor Control Timer Function
Timer B2 Interrupt Generation Frequency Set Counter (1, 2, 3)
b7
b0
Symbol
ICTB2
Address
034Dh
Function
When the INV01 bit is set to “0” (the ICTB2 counter increments w henever
Timer B2 underflow s) and the setting value is n , Timer B2 interrupt is
generated every n th time Timer B2 underflow occurs.
When the INV01 bit is set to “1” (the INV00 bit selects count timing of the
ICTB2 counter) and setting value is n , Timer B2 interrupt is generated
every n th time Timer B2 underflow meeting the condition selected in the
INV00 bit occurs.
After Reset
Indeterminate
Setting Range
1 to 15
RW
WO
Nothing is assigned. When w rite, set to “0”.
—
NOTES :
1. Use the MOV instruction to set the ICTB2 register.
2. If the INV01 bit is set to “1”, set the ICTB2 register w hen the TB2S bit is set to “0” (Timer B2 counter stopped).
If the INV01 bit is set to “0” and the TB2S bit to “1” (Timer B2 counter start), do not set the ICTB2 register w hen Timer
B2 underflow s.
3. If the INV00 bit is set to “1”, the first interrupt is generated w hen Timer B2 underflow s n-1 times, n being the value set
in the ICTB2 counter. Subsequent interrupts are generated every n times Timer B2 underflow s.
Timer Ai, Ai-1 Register (i = 1, 2, 4) (1, 2, 3, 4, 5, 6, 7)
(b8)
b0 b7
(b15)
b7
b0
Symbol
TA1, TA2
TA4
TA11, TA21
TA41
Address
0389h to 0388h, 038Bh to 038Ah
038Fh to 038Eh
0343h to 0342h, 0345h to 0344h
0347h to 0346h
Function
If setting value is n , the timer stops w hen the n th count source is
counted after a start trigger is generated.
Positive phase changes to negative phase, and vice versa, w hen
Timers A1, A2 and A4 stop.
After Reset
Indeterminate
Indeterminate
Indeterminate
Indeterminate
Setting Range
RW
0000h to FFFFh
WO
NOTES :
1. Use a 16-bit data for read and w rite.
2 If the TAi or TAi1 register is set to “0000h”, no counters start and no Timer Ai interrupt is generated.
3 Use the MOV instruction to set the TAi and TAi1 registers.
4 When the INV15 bit in the INVC1 register is set to “0” (dead timer enabled), phase sw itches from an inactive level to
an active level w hen the dead time timer stops.
5
When the INV11 bit is set to “0” (three-phase mode 0), the value of the TAi register is transferred to the reload
register by a Timer Ai start trigger.
When the INV11 bit is set to “1” (three-phase mode 1), the value of the TAi1 register is first transferred to the
reload register by a Timer Ai start trigger. Then, the value of the TAi register is transferred by the next trigger. The
values of the TAi1 and TAi registers are transferred alternately to the reload register w ith every Timer Ai start
trigger.
6
7
Do not w rite to these registers w hen the Timer B2 underflow s.
Follow the procedure below to set the TAi1 register.
(a) Write value to the TAi1 register,
(b) Wait one Timer Ai count source cycle, and
(c) Write the same value as (a) to the TAi1 register.
Figure 16.4
ICTB2, TA1, TA2, TA4, TA11, TA21 and TA41 Registers
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M16C/62P Group (M16C/62P, M16C/62PT)
16. Three-Phase Motor Control Timer Function
Timer B2 Special Mode Register (1)
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
Address
039Eh
TB2SC
Bit Name
Bit Symbol
Timer B2 Reload Timing
PWCOM Sw itching Bit
After Reset
XXXXXX00b
Function
0 : Timer B2 underflow
1 : Timer A output at odd-numbered
occurrences (2)
____
IVPCR1
—
(b7-b2)
Three Phase Output Port NMI
Control Bit 1(3)
RW
RW
____
0 : Three-phase output forcible cutoff by NMI
input (high-impedance) disabled
____
1 : Three-phase output forcible cutoff by NMI
input (high-impedance) enabled
Nothing is assigned. When w rite, set to “0”.
When read, their contents are indeterminate.
RW
—
NOTES :
1. Write to this register after setting the PRC1 bit in the PRCR register to “1” (w rite enable).
2. If the INV11 bit is “0” (three-phase mode 0) or the INV06 bit is “1” (saw tooth w ave modulation mode), set this bit to “0” (Timer
B2 underflow ).
__
__
3. Related pins are U(P8_0/TA4OUT), U(P8_1/TA4IN), V(P7_2/CLK2/TA1OUT), V(P7_3/CTS2/RTS2/TA1IN),
___
____
W(P7_4/TA2OUT), W(P7_5/TA2IN). If a low -level signal is applied to the NMI
pin w hen the IVPCR1 bit = 1, the target pins go to a high-impedance state regardless of w hich functions of those pins are
____
being used. After forced interrupt (cutoff), input “H” to the NMI pin and set IVPCR1 bit to “0”: this forced cutoff w ill be reset.
Three-Phase Output Buffer Register i
(1)
(i=0, 1)
b7 b6 b5 b4 b3 b2 b1 b0
0 0
Symbol
IDB0, IDB1
Bit Symbol
DUi
DVi
00h
Function
Bit Name
U-Phase Output Buffer i
__
DUBi
After Reset
Address
034Ah, 034Bh
U-Phase Output Buffer i
V-Phase Output Buffer i
Write output level
0 : Active level
1 : Inactive level
RW
RW
RW
When read, the value of the three-phase shift
register is read.
RW
__
DVBi
DWi
V -Phase Output Buffer i
RW
W-Phase Output Buffer i
RW
__
DWBi
—
(b7-b6)
W-Phase Output Buffer i
Reserved Bit
RW
Set to “0”
RO
NOTES :
1. Values of the IDB0 and IDB1 registers are transferred to the three-phase output shift register by a transfer trigger.
After the transfer trigger occurs, the values w ritten in the IDB0 register determine each phase output signal first.
Then the value w ritten in the IDB1 register on the falling edge of Timers A1, A2 and A4 one-shot pulse determines
each phase output signal.
Figure 16.5
TB2SC, IDB0 and IDB1 Registers
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M16C/62P Group (M16C/62P, M16C/62PT)
16. Three-Phase Motor Control Timer Function
Dead Time Timer (1, 2)
b7
b0
Symbol
DTT
Address
034Ch
Function
If setting value is n , the timer stops w hen counting n times a count
source selected by the INV12 after start trigger occurs. Positive
or negative phase, w hich changes from inactive level to active
level, shifts w hen the dead time timer stops.
After Reset
Indeterminate
Setting Range
1 to 255
RW
WO
NOTES :
1. Use the MOV instruction to set the DTT register.
2. The DTT register is enabled w hen the INV15 bit in the INVC1 register is set to “0” (dead time enabled). No dead time
can be set w hen the INV15 bit is set to “1” (dead time disabled). The INV06 bit in the INVC0 register determines
start trigger of the DTT register.
Timer B2 Register (1)
(b15)
b7
(b8)
b0 b7
b0
Symbol
TB2
Address
0395h, 0394h
After Reset
Indeterminate
Setting Range
Function
If setting value is n , count source is divided by n +1.
Timers A1, A2 and A4 start every time an underflow occurs.
0000h to FFFFh
RW
RW
NOTES :
1. Use a 16-bit data for read and w rite.
Trigger Select Register
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
TRGSR
Address
0383h
Bit Symbol
TA1TGL
TA1TGH
TA2TGL
TA2TGH
TA3TGL
Bit Name
Set to “01b” (TB2 underflow ) before using
a V-phase output control circuit
Timer A2 Event/Trigger Select Bit
Set to “01b” (TB2 underflow ) before using
a W-phase output control circuit
Timer A3 Event/Trigger Select Bit
b5 b4
0 0 : Input on TA3IN is selected (1)
0 1 : TB2 is selected (2)
1 0 : TA2 is selected (2)
1 1 : TA4 is selected (2)
Timer A4 Event/Trigger Select Bit
NOTES :
1. Set the corresponding port direction bit to “0” (input mode).
2. Overflow or underflow .
Figure 16.6
DTT, TB2 and TRGSR Registers
Rev.2.41 Jan 10, 2006
REJ09B0185-0241
Function
Timer A1 Event/Trigger Select Bit
TA3TGH
TA4TGL
TA4TGH
After Reset
00h
Page 171 of 390
Set to “01b” (TB2 underflow ) before using
a U-phase output control circuit
RW
RW
RW
RW
RW
RW
RW
RW
RW
M16C/62P Group (M16C/62P, M16C/62PT)
16. Three-Phase Motor Control Timer Function
Count Start Flag
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
TABSR
Bit Symbol
Timer
TA0S
Timer
TA1S
TA2S
Timer
TA3S
Timer
TA4S
Timer
Timer
TB0S
TB1S
Timer
TB2S
Timer
Figure 16.7
Address
0380h
Bit Name
A0 Count Start Flag
A1 Count Start Flag
A2 Count Start Flag
A3 Count Start Flag
A4 Count Start Flag
B0 Count Start Flag
B1 Count Start Flag
B2 Count Start Flag
TABSR Register
Rev.2.41 Jan 10, 2006
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After Reset
00h
Function
0 : Stops counting
1 : Starts counting
RW
RW
RW
RW
RW
RW
RW
RW
RW
M16C/62P Group (M16C/62P, M16C/62PT)
16. Three-Phase Motor Control Timer Function
Timer Ai Mode Register (i=1, 2, 4)
b7 b6 b5 b4 b3 b2 b1 b0
0 1 0 0 1 0
Symbol
Address
TA1MR, TA2MR
0397h, 0398h
039Ah
TA4MR
Bit Name
Bit Symbol
Operation Mode Select Bit
TMOD0
TMOD1
Pulse output Function Select
MR0
Bit
MR1
MR2
MR3
TCK0
TCK1
After Reset
00h
00h
Function
Set to “10b” (one-shot timer mode) w ith the threephase motor control timer function
RW
RW
RW
Set to “0” w ith the three-phase motor control timer
function
RW
External Trigger Select Bit
Set to “0” w ith the three-phase motor control timer
function
RW
Trigger Select Bit
Set to “1” (selected by the TRGSR register) w ith
the three-phase motor control timer function
RW
Set to “0” w ith the three-phase motor control timer function
Count Source Select Bit
b7 b6
0 0 : f1 or f2 (1)
0 1 : f8
1 0 : f32
1 1 : fC32
RW
RW
RW
NOTES :
1. Selected by PCLK0 bit in the PCLKR register.
Timer B2 Mode Register
b7 b6 b5 b4 b3 b2 b1 b0
0
0 0
Symbol
Address
After Reset
TB2MR
039Dh
00XX0000b
Bit Name
Bit Symbol
Function
TMOD0
Operation Mode Select Bit
Set to “00b” (timer mode) w hen using the threephase motor control timer function
TMOD1
Disabled w hen using the three-phase motor control timer function.
MR0
When w rite, set to “0”.
When read, its content is indeterminate.
MR1
MR2
MR3
TCK0
Set to “0” w hen using three-phase motor control timer function
When w rite in three-phase motor control timer function, set to “0”.
When read in three-phase motor control timer function,
its content is indeterminate.
Count Source Select Bit
TCK1
0 0 : f1 or f2 (1)
0 1 : f8
1 0 : f32
1 1 : fC32
TA1MR, TA2MR, TA4MR and TB2MR Registers
Rev.2.41 Jan 10, 2006
REJ09B0185-0241
Page 173 of 390
RW
RW
RW
RO
b7 b6
NOTES :
1. Selected by PCLK0 bit in the PCLKR register.
Figure 16.8
RW
RW
RW
RW
RW
M16C/62P Group (M16C/62P, M16C/62PT)
16. Three-Phase Motor Control Timer Function
The three-phase motor control timer function is enabled by setting the INV02 bit in the INVC0 register to “1”. When
this function is on, timer B2 is used to control the carrier wave, and timers A4, A1 and A2 are used to control threephase PWM outputs (U, U, V, V, W and W). The dead time is controlled by a dedicated dead time timer. Figure 16.9
shows the example of Triangular Wave Modulation Operation and Figure 16.10 shows the example of Sawtooth Wave
Modulation Operation.
Triangular Waveform as a Carrier Wave
Triangular Wave
Signal Wave
TB2S Bit in
TABSR Register
Timer B2
Timer A1
Reload Control Signal (1)
Timer A4
Start Trigger Signal (1)
TA4 Register (2)
m
n
p
q
r
TA4-1 Register (2)
m
n
p
q
r
Reload Register (2)
Timer A4
One-Shot Pulse (1)
m
m
m
n
m
n
n
n
p
p
p
n
q
q
p
q
q
Rewrite the IDB0 and IDB1 registers
U-Phase Output
Signal (1)
Transfer a counter
value to the threephase shift register
U-Phase Output
Signal (1)
U-Phase
INV14 = 0
(“L” active)
U-Phase
Dead time
U-Phase
INV14 = 1
(“H” active)
Dead time
U-Phase
INV00, INV01: Bits in the INVC0 register
INV11, INV14: Bits in the INVC1 register
NOTES:
1. Internal signals. See Figure 16.1 Three-phase Motor Control Timer Functions Block Diagram.
2. Applies only when the INV11 bit is set to 1 (three-phase mode).
The above applies to INVC0 = 00XX11XXb and INVC1 = 010XXXX0b (X varies depending on each system.)
Examples of PWM output change are
(a) When INV11=1 (three-phase mode 1)
- INV01=0 and ICTB2=2h (Timer B2 interrupt is
generated with every second Timer B2 underflow) or
INV01=1, INV00=1and ICTB2=1h (Timer B2 interrupt is
generated on the falling edge of Timer A reload control
signal)
- Default value of the timer: TA41=m, TA4=m
The TA4 and TA41 registers are changed whenever
Timer B2 interrupt is generated.
First time: TA41=n, TA4:=n.
Second time: TA41=p, TA4=p.
- Default value of the IDB0 and IDB1 registers
DU0=1, DUB0=0, DU1=0, DUB1=1
They are changed to DU0=1, DUB0=0, DU1=1, DUB1=0
by the third Timer B2 interrupt.
Figure 16.9
(b) When INV11=0 (three-phase mode 0)
- INV01=0, ICTB2=1h (Timer B2 interrupt is generated
whenever Timer B2 underflows)
- Default value of the timer: TA4=m
The TA4 register is changed whenever Timer B2
interrupt is generated.
First time: TA4=m. Second time: TA4=n.
Third time: TA4=n. Fourth time: TA=p.
Fifth time: TA4=p.
- Default value of the IDB0 and IDB1 registers:
DU0=1, DUB0=0, DU1=0, DUB1=1
They are changed to DU0=1, DUB0=0, DU1=1, DUB1=0
by the sixth Timer B2 interrupt.
Triangular Wave Modulation Operation
Rev.2.41 Jan 10, 2006
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M16C/62P Group (M16C/62P, M16C/62PT)
16. Three-Phase Motor Control Timer Function
Sawtooth Waveform as a Carrier Wave
Sawtooth Wave
Signal Wave
Timer B2
Timer A4 Start
Trigger Signal(1)
Timer A4 One-Shot
Pulse(1)
Rewrite the IDB0 and IDB1
registers
Transfer the counter to the threephase shift register
U-Phase Output
Signal(1)
U-Phase Output
Signal(1)
INV14 = 0
(“L” active)
U-Phase
Dead time
U-Phase
INV14 = 1
(“H” active)
U-Phase
Dead time
U-Phase
INV14: Bits in the INVC1 register
NOTES:
1. Internal signals. See Figure 16.1 Three-phase Motor Control Timer Functions Block Diagram.
The above applies to INVC0 = 01XX110Xb and INVC1 = 010XXX00b (X varies depending on each system.)
The examples of PWM output change are
- Default value of the IDB0 and IDB1 registers: DU0=0, DUB0=1, DU1=1, DUB1=1
They are changed to DU0=1, DUB0=0, DU1=1, DUB1=1 by the timer B2 interrupt.
Figure 16.10
Sawtooth Wave Modulation Operation
Rev.2.41 Jan 10, 2006
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M16C/62P Group (M16C/62P, M16C/62PT)
17. Serial Interface
17. Serial Interface
Note
The M16C/62P (80-pin version) and M16C/62PT (80-pin version) do not include CLK2, CTS2/RTS2 and
SIN pins. Do not use the function which needs these pins.
Serial interface is configured with 5 channels: UART0 to UART2, SI/O3 and SI/O4.
17.1
UARTi (i=0 to 2)
Note
The M16C/62P (80-pin version) and M16C/62PT (80-pin version) do not include CLK2, CTS2/RTS2 pins
of UART2.
[Precautions when using UART2]
• Clock synchronous
serial I/O mode
• Clock asynchronous
serial I/O mode
(UART mode)
• Special mode 2
• Special mode 3
• Special mode 4
(SIM mode)
Cannot be used.
The CTS2/RTS2 function and the external clock of transfer clock cannot be used. Set
the CKDIR bit in the U2MR register to “0” and the CRD bit in the U2C0 register to
“1” when using the UART mode.
The slave mode cannot be used. Set the CKDIR bit register to “0” when using the
Special mode 2.
The external clock of transfer clock cannot be used. Set the CKDIR bit register to “0”
when using the Special mode 3.
The external clock of transfer clock cannot be used. Set the CKDIR bit register to “0”
when using the Special mode 4 (SIM mode).
UARTi each have an exclusive timer to generate a transfer clock, so they operate independently of each other.
Figures 17.1 to 17.3 shows the block diagram of UART0 to UART2. Figure 17.4 shows the UARTi Transmit/
Receive Unit.
UARTi has the following modes:
• Clock synchronous serial I/O mode
• Clock asynchronous serial I/O mode (UART mode).
• Special mode 1 (I2C mode)
• Special mode 2
• Special mode 3 (Bus collision detection function, IE mode) : UART0, UART1
• Special mode 4 (SIM mode) : UART2
Figures 17.5 to 17.12 show the UARTi-related registers.
Refer to tables listing each mode for register setting.
Rev.2.41 Jan 10, 2006
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M16C/62P Group (M16C/62P, M16C/62PT)
17. Serial Interface
1/2
Main clock, PLL clock, or on-chip oscillator clock
f2SIO
0
f1SIO
1
PCLK1
f1SIO or f2SIO
1/8
f8SIO
1/4
f32SIO
(UART0)
RXD polarity
reversing circuit
RXD0
1/16
Clock source selection
CLK1 to CLK0
f1SIO or f2SIO 00h
01h
f8SIO
f32SIO 10h
UART reception SMD2 toSMD0
010, 100, 101, 110
Reception
control circuit
Clock synchronous
type
001
CKDIR
Internal
Receive
clock
Transmit/
receive
unit
U0BRG
register
0
UART transmission
Transmission
010, 100, 101, 110
control circuit
Clock synchronous type
001
Clock synchronous type
(when internal clock is selected)
0
1/2
1 / (n0+1)
1/16
1
External
Transmit
clock
1
CLK0
Clock synchronous type
(when internal clock is selected)
CKPOL
CLK
polarity
reversing
circuit
Clock synchronous
CKDIR
type
(when external clock is
selected)
CTS/RTS disabled
CTS/RTS selected
CTS0 /
RTS0
RTS0
1
CRS 0
0
CTS0 from UART1
1
RCSP
CTS/RTS disabled
0
CTS0
1
VSS
Figure 17.1
CRD
UART0 Block Diagram
Rev.2.41 Jan 10, 2006
REJ09B0185-0241
Page 177 of 390
n0: Values set to the U0BRG register
PCLK1: Bit in the PCLKR register
SMD2 to SMD0, CKDIR: Bits in U0MR register
CLK1 to CLK0, CKPOL, CRD, CRS: Bits in U0C0 register
CLKMD0, CLKMD1, RCSP: Bits in UCON register
TXD
polarity
reversing
circuit
TXD0
M16C/62P Group (M16C/62P, M16C/62PT)
17. Serial Interface
1/2
Main clock, PLL clock, or on-chip oscillator clock
f2SIO
0
f1SIO
1
PCLK1
f1SIO or f2SIO
f8SIO
1/8
f32SIO
1/4
(UART1)
RXD1
RXD polarity reversing
circuit
1/16
Clock source selection
CLK1 to CLK0
CKDIR
00
Internal
01
0
f8SIO
10
f32SIO
UART reception SMD2 to SMD0
010, 100, 101, 110
Reception
control circuit
Clock synchronous
type
001
U1BRG
register
f1SIO or f2SIO
1 / (n1+1)
1/16
UART transmission
010, 100, 101, 110
Transmission
control circuit
Clock synchronous
type
001
1
External
Clock synchronous type
(when internal clock is selected)
0
1/2
Clock synchronous type
(when external clock is selected)
CKPOL
CLK1
CLK
polarity
reversing
circuit
0
1
Clock synchronous type
(when internal clock is selected)
CLKMD0
CKDIR
1
CTS1 / RTS1/
CTS0 / CLKS1
Clock output
pin select
1 CTS/RTS selected CTS/RTS disabled
CRS
1
0
CLKMD1
CTS/RTS disabled
0
0
RTS1
0
1
1
CRD
VSS
n1: Values set to the U1BRG register
PCLK1: Bit in the PCLKR register
SMD2 to SMD0, CKDIR: Bits in U1MR register
CLK1 to CLK0, CKPOL, CRD, CRS: Bits in U1C0 register
CLKMD0, CLKMD1, RCSP: Bits in UCON register
Figure 17.2
UART1 Block Diagram
Rev.2.41 Jan 10, 2006
REJ09B0185-0241
Page 178 of 390
RCSP
CTS1
CTS0 from UART0
Receive
clock
Transmit
clock
Transmit/
receive
unit
TXD
polarity
reversing
circuit
TXD1
M16C/62P Group (M16C/62P, M16C/62PT)
17. Serial Interface
1/2
Main clock, PLL clock, or on-chip oscillator clock
f2SIO
0
f1SIO
1
PCLK1
f1SIO or f2SIO
1/8
f8SIO
1/4
(UART2)
RXD2
RXD polarity reversing
circuit
Clock source selection
CLK1 to CLK0 CKDIR
00
Internal
f1SIO or f2SIO
01
0
f8SIO
10
f32SIO
1/16
U2BRG
register
UART reception SMD2 to SMD0
010, 100, 101, 110
Reception
Clock synchronous
control circuit
type
001
UART transmission
1/16 010, 100, 101, 110
Transmission
control circuit
Clock synchronous
type
001
Clock synchronous type
(when internal clock is selected)
0
1/2
1 / (n2+1)
1
External
1
Clock synchronous type
(when external clock is selected) CKDIR
Clock synchronous type
(when internal clock is selected)
CKPOL
CLK2
CLK
polarity
reversing
circuit
CTS/RTS disabled
CTS/RTS selected
CTS2 /
RTS2
RTS2
1
CRS 0
0
CTS/RTS disabled
CTS2
1
CRD
VSS
n2: Values set to the U2BRG register
PCLK1: Bit in PCLKR register
SMD2 to SMD0, CKDIR: Bits in U2MR register
CLK1 to CLK0, CKPOL, CRD, CRS: Bits in U2C0 register
CLKMD0, CLKMD1, RCSP: Bits in UCON register
NOTES :
1. UART2 is the N-channel open-drain output. Cannot be set to the CMOS output.
Figure 17.3
f32SIO
UART2 Block Diagram
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Page 179 of 390
Receive
clock
Transmit
clock
Transmit/
receive
unit
TXD
polarity
reversing
circuit (1)
TXD2
M16C/62P Group (M16C/62P, M16C/62PT)
17. Serial Interface
IOPOL
No reverse
RXDi
0
RXD data
reverse circuit
1
Reverse
Clock
synchronous type
PRYE
STPS
PAR
disabled
1SP
0
0
SP
SP
UART
(7 bits)
UART
(8 bits)
Clock
synchronous
type
0
UARTi receive register
0
PAR
1
1
1
PAR enabled
2SP
1
1
UART
SMD2 to SMD0 UART
(9 bits)
0
UART(7 bits)
0
0
0
0
0
0
0
Clock
synchronous type
UART
(8 bits)
UART
(9 bits)
D8
D7
D6
D5
D4
D3
D2
D1
D0
UiRB register
Logic reverse circuit + MSB/LSB conversion circuit
Data bus high-order bits
Data bus low-order bits
Logic reverse circuit + MSB/LSB conversion circuit
D8
D7
D6
D5
D4
D3
D2
D1
D0
UiTB register
UART
(8 bits)
UART
(9 bits)
PRYE
STPS
PAR
enabled
2SP
1
1
SP
SP
PAR
0
1SP
SMD2 to SMD0 UART
UART
(9 bits)
1
Clock
synchronous type
1
1
0
0
0
0
PAR
disabled
Clock
synchronous
type
UART
(7 bits)
UART
(8 bits)
Clock
synchronous type
i=0 to 2
SP: Stop bit
PAR: Parity bit
SMD2 to SMD0, STPS, PRYE, IOPOL, CKDIR: Bits in UiMR register
UiERE: Bit in UiC1 register
Figure 17.4
UARTi Transmit/Receive Unit
Rev.2.41 Jan 10, 2006
REJ09B0185-0241
Page 180 of 390
UARTi transmit register
UART(7 bits)
Error signal output
disable
0
IOPOL
0
Error signal
output circuit
UiERE 1
Error signal output
enable
1
No reverse
TXD data
reverse circuit
Reverse
TXDi
M16C/62P Group (M16C/62P, M16C/62PT)
17. Serial Interface
UARTi Transmit Buffer Register (i=0 to 2)(1)
(b15)
b7
(b8)
b0 b7
b0
Symbol
U0TB
U1TB
U2TB
Address
03A3h to 03A2h
03ABh to 03AAh
037Bh to 037Ah
After Reset
Indeterminate
Indeterminate
Indeterminate
RW
Function
WO
Transmit data
Nothing is assigned. When w rite, set to “0”.
When read, their contents are indeterminate.
—
NOTES :
1. Use MOV instruction to w rite to this register.
UARTi Receive Buffer Register (i=0 to 2)
(b15)
b7
(b8)
b0 b7
b0
Symbol
U0RB
U1RB
U2RB
Bit
Symbol
—
(b7-b0)
—
(b8)
—
(b10-b9)
ABT
OER
FER
PER
SUM
Address
03A7h to 03A6h
03AFh to 03AEh
037Fh to 037Eh
Function
Bit Name
—
Receive data (D7 to D0)
—
Receive data (D8)
Nothing is assigned. When w rite, set to “0”.
When read, their contents are “0”.
Arbitration Lost Detecting
Flag (2)
Overrun Error Flag
(1)
Framing Error Flag
(1, 3)
Parity Error Flag
Error Sum Flag
(1,3)
(1, 3)
After Reset
Indeterminate
Indeterminate
Indeterminate
RW
RO
RO
—
0 : Not detected
1 : Detected
RW
0 : No overrun error
1 : Overrun error found
RO
0 : No framing error
1 : Framing error found
RO
0 : No parity error
1 : Parity error found
RO
0 : No error
1 : Error found
RO
NOTES :
1. When the SMD2 to SMD0 bits in the UiMR register = 000b (serial interface disabled) or the RE bit in the UiC1 register =
0 (reception disabled), all of the SUM, PER, FER and OER bits are set to “0” (no error). The SUM bit is set to “0” (no
error) w hen all of the PER, FER and OER bits = 0 (no error).
Also, the PER and FER bits are set to “0” by reading the low er byte of the UiRB register.
2. The ABT bit is set to “0” by w riting “0” in a program. (Writing “1” has no effect.)
3. These error flags are disabled w hen the SMD2 to SMD0 bits are set to “001b” (clock synchronous serial
I/O mode) or to “010b” (I2C mode). When read, the contents are indeterminate.
Figure 17.5
UiTB and UiRB Registers
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Page 181 of 390
M16C/62P Group (M16C/62P, M16C/62PT)
17. Serial Interface
UARTi Bit Rate Generator Register (i=0 to 2) (1, 2, 3)
b7
b0
Symbol
U0BRG
U1BRG
U2BRG
Address
03A1h
03A9h
0379h
Function
Assuming that set value = n, UiBRG divides the count source by n + 1
NOTES :
1. Write to this register w hile serial interface is neither transmitting nor receiving.
2. Use MOV instruction to w rite to this register.
3. Write to this register after setting the CLK1 to CLK0 bits in the UiC0 register.
Figure 17.6
UiBRG Register
Rev.2.41 Jan 10, 2006
REJ09B0185-0241
Page 182 of 390
After Reset
Indeterminate
Indeterminate
Indeterminate
Setting Range
00h to FFh
RW
WO
M16C/62P Group (M16C/62P, M16C/62PT)
17. Serial Interface
UARTi Transmit/Receive Mode Register (i=0 to 2)
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
Address
After Reset
03A0h, 03A8h, 0378h
00h
U0MR to U2MR
Bit Symbol
Bit Name
Function
Serial I/O Mode Select Bit (2)
b2 b1 b0
0 0 0 : Serial interface disabled
SMD0
0 0 1 : Clock synchronous serial I/O mode
0 1 0 : I2C mode (3)
1 0 0 : UART mode transfer data 7 bits long
SMD1
1 0 1 : UART mode transfer data 8 bits long
1 1 0 : UART mode transfer data 9 bits long
Do not set except above
SMD2
CKDIR
STPS
IOPOL
RW
RW
Stop Bit Length Select Bit
0 : 1 stop bit
1 : 2 stop bits
RW
Odd/Even Parity Select Bit
Effective w hen PRYE = 1
0 : Odd parity
1 : Even parity
RW
0 : Parity disabled
1 : Parity enabled
RW
Parity Enable Bit
TXD, RXD I/O Polarity Reverse 0 : No reverse
Bit
1 : Reverse
UiMR Register
Rev.2.41 Jan 10, 2006
REJ09B0185-0241
RW
0 : Internal clock
1 : External clock (1)
NOTES :
1. Set the corresponding port direction bit for each CLKi pin to “0” (input mode).
2. To receive data, set the corresponding port direction bit for each RXDi pin to “0” (input mode).
3. Set the corresponding port direction bit for SCL and SDA pins to “0” (input mode).
Figure 17.7
RW
Internal/External Clock Select
Bit
PRY
PRYE
RW
Page 183 of 390
RW
M16C/62P Group (M16C/62P, M16C/62PT)
17. Serial Interface
UARTi Transmit/Receive Control Register 0 (i=0 to 2)
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
Address
After Reset
03A4h, 03ACh, 037Ch
00001000b
U0C0 to U2C0
Bit Name
Function
Bit Symbol
UiBRG Count Source
b1 b0
CLK0
0 0 : f1SIO or f2SIO is selected (5)
Select Bit (6)
0 1 : f8SIO is selected
1 0 : f32SIO is selected
CLK1
1 1 : Do not set to this value
RW
RW
RW
_____ _____
CRS
TXEPT
CTS/RTS Function
Select Bit (4)
Effective w hen CRD = 0
_____
0 : CTS function is selected (1)
_____
1 : RTS function is selected
Transmit Register Empty
Flag
0 : Data present in transmit register
(during transmission)
1 : No data present in transmit register
(transmission completed)
_____ _____
CTS/RTS Disable Bit
CRD
Data Output Select Bit (2)
NCH
CLK Polarity Select Bit
CKPOL
UFORM
Transfer Format Select
Bit (3)
RW
RO
_____ ____
0 : CTS/RTS function enabled
____ ____
1 : CTS/RTS function disabled
(P6_0, P6_4 and P7_3 can be used as I/O ports)
0 : TXDi/SDAi and SCLi pins are CMOS output
1 : TXDi/SDAi and SCLi pins are N-channel
open-drain output
RW
RW
0 : Transmit data is output at falling edge of transfer
clock and receive data is input at rising edge
1 : Transmit data is output at rising edge of transfer
clock and receive data is input at falling edge
RW
0 : LSB first
1 : MSB first
RW
NOTES :
______
1. Set the corresponding port direction bit for each CLKi pin to “0” (input mode).
2. TXD2/SDA2 and SCL2 are N-channel open-drain output. Cannot be set to the CMOS output. No NCH bit in U2C0
register is assigned. When w rite, set to “0”.
3. The UFORM bit is enabled w hen the SMD2 to SMD0 bits in the UiMR register are set to “001b” (clock synchronous
serial I/O mode), or “101b” (UART mode, 8-bit transfer data).
Set this bit to “1” w hen the SMD2 to SMD0 bits are set to “010b” (I2C mode), and to “0” w hen the SMD2 to SMD0 bits
are set to “100b” (UART mode, 7-bit transfer data) or “110b” (UART mode, 9-bit transfer data).
______ ______
4. CTS1/RTS1 can be used w hen the CLKMD1 bit in the UCON register = 0 (only CLK1 output) and the RCSP
______ ______
bit in the UCON register = 0 (CTS0/RTS0 not separated).
5. Selected by PCLK1 bit in the PCLKR register.
6. When changing the CLK1 to CLK0 bits, set the UiBRG register.
Figure 17.8
UiC0 Register
Rev.2.41 Jan 10, 2006
REJ09B0185-0241
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M16C/62P Group (M16C/62P, M16C/62PT)
17. Serial Interface
UARTi Transmit/Receive Control Register 1 (i=0, 1)
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
Address
03A5h, 03ADh
U0C1, U1C1
Bit Symbol
Bit Name
Transmit Enable Bit
TE
TI
RE
RI
—
(b5-b4)
UiLCH
UiERE
After Reset
00XX0010b
Function
0 : Transmission disabled
1 : Transmission enabled
RW
Transmit Buffer Empty Flag
0 : Data present in UiTB register
1 : No data present in UiTB register
RO
Receive Enable Bit
0 : Reception disabled
1 : Reception enabled
RW
Receive Complete Flag
0 : No data present in UiRB register
1 : Data present in UiRB register
RO
RW
Nothing is assigned. When w rite, set to “0”.
When read, these contents are indeterminate.
—
Data Logic Select Bit (1)
0 : No reverse
1 : Reverse
RW
Error Signal Output Enable Bit
0 : Output disabled
1 : Output enabled
RW
NOTES :
1. The UiLCH bit is enabled w hen the SMD2 to SMD0 bits in the UiMR register are set to “001b” (clock synchronous serial
I/O mode), “100b” (UART mode, 7-bit transfer data), or “101b” (UART mode, 8-bit transfer data).
Set this bit to “0” w hen the SMD2 to SMD0 bits are set to “010b” (I2C mode) or “110b” (UART mode, 9-bit transfer
data).
UART2 Transmit/Receive Control Register 1
b7 b6 b5 b4 b3 b2 b1 b0
Address
037Dh
Bit Name
Transmit Enable bit
After Reset
00000010b
Function
0 : Transmission disabled
1 : Transmission enabled
RW
Transmit Buffer Empty Flag
0 : Data present in U2TB register
1 : No data present in U2TB register
RO
Receive Enable Bit
0 : Reception disabled
1 : Reception enabled
RW
Receive Complete Flag
0 : No data present in U2RB register
1 : Data present in U2RB register
RO
U2IRS
UART2 Transmit Interrupt Factor
Select Bit
0 : Transmit buffer empty (TI = 1)
1 : Transmit is completed (TXEPT = 1)
RW
U2RRM
UART2 Continuous Receive Mode 0 : Continuous receive mode disabled
1 : Continuous receive mode enabled
Enable Bit
RW
Symbol
U2C1
Bit Symbol
TE
TI
RE
RI
U2LCH
U2ERE
Data Logic Select Bit
(1)
Error Signal Output Enable Bit
RW
0 : No reverse
1 : Reverse
RW
0 : Output disabled
1 : Output enabled
RW
NOTES :
1. The U2LCH bit is enabled w hen the SMD2 to SMD0 bits in the U2MR register are set to “001b” (clock synchronous
serial I/O mode), “100b” (UART mode, 7-bit transfer data), or “101b” (UART mode, 8-bit transfer data).
Set this bit to “0” w hen the SMD2 to SMD0 bits are set to “010b” (I2C mode) or “110b” (UART mode, 9-bit transfer
data).
Figure 17.9
U0C1 to U2C1 Registers
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M16C/62P Group (M16C/62P, M16C/62PT)
17. Serial Interface
UART Transmit/Receive Control Register 2
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
Address
After Reset
03B0h
X0000000b
UCON
Bit Symbol
Function
Bit Name
UART0 Transmit Interrupt Factor 0 : Transmit buffer empty (Tl = 1)
U0IRS
Select Bit
1 : Transmission completed (TXEPT = 1)
RW
U1IRS
UART1 Transmit Interrupt Factor 0 : Transmit buffer empty (Tl = 1)
Select Bit
1 : Transmission completed (TXEPT = 1)
RW
U0RRM
UART0 Continuous Receive
Mode Enable Bit
0 : Continuous receive mode disabled
1 : Continuous receive mode enable
RW
U1RRM
UART1 Continuous Receive
Mode Enable Bit
0 : Continuous receive mode disabled
1 : Continuous receive mode enabled
RW
UART1 CLK/CLKS Select Bit 0
Effective w hen CLKMD1 = 1
0 : Clock output from CLK1
1 : Clock output from CLKS1
RW
CLKMD0
CLKMD1
RCSP
—
(b7)
UART1 CLK/CLKS Select Bit 1 (1) 0 : CLK output is only CLK1
1 : Transfer clock output from multiple pins
function selected
Separate UART0
___________
CTS/RTS Bit
RW
RW
_____ _____
0 : CTS/RTS shared pin
_____ _____
1 : CTS/RTS separated
(CTS0 supplied from the P6_4 pin)
Nothing is assigned. When w rite, set to “0”.
When read, its content is indeterminate.
RW
—
NOTES :
1. When using multiple transfer clock output pins, make sure the follow ing conditions are met:
CKDIR bit in the U1MR register = 0 (internal clock)
UARTi Special Mode Register (i=0 to 2)
b7 b6 b5 b4 b3 b2 b1 b0
A ddress
A f ter Reset
Symbol
X0000000b
036Fh, 0373h, 0377h
U0SMR to U2SMR
Bit Name
Function
Bit Symbol
0 : Other than I2 C mode
I2 C Mode Select Bit
IICM
1 : I2 C mode
RW
RW
A rbitration Lost Detecting Flag
Control Bit
0 : Update per bit
1 : Update per byte
Bus Busy Flag
0 : STOP condition detected
1 : STA RT condition detected (busy)
Reserved Bit
Set to “0”
SCLL sync output enable bit
0 : Disable
1 : Enable
A BSCS
Bus Collision Detect Sampling
Clock Select Bit
0 : Rising edge of transf er clock
1 : Underf low signal of Timer A j (2)
RW
A CSE
A uto Clear Function Select Bit
of Transmit Enable Bit
0 : No auto clear f unction
1 : A uto clear at occurrence of bus collision
RW
SSS
Transmit Start Condition Select
Bit
0 : Not synchronized to RXDi
1 : Synchronized to RXDi (3)
RW
—
(b7)
Nothing is assigned.
When w rite, set to “0”. When read, its content is indeterminate.
A BC
BBS
—
(b3) (4)
LSY N(4)
RW
RW (1)
RW
—
NOTES :
1. The BBS bit is set to “0” by w riting “0” in a program (Writing “1” has no ef f ect).
2. Underf low signal of Timer A 3 in UA RT0, underf low signal of Timer A 4 in UA RT1, underf low signal of Timer A 0 in
UA RT2.
3. When a transf er begins, the SSS bit is set to “0” (Not synchronized to RXDi).
4. The f unction of the bit 3 varies depending on the product.
If the product is M3062LFGPFP or M3062LFGPGP, the bit 3 becomes the LSY N bit.
If the product is other than M3062LFGPFP and M3062LFGPGP, the bit 3 is reserved. Theref ore, set it to 0.
(The LSY N bit is an SCLL sync output enable bit.)
When the LSY N bit is set to “1” and the SCLi pin outputs an "L" level signal, the data bit, such as the P6_2 bit in the P6
register f or SCL0 pin, the P6_6 bit in the P6 register f or SCL1 pin, and the P7_1 bit in the P7 register f or SCL2 pin, is set
to “1”.
Figure 17.10
UCON and UiSMR Registers
Rev.2.41 Jan 10, 2006
REJ09B0185-0241
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M16C/62P Group (M16C/62P, M16C/62PT)
17. Serial Interface
UARTi Special Mode Register 2 (i=0 to 2)
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
Address
After Reset
X0000000b
036Eh, 0372h, 0376h
U0SMR2 to U2SMR2
Bit Name
Function
Bit Symbol
I2C Mode Select Bit 2
See Table 17.13 I2C Mode Functions
IICM2
CSC
SWC
ALS
STAC
SWC2
SDHI
—
(b7)
RW
RW
Clock-Synchronous Bit
0 : Disabled
1 : Enabled
RW
SCL Wait Output Bit
0 : Disabled
1 : Enabled
RW
SDA Output Stop Bit
0 : Disabled
1 : Enabled
RW
UARTi Initialization Bit
0 : Disabled
1 : Enabled
RW
SCL Wait Output Bit 2
0: Transfer clock
1: “L” output
RW
SDA Output Disable Bit
0: Enabled
1: Disabled (high-impedance)
RW
Nothing is assigned.
When w rite, set to “0”. When read, its content is indeterminate.
—
UARTi special mode register 3 (i=0 to 2)
b7 b6 b5 b4 b3 b2 b1 b0
After Reset
Symbol
Address
000X0X0Xb
036Dh, 0371h, 0375h
U0SMR3 to U2SMR3
Bit Name
Function
Bit Symbol
—
Nothing is assigned.
(b0)
When w rite, set to “0”. When read, its content is indeterminate.
CKPH
—
(b2)
NODC
Clock Phase Set Bit
0 : Without clock delay
1 : With clock delay
RW
—
RW
Nothing is assigned.
When w rite, set to “0”. When read, its content is indeterminate.
Clock Output Select Bit
0 : CLKi is CMOS output
1 : CLKi is N-channel open drain output
—
(b4)
Nothing is assigned.
When w rite, set to “0”. When read, its content is indeterminate.
DL0
SDAi Digital Delay
Setup Bit (1, 2)
DL1
DL2
—
RW
—
b7 b6 b5
0 0 0 : Without delay
0 0 1 : 1 to 2 cycle(s) of UiBRG count source
0 1 0 : 2 to 3 cycles of UiBRG count source
0 1 1 : 3 to 4 cycles of UiBRG count source
1 0 0 : 4 to 5 cycles of UiBRG count source
1 0 1 : 5 to 6 cycles of UiBRG count source
1 1 0 : 6 to 7 cycles of UiBRG count source
1 1 1 : 7 to 8 cycles of UiBRG count source
RW
RW
RW
NOTES :
1. The DL2 to DL0 bits are used to generate a delay in SDAi output by digital means during I2C mode. In other than I2C
mode, set these bits to “000b” (no delay).
2. The amount of delay varies w ith the load on SCLi and SDAi pins. Also, w hen using an external clock, the amount of
delay increases by about 100 ns.
Figure 17.11
UiSMR2 and UiSMR3 Registers
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M16C/62P Group (M16C/62P, M16C/62PT)
17. Serial Interface
UARTi Special Mode Register 4 (i=0 to 2)
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
Address
036Ch, 0370h, 0374h
U0SMR4 to U2SMR4
Bit Name
Bit Symbol
0 : Clear
Start Condition Generate Bit (1)
STAREQ
1 : Start
RSTAREQ
STPREQ
ACKC
SCLHI
SWC9
RW
Stop Condition Generate Bit (1)
0 : Clear
1 : Start
RW
SCL,SDA Output Select Bit
0 : Start and stop conditions not output
1 : Start and stop conditions output
RW
ACK Data Bit
0 : ACK
1 : NACK
RW
ACK Data Output Enable Bit
0 : Serial interface data output
1 : ACK data output
RW
SCL Output Stop Enable Bit
0 : Disabled
1 : Enabled
RW
SCL Wait Bit 3
0 : SCL “L” hold disabled
1 : SCL “L” hold enabled
RW
UiSMR4 Register
Rev.2.41 Jan 10, 2006
REJ09B0185-0241
RW
0 : Clear
1 : Start
NOTES :
1. Set to “0” w hen each condition is generated.
Figure 17.12
RW
Restart Condition Generate Bit (1)
STSPSEL
ACKD
After Reset
00h
Function
Page 188 of 390
M16C/62P Group (M16C/62P, M16C/62PT)
17.1.1
17. Serial Interface
Clock Synchronous Serial I/O Mode
The clock synchronous serial I/O mode uses a transfer clock to transmit and receive data. Table 17.1 lists the
Clock Synchronous Serial I/O Mode Specifications. Table 17.2 lists the Registers to Be Used and Settings in
Clock Synchronous Serial I/O Mode.
Table 17.1
Clock Synchronous Serial I/O Mode Specifications
Item
Transfer Data Format
Transfer Clock
Specification
Transfer data length: 8 bits
• CKDIR bit in the UiMR(i=0 to 2) register = 0 (internal clock) : fj/ (2(n+1))
fj = f1SIO, f2SIO, f8SIO, f32SIO n: Setting value of UiBRG register 00h to FFh
• CKDIR bit = 1 (external clock) : Input from CLKi pin
Transmission, Reception
Control
Transmission Start
Condition
Selectable from CTS function, RTS function or CTS/RTS function disable
Reception Start Condition
Interrupt Request
Generation Timing
Error Detection
Select Function
Before transmission can start, meet the following requirements (1)
• The TE bit in the UiC1 register = 1 (transmission enabled)
• The TI bit in the UiC1 register = 0 (data present in UiTB register)
• If CTS function is selected, input on the CTSi pin = L
Before reception can start, meet the following requirements (1)
• The RE bit in the UiC1 register = 1 (reception enabled)
• The TE bit in the UiC1 register = 1 (transmission enabled)
• The TI bit in the UiC1 register = 0 (data present in the UiTB register)
For transmission, one of the following conditions can be selected
• The UiIRS bit (3) = 0 (transmit buffer empty): when transferring data from the UiTB
register to the UARTi transmit register (at start of transmission)
• The UiIRS bit =1 (transfer completed): when the serial interface finished sending data
from the UARTi transmit register
For reception
• When transferring data from the UARTi receive register to the UiRB register (at
completion of reception)
Overrun error (2)
This error occurs if the serial interface started receiving the next data before reading
the UiRB register and received the 7th bit of the next data
• CLK polarity selection
Transfer data input/output can be chosen to occur synchronously with the rising or the
falling edge of the transfer clock
• LSB first, MSB first selection
Whether to start sending/receiving data beginning with bit 0 or beginning with bit 7 can
be selected
• Continuous receive mode selection
Reception is enabled immediately by reading the UiRB register
• Switching serial data logic
This function reverses the logic value of the transmit/receive data
• Transfer clock output from multiple pins selection (UART1)
The output pin can be selected in a program from two UART1 transfer clock pins that
have been set
• Separate CTS/RTS pins (UART0)
CTS0 and RTS0 are input/output from separate pins
NOTES:
1. When an external clock is selected, the conditions must be met while if the CKPOL bit in the UiC0 register = 0
(transmit data output at the falling edge and the receive data taken in at the rising edge of the transfer clock),
the external clock is in the high state; if the CKPOL bit in the UiC0 register = 1 (transmit data output at the rising
edge and the receive data taken in at the falling edge of the transfer clock), the external clock is in the low state.
2. If an overrun error occurs, the receive data of UiRB register will be indeterminate. The IR bit in the SiRIC
register does not change.
3. The U0IRS and U1IRS bits respectively are the bits 0 and 1 in the UCON register; the U2IRS bit is the bit 4 in
the U2C1 register.
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M16C/62P Group (M16C/62P, M16C/62PT)
Table 17.2
Register
UiTB (3)
UiRB (3)
UiBRG
UiMR (3)
UiC0
Registers to Be Used and Settings in Clock Synchronous Serial I/O Mode
Bit
0 to 7
0 to 7
OER
0 to 7
SMD2 to SMD0
CKDIR
IOPOL
CLK1 to CLK0
CRS
TXEPT
CRD
UiC1
UiSMR
UiSMR2
UiSMR3
UiSMR4
UCON
17. Serial Interface
Function
Set transmission data
Reception data can be read
Overrun error flag
Set a bit rate
Set to “001b”
Select the internal clock or external clock
Set to “0”
Select the count source for the UiBRG register
Select CTS or RTS to use
Transmit register empty flag
Enable or disable the CTS or RTS function
NCH
Select TXDi pin output mode (2)
CKPOL
Select the transfer clock polarity
UFORM
Select the LSB first or MSB first
TE
Set this bit to “1” to enable transmission/reception
TI
Transmit buffer empty flag
RE
Set this bit to “1” to enable reception
RI
Reception complete flag
U2IRS (1)
Select the source of UART2 transmit interrupt
U2RRM (1)
Set this bit to “1” to use continuous receive mode
UiLCH
Set this bit to “1” to use inverted data logic
UiERE
Set to “0”
0 to 7
Set to “0”
0 to 7
Set to “0”
0 to 2
Set to “0”
NODC
Select clock output mode
4 to 7
Set to “0”
0 to 7
Set to “0”
U0IRS, U1IRS
Select the source of UART0/UART1 transmit interrupt
U0RRM, U1RRM Set this bit to “1” to use continuous receive mode
CLKMD0
Select the transfer clock output pin when CLKMD1 = 1
CLKMD1
Set this bit to “1” to output UART1 transfer clock from two pins
RCSP
Set this bit to “1” to accept as input the CTS0 signal of the UART0 from
the P6_4 pin
7
Set to “0”
NOTES:
1. Set the bit 4 and bit 5 in the U0C1 and U1C1 register to “0”. The U0IRS, U1IRS, U0RRM and
U1RRM bits in the UCON register.
2. TXD2 pin is N channel open-drain output. Set the NCH bit in the U2C0 register to “0”.
3. Not all register bits are described above. Set those bits to “0” when writing to the registers in clock
synchronous serial I/O mode.
i=0 to 2
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M16C/62P Group (M16C/62P, M16C/62PT)
17. Serial Interface
Table 17.3 lists the functions of the input/output pins during clock synchronous serial I/O mode. Table 17.3
shows pin functions for the case where the multiple transfer clock output pin select function is deselected.
Table 17.4 lists the P6_4 Pin Functions during clock synchronous serial I/O mode. Note that for a period from
when the UARTi operating mode is selected to when transfer starts, the TXDi pin outputs an “H” (If the Nchannel open-drain output is selected, this pin is in a high-impedance state).
Table 17.3
Pin Functions (when not select multiple transfer clock output pin function)
Pin Name
TXDi (i = 0 to 2)
(P6_3, P6_7,
P7_0)
RXDi
(P6_2, P6_6,
P7_1)
CLKi
(P6_1, P6_5,
P7_2)
Function
Method of Selection
Serial Data Output (Outputs dummy data when performing reception only)
Serial Data Input
Transfer Clock
Output
Transfer Clock
Input
CTS Input
CTSi/RTSi
(P6_0, P6_4,
P7_3)
RTS Output
I/O Port
Table 17.4
PD6_2 bit and PD6_6 bit in the PD6 register = 0, PD7_1 bit in the
PD7 register = 0
(Can be used as an input port when performing transmission only)
CKDIR bit in the UiMR register = 0
CKDIR bit = 1
PD6_1 bit and PD6_5 bit in the PD6 register = 0, PD7_2 bit in the
PD7 register = 0
CRD bit in the UiC0 register = 0
CRS bit in the UiC0 register = 0
PD6_0 and PD6_4 bit in the PD6 register = 0, PD7_3 bit in the PD7
register = 0
CRD bit = 0
CRS bit = 1
CRD bit = 1
P6_4 Pin Functions
Pin Function
P6_4
CTS1
U1C0 Register
CRD
CRS
1
−
0
0
Bit Set Value
UCON Register
RCSP
CLKMD1
CLKMD0
0
0
−
0
0
−
PD6 Register
PD6_4
Input: 0, Output: 1
0
RTS1
0
1
0
0
−
−
CTS0 (1)
CLKS1
0
0
1
0
−
0
−
−
−
(2)
1
−
1
− : “0” or “1”
NOTES:
1. In addition to this, set the CRD bit in the U0C0 register to “0” (CTS0/RTS0 enabled) and the CRS bit
in the U0C0 register to “1” (RTS0 selected).
2. When the CLKMD1 bit = 1 and the CLKMD0 bit = 0, the following logic levels are output:
•High if the CLKPOL bit in the U1C0 register = 0
•Low if the CLKPOL bit = 1
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M16C/62P Group (M16C/62P, M16C/62PT)
17. Serial Interface
(1) Example of Transmit Timing (when internal clock is selected)
Tc
Transfer clock
TE bit in
UiC1 register
TI bit in
UiC1 register
“1”
“0”
Data is set in the UiTB register
“1”
“0”
Data is transferred from the UiTB register to the UARTi transmit register
“H”
CTSi
TCLK
“L”
Pulse stops because an “H” signal is
applied to CTSi
Pulse stops because the TE bit is set to “0”
CLKi
D0 D1 D2 D3 D4 D5 D6 D7
TXDi
TXEPT bit in
UiC0 register
“1”
IR bit in
SiTIC register
“1”
D0 D1 D2 D3 D4 D5 D6 D7
D0 D1 D2 D3 D4 D5 D6 D7
“0”
“0”
i = 0 to 2
Set to “0” by an interrupt request acknowledgement or by program
The above timing diagram applies to the case where the register bits are set as follows:
· CKDIR bit in UiMR register = 0 (internal clock)
· CRD bit in UiC0 register = 0 (CTS/RTS enabled), CRS bit = 0 (CTS selected)
· CKPOL bit in UiC0 register = 0 (transmit data output at the falling edge and receive data
taken in at the rising edge of the transfer clock)
· UiIRS bit = 0 (an interrupt request occurs when the transmit buffer becomes empty):
U0IRS bit is bit 0 in UCON register
U1IRS bit is bit 1 in UCON register
U2IRS bit is bit 4 in U2C1 register
TC = TCLK = 2(n + 1) / fj
fj: frequency of UiBRG count source
(f1SIO, f2SIO, f8SIO, f32SIO)
n: value set to UiBRG register
(2) Example of Receive Timing (when external clock is selected)
RE bit in
UiC1 register
“1”
TE bit in
UiC1 register
“1”
TI bit in
UiC1 register
“1”
“0”
Dummy data is set in the to UiTB register
“0”
“0”
Data is transferred from the UiTB register to the UARTi transmit register
“H”
RTSi
An “L” signal is applied when
the UiRB register is read
“L”
1 / fEXT
CLKi
Received data is taken in
D0 D1 D2 D3 D4 D5 D6 D7
RXDi
Data is transferred from the UARTi
RI bit in
UiC1 register
“1” receive register to the UiRB register
“0”
IR bit in
SiRIC register
“1”
D0 D1 D2 D3 D4 D5 D6
D7
D0 D1 D2 D3 D4 D5 D6
Read by the UiRB register
“0”
Set to “0” by an interrupt request acknowledgement or by program
OER flag in UiRB “1”
register
“0”
i=0 to 2
The above timing diagram applies to the case where the register bits are set
Make sure the following conditions are met when input to
as follows:
the CLKi pin before receiving data is high:
· CKDIR bit in UiMR register = 1 (external clock)
· TE bit in UiC0 register = 1 (transmit enabled)
· CRD bit in UiC0 register = 0 (CTS/RTS enabled), CRS bit = 1 (RTS selected)
· RE bit in UiC0 register = 1 (receive enabled)
· CKPOL bit in UiC0 register = 0 (transmit data output at the falling edge and receive · Write dummy data to the UiTB register
data taken in at the rising edge of the transfer clock)
fEXT: frequency of external clock
Figure 17.13
Transmit and Receive Operation
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M16C/62P Group (M16C/62P, M16C/62PT)
17.1.1.1
17. Serial Interface
Counter Measure for Communication Error Occurs
If a communication error occurs while transmitting or receiving in clock synchronous serial I/O mode, follow
the procedures below.
• Resetting the UiRB register (i=0 to 2)
(1) Set the RE bit in the UiC1 register to “0” (reception disabled)
(2) Set the SMD2 to SMD0 bits in the UiMR register to “000b” (Serial interface disabled)
(3) Set the SMD2 to SMD0 bits in the UiMR register to “001b” (Clock synchronous serial I/O mode)
(4) Set the RE bit in the UiC1 register to “1” (reception enabled)
• Resetting the UiTB register (i=0 to 2)
(1) Set the SMD2 to SMD0 bits in the UiMR register “000b” (Serial interface disabled)
(2) Set the SMD2 to SMD0 bits in the UiMR register “001b” (Clock synchronous serial I/O mode)
(3) “1” is written to RE bit in the UiC1 register (transmission enabled), regardless of the TE bit in the UiCi
register
17.1.1.2
CLK Polarity Select Function
Use the CKPOL bit in the UiC0 register (i = 0 to 2) to select the transfer clock polarity. Figure 17.14 shows the
Transfer Clock Polarity.
(1) When the CKPOL bit in the UiC0 register = 0 (transmit data output at the falling
edge and the receive data taken in at the rising edge of the transfer clock)
CLKi
(NOTE 2)
TXDi
D0
D1
D2
D3
D4
D5
D6
D7
RXDi
D0
D1
D2
D3
D4
D5
D6
D7
(2) When the CKPOL bit = 1 (transmit data output at the rising edge and the receive
data taken in at the falling edge of the transfer clock)
(NOTE 3)
CLKi
TXDi
D0
D1
D2
D3
D4
D5
D6
D7
RXDi
D0
D1
D2
D3
D4
D5
D6
D7
NOTES:
1. This applies to the case where the UFORM bit in the UiC0 register = 0
(LSB first) and the UiLCH bit in the UiC1 register = 0 (no reverse).
2. When not transferring, the CLKi pin outputs a high signal.
3. When not transferring, the CLKi pin outputs a low signal.
i = 0 to 2
Figure 17.14
Transfer Clock Polarity
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M16C/62P Group (M16C/62P, M16C/62PT)
17.1.1.3
17. Serial Interface
LSB First/MSB First Select Function
Use the UFORM bit in the UiC0 register (i = 0 to 2) to select the transfer format. Figure 17.15 shows the
Transfer Format.
(1) When the UFORM bit in the UiC0 register = 0 (LSB first)
CLKi
TXDi
D0
D1
D2
D3
D4
D5
D6
D7
RXDi
D0
D1
D2
D3
D4
D5
D6
D7
(2) When the UFORM bit = 1 (MSB first)
CLKi
TXDi
D7
D6
D5
D4
D3
D2
D1
D0
RXDi
D7
D6
D5
D4
D3
D2
D1
D0
NOTES:
1. This applies to the case where the CKPOL bit in the UiC0 register = 0
(transmit data output at the falling edge and the receive data taken in
at the rising edge of the transfer clock) and the UiLCH bit in the UiC1
register = 0 (no reverse).
i = 0 to 2
Figure 17.15
17.1.1.4
Transfer Format
Continuous Receive Mode
In continuous receive mode, receive operation becomes enable when the receive buffer register is read. It is not
necessary to write dummy data into the transmit buffer register to enable receive operation in this mode.
However, a dummy read of the receive buffer register is required when starting the operating mode.
When the UiRRM bit (i = 0 to 2) = 1 (continuous receive mode), the TI bit in the UiC1 register is set to “0”
(data present in the UiTB register) by reading the UiRB register. In this case, i.e., UiRRM bit = 1, do not write
dummy data to the UiTB register in a program. The U0RRM and U1RRM bits are the bit 2 and bit 3 in the
UCON register, respectively, and the U2RRM bit is the bit 5 in the U2C1 register.
Rev.2.41 Jan 10, 2006
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M16C/62P Group (M16C/62P, M16C/62PT)
17.1.1.5
17. Serial Interface
Serial Data Logic Switching Function
When the UiLCH bit in the UiC1 register (i = 0 to 2) = 1 (reverse), the data written to the UiTB register has its
logic reversed before being transmitted. Similarly, the received data has its logic reversed when read from the
UiRB register. Figure 17.16 shows Serial Data Logic Switching.
(1) When The UiLCH Bit in The UiC1 Register = 0 (No Reverse)
Transfer Clock
TXDi
(No Reverse)
“H”
“L”
“H”
“L”
D0
D1
D2
D3
D4
D5
D6
D7
D3
D4
D5
D6
D7
(2) When The UiLCH Bit = 1 (Reverse)
Transfer Clock
TXDi
(Reverse)
“H”
“L”
“H”
“L”
D0
D1
D2
NOTES :
1. This applies to the case where the CKPOL bit in the UiC0 register = 0
(transmit data output at the falling edge and the receive data taken
in at the rising edge of the transfer clock) and the UFORM bit = 0
(LSB first).
i = 0 to 2
Figure 17.16
17.1.1.6
Serial Data Logic Switching
Transfer Clock Output From Multiple Pins (UART1)
Use the CLKMD1 to CLKMD0 bits in the UCON register to select one of the two transfer clock output pins
(see Figure 17.17). This function can be used when the selected transfer clock for UART1 is an internal clock.
Microcomputer
TXD1 (P6_7)
CLKS1 (P6_4)
CLK1 (P6_5)
IN
IN
CLK
CLK
Transfer enabled
when the CLKMD0
bit in the UCON
register = 0
Transfer enabled
when the CLKMD0
bit = 1
NOTES :
1. This applies to the case where the CKDIR bit in the U1MR register= 0
(internal clock) and the CLKMD1 bit in the UCON register = 1
(transfer clock output from multiple pins).
Figure 17.17
Transfer Clock Output from Multiple Pins
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M16C/62P Group (M16C/62P, M16C/62PT)
17.1.1.7
17. Serial Interface
CTS/RTS Function
When the CTS function is used transmit and receive operation start when “L” is applied to the CTSi/RTSi (i=0
to 2) pin. Transmit and receive operation begins when the CTSi/RTSi pin is held “L”. If the “L” signal is
switched to “H” during a transmit or receive operation, the operation stops before the next data.
When the RTS function is used, the CTSi/RTSi pin outputs on “L” signal when the microcomputer is ready to
receive. The output level becomes “H” on the first falling edge of the CLKi pin.
• CRD bit in UiC0 register = 1 (disable CTS/RTS of UART0)
CTSi/RTSi pin is programmable I/O function
• CRD bit = 0, CRS bit = 0 (CTS function is selected)
CTSi/RTSi pin is CTS function
• CRD bit = 0, CRS bit = 1 (RTS function is selected)
CTSi/RTSi pin is RTS function
17.1.1.8
CTS/RTS Separate Function (UART0)
This function separates CTS0/RTS0, outputs RTS0 from the P6_0 pin, and accepts as input the CTS0 from the
P6_4 pin. To use this function, set the register bits as shown below.
• CRD bit in U0C0 register = 0 (enable CTS/RTS of UART0)
• CRS bit in U0C0 register = 1 (output RTS of UART0)
• CRD bit in U1C0 register = 0 (enable CTS/RTS of UART1)
• CRS bit in U1C0 register = 0 (input CTS of UART1)
• RCSP bit in UCON register = 1 (inputs CTS0 from the P6_4 pin)
• CLKMD1 bit in UCON register = 0 (CLKS1 not used)
Note that when using the CTS/RTS separate function, CTS/RTS of UART1 separate function cannot be used.
IC
Microcomputer
Figure 17.18
TXD0 (P6_3)
RXD0 (P6_2)
IN
CLK0 (P6_1)
CLK
RTS0 (P6_0)
CTS
CTS0 (P6_4)
RTS
CTS/RTS Separate Function
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OUT
M16C/62P Group (M16C/62P, M16C/62PT)
17.1.2
17. Serial Interface
Clock Asynchronous Serial I/O (UART) Mode
The UART mode allows transmitting and receiving data after setting the desired bit rate and transfer data
format. Table 17.5 lists the UART Mode Specifications.
Table 17.5
UART Mode Specifications
Item
Transfer Data Format
Transfer Clock
Transmission, Reception
Control
Transmission Start
Condition
Reception Start Condition
Interrupt Request
Generation Timing
Error Detection
Select Function
Specification
• Character bit (transfer data): Selectable from 7, 8 or 9 bits
• Start bit: 1 bit
• Parity bit: Selectable from odd, even, or none
• Stop bit: Selectable from 1 or 2 bits
• CKDIR bit in the UiMR(i=0 to 2) register = 0 (internal clock) : fj/ (16(n+1))
fj = f1SIO, f2SIO, f8SIO, f32SIO n: Setting value of UiBRG register 00h to FFh
• CKDIR bit = 1 (external clock) : fEXT/(16(n+1))
• fEXT: Input from CLKi pin n :Setting value of UiBRG register 00h to FFh
Selectable from CTS function, RTS function or CTS/RTS function disable
Before transmission can start, meet the following requirements
• The TE bit in the UiC1 register= 1 (transmission enabled)
• The TI bit in the UiC1 register = 0 (data present in UiTB register)
• If CTS function is selected, input on the CTSi pin = L
Before reception can start, meet the following requirements
• The RE bit in the UiC1 register = 1 (reception enabled)
• Start bit detection
For transmission, one of the following conditions can be selected
• The UiIRS bit (2) = 0 (transmit buffer empty): when transferring data from the UiTB
register to the UARTi transmit register (at start of transmission)
• The UiIRS bit =1 (transfer completed): when the serial interface finished sending data
from the UARTi transmit register
For reception
• When transferring data from the UARTi receive register to the UiRB register (at
completion of reception)
• Overrun error (1)
This error occurs if the serial interface started receiving the next data before reading
the UiRB register and received the bit one before the last stop bit of the next data
• Framing error (3)
This error occurs when the number of stop bits set is not detected
• Parity error (3)
This error occurs when if parity is enabled, the number of “1” in parity and character
bits does not match the number of “1” set
• Error sum flag
This flag is set to “1” when any of the overrun, framing or parity errors occur
• LSB first, MSB first selection
Whether to start sending/receiving data beginning with bit 0 or beginning with bit 7 can
be selected
• Serial data logic switch
This function reverses the logic of the transmit/receive data. The start and stop bits
are not reversed.
• TXD, RXD I/O polarity switch
This function reverses the polarities of the TXD pin output and RXD pin input. The
logic levels of all I/O data is reversed.
• Separate CTS/RTS pins (UART0)
CTS0 and RTS0 are input/output from separate pins
NOTES:
1. If an overrun error occurs, the receive data of UiRB register will be indeterminate. The IR bit in the SiRIC
register does not change.
2. The U0IRS and U1IRS bits are bits 0 and 1 in the UCON register. The U2IRS bit is bit 4 in the U2C1 register.
3. The timing at which the framing error flag and the parity error flag are set is detected when data is transferred
from the UARTi receive register to the UiRB register.
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M16C/62P Group (M16C/62P, M16C/62PT)
Table 17.6
Register
UiTB
UiRB
UiBRG
UiMR
UiC0
Registers to Be Used and Settings in UART Mode
Bit
Function
0 to 8
0 to 8
OER,FER,PER,SUM
0 to 7
SMD2 to SMD0
CKDIR
STPS
PRY, PRYE
IOPOL
CLK0, CLK1
CRS
TXEPT
CRD
NCH
CKPOL
UFORM
UiC1
UiSMR
UiSMR2
UiSMR3
UiSMR4
UCON
17. Serial Interface
TE
TI
RE
RI
U2IRS (2)
U2RRM (2)
UiLCH
UiERE
0 to 7
0 to 7
0 to 7
0 to 7
U0IRS, U1IRS
U0RRM, U1RRM
CLKMD0
CLKMD1
RCSP
7
(1)
Set transmission data
Reception data can be read (1)
Error flag
Set a bit rate
Set these bits to “100b” when transfer data is 7 bits long
Set these bits to “101b” when transfer data is 8 bits long
Set these bits to “110b” when transfer data is 9 bits long
Select the internal clock or external clock
Select the stop bit
Select whether parity is included and whether odd or even
Select the TXD/RXD input/output polarity
Select the count source for the UiBRG register
Select CTS or RTS to use
Transmit register empty flag
Enable or disable the CTS or RTS function
Select TXDi pin output mode (3)
Set to “0”
LSB first or MSB first can be selected when transfer data is 8 bits long. Set this
bit to “0” when transfer data is 7 or 9 bits long.
Set this bit to “1” to enable transmission
Transmit buffer empty flag
Set this bit to “1” to enable reception
Reception complete flag
Select the source of UART2 transmit interrupt
Set to “0”
Set this bit to “1” to use inverted data logic
Set to “0”
Set to “0”
Set to “0”
Set to “0”
Set to “0”
Select the source of UART0/UART1 transmit interrupt
Set to “0”
Invalid because CLKMD1 = 0
Set to “0”
Set this bit to “1” to accept as input CTS0 signal of UART0 from the P6_4 pin
Set to “0”
NOTES:
1. The bits used for transmit/receive data are as follows: Bit 0 to bit 6 when transfer data is 7 bits long; bit 0 to bit 7
when transfer data is 8 bits long; bit 0 to bit 8 when transfer data is 9 bits long.
2. Set the bit 4 to bit 5 in the U0C1 and U1C1 registers to “0”. The U0IRS, U1IRS, U0RRM and U1RRM bits are
included in the UCON register.
3. TXD2 pin is N channel open-drain output. Set the NCH bit in the U2C0 register to “0”.
i=0 to 2
Rev.2.41 Jan 10, 2006
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M16C/62P Group (M16C/62P, M16C/62PT)
17. Serial Interface
Table 17.7 lists the functions of the input/output pins during UART mode. Table 17.8 lists the P6_4 Pin
Functions. Note that for a period from when the UARTi operating mode is selected to when transfer starts, the
TXDi pin outputs an “H” (If the N-channel open-drain output is selected, this pin is in a high-impedance state).
Table 17.7
I/O Pin Functions
Pin Name
TXDi (i = 0 to 2)
(P6_3, P6_7,
P7_0)
RXDi
(P6_2, P6_6,
P7_1)
CLKi
(P6_1, P6_5,
P7_2)
Function
Method of Selection
Serial Data Output (“H” outputs when performing reception only)
Serial Data Input
Input/Output Port
Transfer Clock
Input
CTS Input
CTSi/RTSi
(P6_0, P6_4,
P7_3)
RTS Output
Input/Output Port
Table 17.8
PD6_2 bit and PD6_6 bit in the PD6 register = 0, PD7_1 bit in the
PD7 register = 0
(Can be used as an input port when performing transmission only)
CKDIR bit in the UiMR register = 0
CKDIR bit = 1
PD6_1 bit and PD6_5 bit in the PD6 register = 0, PD7_2 bit in the
PD7 register = 0
CRD bit in the UiC0 register = 0
CRS bit in the UiC0 register = 0
PD6_0 bit and PD6_4 bit in the PD6 register = 0, PD7_3 bit in the
PD7 register = 0
CRD bit = 0
CRS bit = 1
CRD bit = 1
P6_4 Pin Functions
Pin Function
P6_4
CTS1
U1C0 Register
CRD
CRS
1
−
0
0
Bit Set Value
UCON Register
RCSP
CLKMD1
0
0
0
0
PD6 Register
PD6_4
Input: 0, Output: 1
0
RTS1
0
1
0
0
−
CTS0 (1)
0
0
1
0
0
− : “0” or “1”
NOTES:
1. In addition to this, set the CRD bit in the U0C0 register to “0” (CTS0/RTS0 enabled) and the CRS bit
in the U0C0 register to “1” (RTS0 selected).
Rev.2.41 Jan 10, 2006
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M16C/62P Group (M16C/62P, M16C/62PT)
17. Serial Interface
(1) 8-bit Data Transmit Timing (with a parity and 1 stop bit)
The transfer clock stops momentarily, because an “H” single is applied to the CTS pin,
when the stop bit is verified.
The transfer clock resumes running as soon as an “L” single is applied to the CTS pin.
Tc
Transfer Clock
“1”
TE bit in UiC1
register
“0”
Data is set in the UiTB register
“1”
TI bit in UiC1
register
“0”
Data is transferred from the UiTB register to
the UARTi transmit register
“H”
CTSi
“L”
TXDi
ST
TXEPT bit in UiC0
register
“1”
IR bit in
SiTIC register
“1”
D0
Stop
bit
Parity
bit
Start bit
D1
D2
D3
D4
D5
D6
D7
P
SP
ST
Pulse stops because the TE bit is set to “0”
D0
D1
D2
D3
D4
D5
D6
D7
P
SP
ST
D0
D1
“0”
“0”
i=0 to 2
Set to “0” by an interrupt request acknowledgement or by program
The above timing diagram applies to the case where the register bits are set
as follows:
· PRYE bit in UiMR register = 1 (parity enabled)
· STPS bit in UiMR register = 0 (1 stop bit)
· CRD bit in UiC0 register = 0 (CTS/RTS enabled) and
CRS bit = 0 (CTS selected)
· UiIRS bit = 1 (an interrupt request occurs when transmit completed):
U0IRS bit is bit 0 in UCON register
U1IRS bit is bit 1 in UCON register
U2IRS bit is bit 4 in U2C1 register
TC = 16 (n + 1) / fj or 16 (n + 1) / fEXT
fj : frequency of UiBRG count source
(f1SIO, f2SIO, f8SIO, f32SIO)
fEXT : frequency of UiBRG count source (external clock)
n : value set to UiBRG
(1) 9-bit Data Transmit Timing (with no parity and 2 stop bits)
Tc
Transfer Clock
TE bit in UiC1
register
“1”
TI bit in UiC1
register
“1”
“0”
Data is set in the UiTB register
“0”
Data is transferred from the UiTB register to the UARTi transmit register
Stop
bit
Start bit
TXDi
ST
TXEPT bit in
UiC0 register
“1”
IR bit in
SiTIC register
“1”
D0
D1
D2
D3
D4
D5
D6
D7
D8
Stop
bit
SP SP
ST
D0
D1
D2
D3
D4
D5
D6
D7
D8
SP SP
ST
D0
D1
“0”
“0”
Set to “0” by an interrupt request acknowledgement or by program
i=0 to 2
The above timing diagram applies to the case where the register bits are set
as follows:
· PRYE bit in UiMR register = 0 (parity disabled)
· STPS bit in UiMR register = 1 (2 stop bits)
· CRD bit in UiC0 register = 1 (CTS/RTS disabled)
· UiIRS bit = 0 (an interrupt request occurs when transmit
buffer becomes empty):
U0IRS bit is bit 0 in UCON register
U1IRS bit is bit 1 in UCON register
U2IRS bit is bit 4 in U2C1 register
Figure 17.19
Transmit Operation
Rev.2.41 Jan 10, 2006
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TC = 16 (n + 1) / fj or 16 (n + 1) / fEXT
fj : frequency of UiBRG count source
(f1SIO, f2SIO, f8SIO, f32SIO)
fEXT : frequency of UiBRG count source (external clock)
n : value set to UiBRG
M16C/62P Group (M16C/62P, M16C/62PT)
17. Serial Interface
• Example of Receive Timing when Transfer Data is 8 Bits Long (parity disabled, one stop bit)
UiBRG count
source
“1”
“0”
RE bit in UiC1
register
Stop bit
Start bit
RXDi
D7
D1
D0
Sampled “L”
Receive data taken in
Transfer clock
Reception triggered when transfer clock
“1” is generated by falling edge of start bit
RI bit in UiC1
register
Transferred from UARTi receive
register to UiRB register
“0”
“H”
“L”
RTSi
“1”
“0”
IR bit in SiRIC
register
Set to “0” by an interrupt request acknowledgement or by program
The above timing diagram applies to the case where the register bits are set as follows:
· PRYE bit in UiMR register = 0 (parity disabled)
· STPS bit in UiMR register = 0 (1 stop bit)
· CRD bit in UiC0 register = 0 (CTSi/RTSi enabled) and CRS bit = 1 (RTSi selected)
i = 0 to 2
Figure 17.20
17.1.2.1
Receive Operation
Bit Rate
In UART mode, the frequency set by the UiBRG register (i=0 to 2) divided by 16 become the bit rates. Table
17.9 lists Example of Bit Rates and Settings.
Table 17.9
Bit Rate
(bps)
Example of Bit Rates and Settings
Count Source
of UiBRG
Peripheral Function Clock : 16MHz
1200
f8
Set Value of
UiBRG : n
103 (67h)
2400
f8
4800
Peripheral Function Clock : 24MHz
1202
Set value of
UiBRG : n
155 (9Bh)
51 (33h)
2404
77 (4Dh)
2404
f8
25 (19h)
4808
38 (26h)
4808
9600
f1
103 (67h)
9615
155 (9Bh)
9615
14400
f1
68 (44h)
14493
103 (67h)
14423
19200
f1
51 (33h)
19231
77 (4Dh)
19231
28800
f1
34 (22h)
28571
51 (33h)
28846
31250
f1
31 (1Fh)
31250
47 (2Fh)
31250
38400
f1
25 (19h)
38462
38 (26h)
38462
51200
f1
19 (13h)
50000
28 (1Ch)
51724
Rev.2.41 Jan 10, 2006
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Bit Rate (bps)
Bit Rate (bps)
1202
M16C/62P Group (M16C/62P, M16C/62PT)
17.1.2.2
17. Serial Interface
Counter Measure for Communication Error Occurs
If a communication error occurs while transmitting or receiving in UART mode, follow the procedures below.
• Resetting the UiRB register (i=0 to 2)
(1) Set the RE bit in the UiC1 register to “0” (reception disabled)
(2) Set the RE bit in the UiC1 register to “1” (reception enabled)
• Resetting the UiTB register (i=0 to 2)
(1) Set the SMD2 to SMD0 bits in the UiMR register “000b” (Serial interface disabled)
(2) Set the SMD2 to SMD0 bits in the UiMR register “001b”, “101b”, “110b”.
(3) “1” is written to RE bit in the UiC1 register (transmission enabled), regardless of the TE bit in the UiCi
register
17.1.2.3
LSB First/MSB First Select Function
As shown in Figure 17.21, use the UFORM bit in the UiC0 register to select the transfer format. This function is
valid when transfer data is 8 bits long.
(1) When the UFORM Bit in the UiC0 Register = 0 (LSB First)
CLKi
TXDi
ST
D0
D1
D2
D3
D4
D5
D6
D7
P
SP
RXDi
ST
D0
D1
D2
D3
D4
D5
D6
D7
P
SP
(2) When the UFORM Bit = 1 (MSB First)
CLKi
TXDi
ST
D7
D6
D5
D4
D3
D2
D1
D0
P
SP
RXDi
ST
D7
D6
D5
D4
D3
D2
D1
D0
P
SP
NOTES :
1. This applies to the case where the CKPOL bit in the UiC0 register = 0
(transmit data output at the falling edge and the receive data taken
in at the rising edge of the transfer clock), the UiLCH bit in the UiC1
register = 0 (no reverse), the STPS bit in the UiMR register = 0
(1 stop bit) and the PRYE bit in the UiMR register = 1 (parity enabled).
Figure 17.21
Transfer Format
Rev.2.41 Jan 10, 2006
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ST : Start bit
P : Parity bit
SP : Stop bit
i = 0 to 2
M16C/62P Group (M16C/62P, M16C/62PT)
17.1.2.4
17. Serial Interface
Serial Data Logic Switching Function
The data written to the UiTB register has its logic reversed before being transmitted. Similarly, the received
data has its logic reversed when read from the UiRB register. Figure 17.22 shows Serial Data Logic Switching.
(1) When the UiLCH bit in the UiC1 Register = 0 (No Reverse)
Transfer Clock
“H”
“L”
TXDi
(No Reverse)
“H”
ST
D0
D1
D2
D3
D4
D5
D6
D7
P
SP
D2
D3
D4
D5
D6
D7
P
SP
“L”
(2) When the UiLCH Bit = 1 (Reverse)
Transfer Clock
TXDi
(Reverse)
“H”
“L”
“H”
ST
“L”
D0
D1
ST : Start bit
P : Parity bit
SP : Stop bit
i = 0 to 2
NOTES :
1. This applies to the case where the CKPOL bit in the UiC0 register = 0
(transmit data output at the falling edge of the transfer clock),
the UFORM bit in the UiC0 register = 0 (LSB first),
the STPS bit in the UiMR register = 0 (1 stop bit) and
the PRYE bit in the UiMR register = 1 (parity enabled).
Figure 17.22
17.1.2.5
Serial Data Logic Switching
TXD and RXD I/O Polarity Inverse Function
This function inverses the polarities of the TXDi pin output and RXDi pin input. The logic levels of all input/
output data (including the start, stop and parity bits) are inversed. Figure 17.23 shows the TXD and RXD I/O
Polarity Inverse.
(1) When the IOPOL Bit in the UiMR Register = 0 (No Reverse)
Transfer Clock
TXDi
“H”
“L”
“H”
(No Reverse) “L”
RXDi
“H”
(No Reverse) “L”
ST
D0
D1
D2
D3
D4
D5
D6
D7
P
SP
ST
D0
D1
D2
D3
D4
D5
D6
D7
P
SP
(2) When the IOPOL Bit = 1 (Reverse)
Transfer Clock
“H”
TXDi
“H”
“L”
(Reverse)
RXDi
“L”
“H”
(Reverse) “L”
ST
D0
D1
D2
D3
D4
D5
D6
D7
P
SP
ST
D0
D1
D2
D3
D4
D5
D6
D7
P
SP
NOTES :
1. This applies to the case where the UFORM bit in the UiC0 register = 0
(LSB first), the STPS bit in the UiMR register = 0 (1 stop bit) and the
PRYE bit in the UiMR register = 1 (parity enabled).
Figure 17.23
TXD and RXD I/O Polarity Inverse
Rev.2.41 Jan 10, 2006
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ST : Start bit
P : Parity bit
SP : Stop bit
i = 0 to 2
M16C/62P Group (M16C/62P, M16C/62PT)
17.1.2.6
17. Serial Interface
CTS/RTS Function
When the CTS function is used transmit operation start when “L” is applied to the CTSi/RTSi (i=0 to 2) pin.
Transmit operation begins when the CTSi/RTSi pin is held “L”. If the “L” signal is switched to “H” during a
transmit operation, the operation stops before the next data.
When the RTS function is used, the CTSi/RTSi pin outputs on “L” signal when the microcomputer is ready to
receive. The output level becomes “H” on the first falling edge of the CLKi pin.
• CRD bit in UiC0 register = 1 (disable CTS/RTS function of UART0)
CTSi/RTSi pin is programmable I/O function
• CRD bit = 0, CRS bit = 0 (CTS function is selected)
CTSi/RTSi pin is CTS function
• CRD bit = 0, CRS bit = 1 (RTS function is selected)
CTSi/RTSi pin is RTS function
17.1.2.7
CTS/RTS Separate Function (UART0)
This function separates CTS0/RTS0, outputs RTS0 from the P6_0 pin, and accepts as input the CTS0 from the
P6_4 pin. To use this function, set the register bits as shown below.
• CRD bit in U0C0 register = 0 (enable CTS/RTS of UART0)
• CRS bit in U0C0 register = 1 (output RTS of UART0)
• CRD bit in U1C0 register = 0 (enable CTS/RTS of UART1)
• CRS bit in U1C0 register = 0 (input CTS of UART1)
• RCSP bit in UCON register = 1 (inputs CTS0 from the P6_4 pin)
• CLKMD1 bit in UCON register = 0 (CLKS1 not used)
Note that when using the CTS/RTS separate function, CTS/RTS of UART1 separate function cannot be used.
IC
Microcomputer
Figure 17.24
TXD0 (P6_3)
IN
RXD0 (P6_2)
OUT
RTS0 (P6_0)
CTS
CTS0 (P6_4)
RTS
CTS/RTS Separate Function
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M16C/62P Group (M16C/62P, M16C/62PT)
17.1.3
17. Serial Interface
Special Mode 1 (I2C mode)
I2C mode is provided for use as a simplified I2C interface compatible mode. Table 17.10 lists the specifications
of the I2C mode. Table 17.11 to 17.12 lists the registers used in the I2C mode and the register values set. Table
13.13 lists the I2C Mode Functions. Figure 17.25 shows the block diagram for I2C mode. Figure 17.26 shows
Transfer to UiRB Register and Interrupt Timing.
As shown in Table 17.13, the microcomputer is placed in I2C mode by setting the SMD2 to SMD0 bits to
“010b” and the IICM bit to “1”. Because SDAi transmit output has a delay circuit attached, SDAi output does
not change state until SCLi goes low and remains stably low.
Table 17.10
I2C Mode Specifications
Item
Transfer Data Format
Transfer Clock
Transmission Start
Condition
Reception Start Condition
Interrupt Request
Generation Timing
Error Detection
Select Function
Specification
Transfer data length: 8 bits
• During master
CKDIR bit in the UiMR (i=0 to 2) register = 0 (internal clock) : fj/ (2(n+1))
fj = f1SIO, f2SIO, f8SIO, f32SIO n: Setting value of UiBRG register 00h to FFh
• During slave
CKDIR bit = 1 (external clock) : Input from SCLi pin
Before transmission can start, met the following requirements (1)
• The TE bit in the UiC1 register= 1 (transmission enabled)
• The TI bit in the UiC1 register = 0 (data present in UiTB register)
Before reception can start, met the following requirements (1)
• The RE bit in UiC1 register= 1 (reception enabled)
• The TE bit in UiC1 register= 1 (transmission enabled)
• The TI bit in UiC1 register= 0 (data present in the UiTB register)
When start or stop condition is detected, acknowledge undetected, and acknowledge
detected
Overrun error (2)
This error occurs if the serial interface started receiving the next data before reading
the UiRB register and received the 8th bit of the next data
• Arbitration lost
Timing at which the ABT bit in the UiRB register is updated can be selected
• SDAi digital delay
No digital delay or a delay of 2 to 8 UiBRG count source clock cycles selectable
• Clock phase setting
With or without clock delay selectable
NOTES:
1. When an external clock is selected, the conditions must be met while the external clock is in the high state.
2. If an overrun error occurs, the value of UiRB register will be indeterminate. The IR bit in the SiRIC register does
not change.
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M16C/62P Group (M16C/62P, M16C/62PT)
17. Serial Interface
Start and stop condition generation block
SDAi
STSPSEL=1
Delay
circuit
SDA(STSP)
SCL(STSP)
STSPSEL=0
ACKC=1
IICM2=1
Transmission
register
ACKC=0
IICM=1 and
IICM2=0
UARTi
SDHI
ACKD register
D Q
T
Noise
Filter
UARTi transmit,
NACK interrupt
request
ALS
DMA0
(UART0, UART2)
Arbitration
IICM2=1
Reception register
UARTi
Start condition
detection
S
R
Q
IICM=1 and
IICM2=0
NACK
D Q
T
Falling edge
detection
SCLi
R
IICM=0
I/O port
STSPSEL=0
UARTi receive,
ACK interrupt request,
DMA1 request
Bus
busy
Stop condition
detection
Noise
Filter
DMA0, DMA1 request
(UART1: DMA0 only)
D Q
T
Port register(1)
ACK
9th bit
Q
Internal clock
SWC2
IICM=1 UARTi STSPSEL=1
External
clock
Start/stop condition detection
interrupt request
CLK
control
UARTi
R
S
9th bit falling edge
SWC
This diagram applies to the case where the SMD2 to SMD0 bits in the UiMR register = 010b and the IICM bit in the UiSMR register = 1.
IICM
: Bit in UiSMR register
IICM2, SWC, ALS, SWC2, SDHI : Bit in UiSMR2 register
STSPSEL, ACKD, ACKC
: Bit in UiSMR4 register
i=0 to 2
NOTES :
1. If the IICM bit = 1, the pin can be read even when the PD6_2, PD6_6 or PD7_1 bit = 1 (output mode).
Figure 17.25
I2C Mode Block Diagram
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M16C/62P Group (M16C/62P, M16C/62PT)
Table 17.11
Registers to Be Used and Settings in I2C Mode (1)
Register
UiTB (3)
UiRB (3)
UiBRG
UiMR (3)
UiC0
UiC1
UiSMR
UiSMR2
17. Serial Interface
Bit
0 to 7
0 to 7
8
ABT
OER
0 to 7
SMD2 to SMD0
CKDIR
IOPOL
CLK1, CLK0
CRS
TXEPT
CRD (4)
NCH
CKPOL
UFORM
TE
TI
RE
RI
U2IRS (1)
U2RRM (1),
UiLCH, UiERE
IICM
ABC
BBS
3 to 7
IICM2
CSC
SWC
ALS
STAC
SWC2
SDHI
7
Function
Master
Slave
Set transmission data
Set transmission data
Reception data can be read
Reception data can be read
ACK or NACK is set in this bit
ACK or NACK is set in this bit
Arbitration lost detection flag
Invalid
Overrun error flag
Overrun error flag
Set a bit rate
Invalid
Set to “010b”
Set to “010b”
Set to “0”
Set to “1”
Set to “0”
Set to “0”
Select the count source for the UiBRG
Invalid
register
Invalid because CRD = 1
Invalid because CRD = 1
Transmit buffer empty flag
Transmit buffer empty flag
Set to “1”
Set to “1”
Set to “1” (2)
Set to “1” (2)
Set to “0”
Set to “0”
Set to “1”
Set to “1”
Set this bit to “1” to enable transmission Set this bit to “1” to enable transmission
Transmit buffer empty flag
Transmit buffer empty flag
Set this bit to “1” to enable reception
Set this bit to “1” to enable reception
Reception complete flag
Reception complete flag
Invalid
Invalid
Set to “0”
Set to “0”
Set to “1”
Select the timing at which arbitration-lost
is detected
Bus busy flag
Set to “0”
See Table 17.13 I2C Mode Functions
Set this bit to “1” to enable clock
synchronization
Set this bit to “1” to have SCLi output fixed
to “L” at the falling edge of the 9th bit of
clock
Set this bit to “1” to have SDAi output
stopped when arbitration-lost is detected
Set to “0”
Set this bit to “1” to have SCLi output
forcibly pulled low
Set this bit to “1” to disable SDAi output
Set to “0”
Set to “1”
Invalid
Bus busy flag
Set to “0”
See Table 17.13 I2C Mode Functions
Set to “0”
Set this bit to “1” to have SCLi output fixed
to “L” at the falling edge of the 9th bit of
clock
Set to “0”
Set this bit to “1” to initialize UARTi at
start condition detection
Set this bit to “1” to have SCLi output
forcibly pulled low
Set this bit to “1” to disable SDAi output
Set to “0”
NOTES:
1. Set the bit 4 and bit 5 in the U0C1 and U1C1 register to “0”. The U0IRS, U1IRS, U0RRM and U1RRM bits are
in the UCON register.
2. TXD2 pin is N channel open-drain output. No NCH bit in the U2C0 register is assigned. When write, set to “0”.
3. Not all register bits are described above. Set those bits to “0” when writing to the registers in I2C mode.
4. When using UART1 in I2C mode and enabling the CTS/RTS separate function of UART0, set the CRD bit in the
U1C0 register to “0” (CTS/RTS enable) and the CRS bit to “0” (CTS input).
i=0 to 2
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M16C/62P Group (M16C/62P, M16C/62PT)
Table 17.12
17. Serial Interface
Registers to Be Used and Settings in I2C Mode (2)
Register
Bit
Function
Master
UiSMR3
UiSMR4
0, 2, 4 and NODC
CKPH
DL2 to DL0
STAREQ
SWC9
Set to “0”
See Table 17.13 I2C Mode Functions
Set the amount of SDAi digital delay
Set this bit to “1” to generate start
condition
Set this bit to “1” to generate restart
condition
Set this bit to “1” to generate stop
condition
Set this bit to “1” to output each condition
Select ACK or NACK
Set this bit to “1” to output ACK data
Set this bit to “1” to have SCLi output
stopped when stop condition is detected
Set to “0”
IFSR26, ISFR27
U0IRS, U1IRS
2 to 7
Set to “1”
Invalid
Set to “0”
RSTAREQ
STPREQ
STSPSEL
ACKD
ACKC
SCLHI
IFSR2A
UCON
i=0 to 2
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Slave
Set to “0”
See Table 17.13 I2C Mode Functions
Set the amount of SDAi digital delay
Set to “0”
Set to “0”
Set to “0”
Set to “0”
Select ACK or NACK
Set this bit to “1” to output ACK data
Set to “0”
Set this bit to “1” to set the SCLi to “L” hold
at the falling edge of the 9th bit of clock
Set to “1”
Invalid
Set to “0”
M16C/62P Group (M16C/62P, M16C/62PT)
Table 17.13
17. Serial Interface
I2C Mode Functions
Function
Clock Synchronous Serial I/O
Mode (SMD2 to SMD0 = 001b,
IICM = 0)
I2C Mode (SMD2 to SMD0 = 010b, IICM = 1)
IICM2 = 0
(NACK/ACK interrupt)
IICM2 = 1
(UART transmit/receive interrupt)
CKPH = 0
(No clock delay)
CKPH = 0
(No clock delay)
CKPH = 1
(Clock delay)
CKPH = 1
(Clock delay)
Factor of Interrupt Number
6, 7 and 10 (1, 5, 7)
−
Start condition detection or stop condition detection
(See Table 17.14 STSPSEL Bit Functions)
Factor of Interrupt Number
15, 17 and 19 (1, 6)
UARTi transmission
Transmission started or
completed (selected by UiIRS)
No acknowledgment
detection (NACK)
Rising edge of SCLi 9th bit
UARTi transmission
Rising edge of SCLi
9th bit
Factor of Interrupt Number
16, 18 and 20 (1, 6)
UARTi reception
When 8th bit received
CKPOL = 0 (rising edge)
CKPOL = 1 (falling edge)
Acknowledgment detection (ACK)
Rising edge of SCLi 9th bit
UARTi reception
Falling edge of SCLi 9th bit
Timing for Transferring Data
From the UART Reception
Shift Register to the UiRB
Register
CKPOL = 0 (rising edge)
CKPOL = 1 (falling edge)
Rising edge of SCLi 9th bit
Falling edge of SCLi
9th bit
UARTi Transmission Output
Delay
Not delayed
Delayed
Functions of P6_3, P6_7 and
P7_0 Pins
TXDi output
SDAi input/output
Functions of P6_2, P6_6 and
P7_1 Pins
RXDi input
SCLi input/output
Functions of P6_1, P6_5 and
P7_2 Pins
CLKi input or output selected
− (Cannot be used in I2C mode)
UARTi transmission
Falling edge of SCLi
next to the 9th bit
Falling and rising
edges of SCLi 9th
bit
Noise Filter Width
15ns
200ns
Read RXDi and SCLi Pin
Levels
Possible when the corresponding
port direction bit = 0
Always possible no matter how the corresponding port direction bit is set
Initial Value of TXDi and
SDAi Outputs
CKPOL = 0 (H)
CKPOL = 1 (L)
The value set in the port register before setting I2C mode (2)
Initial and End Values of SCLi −
H
DMA1 Factor (6)
UARTi reception
Acknowledgment detection (ACK)
UARTi reception
Falling edge of SCLi 9th bit
Store Received Data
1st to 8th bits of the received data
are stored into bits 7 to 0 in the
UiRB register
1st to 8th bits of the received data are
stored into bits 7 to 0 in the UiRB
register
1st to 7th bits of the received data are
stored into bits 6 to 0 in the UiRB register.
8th bit is stored into bit 8 in the UiRB
register.
L
H
L
1st to 8th bits are
stored into bits 7 to
0 in the UiRB
register (3)
Read Received Data
The UiRB register status is read
Bits 6 to 0 in the
UiRB register (4) are
read as bits 7 to 1.
Bit 8 in the UiRB
register is read as
bit 0.
NOTES:
1. If the source or factor of any interrupt is changed, the IR bit in the interrupt control register for the changed interrupt may
inadvertently be set to “1” (interrupt requested). (Refer to 24.7 Interrupt)
If one of the bits shown below is changed, the interrupt source, the interrupt timing, etc. change. Therefore, always be sure to
clear the IR bit to “0” (interrupt not requested) after changing those bits.
SMD2 to SMD0 bits in the UiMR register, IICM bit in the UiSMR register, IICM2 bit in the UiSMR2 register, CKPH bit in the
UiSMR3 register
2. Set the initial value of SDAi output while the SMD2 to SMD0 bits in the UiMR register = 000b (serial interface disabled).
3. Second data transfer to UiRB register (Rising edge of SCLi 9th bit)
4. First data transfer to UiRB register (Falling edge of SCLi 9th bit)
5. See Figure 17.28 STSPSEL Bit Functions.
6. See Figure 17.26 Transfer to UiRB Register and Interrupt Timing.
7. When using UART0, be sure to set the IFSR26 bit in the IFSR2A register to “1” (factor of interrupt: UART0 bus collision).
When using UART1, be sure to set the IFSR27 bit to “1” (factor of interrupt: UART1 bus collision).
i = 0 to 2
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M16C/62P Group (M16C/62P, M16C/62PT)
17. Serial Interface
(1) IICM2= 0 (ACK and NACK interrupts), CKPH= 0 (no clock delay)
1st bit
2nd bit
3rd bit
4th bit
5th bit
6th bit
7th bit
8th bit
9th bit
SCLi
D7
SDAi
D6
D5
D4
D3
D2
D1
D0
D8 (ACK, NACK)
ACK interrupt (DMA1 request),
NACK interrupt
Transfer to UiRB register
b15
b9
•••
b8
b7
D8
D7
b0
D6
D5
D4
D3
D2
D1
D0
D2
D1
D0
D3
D2
D1
UiRB register
(2) IICM2= 0, CKPH= 1 (clock delay)
1st bit
2nd bit
3rd bit
4th bit
5th bit
6th bit
7th bit
8th bit
9th bit
SCLi
D7
SDAi
D6
D5
D4
D3
D2
D1
D0
D8 (ACK, NACK)
ACK interrupt (DMA1 request),
NACK interrupt
Transfer to UiRB register
b15
b9
•••
b8
b7
D8
D7
b0
D6
D5
D4
D3
UiRB register
(3) IICM2= 1 (UART transmit/receive interrupt), CKPH= 0
1st bit
2nd bit
3rd bit
4th bit
5th bit
6th bit
7th bit
8th bit
9th bit
SCLi
D7
SDAi
D6
D5
D4
D3
D2
D1
D0
D8 (ACK, NACK)
Receive interrupt Transmit interrupt
(DMA1 request)
Transfer to UiRB register
b15
b9
•••
b8
b7
b0
D0
D7
D6
D5
D4
UiRB register
(4) IICM2= 1, CKPH= 1
1st bit
2nd bit
3rd bit
4th bit
5th bit
6th bit
7th bit
8th bit
9th bit
SCLi
SDAi
D7
D6
D5
D4
D3
D2
D1
D0
D8 (ACK, NACK)
Receive interrupt
(DMA1 request)
Transfer to UiRB register
b15
b9
•••
b8
D0
b7
b0
D7
D6
D5
D4
D3
D2
D1
Transmit interrupt
Transfer to UiRB register
b15
b9
•••
UiRB register
i=0 to 2
This diagram applies to the case where the following condition is met.
· UiMR register CKDIR bit = 0 (Slave selected)
Figure 17.26
Transfer to UiRB Register and Interrupt Timing
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b8
b7
D8
D7
b0
D6
D5
D4
D3
D2
UiRB register
D1
D0
M16C/62P Group (M16C/62P, M16C/62PT)
17.1.3.1
17. Serial Interface
Detection of Start and Stop Condition
Whether a start or a stop condition has been detected is determined.
A start condition-detected interrupt request is generated when the SDAi pin changes state from high to low
while the SCLi pin is in the high state. A stop condition-detected interrupt request is generated when the SDAi
pin changes state from low to high while the SCLi pin is in the high state.
Because the start and stop condition-detected interrupts share the interrupt control register and vector, check the
BBS bit in the UiSMR register to determine which interrupt source is requesting the interrupt.
3 to 6 cycles < duration for setting-up
3 to 6 cycles < duration for holding
(1)
(1)
Duration for
setting up
Duration for
holding
SCLi
SDAi
(Start condition)
SDA i
(Stop condition)
i = 0 to 2
NOTES :
1. When the PCLK1 bit in the PCLKR register = 1, this is the cycle number of
f1SIO, and the PCLK1 bit = 0, this is the cycle number of f2SIO.
Figure 17.27
17.1.3.2
Detection of Start and Stop Condition
Output of Start and Stop Condition
A start condition is generated by setting the STAREQ bit in the UiSMR4 register (i = 0 to 2) to “1” (start).
A restart condition is generated by setting the RSTAREQ bit in the UiSMR4 register to “1” (start).
A stop condition is generated by setting the STPREQ bit in the UiSMR4 register to “1” (start).
The output procedure is described below.
(1) Set the STAREQ bit, RSTAREQ bit or STPREQ bit to “1” (start).
(2) Set the STSPSEL bit in the UiSMR4 register to “1” (output).
The function of the STSPSEL bit is shown in Table 17.14 and Figure 17.28.
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M16C/62P Group (M16C/62P, M16C/62PT)
Table 17.14
17. Serial Interface
STSPSEL Bit Functions
Function
Output of SCLi and SDAi Pins
Start/Stop Condition Interrupt
Request Generation Timing
STSPSEL = 0
Output of transfer clock and data
Output of start/stop condition is
accomplished by a program using
ports (not automatically generated
in hardware)
Start/stop condition detection
STSPSEL = 1
Output of a start/stop condition
according to the STAREQ,
RSTAREQ and STPREQ bit
Finish generating start/stop
condition
(1) When Slave
CKDIR=1 (external clock)
STSPSEL bit
0
1st 2nd 3rd 4th 5th 6th 7th 8th 9th bit
SCLi
SDAi
Start condition
detection interrupt
Stop condition
detection interrupt
(2) When Master
CKDIR=0 (internal clock), CKPH=1 (clock delayed)
STSPSEL bit
Set to “1” in
a program
Set to “0” in
a program
Set to “1” in
a program
Set to “0” in
a program
1st 2nd 3rd 4th 5th 6th 7th 8th 9th bit
SCLi
SDAi
Set STAREQ=1
(start)
Figure 17.28
17.1.3.3
Set STPREQ=1
Stop condition detection
Start condition detection (start)
interrupt
interrupt
STSPSEL Bit Functions
Arbitration
Unmatching of the transmit data and SDAi pin input data is checked synchronously with the rising edge of
SCLi. Use the ABC bit in the UiSMR register to select the timing at which the ABT bit in the UiRB register is
updated. If the ABC bit = 0 (updated bitwise), the ABT bit is set to “1” at the same time unmatching is detected
during check, and is cleared to “0” when not detected. In cases when the ABC bit is set to “1”, if unmatching is
detected even once during check, the ABT bit is set to “1” (unmatching detected) at the falling edge of the clock
pulse of 9th bit. If the ABT bit needs to be updated bytewise, clear the ABT bit to “0” (undetected) after
detecting acknowledge in the first byte, before transferring the next byte.
Setting the ALS bit in the UiSMR2 register to “1” (SDA output stop enabled) factors arbitration-lost to occur, in
which case the SDAi pin is placed in the high-impedance state at the same time the ABT bit is set to “1”
(unmatching detected).
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M16C/62P Group (M16C/62P, M16C/62PT)
17.1.3.4
17. Serial Interface
Transfer Clock
Data is transmitted/received using a transfer clock like the one shown in Figure 17.26 Transfer to UiRB
Register and Interrupt Timing.
The CSC bit in the UiSMR2 register is used to synchronize the internally generated clock (internal SCLi) and
an external clock supplied to the SCLi pin. In cases when the CSC bit is set to “1” (clock synchronization
enabled), if a falling edge on the SCLi pin is detected while the internal SCLi is high, the internal SCLi goes
low, at which time the value of the UiBRG register is reloaded with and starts counting in the low-level interval.
If the internal SCLi changes state from low to high while the SCLi pin is low, counting stops, and when the
SCLi pin goes high, counting restarts.
In this way, the UARTi transfer clock is comprised of the logical product of the internal SCLi and SCLi pin
signal. The transfer clock works from a half period before the falling edge of the internal SCLi 1st bit to the
rising edge of the 9th bit. To use this function, select an internal clock for the transfer clock.
The SWC bit in the UiSMR2 register allows to select whether the SCLi pin should be fixed to or freed from
low-level output at the falling edge of the 9th clock pulse.
If the SCLHI bit in the UiSMR4 register is set to “1” (enabled), SCLi output is turned off (placed in the highimpedance state) when a stop condition is detected.
Setting the SWC2 bit in the UiSMR2 register = 1 (0 output) makes it possible to forcibly output a low-level
signal from the SCLi pin even while sending or receiving data. Clearing the SWC2 bit to “0” (transfer clock)
allows the transfer clock to be output from or supplied to the SCLi pin, instead of outputting a low-level signal.
If the SWC9 bit in the UiSMR4 register is set to “1” (SCL hold low enabled) when the CKPH bit in the
UiSMR3 register = 1, the SCLi pin is fixed to low-level output at the falling edge of the clock pulse next to the
9th. Setting the SWC9 bit = 0 (SCL hold low disabled) frees the SCLi pin from low-level output.
17.1.3.5
SDA Output
The data written to the UiTB register bit 7 to bit 0 (D7 to D0) is sequentially output beginning with D7.
The 9th bit (D8) is ACK or NACK.
The initial value of SDAi transmit output can only be set when IICM = 1 (I2C mode) and the SMD2 to SMD0
bits in the UiMR register = 000b (Serial interface disabled).
The DL2 to DL0 bits in the UiSMR3 register allow to add no delays or a delay of 2 to 8 UiBRG count source
clock cycles to SDAi output.
Setting the SDHI bit in the UiSMR2 register = 1 (SDA output disabled) forcibly places the SDAi pin in the
high-impedance state. Do not write to the SDHI bit synchronously with the rising edge of the UARTi transfer
clock. This is because the ABT bit may inadvertently be set to “1” (detected).
17.1.3.6
SDA Input
When the IICM2 bit = 0, the 1st to 8th bits (D7 to D0) of received data are stored in the UiRB register bit 7 to
bit 0. The 9th bit (D8) is ACK or NACK.
When the IICM2 bit = 1, the 1st to 7th bits (D7 to D1) of received data are stored in the UiRB register bit 6 to
bit 0 and the 8th bit (D0) is stored in the UiRB register bit 8. Even when the IICM2 bit = 1, providing the CKPH
bit = 1, the same data as when the IICM2 bit = 0 can be read out by reading the UiRB register after the rising
edge of the corresponding clock pulse of 9th bit.
17.1.3.7
ACK and NACK
If the STSPSEL bit in the UiSMR4 register is set to “0” (start and stop conditions not generated) and the ACKC
bit in the UiSMR4 register is set to “1” (ACK data output), the value of the ACKD bit in the UiSMR4 register is
output from the SDAi pin.
If the IICM2 bit = 0, a NACK interrupt request is generated if the SDAi pin remains high at the rising edge of
the 9th bit of transmit clock pulse. An ACK interrupt request is generated if the SDAi pin is low at the rising
edge of the 9th bit of transmit clock pulse.
If ACKi is selected for the factor of DMA1 request, a DMA transfer can be activated by detection of an
acknowledge.
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M16C/62P Group (M16C/62P, M16C/62PT)
17.1.3.8
17. Serial Interface
Initialization of Transmission/Reception
If a start condition is detected while the STAC bit = 1 (UARTi initialization enabled), the serial interface
operates as described below.
• The transmit shift register is initialized, and the content of the UiTB register is transferred to the transmit
shift register. In this way, the serial interface starts sending data synchronously with the next clock pulse
applied. However, the UARTi output value does not change state and remains the same as when a start
condition was detected until the first bit of data is output synchronously with the input clock.
• The receive shift register is initialized, and the serial interface starts receiving data synchronously with the
next clock pulse applied.
• The SWC bit is set to “1” (SCL wait output enabled). Consequently, the SCLi pin is pulled low at the
falling edge of the 9th clock pulse.
Note that when UARTi transmission/reception is started using this function, the TI does not change state. Note
also that when using this function, the selected transfer clock should be an external clock.
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M16C/62P Group (M16C/62P, M16C/62PT)
17.1.4
17. Serial Interface
Special Mode 2
Multiple slaves can be serially communicated from one master. Transfer clock polarity and phase are selectable.
Table 17.15 lists the Special Mode 2 Specifications. Table 17.16 lists the Registers to Be Used and Settings in
Special Mode 2. Figure 17.29 shows Serial Bus Communication Control Example (UART2).
Table 17.15
Special Mode 2 Specifications
Item
Transfer Data Format
Transfer Clock
Transmit/Receive Control
Transmission Start
Condition
Reception Start Condition
Interrupt Request
Generation Timing
Error Detection
Select Function
Specification
Transfer data length: 8 bits
• Master mode
CKDIR bit in UiMR(i=0 to 2) register = 0 (internal clock) : fj/ (2(n+1))
fj = f1SIO, f2SIO, f8SIO, f32SIO n: Setting value of UiBRG register 00h to FFh
• Slave mode
CKDIR bit = 1 (external clock selected) : Input from CLKi pin
Controlled by input/output ports
Before transmission can start, meet the following requirements (1)
• The TE bit in UiC1 register= 1 (transmission enabled)
• The TI bit in UiC1 register = 0 (data present in UiTB register)
Before reception can start, meet the following requirements (1)
• The RE bit in UiC1 register= 1 (reception enabled)
• The TE bit in UiC1 register= 1 (transmission enabled)
• The TI bit in UiC1 register= 0 (data present in the UiTB register)
For transmission, one of the following conditions can be selected
• The UiIRS bit in UiC1 register = 0 (transmit buffer empty): when transferring data from
the UiTB register to the UARTi transmit register (at start of transmission)
• The UiIRS bit =1 (transfer completed): when the serial interface finished sending data
from the UARTi transmit register
For reception
• When transferring data from the UARTi receive register to the UiRB register (at
completion of reception)
Overrun error (2)
This error occurs if the serial interface started receiving the next data before reading
the UiRB register and received the 7th bit of the next data
Clock phase setting
Selectable from four combinations of transfer clock polarities and phases
NOTES:
1. When an external clock is selected, the conditions must be met while if the CKPOL bit in the UiC0 register = 0
(transmit data output at the falling edge and the receive data taken in at the rising edge of the transfer clock),
the external clock is in the high state; if the CKPOL bit = 1 (transmit data output at the rising edge and the
receive data taken in at the falling edge of the transfer clock), the external clock is in the low state.
2. If an overrun error occurs, the value of UiRB register will be indeterminate. The IR bit in the SiRIC register does
not change.
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M16C/62P Group (M16C/62P, M16C/62PT)
17. Serial Interface
P1_3
P1_2
P9_3
P7_2(CLK2)
P7_2(CLK2)
P7_1(RXD2)
P7_1(RXD2)
P7_0(TXD2)
P7_0(TXD2)
Microcomputer
(Master)
Microcomputer
(Slave)
P9_3
P7_2(CLK2)
P7_1(RXD2)
P7_0(TXD2)
Microcomputer
(Slave)
Figure 17.29
Serial Bus Communication Control Example (UART2)
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M16C/62P Group (M16C/62P, M16C/62PT)
Table 17.16
Register
UiTB (3)
UiRB (3)
UiBRG
UiMR (3)
UiC0
UiC1
UiSMR
UiSMR2
UiSMR3
UiSMR4
UCON
17. Serial Interface
Registers to Be Used and Settings in Special Mode 2
Bit
0 to 7
0 to 7
OER
0 to 7
SMD2 to SMD0
CKDIR
IOPOL
CLK1, CLK0
CRS
TXEPT
CRD
NCH
CKPOL
UFORM
TE
TI
RE
RI
U2IRS (1)
U2RRM (1), UiLCH,
UiERE
0 to 7
0 to 7
CKPH
NODC
0, 2, 4 to 7
0 to 7
U0IRS, U1IRS
U0RRM, U1RRM
CLKMD0
CLKMD1, RCSP, 7
Function
Set transmission data
Reception data can be read
Overrun error flag
Set a bit rate
Set to “001b”
Set this bit to “0” for master mode or “1” for slave mode
Set to “0”
Select the count source for the UiBRG register
Invalid because CRD = 1
Transmit register empty flag
Set to “1”
Select TXDi pin output format (2)
Clock phases can be set in combination with the CKPH bit in the UiSMR3 register
Set to “0”
Set this bit to “1” to enable transmission
Transmit buffer empty flag
Set this bit to “1” to enable reception
Reception complete flag
Select UART2 transmit interrupt factor
Set to “0”
Set to “0”
Set to “0”
Clock phases can be set in combination with the CKPOL bit in the UiC0 register
Set to “0”
Set to “0”
Set to “0”
Select UART0 and UART1 transmit interrupt factor
Set to “0”
Invalid because CLKMD1 = 0
Set to “0”
NOTES:
1. Set the bit 4 and bit 5 in the U0C0 and U1C1 register to “0”. The U0IRS, U1IRS, U0RRM and U1RRM bits are
in the UCON register.
2. TXD2 pin is N channel open-drain output. No NCH bit in the U2C0 register is assigned. When write, set to “0”.
3. Not all register bits are described above. Set those bits to “0” when writing to the registers in Special Mode 2.
i = 0 to 2
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M16C/62P Group (M16C/62P, M16C/62PT)
17.1.4.1
17. Serial Interface
Clock Phase Setting Function
One of four combinations of transfer clock phases and polarities can be selected using the CKPH bit in the
UiSMR3 register and the CKPOL bit in the UiC0 register.
Make sure the transfer clock polarity and phase are the same for the master and salves to be communicated.
Figure 17.30 shows the Transmission and Reception Timing in Master Mode (Internal Clock).
Figure 17.31 shows the Transmission and Reception Timing (CKPH=0) in Slave Mode (External Clock) while
Figure 17.32 shows the Transmission and Reception Timing (CKPH=1) in Slave Mode (External Clock).
“H”
Clock output
(CKPOL=0, CKPH=0) “L”
Clock output
“H”
(CKPOL=1, CKPH=0) “L”
Clock output
“H”
(CKPOL=0, CKPH=1) “L”
“H”
Clock output
(CKPOL=1, CKPH=1) “L”
Data output timing
“H”
“L”
D0
D1
D2
D3
D4
D5
D6
Data input timing
Figure 17.30
Transmission and Reception Timing in Master Mode (Internal Clock)
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D7
M16C/62P Group (M16C/62P, M16C/62PT)
17. Serial Interface
“H”
Slave control input
“L”
“H”
Clock input
(CKPOL=0, CKPH=0) “L”
Clock input
“H”
(CKPOL=1, CKPH=0)
“L”
Data output timing
(1)
“H”
D0
“L”
Data input timing
D1
D2
D3
D4
D5
D6
D7
Indeterminate
NOTES :
1. UART2 output is an N-channel open drain and must be pulled-up externally.
Figure 17.31
Transmission and Reception Timing (CKPH=0) in Slave Mode (External Clock)
“H”
Slave control input
“L”
“H”
Clock input
(CKPOL=0, CKPH=1) “L”
Clock input
“H”
(CKPOL=1, CKPH=1) “L”
Data output timing
(1)
“H”
“L”
D0
D1
D2
D3
D4
D5
D6
D7
Data input timing
NOTES :
1. UART2 output is an N-channel open drain and must be pulled-up externally.
Figure 17.32
Transmission and Reception Timing (CKPH=1) in Slave Mode (External Clock)
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M16C/62P Group (M16C/62P, M16C/62PT)
17.1.5
17. Serial Interface
Special Mode 3 (IE mode)
In this mode, one bit of IEBus is approximated with one byte of UART mode waveform.
Table 17.17 lists the Registers to Be Used and Settings in IE Mode. Figure 17.33 shows the Bus Collision
Detect Function-Related BitsBus Collision Detect Function-Related Bits.
If the TXDi pin (i = 0 to 2) output level and RXDi pin input level do not match, a UARTi bus collision detect
interrupt request is generated.
Use the IFSR26 and IFSR27 bits in the IFSR2A register to enable the UART0/UART1 bus collision detect
function.
Table 17.17
Register
UiTB
UiRB (3)
UiBRG
UiMR
UiC0
UiC1
UiSMR
UiSMR2
UiSMR3
UiSMR4
IFSR2A
UCON
Registers to Be Used and Settings in IE Mode
Bit
0 to 8
0 to 8
OER, FER, PER, SUM
0 to 7
SMD2 to SMD0
CKDIR
STPS
PRY
PRYE
IOPOL
CLK1, CLK0
CRS
TXEPT
CRD
NCH
CKPOL
UFORM
TE
TI
RE
RI
U2IRS (1)
U2RRM (1),
UiLCH, UiERE
0 to 3, 7
ABSCS
ACSE
SSS
0 to 7
0 to 7
0 to 7
IFSR26, IFSR27
U0IRS, U1IRS
U0RRM, U1RRM
CLKMD0
CLKMD1, RCSP, 7
Function
Set transmission data
Reception data can be read
Error flag
Set a bit rate
Set to “110b”
Select the internal clock or external clock
Set to “0”
Invalid because PRYE=0
Set to “0”
Select the TXD/RXD input/output polarity
Select the count source for the UiBRG register
Invalid because CRD=1
Transmit register empty flag
Set to “1”
Select TXDi pin output mode (2)
Set to “0”
Set to “0”
Set this bit to “1” to enable transmission
Transmit buffer empty flag
Set this bit to “1” to enable reception
Reception complete flag
Select the source of UART2 transmit interrupt
Set to “0”
Set to “0”
Select the sampling timing at which to detect a bus collision
Set this bit to “1” to use the auto clear function of transmit enable bit
Select the transmit start condition
Set to “0”
Set to “0”
Set to “0”
Set to “1”
Select the source of UART0/UART1 transmit interrupt
Set to “0”
Invalid because CLKMD1 = 0
Set to “0”
NOTES:
1. Set the bit 4 and bit 5 in the U0C0 and U1C1 registers to “0”. The U0IRS, U1IRS, U0RRM and U1RRM bits are
in the UCON register.
2. TXD2 pin is N channel open-drain output. No NCH bit in the U2C0 register is assigned. When write, set to “0”.
3. Not all register bits are described above. Set those bits to “0” when writing to the registers in IE mode.
i= 0 to 2
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M16C/62P Group (M16C/62P, M16C/62PT)
17. Serial Interface
(1) The ABSCS Bit in the UiSMR Register (Bus collision detect sampling clock select)
(i=0 to 2)
If ABSCS=0, bus collision is determined at the rising edge of the transfer clock
Transfer clock
ST
D0
D1
D2
D3
D4
D5
D6
D7
D8
SP
TXDi
RXDi
Trigger signal is applied to the TAjIN pin
Timer Aj
If ABSCS=1, bus collision is determined when timer
Aj (one-shot timer mode) underflows.
Timer Aj: Timer A3 when UART0; Timer A4 when UART1; Timer A0 when UART2
(2) The ACSE Bit in the UiSMR Register (Auto clear of transmit enable bit)
Transfer clock
ST
D0
D1
D2
D3
D4
D5
D6
D7
D8
SP
TXDi
RXDi
IR bit in UiBCNIC
register (1)
If ACSE bit = 1 (automatically
clear when bus collision occurs), the
TE bit is cleared to “0”
(transmission disabled) when the
IR bit in the UiBCNIC register= 1
(unmatching detected).
TE bit in UiC1
register
NOTES :
1. BCNIC register when UART2.
(3) The SSS Bit in the UiSMR Register (Transmit start condition select)
If SSS bit = 0, the serial interface starts sending data one transfer clock cycle after the transmission enable condition is met.
Transfer clock
ST
D0
D1
D2
D3
D4
D5
D6
D7
D8
SP
D5
D6
D7
D8
SP
TXDi
Transmission enable condition is met
If SSS bit = 1, the serial interface starts sending data at the rising edge
(1)
of RXDi
CLKi
ST
TXDi
D0
D1
D2
D3
D4
(NOTE 2)
RXDi
NOTES :
1. The falling edge of RXDi when IOPOL=0; the rising edge of RXDi when IOPOL =1.
2. The transmit condition must be met before the falling edge (1) of RXD.
This diagram applies to the case where IOPOL=1 (reversed).
Figure 17.33
Bus Collision Detect Function-Related Bits
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M16C/62P Group (M16C/62P, M16C/62PT)
17.1.6
17. Serial Interface
Special Mode 4 (SIM Mode) (UART2)
Based on UART mode, this is an SIM interface compatible mode. Direct and inverse formats can be
implemented, and this mode allows to output a low from the TXD2 pin when a parity error is detected.
Table 17.18 lists the SIM Mode Specifications. Table 17.19 lists the Registers to Be Used and Settings in SIM
Mode.
Table 17.18
SIM Mode Specifications
Item
Transfer Clock
Specification
• Direct format
• Inverse format
• CKDIR bit in U2MR register = 0 (internal clock) : fi/ (16(n+1))
• fi = f1SIO, f2SIO, f8SIO, f32SIO n: Setting value of U2BRG register 00h to FFh
• CKDIR bit = 1 (external clock) : fEXT/(16(n+1))
fEXT: Input from CLK2 pin n: Setting value of U2BRG register 00h to FFh
Transmission Start
Condition
Before transmission can start, meet the following requirements
• The TE bit in the U2C1 register = 1 (transmission enabled)
• The TI bit in the U2C1 register = 0 (data present in U2TB register)
Reception Start Condition
Before reception can start, meet the following requirements
• The RE bit in the U2C1 register = 1 (reception enabled)
• Start bit detection
• For transmission
When the serial interface finished sending data from the U2TB transfer register
(U2IRS bit =1)
• For reception
When transferring data from the UART2 receive register to the U2RB register (at
completion of reception)
Transfer Data Format
Interrupt Request
Generation Timing (2)
Error Detection
• Overrun error (1)
This error occurs if the serial interface started receiving the next data before reading
the U2RB register and received the bit one before the last stop bit of the next data
• Framing error (3)
This error occurs when the number of stop bits set is not detected
• Parity error (3)
During reception, if a parity error is detected, parity error signal is output from the
TXD2 pin.
During transmission, a parity error is detected by the level of input to the RXD2 pin
when a transmission interrupt occurs
• Error sum flag
This flag is set (= 1) when any of the overrun, framing, and parity errors is
encountered
NOTES:
1. If an overrun error occurs, the value of U2RB register will be indeterminate. The IR bit in the S2RIC register
does not change.
2. A transmit interrupt request is generated by setting the U2IRS bit to “1” (transmission complete) and U2ERE bit
to “1” (error signal output) in the U2C1 register after reset is deserted. Therefore, when using SIM mode, set the
IR bit to “0” (no interrupt request) after setting these bits.
3. The timing at which the framing error flag and the parity error flag are set is detected when data is transferred
from the UARTi receive register to the UiRB register.
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M16C/62P Group (M16C/62P, M16C/62PT)
Table 17.19
Register
U2TB (1)
U2RB (1)
U2BRG
U2MR
U2C0
U2C1
U2SMR (1)
U2SMR2
U2SMR3
U2SMR4
17. Serial Interface
Registers to Be Used and Settings in SIM Mode
Bit
0 to 7
0 to 7
OER,FER,PER,SUM
0 to 7
SMD2 to SMD0
CKDIR
STPS
PRY
PRYE
IOPOL
CLK1, CLK0
CRS
TXEPT
CRD
NCH
CKPOL
UFORM
TE
TI
RE
RI
U2IRS
U2RRM
U2LCH
U2ERE
0 to 3
0 to 7
0 to 7
0 to 7
Function
Set transmission data
Reception data can be read
Error flag
Set a bit rate
Set to “101b”
Select the internal clock or external clock
Set to “0”
Set this bit to “1” for direct format or “0” for inverse format
Set to “1”
Set to “0”
Select the count source for the U2BRG register
Invalid because CRD = 1
Transmit register empty flag
Set to “1”
Set to “0”
Set to “0”
Set this bit to “0” for direct format or “1” for inverse format
Set this bit to “1” to enable transmission
Transmit buffer empty flag
Set this bit to “1” to enable reception
Reception complete flag
Set to “1”
Set to “0”
Set this bit to “0” for direct format or “1” for inverse format
Set to “1”
Set to “0”
Set to “0”
Set to “0”
Set to “0”
NOTES:
1. Not all register bits are described above. Set those bits to “0” when writing to the registers in SIM mode.
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M16C/62P Group (M16C/62P, M16C/62PT)
17. Serial Interface
(1) Transmit Timing
Tc
Transfer clock
“1”
TE bit in U2C1
register
“0”
(Note 1)
Data is written to the UARTi register
“1”
TI bit in U2C1
register
“0”
Start
bit
TXD2
ST
D0
Stop
bit
Parity
bit
D1
D2
D3
D4
D5
D7
D6
P
Data is transferred from the UiTB
register to the UARi transmit register
ST
SP
Parity Error signal
returned from
Receiving end
D0
D1
D2
D3
D4
D5
D6
D7
P
SP
An “L” signal is applied from the
SIM card due to a parity error
RXD2 pin level (2)
ST
D0
D1
D2
D3
D4
D5
D7
D6
P
ST
SP
D0
D1
D2
D3
D4
An interrupt routine
detects “H” or “L”
TXEPT bit in U2C0 “1”
register
“0”
D5
D6
D7
SP
P
An interrupt routine detects “H” or “L”
“1”
IR bit in S2TIC
register
“0”
The above timing diagram applies to the case where data is
transferred in the direct format.
• STPS bit in U2MR register = 0 (1 stop bit)
• PRY bit in U2MR register = 1 (even)
• UFORM bit in U2C0 register = 0 (LSB first)
• U2LCH bit in U2C1 register = 0 (no reverse)
• U2IRSCH bit in U2C1 register = 1 (transmit is completed)
Set to “0” by an interrupt request acknowledgement or by program
TC = 16 (n + 1) / fi or 16 (n + 1) / fEXT
fi : frequency of U2BRG count source (f1SIO, f2SIO, f8SIO, f32SIO)
fEXT : frequency of U2BRG count source (external clock)
n : value set to U2BRG
(2) Receive Timing
Tc
Transfer clock
RE bit in U2C1
register
“1”
“0”
Transmit Waveform
from the
Transmitting end
ST
Stop
bit
Parity
bit
Start
bit
D0
D1
D2
D3
D4
D5
D6
D7
P
ST
SP
D0
D1
D2
D3
D4
D5
D6
D7
P
SP
TXD2
TxD2 provides “L” output
due to a parity error
RXD2 pin level (1)
ST
RI bit in U2C0
register
“1”
IR bit in S2RIC
register
“1”
D0
D1
D2
D3
D4
D5
D6
D7
P
ST
SP
D0
D1
D2
D3
D4
D5
D6
D7
P
“0”
Read the U2RB register
“0”
The above timing diagram applies to the case where data is
transferred in the direct format.
• STPS bit in U2MR register = 0 (1 stop bit)
• PRY bit in U2MR register = 1 (even)
• UFORM bit in U2C0 register = 0 (LSB first)
• U2LCH bit in U2C1 register = 0 (no reverse)
• U2IRSCH bit in U2C1 register = 1 (transmit is completed)
Set to “0” by an interrupt request acknowledgement or by program
TC = 16 (n + 1) / fi or 16 (n + 1) / fEXT
fi : frequency of U2BRG count source
(f1SIO, f2SIO, f8SIO, f32SIO)
fEXT : frequency of U2BRG count source (external clock)
n : value set to U2BRG
NOTES:
1. Data transmission starts when BRG overflows after a value is set to the U2TB register on the rising edge of the TI bit.
2. Because the TxD2 and RxD2 pins are connected, a composite waveform, consisting of transmit waveform from the
TxD2 pin and parity error signal from the receiving end, is generated.
3. Because the TxD2 and RxD2 pins are connected, a composite waveform, consisting of transmit waveform from the
transmitting end and parity error signal from the TxD2 pin, is generated.
Figure 17.34
SP
Transmit and Receive Timing in SIM Mode
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M16C/62P Group (M16C/62P, M16C/62PT)
17. Serial Interface
Microcomputer
SIM card
TXD2
RXD2
Figure 17.35
17.1.6.1
SIM Interface Connection
Parity Error Signal Output
The parity error signal is enabled by setting the U2ERE bit in the U2C1 register to “1”.
The parity error signal is output when a parity error is detected while receiving data. This is achieved by pulling
the TXD2 output low with the timing shown in Figure 17.36. If the R2RB register is read while outputting a
parity error signal, the PER bit is cleared to “0” and at the same time the TXD2 output is returned high.
When transmitting, a transmission-finished interrupt request is generated at the falling edge of the transfer clock
pulse that immediately follows the stop bit. Therefore, whether a parity signal has been returned can be
determined by reading the port that shares the RXD2 pin in a transmission-finished interrupt routine.
Transfer
clock
RXD2
TXD2
IR bit in U2C1
register
“H”
“L”
“H”
“L”
ST
D0
D1
D2
“H”
D3
D4
D5
D6
D7
(NOTE 1)
“1”
“0”
NOTES :
1. The output of microcomputer is in the high-impedance state
(pulled up externally).
Parity Error Signal Output Timing
Rev.2.41 Jan 10, 2006
REJ09B0185-0241
SP
“L”
This timing diagram applies to the case where the direct format is
implemented.
Figure 17.36
P
Page 225 of 390
ST : Start bit
P : Even Parity
SP : Stop bit
M16C/62P Group (M16C/62P, M16C/62PT)
17.1.6.2
17. Serial Interface
Format
When direct format, set the PRYE bit in the U2MR register to “1”, the PRY bit to “1”, the UFORM bit in the
U2C0 register to “0” and the U2LCH bit in the U2C1 register to “0”. When data are transmitted, data set in the
U2TB register are transmitted with the even-numbered parity, starting from D0. When data are received,
received data are stored in the U2RB register, starting from D0. The even-numbered parity determines whether
a parity error occurs.
When inverse format, set the PRYE bit to “1”, the PRY bit to “0”, the UFORM bit to “1” and the U2LCH bit to
“1”. When data are transmitted, values set in the U2TB register are logically inversed and are transmitted with
the odd-numbered parity, starting from D7. When data are received, received data are logically inversed to be
stored in the U2RB register, starting from D7. The odd-numbered parity determines whether a parity error
occurs.
(1) Direct format
Transfer
clcck
“H”
“L”
TXD2
“H”
“L”
D0
D1
D2
D3
D4
D5
D6
D7
P
P : Even parity
(2) Inverse format
Transfer
clcck
TXD2
“H”
“L”
“H”
“L”
D7
D6
D5
D4
D3
D2
D1
D0
P
P : Odd parity
Figure 17.37
SIM Interface Format
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M16C/62P Group (M16C/62P, M16C/62PT)
17.2
17. Serial Interface
SI/O3 and SI/O4
Note
The M16C/62P (80-pin version) and M16C/62PT (80-pin version) do not include SIN3 pin of SI/O3. SI/O3
is only for transmission. Reception is impossible.
SI/O3 and SI/O4 are exclusive clock-synchronous serial I/Os.
Figure 17.38 shows the SI/O3 and SI/O4 Block Diagram, and Figure 17.39 to Figure 17.40 show the SI/O3 and SI/O4related registers.
Table 17.20 shows the SI/O3 and SI/O4 Specifications.
.
1/2
Main clock,
f1SIO
PLL clock,
or on-chip oscillator clock
Clock source select
SMi1 to SMi0
f2SIO PCLK1=0
1/8
PCLK1=1
1/4
f8SIO
01b
f32SIO
10b
Synchronous
circuit
SMi4
CLKi
CLK
polarity
reversing
circuit
Data bus
00b
SMi3
SMi6
1/(n+1)
1/2
SiBRG register
SMi6
SI/O counter i
SMi2
SMi3
SMi5 LSB
SOUTi
MSB
SiTRR register
SINi
8
NOTES :
1. i = 3, 4.
n = A value set in the SiBRG register.
Figure 17.38
SI/O3 and SI/O4 Block Diagram
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SI/Oi
interrupt request
M16C/62P Group (M16C/62P, M16C/62PT)
17. Serial Interface
SI/Oi Control Register (i=3, 4) (1)
b7 b6 b5 b4 b3 b2 b1 b0
Address
Symbol
0362h
S3C
0366h
S4C
Bit Symbol
Bit Name
Internal Synchronous
Clock Select Bit(6)
SMi0
SMi1
SMi2
SMi3
SMi6
RW
b1 b0
0 0 : Selecting f1SIO or f2SIO (5)
0 1 : Selecting f8SIO
1 0 : Selecting f32SIO
1 1 : Do not set to this value
RW
RW
SOUTi Output Disable Bit (4)
0 : SOUTi output
1 : SOUTi output disable (High-Impedance)
RW
S I/Oi Port Select Bit
0 : Input/output port
1 : SOUTi output, CLKi function
RW
CLK Polarity Select Bit
0 : Transmit data is output at falling edge of transfer
clock and receive data is input at rising edge
1 : Transmit data is output at rising edge of transfer
clock and receive data is input at falling edge
RW
Transfer Direction Select Bit
0 : LSB first
1 : MSB first
RW
Synchronous Clock
Select Bit
0 : External clock (2)
1 : Internal clock (3)
RW
SOUTi Initial Value Set Bit
Effective w hen SMi3 = 0
0 : “L” output
1 : “H” output
RW
SMi4
SMi5
After Reset
01000000b
01000000b
Function
SMi7
NOTES :
1. Make sure this register is w ritten to by the next instruction after setting the PRC2 bit in the PRCR register to “1” (w rite
enable).
2. Set the SMi3 bit to “1” and the corresponding port direction bit to “0” (input mode).
3. Set the SMi3 bit to “1” (SOUTi output, CLKi function).
4. When the SMi2 bit is set to “1,” the target pin goes to a high-impedance state regardless of w hich function of the pin is
being used.
5. Selected by PCLK1 bit in the PCLKR register.
6. When changing the SMi1 to SMi0 bits, set the SiBRG register.
Figure 17.39
SiC Register
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M16C/62P Group (M16C/62P, M16C/62PT)
17. Serial Interface
SI/Oi Bit Rate Generation Register (i=3, 4) (1, 2, 3)
b7
b0
Symbol
S3BRG
S4BRG
Address
0363h
0367h
Function
After Reset
Indeterminate
Indeterminate
Setting Range
Assuming that set value = n, BRGi divides the count source by n + 1
00h to FFh
RW
WO
NOTES :
1. Write to this register w hile serial interface is neither transmitting nor receiving.
2. Use MOV instruction to w rite to this register.
3. Write to this register after setting the SMi1 to SMi0 bits in the SiC register.
SI/Oi Bit Transmit/Receive Register (i=3, 4) (1, 2)
b7
b0
Symbol
S3TRR
S4TRR
Address
0360h
0364h
After Reset
Indeterminate
Indeterminate
Function
Transmission/reception starts by w riting transmit data to this register. After
transmission/reception finishes, reception data can be read by reading this register.
NOTES :
1. Write to this register w hile serial interface is neither transmitting nor receiving.
2. To receive data, set the corresponding port direction bit for SINi to “0” (input mode).
Figure 17.40
SiBRG and SiTRR Registers
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RW
RW
M16C/62P Group (M16C/62P, M16C/62PT)
17. Serial Interface
Table 17.20 SI/O3 and SI/O4 Specifications
Item
Specification
Transfer Data Format
• Transfer data length: 8 bits
Transfer Clock
• SMi6 bit in SiC (i=3, 4) register = 1 (internal clock) : fj/ (2(n+1))
fj = f1SIO, f8SIO, f32SIO. n = Setting value of SiBRG register 00h to FFh.
• SMi6 bit = 0 (external clock) : Input from CLKi pin (1)
Transmission/Reception • Before transmission/reception can start, meet the following requirements
Start Condition
Write transmit data to the SiTRR register (2, 3)
Interrupt Request
• When SMi4 bit in SiC register = 0
The rising edge of the last transfer clock pulse (4)
Generation Timing
When SMi4 = 1
The falling edge of the last transfer clock pulse (4)
CLKi Pin Function
SOUTi Pin Function
SINi Pin Function
Select Function
I/O port, transfer clock input, transfer clock output
I/O port, transmit data output, high-impedance
I/O port, receive data input
• LSB first or MSB first selection
Whether to start sending/receiving data beginning with bit 0 or beginning with
bit 7 can be selected
• Function for setting an SOUTi initial value set function
When the SMi6 bit in the SiC register = 0 (external clock), the SOUTi pin output
level while not transmitting can be selected.
• CLK polarity selection
Whether transmit data is output/input timing at the rising edge or falling edge
of transfer clock can be selected.
NOTES:
1. To set SMi6 bit to “0” (external clock), follow the procedure described below.
• If the SMi4 bit = 0, write transmit data to the SiTRR register while input on the CLKi pin is high. The
same applies when rewriting the SMi7 bit in the SiC register.
• If the SMi4 bit = 1, write transmit data to the SiTRR register while input on the CLKi pin is low. The
same applies when rewriting the SMi7 bit.
• Because shift operation continues as long as the transfer clock is supplied to the SI/Oi circuit, stop
the transfer clock after supplying eight pulses. If the SMi6 bit = 1 (internal clock), the transfer clock
automatically stops.
2. Unlike UART0 to UART2, SI/Oi (i = 3 to 4) is not separated between the transfer register and buffer.
Therefore, do not write the next transmit data to the SiTRR register during transmission.
3. When SMi6 bit = 1 (internal clock), SOUTi retains the last data for a 1/2 transfer clock period after
completion of transfer and, thereafter, goes to a high-impedance state. However, if transmit data is
written to the SiTRR register during this period, SOUTi immediately goes to a high-impedance state,
with the data hold time thereby reduced.
4. When the SMi6 bit = 1 (internal clock), the transfer clock stops in the high state if the SMi4 bit = 0, or
stops in the low state if the SMi4 bit = 1.
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M16C/62P Group (M16C/62P, M16C/62PT)
17.2.1
17. Serial Interface
SI/Oi Operation Timing
Figure 17.41 shows the SI/Oi Operation Timing.
0.5 to 1.0 cycle (max.)(3)
"H"
SI/Oi internal clock "L"
CLKi output "H"
"L"
Signal written to the "H"
SiTRR register "L"
(NOTE 2)
SOUTi output "H"
D0
"L"
D1
D2
D3
D4
D5
D6
D7
SINi input "H"
"L"
SiIC register "1"
IR bit "0"
i= 3, 4
NOTES :
1. This diagram applies to the case where the SiC register bits are set as follows:
SMi2=0 (SOUTi output), SMi3=1 (SOUTi output, CLKi function), SMi4=0 (transmit data output at the falling edge and receive data input at
the rising edge of the transfer clock), SMi5=0 (LSB first) and SMi6=1 (internal clock)
2. When the SMi6 bit = 1 (internal clock), the SOUTi pin is placed in the high-impedance state after the transfer finishes.
3. If the SMi6 bit=0 (internal clock), the serial I/O starts sending or receiving data a maximum of 0.5 to 1.0 transfer clock cycles after writing to the
SiTRR register.
Figure 17.41
17.2.2
SI/Oi Operation Timing
CLK Polarity Selection
The SMi4 bit in the SiC register allows selection of the polarity of the transfer clock. Figure 17.42 shows the
Polarity of Transfer Clock.
(1) When the SMi4 bit in the SiC register = 0
CLKi
(NOTE 2)
SOUTi
D0
D1
D2
D3
D4
D5
D6
D7
SINi
D0
D1
D2
D3
D4
D5
D6
D7
(2) When the SMi4 bit = 1
(NOTE 3)
CLKi
SOUTi
D0
D1
D2
D3
D4
D5
D6
D7
SINi
D0
D1
D2
D3
D4
D5
D6
D7
i=3 and 4
NOTES:
1. This diagram applies to the case where the SiC register bits are set as follows:
SMi5=0 (LSB first) and SMi6=1 (internal clock)
2. When the SMi6 bit=1 (internal clock), a high level is output from the CLKi
pin if not transferring data.
3. When the SMi6 bit=1 (internal clock), a low level is output from the CLKi
pin if not transferring data.
Figure 17.42
Polarity of Transfer Clock
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M16C/62P Group (M16C/62P, M16C/62PT)
17.2.3
17. Serial Interface
Functions for Setting an SOUTi Initial Value
If the SMi6 bit in the SiC register = 0 (external clock), the SOUTi pin output can be fixed high or low when not
transferring. However, the last bit value of the former data is retained between data and data when transmitting
the continuous data. Figure 17.43 shows the timing chart for setting an SOUTi initial value and how to set it.
(Example) When “H” Selected for SOUTi Initial Value (1)
Signal written to
SiTRR register
Setting of the initial value of SOUTi
output and starting of transmission/
reception
SMi7 bit
Set the SMi3 bit to “0”
(SOUTi pin functions as an I/O port)
Set the SMi7 bit to “1”
(SOUTi initial value = H)
SMi3 bit
D0
SOUTi (internal)
Set the SMi3 bit to “1”
(SOUTi pin functions as
SOUTi output)
“H” level is output
from the SOUTi pin
D0
Port output
SOUTi pin output
Write to the SiTRR register
Initial value = H
(3)
(i = 3, 4)
Setting the SOUTi Port selection switching
initial value to “H” (2) (I/O port → SOUTi)
NOTES:
1. This diagram applies to the case where the bits in the SiC register are set as follows:
SMi2 = 0 (SOUTi output), SMi5 = 0 (LSB first) and SMi6 = 0 (external clock)
2. SOUTi can only be initialized when input on the CLKi pin is in the high state if the
SMi4 bit in the SiC register = 0 (transmit data output at the falling edge of the transfer clock)
or in the low state if the SMi4 bit = 1 (transmit data output at the rising edge of the
transfer clock).
3. If the SMi6 bit = 1 (internal clock) or if the SMi2 bit = 1 (SOUT output disabled),
this output goes to the high-impedance state.
Figure 17.43
SOUTi’s Initial Value Setting
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Serial transmit/reception starts
M16C/62P Group (M16C/62P, M16C/62PT)
18. A/D Converter
18. A/D Converter
The microcomputer contains one A/D converter circuit based on 10-bit successive approximation method configured
with a capacitive-coupling amplifier. The analog inputs share the pins with P10_0 to P10_7, P9_5, P9_6, and P0_0 to
P0_7, and P2_0 to P2_7. Similarly, ADTRG input shares the pin with P9_7. Therefore, when using these inputs, make
sure the corresponding port direction bits are set to “0” (= input mode).
When not using the A/D converter, set the VCUT bit to “0” (= Vref unconnected), so that no current will flow from the
VREF pin into the resistor ladder, helping to reduce the power consumption of the chip.
The A/D conversion result is stored in the ADi register bits for ANi, AN0_i, and AN2_i pins (i = 0 to 7).
Table 18.1 shows the Performance of A/D Converter. Figure 18.1 shows the A/D Converter Block Diagram, and
Figures 18.2 and 18.3 show the A/D converter-related registers.
Table 18.1
Performance of A/D Converter
Item
Performance
Method of A/D Conversion Successive approximation (capacitive coupling amplifier)
Analog input Voltage (1)
0V to AVCC (VCC1)
fAD/divide-by-2 of fAD/divide-by-3 of fAD/divide-by-4 of fAD/divide-by-6 of
Operating clock φAD (2)
fAD/divide-by-12 of fAD
Resolution
8-bit or 10-bit (selectable)
Integral Nonlinearity Error When AVCC = VREF = 5V
• With 8-bit resolution: ±2LSB
• With 10-bit resolution
AN0 to AN7 input, AN0_0 to AN0_7 input and AN2_0 to AN2_7 input : 3LSB
ANEX0 and ANEX1 input (including mode in which external Op-Amp is connected)
: ±7LSB
When AVCC = VREF = 3.3V
• With 8-bit resolution: ±2LSB
• With 10-bit resolution
AN0 to AN7 input, AN0_0 to AN0_7 input and AN2_0 to AN2_7 input : ±5LSB
ANEX0 and ANEX1 input (including mode in which external Op-Amp is connected)
: ±7LSB
Operating Modes
One-shot mode, repeat mode, single sweep mode, repeat sweep mode 0,
and repeat sweep mode 1
8 pins (AN0 to AN7) + 2 pins (ANEX0 and ANEX1) + 8 pins (AN0_0 to AN0_7)
Analog Input Pins (3)
+ 8 pins (AN2_0 to AN2_7)
A/D Conversion Start
• Software trigger
Condition
The ADST bit in the ADCON0 register is set to “1” (A/D conversion starts)
• External trigger (retriggerable)
Input on the ADTRG pin changes state from high to low after the ADST bit is set to “1”
(A/D conversion starts)
Conversion Speed
• Without sample and hold function
8-bit resolution: 49 φAD cycles, 10-bit resolution: 59 φAD cycles
• With sample and hold function
8-bit resolution: 28 φAD cycles, 10-bit resolution: 33 φAD cycles
NOTES:
1. Does not depend on use of sample and hold function.
2. φAD frequency must be 12 MHz or less. And divide the fAD if VCC1 is less than 4.0V, and φAD frequency into
10 MHz or less.
When sample & hold is disabled, φAD frequency must be 250kHz or more.
When sample & hold is enabled, φAD frequency must be 1MHz or more.
3. If VCC2 < VCC1, do not use AN0_0 to AN0_7 and AN2_0 to AN2_7 as analog input pins.
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M16C/62P Group (M16C/62P, M16C/62PT)
18. A/D Converter
A/D conversion rate selection
0
1/3
fAD
Software trigger
CKS2
VREF
0
AVSS
1
1/2
φAD
0
0
CKS
TRG
A/D trigger
1
ADTRG
CKS1
1
1/2
1
0
1
Resistor ladder
VCUT
Successive conversion register
ADCON1 register
ADCON0 register
AD0 register (16)
AD1 register (16)
AD2 register (16)
AD3 register (16)
AD4 register (16)
AD5 register (16)
AD6 register (16)
AD7 register (16)
Decoder
for A/D register
Data bus high-order
ADCON2 register
Data bus low-order
(1)
PM00
PM01
Vref
Decoder
for channel
selection
VIN
Port P0 group
CH2 to CH0
=000b
=001b
=010b
=011b
=100b
=101b
=110b
=111b
AN0_0
AN0_1
AN0_2
AN0_3
AN0_4
AN0_5
AN0_6
AN0_7
Port P2 group
AN2_0
AN2_1
AN2_2
AN2_3
AN2_4
AN2_5
AN2_6
AN2_7
CH2 to CH0
=000b
=001b
=010b
=011b
=100b
=101b
=110b
=111b
Port P10 group
AN0
AN1
AN2
AN3
AN4
AN5
AN6
AN7
ANEX1
ADGSEL1 to ADGSEL0=00b
OPA1 to OPA0=00b
PM01 to PM00=00b
ADGSEL1 to ADGSEL0=10b
OPA1 to OPA0=00b
PM01 to PM00=00b
ADGSEL1 to ADGSEL0=11b
OPA1 to OPA0=00b
ADGSEL1 to ADGSEL0=00b
OPA1 to OPA0=11b
PM01 to PM00=00b
ADGSEL1 to ADGSEL0=10b
OPA1 to OPA0=11b
PM01 to PM00=00b
ADGSEL1 to ADGSEL0=11b
OPA1 to OPA0=11b
ANEX0
CH2 to CH0
=000b
=001b
=010b
=011b
=100b
=101b
=110b
=111b
OPA0=1
OPA1 to OPA0
=01b
OPA1=1
OPA1=1
NOTES :
1. Port P0 group (AN0_0 to AN0_7) can be used as analog input pins even when PM01 to PM00 bits
are set to “01b” (memory expansion mode) and PM05 to PM04 bits are set to “11b” (multiplex bus
allocated to the entire CS space).
Figure 18.1
A/D Converter Block Diagram
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Comparator
M16C/62P Group (M16C/62P, M16C/62PT)
18. A/D Converter
A/D Control Register 0 (1)
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
ADCON0
Bit Symbol
CH0
CH1
CH2
Address
03D6h
Bit Name
Function varies w ith each operation mode
A/D Operation Mode Select Bit 0
b4 b3
0 0 : One-shot mode
0 1 : Repeat mode
1 0 : Single sw eep mode
1 1 : Repeat sw eep mode 0 or
Repeat sw eep mode 1
MD1
ADST
CKS0
Function
Analog Input Pin Select Bit
MD0
TRG
After Reset
00000XXXb
Trigger Select Bit
0 : Softw are trigger
A/D Conversion Start Flag
1 : ADTRG trigger
0 : A/D conversion disabled
1 : A/D conversion started
Frequency Select Bit 0
Refer to NOTE 3 for the ADCON2 Register
________
RW
RW
RW
RW
RW
RW
RW
RW
RW
NOTES :
1. If the ADCON0 register is rew ritten during A/D conversion, the conversion result w ill be indeterminate.
A/D Control Register 1 (1)
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
ADCON1
Symbol
SCAN0
SCAN1
MD2
BITS
CKS1
VCUT
OPA0
OPA1
Address
03D7h
Address
A/D Sw eep Pin Select Bit
After Reset
00h
After Reset
Function varies w ith each operation mode
A/D Operation Mode Select Bit 1 0 : Any mode other than repeat sw eep mode 1
1 : Repeat sw eep mode 1
RW
RW
RW
RW
8/10-Bit Mode Select Bit
0 : 8-bit mode
1 : 10-bit mode
Frequency Select Bit 1
Vref Connect Bit (2)
Refer to NOTE 3 for the ADCON2 Register
0 : Vref not connected
1 : Vref connected
RW
External Op-Amp Connection
Mode Bit
Function varies w ith each operation mode
RW
RW
RW
RW
NOTES :
1. If the ADCON1 register is rew ritten during A/D conversion, the conversion result w ill be indeterminate.
2. If the VCUT bit is reset from “0” (Vref unconnected) to “1” (Vref connected), w ait for 1 µs or more before starting
A/D conversion.
Figure 18.2
ADCON0 to ADCON1 Registers
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M16C/62P Group (M16C/62P, M16C/62PT)
18. A/D Converter
A/D Control Register 2 (1)
b7 b6 b5 b4 b3 b2 b1 b0
0
Symbol
ADCON2
Address
03D4h
After Reset
00h
Bit Symbol
Bit Name
Function
SMP
A/D Conversion Method Select 0 : Without sample and hold
Bit
1 : With sample and hold
A/D Input Group Select Bit
ADGSEL0
—
(b3)
Reserved Bit
Set to “0”
Frequency Select Bit 2 (3)
0: Selects fAD, fAD divided by 2, or fAD
divided by 4.
1: Selects fAD divided by 3, fAD divided
by 6, or fAD divided by 12.
CKS2
—
(b7-b5)
RW
b2 b1
0 0 : Port P10 group is selected
0 1 : Do not set
1 0 : Port P0 group is selected (2)
1 1 : Port P2 group is selected
ADGSEL1
RW
Nothing is assigned.
When w rite, set to “0”. When read, their contents are “0”.
RW
RW
RW
RW
—
NOTES :
1. If the ADCON2 register is rew ritten during A/D conversion, the conversion result w ill be indeterminate.
2. If VCC2 < VCC1, do not use AN0_0 to AN0_7 and AN2_0 to AN2_7 as analog input pins.
3. The ØAD frequency must be 12 MHz or less. The selected ØAD frequency is determined by a combination of the CKS0
bit in the ADCON0 register, the CKS1 bit in the ADCON1 register, and the CKS2 bit in the ADCON2 register.
CKS2
0
0
0
0
1
1
1
1
Figure 18.3
CKS1
0
0
1
1
0
0
1
1
CKS0
0
1
0
1
0
1
0
1
ADCON2 Register
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ØAD
Divide-by-4 of fAD
Divide-by-2 of fAD
fAD
Ddivide-by-12 of fAD
Divide-by-6 of fAD
Divide-by-3 of fAD
M16C/62P Group (M16C/62P, M16C/62PT)
18. A/D Converter
A/D Register i (i=0 to 7)
(b15)
b7
(b8)
b0 b7
b0
Symbol
AD0
AD1
AD2
AD3
AD4
AD5
AD6
AD7
Address
03C1h to 03C0h
03C3h to 03C2h
03C5h to 03C4h
03C7h to 03C6h
03C9h to 03C8h
03CBh to 03CAh
03CDh to 03CCh
03CFh to 03CEh
After Reset
Indeterminate
Indeterminate
Indeterminate
Indeterminate
Indeterminate
Indeterminate
Indeterminate
Indeterminate
Function
When the BITS bit in the ADCON1
register is “1” (10-bit mode)
When the BITS bit is “0”
(8-bit mode)
Eight low -order bits of A/D conversion
result
A/D conversion result
Tw o high-order bits of A/D conversion
result
When read, the content is indeterminate
Nothing is assigned.
When w rite, set to “0”. When read, their contents are “0”.
Figure 18.4
AD0 to AD7 Registers
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RW
RW
RO
RO
—
M16C/62P Group (M16C/62P, M16C/62PT)
18.1
18. A/D Converter
Mode Description
18.1.1
One-Shot Mode
In one-shot mode, analog voltage applied to a selected pin is converted to a digital code once. Table 18.2 shows
the One-Shot Mode Specifications. Figure 18.5 shows the ADCON0 and ADCON1 Registers (One-shot Mode).
Table 18.2
One-Shot Mode Specifications
Item
Function
A/D Conversion Start
Condition
A/D Conversion Stop
Condition
Interrupt Request
Generation Timing
Analog Input Pin (1)
Specification
The CH2 to CH0 bits in the ADCON0 register, the ADGSEL1 to ADGSEL0 bits
in the ADCON2 register and the OPA1 to OPA0 bits in the ADCON1 register
select a pin. Analog voltage applied to the pin is converted to a digital code
once.
• When the TRG bit in the ADCON0 register is “0” (software trigger)
The ADST bit in the ADCON0 register is set to “1” (A/D conversion starts)
• When the TRG bit is “1” (ADTRG trigger)
Input on the ADTRG pin changes state from high to low after the ADST bit is
set to “1” (A/D conversion starts)
• Completion of A/D conversion (If a software trigger is selected, the ADST bit
is cleared to “0” (A/D conversion halted))
• Set the ADST bit to “0”
Completion of A/D conversion
Select one pin from AN0 to AN7, AN0_0 to AN0_7, AN2_0 to AN2_7,
ANEX0 to ANEX1
Reading of Result of A/D Read one of the AD0 to AD7 registers that corresponds to the selected pin
Converter
NOTES:
1. If VCC2 < VCC1, do not use AN0_0 to AN0_7 and AN2_0 to AN2_7 as analog input pins.
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M16C/62P Group (M16C/62P, M16C/62PT)
18. A/D Converter
A/D Control Register 0 (1)
b7 b6 b5 b4 b3 b2 b1 b0
0 0
Symbol
ADCON0
Address
03D6h
Bit Symbol
Bit Name
Analog Input Pin Select Bit
After Reset
00000XXXb
Function
(2, 3)
CH1
CH2
MD0
MD1
TRG
ADST
CKS0
b2 b1 b0
0 0 0 : AN0 is
0 0 1 : AN1 is
0 1 0 : AN2 is
0 1 1 : AN3 is
1 0 0 : AN4 is
1 0 1 : AN5 is
1 1 0 : AN6 is
1 1 1 : AN7 is
CH0
RW
selected
selected
selected
selected
selected
selected
selected
selected
A/D Operation Mode Select
Bit 0 (3)
b4 b3
Trigger Select Bit
0 : Softw are trigger
A/D Conversion Start Flag
1 : ADTRG trigger
0 : A/D conversion disabled
1 : A/D conversion started
Frequency Select Bit 0
Refer to NOTE 3 for the ADCON2 Register
0 0 : One-shot mode
_________
RW
RW
RW
RW
RW
RW
RW
RW
NOTES :
1. If the ADCON0 register is rew ritten during A/D conversion, the conversion result w ill be indeterminate.
2. AN0_0 to AN0_7, and AN2_0 to AN2_7 can be used in the same w ay as AN0 to AN7. Use the ADGSEL1 to
ADGSEL0 bits in the ADCON2 register to select the desired pin. How ever, if VCC2 < VCC1, do not use AN0_0 to
AN0_7 and AN2_0 to AN2_7 as analog input pins.
3. After rew riting the MD1 to MD0 bits, set the CH2 to CH0 bits over again using another instruction.
A/D Control Register 1 (1)
b7 b6 b5 b4 b3 b2 b1 b0
1
0
Symbol
ADCON1
Symbol
SCAN0
Address
03D7h
Address
A/D Sw eep Pin Select Bit
After Reset
00h
After Reset
Invalid in one-shot mode
SCAN1
MD2
BITS
CKS1
VCUT
OPA0
RW
RW
RW
A/D Operation Mode Select Bit 1 Set to “0” w hen one-shot mode is selected
8/10-Bit Mode Select Bit
0 : 8-bit mode
1 : 10-bit mode
Frequency Select Bit 1
Vref Connect Bit (2)
Refer to NOTE 3 for the ADCON2 Register
1 : Vref connected
External Op-Amp Connection
Mode Bit
b7 b6
OPA1
0 0 : ANEX0 and ANEX1 are not used
0 1 : ANEX0 input is A/D converted
1 0 : ANEX1 input is A/D converted
1 1 : External op-amp connection mode
RW
RW
RW
RW
RW
RW
NOTES :
1. If the ADCON1 register is rew ritten during A/D conversion, the conversion result w ill be indeterminate.
2. If the VCUT bit is reset from “0” (Vref unconnected) to “1” (Vref connected), w ait for 1 µs or more before starting
A/D conversion.
Figure 18.5
ADCON0 and ADCON1 Registers (One-shot Mode)
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M16C/62P Group (M16C/62P, M16C/62PT)
18.1.2
18. A/D Converter
Repeat Mode
In repeat mode, analog voltage applied to a selected pin is repeatedly converted to a digital code. Table 18.3
shows the Repeat Mode Specifications. Figure 18.6 shows the ADCON0 and ADCON1 Registers (Repeat
Mode).
Table 18.3
Repeat Mode Specifications
Item
Function
A/D Conversion Start
Condition
A/D Conversion Stop
Condition
Interrupt Request
Generation timing
Analog Input Pin (1)
Specification
The CH2 to CH0 bits in the ADCON0 register, the ADGSEL1 to ADGSEL0 bits
in the ADCON2 register and the OPA1 to OPA0 bits in the ADCON1 register
select a pin. Analog voltage applied to this pin is repeatedly converted to a
digital code.
• When the TRG bit in the ADCON0 register is “0” (software trigger)
The ADST bit in the ADCON0 register is set to “1” (A/D conversion starts)
• When the TRG bit is “1” (ADTRG trigger)
Input on the ADTRG pin changes state from high to low after the ADST bit is
set to “1” (A/D conversion starts)
Set the ADST bit to “0” (A/D conversion halted)
None generated
Select one pin from AN0 to AN7, AN0_0 to AN0_7, AN2_0 to AN2_7,
ANEX0 to ANEX1
Reading of Result of A/D Read one of the AD0 to AD7 registers that corresponds to the selected pin
Converter
NOTES:
1. If VCC2 < VCC1, do not use AN0_0 to AN0_7 and AN2_0 to AN2_7 as analog input pins.
Rev.2.41 Jan 10, 2006
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M16C/62P Group (M16C/62P, M16C/62PT)
18. A/D Converter
A/D Control Register 0 (1)
b7 b6 b5 b4 b3 b2 b1 b0
0 1
Symbol
ADCON0
Address
03D6h
Bit Symbol
Bit Name
Analog Input Pin Select Bit (2, 3)
CH1
CH2
TRG
ADST
CKS0
Function
RW
b2 b1 b0
0 0 0 : AN0 is
0 0 1 : AN1 is
0 1 0 : AN2 is
0 1 1 : AN3 is
1 0 0 : AN4 is
1 0 1 : AN5 is
1 1 0 : AN6 is
1 1 1 : AN7 is
CH0
MD0
MD1
After Reset
00000XXXb
selected
selected
selected
selected
selected
selected
selected
selected
A/D Operation Mode Select
Bit 0 (3)
b4 b3
Trigger Select Bit
0 : Softw are trigger
A/D Conversion Start Flag
1 : ADTRG trigger
0 : A/D conversion disabled
1 : A/D conversion started
Frequency Select Bit 0
Refer to NOTE 3 for the ADCON2 Register
0 1 : Repeat mode
_________
RW
RW
RW
RW
RW
RW
RW
RW
NOTES :
1. If the ADCON0 register is rew ritten during A/D conversion, the conversion result w ill be indeterminate.
2. AN0_0 to AN0_7, and AN2_0 to AN2_7 can be used in the same w ay as AN0 to AN7. Use the ADGSEL1 to
ADGSEL0 bits in the ADCON2 register to select the desired pin. How ever, if VCC2 < VCC1, do not use AN0_0 to
AN0_7 and AN2_0 to AN2_7 as analog input pins.
3. After rew riting the MD1 to MD0 bits, set the CH2 to CH0 bits over again using another instruction.
A/D Control Register 1 (1)
b7 b6 b5 b4 b3 b2 b1 b0
1
0
Symbol
ADCON1
Symbol
SCAN0
Address
03D7h
Address
A/D Sw eep Pin Select Bit
After Reset
00h
After Reset
Invalid in repeat mode
SCAN1
MD2
BITS
CKS1
VCUT
OPA0
RW
RW
RW
A/D Operation Mode Select Bit 1 Set to “0” w hen repeat mode is selected
8/10-Bit Mode Select Bit
0 : 8-bit mode
1 : 10-bit mode
Frequency Select Bit 1
Vref Connect Bit (2)
Refer to NOTE 3 for the ADCON2 Register
1 : Vref connected
External Op-Amp Connection
Mode Bit
b7 b6
OPA1
0 0 : ANEX0 and ANEX1 are not used
0 1 : ANEX0 input is A/D converted
1 0 : ANEX1 input is A/D converted
1 1 : External op-amp connection mode
RW
RW
RW
RW
RW
RW
NOTES :
1. If the ADCON1 register is rew ritten during A/D conversion, the conversion result w ill be indeterminate.
2. If the VCUT bit is reset from “0” (Vref unconnected) to “1” (Vref connected), w ait for 1 µs or more before starting
A/D conversion.
Figure 18.6
ADCON0 and ADCON1 Registers (Repeat Mode)
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M16C/62P Group (M16C/62P, M16C/62PT)
18.1.3
18. A/D Converter
Single Sweep Mode
In single sweep mode, analog voltage that is applied to selected pins is converted one-by-one to a digital code.
Table 18.4 shows the Single Sweep Mode Specifications. Figure 18.7 shows the ADCON0 Register and
ADCON1 Register (Single Sweep Mode).
Table 18.4
Single Sweep Mode Specifications
Item
Function
A/D Conversion Start
Condition
A/D Conversion Stop
Condition
Interrupt Request
Generation timing
Analog Input Pin
Specification
The SCAN1 to SCAN0 bits in the ADCON1 register and the ADGSEL1 to
ADGSEL0 bits in the ADCON2 register select pins. Analog voltage applied to
this pins is converted one-by-one to a digital code.
• When the TRG bit in the ADCON0 register is “0” (software trigger)
The ADST bit in the ADCON0 register is set to “1” (A/D conversion starts)
• When the TRG bit is “1” (ADTRG trigger)
Input on the ADTRG pin changes state from high to low after the ADST bit is
set to “1” (A/D conversion starts)
• Completion of A/D conversion (If a software trigger is selected, the ADST bit
is cleared to “0” (A/D conversion halted))
• Set the ADST bit to “0”
Completion of A/D conversion
Select from AN0 to AN1 (2 pins), AN0 to AN3 (4 pins), AN0 to AN5 (6 pins),
AN0 to AN7 (8 pin) (1)
Reading of Result of A/D Read one of the AD0 to AD7 registers that corresponds to the selected pin
Converter
NOTES:
1. AN0_0 to AN0_7, and AN2_0 to AN2_7 can be used in the same way as AN0 to AN7. However, if
VCC2 < VCC1, do not use AN0_0 to AN0_7 and AN2_0 to AN2_7 as analog input pins.
Rev.2.41 Jan 10, 2006
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M16C/62P Group (M16C/62P, M16C/62PT)
18. A/D Converter
A/D Control Register 0 (1)
b7 b6 b5 b4 b3 b2 b1 b0
1 0
Symbol
ADCON0
Address
03D6h
Bit Symbol
CH0
CH1
CH2
MD0
MD1
TRG
ADST
CKS0
After Reset
00000XXXb
Function
RW
Analog Input Pin Select Bit
Bit Name
Invalid in single sw eep mode
A/D Operation Mode Select
Bit 0
b4 b3
RW
RW
RW
RW
RW
Trigger Select Bit
0 : Softw are trigger
A/D Conversion Start Flag
1 : ADTRG trigger
0 : A/D conversion disabled
1 : A/D conversion started
Frequency Select Bit 0
Refer to NOTE 3 for the ADCON2 Register
1 0 : Single sw eep mode
_________
RW
RW
RW
NOTES :
1. If the ADCON0 register is rew ritten during A/D conversion, the conversion result w ill be indeterminate.
A/D Control Register 1 (1)
b7 b6 b5 b4 b3 b2 b1 b0
1
0
Symbol
ADCON1
Symbol
Address
03D7h
Address
A/D Sw eep Pin Select Bit (2)
SCAN0
BITS
CKS1
VCUT
OPA0
After Reset
When single sw eep mode is selected
RW
b1 b0
RW
0 0 : AN0 to AN1 (2 pins)
0 1 : AN0 to AN3 (4 pins)
1 0 : AN0 to AN5 (6 pins)
1 1 : AN0 to AN7 (8 pins)
SCAN1
MD2
After Reset
00h
A/D Operation Mode Select Bit 1 Set to “0” w hen single sw eep mode is selected
8/10-Bit Mode Select Bit
0 : 8-bit mode
1 : 10-bit mode
Frequency Select Bit 1
Vref Connect Bit (3)
Refer to NOTE 3 for the ADCON2 Register
1 : Vref connected
External Op-Amp Connection
Mode Bit
b7 b6
OPA1
0 0 : ANEX0 and ANEX1 are not used
0 1 : Do not set to this value
1 0 : Do not set to this value
1 1 : External op-amp connection mode
RW
RW
RW
RW
RW
RW
RW
NOTES :
1. If the ADCON1 register is rew ritten during A/D conversion, the conversion result w ill be indeterminate.
2. AN0_0 to AN0_7, and AN2_0 to AN2_7 can be used in the same w ay as AN0 to AN7. Use the ADGSEL1 to
ADGSEL0 bits in the ADCON2 register to select the desired pin. How ever, if VCC2 < VCC1, do not use AN0_0 to
AN0_7 and AN2_0 to AN2_7 as analog input pins.
3. If the VCUT bit is reset from “0” (Vref unconnected) to “1” (Vref connected), w ait for 1 µs or more before starting
A/D conversion.
Figure 18.7
ADCON0 Register and ADCON1 Register (Single Sweep Mode)
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M16C/62P Group (M16C/62P, M16C/62PT)
18.1.4
18. A/D Converter
Repeat Sweep Mode 0
In repeat sweep mode 0, analog voltage applied to selected pins is repeatedly converted to a digital code.
Table 18.5 shows the Repeat Sweep Mode 0 Specifications. Figure 18.8 shows the ADCON0 Register and
ADCON1 Registers (Repeat Sweep Mode 0).
Table 18.5
Repeat Sweep Mode 0 Specifications
Item
Function
A/D Conversion Start
Condition
A/D Conversion Stop
Condition
Interrupt Request
Generation timing
Analog Input Pin
Specification
The SCAN1 to SCAN0 bits in the ADCON1 register and the ADGSEL1 to
ADGSEL0 bits in the ADCON2 register select pins. Analog voltage applied to
the pins is repeatedly converted to a digital code.
• When the TRG bit in the ADCON0 register is “0” (software trigger)
The ADST bit in the ADCON0 register is set to “1” (A/D conversion starts)
• When the TRG bit is “1” (ADTRG trigger)
Input on the ADTRG pin changes state from high to low after the ADST bit is
set to “1” (A/D conversion starts)
Set the ADST bit to “0” (A/D conversion halted)
None generated
Select from AN0 to AN1 (2 pins), AN0 to AN3 (4 pins), AN0 to AN5 (6 pins),
AN0 to AN7 (8 pin) (1)
Reading of Result of A/D Read one of the AD0 to AD7 registers that corresponds to the selected pin
Converter
NOTES:
1. AN0_0 to AN0_7, and AN2_0 to AN2_7 can be used in the same way as AN0 to AN7. However, if
VCC2 < VCC1, do not use AN0_0 to AN0_7 and AN2_0 to AN2_7 as analog input pins.
Rev.2.41 Jan 10, 2006
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M16C/62P Group (M16C/62P, M16C/62PT)
18. A/D Converter
A/D Control Register 0 (1)
b7 b6 b5 b4 b3 b2 b1 b0
1 1
Symbol
ADCON0
Bit Symbol
CH0
CH1
CH2
MD0
Address
03D6h
After Reset
00000XXXb
Bit Name
Function
Analog Input Pin Select Bit
Invalid in repeat sw eep mode 0
A/D Operation Mode Select
Bit 0
b4 b3
1 1 : Repeat sw eep mode 0 or
Repeat sw eep mode 1
MD1
TRG
ADST
CKS0
RW
RW
RW
RW
RW
RW
Trigger Select Bit
0 : Softw are trigger
A/D Conversion Start Flag
1 : ADTRG trigger
0 : A/D conversion disabled
1 : A/D conversion started
Frequency Select Bit 0
Refer to NOTE 3 for the ADCON2 Register
_________
RW
RW
RW
NOTES :
1. If the ADCON0 register is rew ritten during A/D conversion, the conversion result w ill be indeterminate.
A/D Control Register 1 (1)
b7 b6 b5 b4 b3 b2 b1 b0
1
0
Symbol
ADCON1
Symbol
Address
03D7h
Address
A/D Sw eep Pin Select Bit (2)
SCAN0
BITS
CKS1
VCUT
OPA0
After Reset
When repeat sw eep mode 0 is selected
RW
b1 b0
RW
0 0 : AN0 to AN1 (2 pins)
0 1 : AN0 to AN3 (4 pins)
1 0 : AN0 to AN5 (6 pins)
1 1 : AN0 to AN7 (8 pins)
SCAN1
MD2
After Reset
00h
A/D Operation Mode Select Bit 1 Set to “0” w hen repeat sw eep mode 0 is
selected
8/10-Bit Mode Select Bit
0 : 8-bit mode
1 : 10-bit mode
Frequency Select Bit 1
Vref Connect Bit (3)
Refer to NOTE 3 for the ADCON2 Register
1 : Vref connected
External Op-Amp Connection
Mode Bit
b7 b6
OPA1
0 0 : ANEX0 and ANEX1 are not used
0 1 : Do not set to this value
1 0 : Do not set to this value
1 1 : External op-amp connection mode
RW
RW
RW
RW
RW
RW
RW
NOTES :
1. If the ADCON1 register is rew ritten during A/D conversion, the conversion result w ill be indeterminate.
2. AN0_0 to AN0_7, and AN2_0 to AN2_7 can be used in the same w ay as AN0 to AN7. Use the ADGSEL1 to
ADGSEL0 bits in the ADCON2 register to select the desired pin. How ever, if VCC2 < VCC1, do not use AN0_0 to
AN0_7 and AN2_0 to AN2_7 as analog input pins.
3. If the VCUT bit is reset from “0” (Vref unconnected) to “1” (Vref connected), w ait for 1 µs or more before starting
A/D conversion.
Figure 18.8
ADCON0 Register and ADCON1 Registers (Repeat Sweep Mode 0)
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M16C/62P Group (M16C/62P, M16C/62PT)
18.1.5
18. A/D Converter
Repeat Sweep Mode 1
In repeat sweep mode 1, analog voltage selectively applied to all pins is repeatedly converted to a digital code.
Table 18.6 shows the Repeat Sweep Mode 1 Specifications. Figure 18.9 shows the ADCON0 Register and
ADCON1 Register (Repeat Sweep Mode 1).
Table 18.6
Repeat Sweep Mode 1 Specifications
Item
Function
A/D Conversion Start
Condition
A/D Conversion Stop
Condition
Interrupt Request
Generation timing
Analog Input Pins to be
Given Priority when A/D
Converted
Reading of Result of A/D
Converter
Specification
The input voltages on all pins selected by the ADGSEL1 to ADGSEL0 bits in the
ADCON2 register are A/D converted repeatedly, with priority given to pins
selected by the SCAN1 to SCAN0 bits in the ADCON1 register and ADGSEL1
to ADGSEL0 bits.
Example : If AN0 selected, input voltages are A/D converted in order of
AN0→AN1→AN0→AN2→AN0→AN3, and so on.
• When the TRG bit in the ADCON0 register is “0” (software trigger)
The ADST bit in the ADCON0 register is set to “1” (A/D conversion starts)
• When the TRG bit is “1” (ADTRG trigger)
Input on the ADTRG pin changes state from high to low after the ADST bit is
set to “1” (A/D conversion starts)
Set the ADST bit to “0” (A/D conversion halted)
None generated
Select from AN0 (1 pin), AN0 to AN1 (2 pins), AN0 to AN2 (3 pins),
AN0 to AN3 (4 pins) (1)
Read one of the AD0 to AD7 registers that corresponds to the selected pin
NOTES:
1. AN0_0 to AN0_7, and AN2_0 to AN2_7 can be used in the same way as AN0 to AN7. However, if
VCC2 < VCC1, do not use AN0_0 to AN0_7 and AN2_0 to AN2_7 as analog input pins.
Rev.2.41 Jan 10, 2006
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M16C/62P Group (M16C/62P, M16C/62PT)
18. A/D Converter
A/D Control Register 0 (1)
b7 b6 b5 b4 b3 b2 b1 b0
1 1
Symbol
ADCON0
Bit Symbol
CH0
CH1
CH2
MD0
Address
03D6h
After Reset
00000XXXb
Bit Name
Function
Analog Input Pin Select Bit
Invalid in repeat sw eep mode 1
A/D Operation Mode Select
Bit 0
b4 b3
1 1 : Repeat sw eep mode 0 or
Repeat sw eep mode 1
MD1
TRG
ADST
CKS0
RW
RW
RW
RW
RW
RW
Trigger Select Bit
0 : Softw are trigger
A/D Conversion Start Flag
1 : ADTRG trigger
0 : A/D conversion disabled
1 : A/D conversion started
Frequency Select Bit 0
Refer to NOTE 3 for the ADCON2 Register
_________
RW
RW
RW
NOTES :
1. If the ADCON0 register is rew ritten during A/D conversion, the conversion result w ill be indeterminate.
A/D Control Register 1 (1)
b7 b6 b5 b4 b3 b2 b1 b0
1
1
Symbol
ADCON1
Symbol
Address
03D7h
Address
A/D Sw eep Pin Select Bit (2)
SCAN0
BITS
CKS1
VCUT
OPA0
After Reset
When repeat sw eep mode 1 is selected
RW
b1 b0
RW
0 0 : AN0 (1 pins)
0 1 : AN0, AN1 (2 pins)
1 0 : AN0 to AN2 (3 pins)
1 1 : AN0 to AN3 (4 pins)
SCAN1
MD2
After Reset
00h
A/D Operation Mode Select Bit 1 Set to “1” w hen repeat sw eep mode 1 is
selected
8/10-Bit Mode Select Bit
0 : 8-bit mode
1 : 10-bit mode
Frequency Select Bit 1
Vref Connect Bit (3)
Refer to NOTE 3 for the ADCON2 Register
1 : Vref connected
External Op-Amp Connection
Mode Bit
b7 b6
OPA1
0 0 : ANEX0 and ANEX1 are not used
0 1 : Do not set to this value
1 0 : Do not set to this value
1 1 : External op-amp connection mode
RW
RW
RW
RW
RW
RW
RW
NOTES :
1. If the ADCON1 register is rew ritten during A/D conversion, the conversion result w ill be indeterminate.
2. AN0_0 to AN0_7, and AN2_0 to AN2_7 can be used in the same w ay as AN0 to AN7. Use the ADGSEL1 to
ADGSEL0 bits in the ADCON2 register to select the desired pin. How ever, if VCC2 < VCC1, do not use AN0_0 to
AN0_7 and AN2_0 to AN2_7 as analog input pins.
3. If the VCUT bit is reset from “0” (Vref unconnected) to “1” (Vref connected), w ait for 1 µs or more before starting
A/D conversion.
Figure 18.9
ADCON0 Register and ADCON1 Register (Repeat Sweep Mode 1)
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M16C/62P Group (M16C/62P, M16C/62PT)
18.2
18. A/D Converter
Function
18.2.1
Resolution Select Function
The desired resolution can be selected using the BITS bit in the ADCON1 register. If the BITS bit is set to “1”
(10-bit conversion accuracy), the A/D conversion result is stored in the bit 0 to bit 9 in the ADi register (i = 0 to
7). If the BITS bit is set to “0” (8-bit conversion accuracy), the A/D conversion result is stored in the bit 0 to bit
7 in the ADi register.
18.2.2
Sample and Hold
If the SMP bit in the ADCON2 register is set to “1” (with sample-and-hold), the conversion speed per pin is
increased to 28 φAD cycles for 8-bit resolution or 33 φAD cycles for 10-bit resolution. Sample and Hold is
effective in all operating modes. Select whether or not to use the Sample and Hold function before starting A/D
conversion.
18.2.3
Extended Analog Input Pins
In one-shot and repeat modes, the ANEX0 and ANEX1 pins can be used as analog input pins. Use the OPA1 to
OPA0 bits in the ADCON1 register to select whether or not use ANEX0 and ANEX1.
The A/D conversion results of ANEX0 and ANEX1 inputs are stored in the AD0 and AD1 registers,
respectively.
18.2.4
18.2.4 External Operation Amplifier (Op-Amp) Connection Mode
Multiple analog inputs can be amplified using a single external op-amp via the ANEX0 and ANEX1 pins. Set
the OPA1 to OPA0 bits in the ADCON1 register to “11b” (external op-amp connection mode). The inputs from
ANi (i = 0 to 7) (1) are output from the ANEX0 pin. Amplify this output with an external op-amp before sending
it back to the ANEX1 pin. The A/D conversion result is stored in the corresponding ADi register. The A/D
conversion speed depends on the response characteristics of the external op-amp. Figure 18.10 shows an
example of How to Connect the Pins in External Op-Amp.
1. AN0_i and AN2_i can be used the same as ANi. However, if VCC2 < VCC1, do not use AN0_i and
AN2_i as analog input pins.
Microcomputer
ADGSEL1 to ADGSEL0 bits in ADCON2 register = 00b
AN0
AN1
AN2
AN3
AN4
AN5
AN6
AN7
Resistor ladder
Successive conversion
register
ADGSEL1 to ADGSEL0 bits = 10b
AN0_0
AN0_1
AN0_2
AN0_3
AN0_4
AN0_5
AN0_6
AN0_7
ADGSEL1 to ADGSEL0 bits = 11b
AN2_0
AN2_1
AN2_2
AN2_3
AN2_4
AN2_5
AN2_6
AN2_7
ANEX0
ANEX1
External Op-Amp
Figure 18.10
External Op-Amp Connection
Rev.2.41 Jan 10, 2006
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Comparator
M16C/62P Group (M16C/62P, M16C/62PT)
18.2.5
18. A/D Converter
18.2.5 Current Consumption Reducing Function
When not using the A/D converter, its resistor ladder and reference voltage input pin (VREF) can be separated
using the VCUT bit in the ADCON1 register. When separated, no current will flow from the VREF pin into the
resistor ladder, helping to reduce the power consumption of the chip.
To use the A/D converter, set the VCUT bit to “1” (Vref connected) and then set the ADST bit in the ADCON0
register to “1” (A/D conversion start). The VCUT and ADST bits cannot be set to “1” at the same time.
Nor can the VCUT bit be set to “0” (Vref unconnected) during A/D conversion.
Note that this does not affect VREF for the D/A converter (irrelevant).
18.2.6
Output Impedance of Sensor under A/D Conversion
To carry out A/D conversion properly, charging the internal capacitor C shown in Figure 18.11 has to be
completed within a specified period of time. T (sampling time) as the specified time. Let output impedance of
sensor equivalent circuit be R0, internal resistance of microcomputer be R, precision (error) of the A/D
converter be X, and the resolution of A/D converter be Y (Y is 1024 in the 10-bit mode, and 256 in the 8-bit
mode).
1
– -------------------------C ( R0 + R )
⎧
VC is generally VC = VIN ⎨ 1 – e
⎩
And when t = T,
t
⎫
⎬
⎭
X
X
VC = VIN – ---- VIN = VIN ⎛ 1 – ----⎞
⎝
Y
Y⎠
1
– --------------------------T
C
(
R0
+ R) = X
e
---Y
1
X
– -------------------------- T = ln ---C ( R0 + R )
Y
Hence,
T
R0 = – ------------------- – R
X
C • ln ---Y
Figure 18.11 shows Analog Input Pin and External Sensor Equivalent Circuit. When the difference between
VIN and VC becomes 0.1LSB, we find impedance R0 when voltage between pins VC changes from 0 to VIN(0.1/1024) VIN in time T. (0.1/1024) means that A/D precision drop due to insufficient capacitor charge is held
to 0.1LSB at time of A/D conversion in the 10-bit mode. Actual error however is the value of absolute precision
added to 0.1LSB.
When f(φAD) = 10 MHz, T = 0.3 µs in the A/D conversion mode with sample & hold. Output impedance R0 for
sufficiently charging capacitor C within time T is determined as follows.
T = 0.3 µs, R = 7.8 kΩ, C = 1.5 pF, X = 0.1, and Y = 1024. Hence,
3
3
0.3 × 10 – 6
R0 = – ---------------------------------------------------– 7.8 ×10 = 13.9 ×10
0.1
1.5 × 10 – 12 • ln -----------1024
Thus, the allowable output impedance of the sensor equivalent circuit, making the precision (error) 0.1LSB or
less, is approximately 13.9 kΩ. maximum.
Rev.2.41 Jan 10, 2006
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M16C/62P Group (M16C/62P, M16C/62PT)
18. A/D Converter
Microcomputer
Sensor equivalent
circuit
R0
R (7.8kΩ)
VIN
Sampling time
C (1.5pF)
VC
Sample and hold enabled:
Sample and hold disabled:
Figure 18.11
Analog Input Pin and External Sensor Equivalent Circuit
Rev.2.41 Jan 10, 2006
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3
φAD
2
φAD
M16C/62P Group (M16C/62P, M16C/62PT)
19. D/A Converter
19. D/A Converter
This is an 8-bit, R-2R type D/A converter. These are two independent D/A converters.
D/A conversion is performed by writing to the DAi register (i = 0 to 1). To output the result of conversion, set the
DAiE bit in the DACON register to “1” (output enabled). Before D/A conversion can be used, the corresponding port
direction bit must be cleared to “0” (input mode). Setting the DAiE bit to “1” removes a pull-up from the
corresponding port.
Output analog voltage (V) is determined by a set value (n : decimal) in the DAi register.
V = VREF X n/ 256 (n = 0 to 255)
VREF : reference voltage
Table 19.1 lists the D/A Converter Performance. Figure 19.1 shows the D/A Converter Block Diagram. Figure 19.2
shows the D/A converter related registers. Figure 19.3 shows the D/A Converter Equivalent Circuit.
Table 19.1
D/A Converter Performance
Item
D/A Conversion Method
Resolution
Analog Output Pin
Performance
R-2R method
8 bits
2 channels (DA0 and DA1)
Data Bus Low-order
DA0 Register
0
R-2R Resistor Ladder
DA0E Bit
1
DA0
DA1 Register
0
R-2R Resistor Ladder
1
DA1E Bit
Figure 19.1
D/A Converter Block Diagram
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DA1
M16C/62P Group (M16C/62P, M16C/62PT)
19. D/A Converter
D/A Control Register (1)
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
DACON
Address
03DCh
After Reset
00h
Bit Name
Bit Symbol
DA0E
DA1E
—
(b7-b2)
Function
RW
D/A0 Output Enable Bit
0 : Output disabled
1 : Output enabled
RW
D/A1 Output Enable Bit
0 : Output disabled
1 : Output enabled
RW
Nothing is assigned.
When w rite, set to “0”. When read, their contents are “0”.
—
NOTES :
1. When not using the D/A converter, clear the DAiE bit (i = 0 to 1) to “0” (output disabled) to reduce the unnecessary
current consumption in the chip and set the DAi register to “00h” to prevent current from flow ing into the R-2R resistor
D/Ai Register (i = 0 to 1) (1)
b7
b0
Address
03D8h
Symbol
DA0
DA1
After Reset
00h
00h
03DAh
Function
Output value of D/A conversion
Setting Range
RW
00h to FFh
RW
NOTES :
1. When not using the D/A converter, clear the DAiE bit (i = 0 to 1) to “0” (output disabled) to reduce the unnecessary
current consumption in the chip and set the DAi register to “00h” to prevent current from flow ing into the R-2R resistor
Figure 19.2
DACON, DA0 and DA1 Registers
DAiE bit
r
“0”
R
R
R
R
2R
2R
2R
2R
R
R
R
2R
DAi
“1”
2R
MSB
DAi register
2R
2R
LSB
“0”
“1”
AVSS
VREF (2)
i = 0 to 1
NOTES:
1. The above diagram shows an instance in which the DA0 register is assigned “2Ah”.
2. VREF is not related to VCUT bit setting in the AD0CON1 register.
Figure 19.3
2R
D/A Converter Equivalent Circuit
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M16C/62P Group (M16C/62P, M16C/62PT)
20. CRC Calculation
20. CRC Calculation
The Cyclic Redundancy Check (CRC) operation detects an error in data blocks. The microcomputer uses a generator
polynomial of CRC_CCITT (X16 + X12 + X5 + 1) to generate CRC code.
The CRC code consists of 16 bits which are generated for each data block in given length, separated in 8 bit units.
After the initial value is set in the CRCD register, the CRC code is set in that register each time one byte of data is
written to the CRCIN register. CRC code generation for one-byte data is finished in two cycles.
Figure 20.1 shows the CRC Circuit Block Diagram. Figure 20.2 shows the CRC-related Registers.
Figure 20.3 shows the Calculation Example using the CRC Operation.
Data bus high-order
Data bus low-order
Eight low-order bits
Eight high-order bits
CRCD register
CRC code generating circuit
X16 + X12 + X5 + 1
CRCIN register
Figure 20.1
CRC Circuit Block Diagram
CRC Data Register
(b15)
b7
(b8)
b0 b7
b0
Symbol
CRCD
Function
Address
03BDh to 03BCh
After Reset
Indeterminate
Setting Range
RW
When data is w ritten to the CRCIN register after setting the initial value in 0000h to FFFFh
the CRCD register, the CRC code can be read out from the CRCD
register.
RW
CRC Input Register
b7
b0
Symbol
CRCIN
Function
Data input
Figure 20.2
CRCD and CRCIN Registers
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Address
03BEh
After Reset
Indeterminate
Setting Range
RW
00h to FFh
RW
M16C/62P Group (M16C/62P, M16C/62PT)
20. CRC Calculation
Setup procedure and CRC operation when generating CRC code “80C4h”
• CRC operation performed by the M16C
CRC code: Remainder of a division in which the value written to the CRCIN register with its bit positions reversed is
divided by the generator polynomial
Generator polynomial: X16 + X12 + X5 + 1 (1 0001 0000 0010 0001b)
• Setting procedure
(1) Reverse the bit positions of the value “80C4h” by program in 1-byte units.
“80h”
“01h”, “C4h”
“23h”
b15
b0
(2) Write 0000h (initial value)
CRCD register
b7
b0
(3) Write 01h
CRCIN register
Two cycles later, the CRC code for “80h”, i.e.,
9188h, has its bit positions reversed to become
“1189h” which is stored in the CRCD register.
b0
b15
CRCD register
1189h
b7
b0
(4) Write 23h
CRCIN register
Two cycles later, the CRC code for “80C4h”, i.e.,
8250h, has its bit positions reversed to become
“0A41h” which is stored in the CRCD register.
b15
b0
CRCD register
0A41h
• Details of CRC operation
As shown in (3) above, bit position of “01h” (00000001b) written to the CRCIN register is inversed and becomes
“10000000b”.
Add “1000 0000 0000 0000 0000 0000b”, as “10000000b” plus 16 digits, to “0000 0000 0000 0000 0000 0000b”,
as “0000 0000 0000 0000b” plus 8 digits as the default value of the CRCD register to perform the modulo-2 division.
1000 1000
1 0001 0000 0010 0001
Generator polynomial
1000 0000 0000
1000 1000 0001
1000 0001
1000 1000
1001
0000
0000
0000
0001
0001
0000
1
1000
0000
1000
0000
0
1
1000
Modulo-2 operation is
operation that complies
with the law given below.
Data
0+0=0
0+1=1
1+0=1
1+1=0
-1 = 1
CRC code
“0001 0001 1000 1001b (1189h)”, the remainder “1001 0001 1000 1000b (9188h)” with inversed bit position, can
be read from the CRCD register.
When going on to (4) above, “23h (00100011b)” written in the CRCIN register is inversed and becomes
“11000100b”.
Add “1100 0100 0000 0000 0000 0000b”, as “11000100b” plus 16 digits, to “1001 0001 1000 1000 0000 0000b”, as
“1001 0001 1000 1000b” plus 8 digits as a remainder of (3) left in the CRCD register to perform the modulo-2 division.
“0000 1010 0100 0001b (0A41h)”, the remainder with inversed bit position, can be read from CRCD register.
Figure 20.3
CRC Calculation
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M16C/62P Group (M16C/62P, M16C/62PT)
21. Programmable I/O Ports
21. Programmable I/O Ports
Note
There is no external connections for port P1_0 to P1_7, P4_4 to P4_7, P7_2 to P7_5 and P9_1 in the
M16C/62P (80-pin version) and the M16C/62PT (80-pin version). Set the direction bits in these ports to
“1” (output mode), and set the output data to “0” (“L”) using the program.
Moreover, P11_0 to P11_7, P12_0 to P12_7, P13_0 to P13_7, P14_0 and P14_1 pins do not exist.
Therefore, P11 to P13, PC14 and PUR13 register do not exist.
The programmable input/output ports (hereafter referred to simply as I/O ports) consist of 113 lines P0 to P14 for the
128-pin version, 87 lines P0 to P10 for the 100-pin version, or 70 lines P0 to P10 for the 80-pin version. Each port can
be set for input or output every line by using a direction register, and can also be chosen to be or not be pulled high
every 4 lines. P8_5 is an input-only port and does not have a pull-up resistor. Port P8_5 shares the pin with NMI, so
that the NMI input level can be read from the P8 register P8_5 bit.
Table 21.1 lists the Number of Pins of the Programmable I/O Ports of Each Package. Figure 21.1 to Figure 21.5 show
the I/O ports. Figure 21.6 shows the I/O Pins.
Each pin functions as an I/O port, a peripheral function input/output, or a bus control pin.
For details on how to set peripheral functions, refer to each functional description in this manual. If any pin is used as
a peripheral function input or D/A converter output pin, set the direction bit for that pin to “0” (input mode). Any pin
used as an output pin for peripheral functions other than the D/A converter is directed for output no matter how the
corresponding direction bit is set.
When using any pin as a bus control pin, refer to 8.2 Bus Control.
P0 to P5, P12, and P13 are capable of VCC2-level input/output; P6 to P11 and P14 are capable of VCC1- level input/
output.
Table 21.1
Number of Pins of the Programmable I/O Ports of Each Package
128-pin Version
100-pin Version
80-pin version (1)
Programmable
P0_0 to P0_7,
P0_0 to P0_7,
P0_0 to P0_7,
I/O Ports
P1_0 to P1_7,
P1_0 to P1_7,
P2_0 to P2_7,
P2_0 to P2_7,
P2_0 to P2_7,
P3_0 to P3_7,
P3_0 to P3_7,
P3_0 to P3_7,
P4_0 to P4_3,
P4_0 to P4_7,
P4_0 to P4_7,
P5_0 to P5_7,
P5_0 to P5_7,
P5_0 to P5_7,
P6_0 to P6_7,
P6_0 to P6_7,
P6_0 to P6_7,
P7_0, P7_1, P7_6, P7_7,
P7_0 to P7_7,
P7_0 to P7_7,
P8_0 to P8_4, P8_6, P8_7
P8_0 to P8_4, P8_6, P8_7 P8_0 to P8_4, P8_6, P8_7 (P8_5 is an input port),
(P8_5 is an input port),
(P8_5 is an input port),
P9_0, P9_2 to P9_7,
P9_0 to P9_7,
P9_0 to P9_7,
P10_0 to P10_7,
P10_0 to P10_7,
P10_0 to P10_7,
P11_0 to P11_7,
P12_0 to P12_7,
P13_0 to P13_7,
P14_0, P14_1
113 pins
87 pins
Total
70 pins
NOTES:
1. There is no connections for port P1_0 to P1_7, P4_4 to P4_7, P7_2 to P7_5 and P9_1 in 80-pin
version.
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M16C/62P Group (M16C/62P, M16C/62PT)
21.1
21. Programmable I/O Ports
Port Pi Direction Register (PDi Register, i = 0 to 13)
Figure 21.7 shows the PDi Registers.
This register selects whether the I/O port is to be used for input or output. The bits in this register correspond one
for one to each port.
During memory extension and microprocessor modes, the PDi registers for the pins functioning as bus control pins
(A0 to A19, D0 to D15, CS0 to CS3, RD, WRL/WR, WRH/BHE, ALE, RDY, HOLD, HLDA, and BCLK) cannot
be modified.
No direction register bit for P8_5 is available.
21.2
Port Pi Register (Pi Register, i = 0 to 13)
Figure 21.8 shows the Pi Registers.
Data input/output to and from external devices are accomplished by reading and writing to the Pi register.
The Pi register consists of a port latch to hold the input/output data and a circuit to read the pin status. For ports set
for input mode, the input level of the pin can be read by reading the corresponding Pi register, and data can be
written to the port latch by writing to the Pi register.
For ports set for output mode, the port latch can be read by reading the corresponding Pi register, and data can be
written to the port latch by writing to the Pi register. The data written to the port latch is output from the pin. The
bits in the Pi register correspond one for one to each port.
During memory extension and microprocessor modes, the PDi registers for the pins functioning as bus control pins
(A0 to A19, D0 to D15, CS0 to CS3, RD, WRL/WR, WRH/BHE, ALE, RDY, HOLD, HLDA, and BCLK) cannot
be modified.
21.3
Pull-up Control Register 0 to Pull-up Control Register 3 (PUR0 to PUR3
Registers)
Figure 21.9 and Figure 21.11 shows the PURi Registers.
The PUR0 to PUR2 register bits can be used to select whether or not to pull the corresponding port high in 4 bit
units. The port chosen to be pulled high has a pull-up resistor connected to it when the direction bit is set for input
mode. To use ports P11 to P14, set the PU37 bit in the PUR3 register to “1”.
However, the pull-up control register has no effect on P0 to P3, P4_0 to P4_3, and P5 during memory extension and
microprocessor modes. Although the register contents can be modified, no pull-up resistors are connected.
21.4
Port Control Register (PCR Register)
Figure 21.12 shows the PCR Register.
When the P1 register is read after setting the PCR0 bit in the PCR register to “1”, the corresponding port latch can
be read no matter how the PD1 register is set.
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M16C/62P Group (M16C/62P, M16C/62PT)
21. Programmable I/O Ports
Pull-up selection
Direction register
P0_0 to P0_7,
P2_0 to P2_7
(inside dotted-line
included)
Port latch
Data bus
P3_0 to P3_7,
P4_0 to P4_7,
P5_0 to P5_4, P5_6,
P11_0 to P11_7 (2),
P12_0 to P12_7 (2),
P13_0 to P13_7 (2),
P14_0, P14_1 (2)
(NOTE 1)
(inside dotted-line
not included)
Analog input
Pull-up selection
Direction register
P1_0 to P1_4
Port P1 control register
Data bus
Port latch
(NOTE 1)
Pull-up selection
Direction register
P1_5 to P1_7
Port P1 control register
Data bus
Port latch
(NOTE 1)
Input to respective peripheral functions
Pull-up selection
Direction
register
P5_7, P6_0, P6_4, P7_3 to P7_6,
P8_0, P8_1, P9_0, P9_2
“1”
Output
Data bus
Port latch
(NOTE 1)
Input to respective peripheral functions
NOTES:
1.
Symbolizes a parasitic diode.
Make sure the input voltage on each port will not exceed VCC.
VCC: VCC1 for the port P6 to P11 and P14, and VCC2 for the port P0 to P5 and P12 to P13.
2. Available in only the 128-pin version.
Figure 21.1
I/O Ports (1)
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M16C/62P Group (M16C/62P, M16C/62PT)
21. Programmable I/O Ports
Pull-up selection
Direction
register
P6_1, P6_5, P7_2
“1”
Data bus
Output
Port latch
Switching
between
CMOS and
Nch
(NOTE 1)
Input to respective peripheral functions
Pull-up selection
P8_2 to P8_4
Direction register
Data bus
Port latch
(NOTE 1)
Input to respective peripheral functions
Pull-up selection
Direction register
P5_5, P7_7, P9_1, P9_7
Data bus
Port latch
(NOTE 1)
Input to respective peripheral functions
NOTES:
1.
Symbolizes a parasitic diode.
Make sure the input voltage on each port will not exceed VCC.
VCC: VCC1 for the port P6 to P11 and P14, and VCC2 for the port P0 to P5 and P12 to P13.
Figure 21.2
I/O Ports (2)
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M16C/62P Group (M16C/62P, M16C/62PT)
21. Programmable I/O Ports
Pull-up selection
Direction register
P6_2, P6_6
Data bus
Port latch
(NOTE 1)
Switching
between
CMOS and Nch
Input to respective peripheral functions
Pull-up selection
Direction register
P6_3, P6_7
“1”
Data bus
Port latch
Output
(NOTE 1)
Switching between CMOS and Nch
P8_5
Data bus
NMI interrupt input
(NOTE 1)
Direction register
P7_0, P7_1
“1”
Data bus
Output
Port latch
(NOTE 2)
Input to respective peripheral functions
NOTES:
1.
Symbolizes a parasitic diode.
Make sure the input voltage on each port will not exceed VCC.
VCC: VCC1 for the port P6 to P11 and P14, and VCC2 for the port P0 to P5 and P12 to P13.
2.
symbolizes a parasitic diode.
Figure 21.3
I/O Ports (3)
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M16C/62P Group (M16C/62P, M16C/62PT)
P10_0 to P10_3
(Inside dotted-line
not included)
P10_4 to P10_7
(Inside dotted-line
included)
21. Programmable I/O Ports
Pull-up selection
Direction register
Port latch
Data bus
(NOTE 1)
Analog input
Input to respective peripheral functions
Pull-up selection
D/A output enabled
Direction register
P9_3, P9_4
Data bus
Port latch
(NOTE 1)
Input to respective peripheral functions
Analog output
D/A output enabled
Pull-up selection
Direction register
P9_6
“1”
Output
Data bus
Port latch
(NOTE 1)
Analog input
Pull-up selection
Direction register
P9_5
“1”
Data bus
Output
Port latch
(NOTE 1)
Input to respective peripheral functions
Analog input
NOTES:
1.
Symbolizes a parasitic diode.
Make sure the input voltage on each port will not exceed VCC.
VCC: VCC1 for the port P6 to P11 and P14, and VCC2 for the port P0 to P5 and P12 to P13.
Figure 21.4
I/O Ports (4)
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M16C/62P Group (M16C/62P, M16C/62PT)
21. Programmable I/O Ports
Pull-up selection
Direction register
P8_7
Data bus
Port latch
(NOTE 1)
fC
Rf
Pull-up selection
Rd
Direction register
P8_6
“1”
Data bus
Port latch
Output
(NOTE 1)
NOTES:
1.
Symbolizes a parasitic diode.
Make sure the input voltage on each port will not exceed VCC.
VCC: VCC1 for the port P6 to P11 and P14, and VCC2 for the port P0 to P5 and P12 to P13.
Figure 21.5
I/O Ports (5)
BYTE
BYTE signal input
(NOTE 1)
CNVSS
CNVSS signal input
(NOTE 1)
RESET
RESET signal input
(NOTE1)
NOTES:
1.
Symbolizes a parasitic diode.
Make sure the input voltage on each port will not exceed VCC1.
Figure 21.6
I/O Pins
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M16C/62P Group (M16C/62P, M16C/62PT)
21. Programmable I/O Ports
Port Pi Direction Register (i=0 to 7 and 9 to 13) (1, 2, 3)
b7 b6 b5 b4 b3 b2 b1 b0
After Reset
Symbol
Address
00h
PD0 to PD3
03E2h, 03E3h, 03E6h, 03E7h
03EAh, 03EBh, 03EEh, 03EFh
00h
PD4 to PD7
00h
PD9 to PD12
03F3h, 03F6h, 03F73h, 03FAh
PD13
03FBh
00h
Bit Name
Function
Bit Symbol
Port Pi_0 Direction Bit
0 : Input mode
PDi_0
(Functions as an input port)
Port Pi_1 Direction Bit
PDi_1
1 : Output mode
PDi_2
Port Pi_2 Direction Bit
(Functions as an output port)
PDi_3
Port Pi_3 Direction Bit
(i = 0 to 7 and 9 to 13)
Port Pi_4 Direction Bit
PDi_4
PDi_5
Port Pi_5 Direction Bit
PDi_6
Port Pi_6 Direction Bit
PDi_7
Port Pi_7 Direction Bit
RW
RW
RW
RW
RW
RW
RW
RW
RW
NOTES :
1. Make sure the PD9 register is w ritten to by the next instruction after setting the PRC2 bit in the PRCR register to “1”
(w rite enabled).
2. During memory extension
and
microprocessor modes, the PDi register
for the pins functioning as bus control pins (A0
_____
_____ ___ ______ ___ ______ _____
_____ _______ _______
to A19, D0 to D15, CS0 to CS3, RD, WRL/WR, WRH/BHE, ALE, RDY , HOLD, HLDA and BCLK) cannot be modified.
3. To use ports P11 to P14, set the PU37 bit in the PUR3 register to “1” (enable).
Port P8 Direction Register
b7 b6 b5 b4 b3 b2 b1 b0
After Reset
Address
Symbol
00X00000b
03F2h
PD8
Function
Bit Name
Bit Symbol
0 : Input mode
PD8_0
Port P8_0 Direction Bit
(Functions as an input port)
Port P8_1 Direction Bit
PD8_1
1
:
Output mode
PD8_2
Port P8_2 Direction Bit
(Functions
as an output port)
PD8_3
Port P8_3 Direction Bit
PD8_4
Port P8_4 Direction Bit
Nothing is assigned. When w rite, set to “0”.
—
When read, its content is indeterminate.
(b5)
PD8_6
PD8_7
Figure 21.7
Port P8_6 Direction Bit
Port P8_7 Direction Bit
PDi Registers
Rev.2.41 Jan 10, 2006
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0 : Input mode
(Functions as an input port)
1 : Output mode
(Functions as an output port)
RW
RW
RW
RW
RW
RW
—
RW
RW
M16C/62P Group (M16C/62P, M16C/62PT)
21. Programmable I/O Ports
Port Pi Register (i=0 to 7 and 9 to 13) (2, 3)
b7 b6 b5 b4 b3 b2 b1 b0
Address
Symbol
After Reset
03E0h, 03E1h, 03E4h, 03E5h
Indeterminate
P0 to P3
03E8h, 03E9h, 03ECh, 03EDh
Indeterminate
P4 to P7
Indeterminate
03F1h, 03F4h, 03F5h, 03F8h
P9 to P12
03F9h
Indeterminate
P13
Bit Name
Function
Bit Symbol
Port Pi_0 Bit
The pin level on any I/O port w hich is set for input
Pi_0
mode can be read by reading the corresponding bit in
Port Pi_1 Bit
Pi_1
this register.
Port Pi_2 Bit
Pi_2
The pin level on any I/O port w hich is set for output
Port Pi_3 Bit
Pi_3
mode can be controlled by w riting to the
Port Pi_4 Bit
Pi_4
orresponding bit in this register
0 : “L” level
Port Pi_5 Bit
Pi_5
1 : “H” level (1)
Port Pi_6 Bit
Pi_6
(i = 0 to 7 and 9 to 13)
Port Pi_7 Bit
Pi_7
RW
RW
RW
RW
RW
RW
RW
RW
RW
NOTES :
1. Since P7_0 and P7_1 are N-channel open drain ports, the data is high-impedance.
2. During memory extension
and microprocessor modes, the Pi_____
register
for the pins functioning as bus control pins (A0 to
_____
_____ ___ ______ ___ ______ _____
_______ _______
A19, D0 to D15, CS0 to CS3, RD, WRL/WR, WRH/BHE, ALE, RDY , HOLD, HLDA and BCLK) cannot be modified.
3. To use ports P11 to P14, set the PU37 bit in the PUR3 register to “1” (enable). If this bit is set to “0” (disable), the P11 to
P14 registers are cleared to “0”.
Port P8 Register
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
P8
Bit Symbol
P8_0
P8_1
P8_2
P8_3
P8_4
P8_5
P8_6
P8_7
Figure 21.8
Address
03F0h
Bit Name
Port P8_0 Bit
Port P8_1 Bit
Port P8_2 Bit
Port P8_3 Bit
Port P8_4 Bit
Port P8_5 Bit
Port P8_6 Bit
Port P8_7 Bit
Pi Registers
Rev.2.41 Jan 10, 2006
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After Reset
Indeterminate
Function
The pin level on any I/O port w hich is set for input mode
can be read by reading the corresponding bit in this
register.
The pin level on any I/O port w hich is set for output
mode can be controlled by w riting to the corresponding
bit in this register (except for P8_5)
0 : “L” level
1 : “H” level
RW
RW
RW
RW
RW
RW
RO
RW
RW
M16C/62P Group (M16C/62P, M16C/62PT)
21. Programmable I/O Ports
Port P14 Control Register (128-Pin Package)
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
PC14
Bit Symbol
After Reset
XX00XXXXb
Function
The pin level on any I/O port w hich is set for input mode
can be read by reading the corresponding bit in this
register.
The pin level on any I/O port w hich is set for output
mode can be controlled by w riting to the corresponding
bit in this register (except for P8_5)
0 : “L” level
1 : “H” level
Address
03DEh
Bit Name
Port P14_0 Bit
P140
Port P14_1 Bit
P141
—
(b3-b2)
PD140
PD141
—
(b7-b6)
Nothing is assigned. When w rite, set to “0”.
When read, their contents are indeterminate.
Port P14_0 Direction Bit
RW
RW
—
0 : Input mode
(Functions as an input port)
1 : Output mode
(Functions as an output port)
Port P14_1 Direction Bit
RW
Nothing is assigned. When w rite, set to “0”.
When read, their contents are indeterminate.
RW
RW
—
Pull-Up Control Register 3 (128-Pin Package)
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
PUR3
Bit Symbol
PU30
PU31
PU32
PU33
PU34
PU35
PU36
PU37
Address
03DFh
Bit Name
P11_0 to P11_3 Pull-UP
P11_4 to P11_7 Pull-UP
P12_0 to P12_3 Pull-UP
P12_4 to P12_7 Pull-UP
P13_0 to P13_3 Pull-UP
P13_4 to P13_7 Pull-UP
P14_0, P14_1 Pull-UP
P11 to P14 Enabling
After Reset
00h
Function
0 : Not pulled high
1 : Pulled high (1)
0 : Unusable (2)
1 : Usable
NOTES :
1. The pin for w hich this bit is “1” (pulled high) and the direction bit is “0” (input mode) is pulled high.
2. If the PU37 bit is set to “0” (unusable), the P11 to P14 registers are cleared to “0”.
Figure 21.9
PC14 and PUR3 Registers
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RW
RW
RW
RW
RW
RW
RW
RW
RW
M16C/62P Group (M16C/62P, M16C/62PT)
21. Programmable I/O Ports
Pull-up Control Register 0 (1)
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
PUR0
Bit Symbol
PU00
PU01
PU02
PU03
PU04
PU05
PU06
PU07
Address
03FCh
Bit Name
P0_0 to P0_3 Pull-Up
P0_4 to P0_7 Pull-Up
P1_0 to P1_3 Pull-Up
P1_4 to P1_7 Pull-Up
P2_0 to P2_3 Pull-Up
P2_4 to P2_7 Pull-Up
P3_0 to P3_3 Pull-Up
P3_4 to P3_7 Pull-Up
After Reset
00h
Function
0 : Not pulled high
1 : Pulled high (2)
RW
RW
RW
RW
RW
RW
RW
RW
RW
NOTES :
1. During memory extension and microprocessor modes, the pins are not pulled high although their corresponding register
contents can be modified.
2. The pin for w hich this bit is “1” (pulled high) and the direction bit is “0” (input mode) is pulled high.
Pull-Up Control Register 1
b7 b6 b5 b4 b3 b2 b1 b0
Bit Symbol
PU10
PU11
PU12
PU13
PU14
PU15
PU16
PU17
After Reset (5)
00000000b
00000010b
Function
Address
03FDh
Symbol
PUR1
Bit Name
P4_0 to P4_3 Pull-Up (2)
P4_4 to P4_7 Pull-Up (4)
P5_0 to P5_3 Pull-Up (2)
P5_4 to P5_7 Pull-Up (2)
P6_0 to P6_3 Pull-Up
P6_4 to P6_7 Pull-Up
P7_2 to P7_3 Pull-Up (1)
P7_4 to P7_7 Pull-Up
0 : Not pulled high
1 : Pulled high (3)
RW
RW
RW
RW
RW
RW
RW
RW
RW
NOTES :
1. The P7_0 and P7_1 pins do not have pull-ups.
2. During memory extension and microprocessor modes, the pins are not pulled high although the contents of these bits
can be modified.
3. The pin for w hich this bit is “1” (pulled high) and the direction bit is “0” (input mode) is pulled high.
4. If the PM01 to PM00 bits in the PM0 register are set to “01b” (memory expansion mode) or “11b” (microprocessor mode)
in a program during single-chip mode, the PU11 bit becomes “1”.
5. The values after hardw are reset 1 and low voltage detection reset (hardw are reset 2) are as follow s:
• 00000000b w hen input on CNVSS pin is “L”
• 00000010b w hen input on CNVSS pin is “H”
The values after softw are reset, w atchdog timer reset and oscillation stop detection reset are as follow s:
• 00000000b w hen PM01 to PM00 bits are “00b” (single-chip mode)
• 00000010b w hen PM01 to PM00 bits are “01b” (memory expansion mode) or “11b” (microprocessor mode)
Figure 21.10
PUR0 and PUR1 Registers
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21. Programmable I/O Ports
Pull-Up Control Register 2
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
PUR2
Bit Symbol
PU20
PU21
PU22
PU23
PU24
PU25
—
(b7-b6)
Address
03FEh
Bit Name
0 : Not pulled high
P8_0 to P8_3 Pull-Up
1 : Pulled high (1)
P8_4 to P8_7 Pull-Up (2)
P9_0 to P9_3 Pull-Up
P9_4 to P9_7 Pull-Up
P10_0 to P10_3 Pull-Up
P10_4 to P10_7 Pull-Up
Nothing is assigned. When w rite, set to “0”.
When read, their contenta are “0”.
After Reset
00h
Function
RW
RW
RW
RW
RW
RW
RW
—
NOTES :
1. The pin for w hich this bit is “1” (pulled high) and the direction bit is “0” (input mode) is pulled high.
2. The P8_5 pin does not have pull-up.
Figure 21.11
PUR2 Register
Port Control Register
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
PCR
Bit Symbol
PCR0
—
(b7-b1)
Figure 21.12
Address
After Reset
03FFh
00h
Bit Name
Function
Port P1 Control Bit
Operation performed w hen the P1 register is read
0 : When the port is set for input, the input levels of
P1_0 to P1_7 pins are read. When set for output,
the port latch is read.
1 : The port latch is read regardless of w hether the
port is set for input or output.
Nothing is assigned. When w rite, set to “0”.
When read, their contents are “0”.
PCR Register
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RW
—
M16C/62P Group (M16C/62P, M16C/62PT)
Table 21.2
21. Programmable I/O Ports
Unassigned Pin Handling in Single-chip Mode
Pin Name
Ports P0 to P7,
P8_0 to P8_4, P8_6 to P8_7,
P9 to P14
XOUT (4)
NMI
AVCC
AVSS, VREF, BYTE
Connection
After setting for input mode, connect every pin to VSS via a resistor (pulldown);
or after setting for output mode, leave these pins open. (1, 2, 3, 5)
Open
Connect via resistor to VCC1 (pull-up)
Connect to VCC1
Connect to VSS
NOTES:
1. When setting the port for output mode and leave it open, be aware that the port remains in input
mode until it is switched to output mode in a program after reset. For this reason, the voltage level
on the pin becomes indeterminate, causing the power supply current to increase while the port
remains in input mode.
Furthermore, by considering a possibility that the contents of the direction registers could be
changed by noise or noise-induced runaway, it is recommended that the contents of the direction
registers be periodically reset in software, for the increased reliability of the program.
2. Make sure the unused pins are processed with the shortest possible wiring from the microcomputer
pins (within 2 cm).
3. When the ports P7_0 and P7_1 are set for output mode, make sure a low-level signal is output from
the pins.
The ports P7_0 and P7_1 are N-channel open-drain outputs.
4. With external clock input to XIN pin.
5. Process the port without a pin in the 80-pin version and the 100-pin version as follows.
80-pin version
• Set the direction bits in these ports to “1” (output mode), and set the output data to “0” (“L”)
using the program.
•Ports P11 to P14 do not exist.
100-pin version
•After reset, PU37 bit is “0” (P11 to P14 do not used).
Do not write “1” to PU37 bit. When read, value of PU37 bit is indeterminate.
•The port direction bit in the P11 to P14 can be set “0” or “1”.
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Table 21.3
21. Programmable I/O Ports
Unassigned Pin Handling in Memory Expansion Mode and Microprocessor Mode
Pin Name
Ports P0 to P7,
P8_0 to P8_4, P8_6 to P8_7,
P9 to P14
P4_5/CS1 to P4_7/CS3
BHE, ALE, HLDA, XOUT (5),
BCLK (6)
Connection
After setting for input mode, connect every pin to VSS via a resistor (pulldown);
or after setting for output mode, leave these pins open. (1, 2, 3, 4, 7)
Connect to VCC2 via a resistor (pulled high) by setting the corresponding
direction bit in the PD4 register for CSi (i=1 to 3) to “0” (input mode) and
the CSi bit in the CSR register to “0” (chip select disabled).
Open
HOLD, RDY
Connect via resistor to VCC2 (pull-up)
NMI (P8_5)
AVCC
AVSS, VREF
Connect via resistor to VCC1 (pull-up)
Connect to VCC1
Connect to VSS
NOTES:
1. When setting the port for output mode and leave it open, be aware that the port remains in input
mode until it is switched to output mode in a program after reset. For this reason, the voltage level
on the pin becomes indeterminate, causing the power supply current to increase while the port
remains in input mode.
Furthermore, by considering a possibility that the contents of the direction registers could be
changed by noise or noise-induced runaway, it is recommended that the contents of the direction
registers be periodically reset in software, for the increased reliability of the program.
2. Make sure the unused pins are processed with the shortest possible wiring from the microcomputer
pins (within 2 cm).
3. If the CNVSS pin has the VSS level applied to it, these pins are set for input ports until the processor
mode is switched over in a program after reset. For this reason, the voltage levels on these pins
become indeterminate, causing the power supply current to increase while they remain set for input
ports.
4. When the ports P7_0 and P7_1 are set for output mode, make sure a low-level signal is output from
the pins.
The ports P7_0 and P7_1 are N-channel open-drain outputs.
5. With external clock input to XIN pin.
6. If the PM07 bit in the PM0 register is set to “1” (BCLK not output), connect this pin to VCC2 via a
resistor (pulled high).
7. Process the port without a pin in the 100-pin version as follows.
•After reset, PU37 bit is “0” (P11 to P14 do not used).
Do not write “1” to PU37 bit. When read, value of PU37 bit is indeterminate.
•The port direction bit in the P11 to P14 can be set “0” or “1”.
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21. Programmable I/O Ports
Microcomputer
Port P0 to P14
(except for P8_5) (2)
Microcomputer
(Input mode)
Port P6 to P14
(except for P8_5) (2)
(Input mode)
(Output mode)
(Input mode)
(Input mode)
Open
VCC1
(Output mode)
VCC2
VCC1
Open
NMI
NMI
AVCC
BHE
HLDA
ALE
XOUT
BCLK (1)
BYTE
HOLD
AVSS
RDY
VREF
AVCC
XOUT
Port P4_5 / CS1
to P4_7 / CS3
Open
VCC1
Open
VCC2
VCC1
AVSS
VREF
VSS
VSS
In single-chip mode
In memory expansion mode or
in microprocessor mode
NOTES :
1. If the PM07 bit in the PM0 register is set to “1” (BCLK not output), connect this pin to VCC2 via a resistor
(pulled high).
2. When not using all of the P11 to P14, the P11 to P14 pins may be left open by setting the PU37 bit in the
PUR3 register to “0” (P11 to P14 unusable) without causing any problem.
Figure 21.13
Unassigned Pins Handling
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M16C/62P Group (M16C/62P, M16C/62PT)
22. Flash Memory Version
22. Flash Memory Version
Aside from the built-in flash memory, the flash memory version microcomputer has the same functions as the masked
ROM version.
In the flash memory version, the flash memory can perform in three rewrite modes: CPU rewrite mode, standard serial
I/O mode and parallel I/O mode.
Table 22.1 lists specifications of the flash memory version. See Table 1.1 to Table 1.3 Performance outline of
M16C/62PT group for the items not listed in Table 22.1.
Table 22.1
Flash Memory Version Specifications
Item
Specification
Flash Memory Rewrite Mode
3 modes (CPU rewrite, standard serial I/O, parallel I/O)
Erase Block
User ROM Area See Figure 22.1 Flash Memory Block Diagram
Boot ROM Area 1 block (4 Kbytes) (1)
Program Method
In units of word, in units of byte (2)
Erase Method
Collective erase, block erase
Program and Erase Control Method
Program and erase controlled by software command
Protect Method
The lock bit protects each block
Number of Commands
8 commands
Program and Erase Endurance
100 times, 1,000 times/10,000 times (option) (3, 4)
Data Retention
10 years
ROM Code Protection
Parallel I/O and standard serial I/O modes are supported
NOTES:
1. The boot ROM area contains a standard serial I/O mode rewrite control program which is stored in it
when shipped from the factory. This area can only be rewritten in parallel input/output mode.
2. Can be programmed in byte units in only parallel input/output mode.
3. Block 1 and block A are 10,000 times of programming and erasure. All other blocks are 1,000 times
of programming and erasure.
4. Definition of program and erase endurance
The programming and erasure times are defined to be per-block erasure times. For example,
assume a case where a 4-Kbyte block A is programmed in 2,048 operations by writing one word at
a time and erased thereafter.
In this case, the block is reckoned as having been programmed and erased once.
If a product is 100 times of programming and erasure, each block in it can be erased up to 100
times. When 10,000 times of programming and erasure, block 1 and block A can each be erased
up to 10,000 times. All other blocks can each be erased up to 1,000 times.
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Table 22.2
22. Flash Memory Version
Flash Memory Rewrite Modes Overview
Flash Memory
CPU rewrite Mode (1)
Rewrite Mode
Function
The User ROM area is rewritten when
the CPU executes software commands.
EW0 mode:
Rewrite in areas other than flash
memory (2)
EW1 mode:
Can be rewritten in the flash memory
User ROM area
Areas which
can be
Rewritten
Operating
Single-chip mode
Mode
Memory expansion mode (EW0 mode)
Boot mode (EW0 mode)
ROM
None
Programmer
Standard Serial I/O Mode
Parallel I/O Mode
The user ROM area is
rewritten using a dedicated
serial programmer.
Standard serial I/O mode 1:
Clock synchronous serial I/O
Standard serial I/O mode 2:
UART
User ROM area
The boot ROM area and
user ROM area is rewritten
using a dedicated parallel
programmer.
User ROM area
Boot ROM area
Boot mode
Parallel I/O mode
Serial programmer
Parallel programmer
NOTES:
1. The PM13 bit remains set to “1” while the FMR01 bit in the FMR0 register = 1 (CPU rewrite mode enabled). The
PM13 bit is reverted to its original value by clearing the FMR01 bit to “0” (CPU rewrite mode disabled).
However, if the PM13 bit is changed during CPU rewrite mode, its changed value is not reflected until after the
FMR01 bit is cleared to “0”.
2. When in CPU rewrite mode, the PM10 and PM13 bits in the PM1 register are set to “1”. The rewrite control
program can only be executed in the internal RAM or in an external area that is enabled for use when the PM13
bit = 1. When the PM13 bit = 0 and the flash memory is used in 4-Mbyte mode, the extended accessible area
(40000h to BFFFFh) cannot be used.
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22.1
22. Flash Memory Version
Memory Map
The flash memory contains the user ROM area and the boot ROM area. The user ROM area has space to store the
microcomputer operating program in single-chip mode or memory expansion mode and a separate 4-Kbyte space
as the block A. Figure 22.1 shows a Flash Memory Block Diagram.
The user ROM area is divided into several blocks, each of which can be protected (locked) from program or erase.
The user ROM area can be rewritten in CPU rewrite, standard serial I/O and parallel I/O modes.
Block A is enabled for use by setting the PM10 bit in the PM1 register to “1” (block A enabled, CS2 area at
addresses 10000h to 26FFFh).
The boot ROM area is located at the same addresses as the user ROM area. It can only be rewritten in parallel I/O
mode (refer to 22.1.1 Boot Mode). A program in the boot ROM area is executed after a hardware reset occurs
while an “H” signal is applied to the CNVSS and P5_0 pins and an “L” signal is applied to the P5_5 pin (refer to
22.1.1 Boot Mode). A program in the user ROM area is executed after a hardware reset occurs while an “L” signal
is applied to the CNVSS pin. However, the boot ROM area cannot be read.
00F000h
00FFFFh
Block A : 4 Kbytes
080000h
Block 12 : 64 Kbytes
08FFFFh
090000h
Block 11 : 64 Kbytes
09FFFFh
0A0000h
Block 10 : 64 Kbytes
0AFFFFh
0B0000h
Block 9 : 64 Kbytes
0BFFFFh
0F0000h
0C0000h
Block 8 : 64 Kbytes
0CFFFFh
Block 5 : 32 Kbytes
0D0000h
Block 7 : 64 Kbytes
0DFFFFh
0F7FFFh
0F8000h
0E0000h
Block 4 : 8 Kbytes
Block 6 : 64 Kbytes
0F9FFFh
0FA000h
Block 3 : 8 Kbytes
0EFFFFh
0FBFFFh
0FC000h
0F0000h
Block 2 : 8 Kbytes
Block 0 to Block 5
(32+8+8+8+4+4) Kbytes
0FDFFFh
0FE000h
0FEFFFh
0FF000h
0FFFFFh
0FFFFFh
User ROM area
Block 1 : 4 Kbytes
Block 0 : 4 Kbytes
0FF000h
0FFFFFh
4 Kbytes
Boot ROM area
NOTES:
1. The boot ROM area can only be rewritten in parallel input/output mode.
2. To specify a block, use an even address in that block.
3. Shown here is a block diagram during single-chip mode.
4. Block A can be made usable by setting the PM10 bit in the PM1 register to “1” (block A enabled, CS2 area allocated at addresses 10000h to 26FFFh).
Block A cannot be erased by the Erase All Unlocked Block command. Use the Block Erase command to erase it.
Figure 22.1
Flash Memory Block Diagram
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22.1.1
22. Flash Memory Version
Boot Mode
The microcomputer enters boot mode when a hardware reset occurs while an “H” signal is applied to the
CNVSS and P5_0 pins and an “L” signal is applied to the P5_5 pin. A program in the boot ROM area is
executed.
In boot mode, the FMR05 bit in the FMR0 register selects access to the boot ROM area or the user ROM area.
The rewrite control program for standard serial I/O mode is stored in the boot ROM area before shipment.
The boot ROM area can be rewritten in parallel I/O mode only. If any rewrite control program using erase-write
mode (EW0 mode) is written in the boot ROM area, the flash memory can be rewritten according to the system
implemented.
22.2
Functions To Prevent Flash Memory from Rewriting
The flash memory has a built-in ROM code protect function for parallel I/O mode and a built-in ID code check
function for standard I/O mode to prevent the flash memory from reading or rewriting.
22.2.1
ROM Code Protect Function
The ROM code protect function inhibits the flash memory from being read or rewritten during parallel input/
output mode. Figure 22.2 shows the ROMCP Register. The ROMCP register is located in the user ROM area.
The ROM code protect function is enabled when the ROMCR bits are set to other than “11b”. In this case, set
the bit 5 to bit 0 to “111111b”.
When exiting ROM code protect, erase the block including the ROMCP1 register by the CPU rewrite mode or
the standard serial I/O mode.
22.2.2
ID Code Check Function
Use the ID code check function in standard serial I/O mode. The ID code sent from the serial programmer is
compared with the ID code written in the flash memory for a match. If the ID codes do not match, commands
sent from the serial programmer are not accepted. However, if the four bytes of the reset vector are
“FFFFFFFFh”, ID codes are not compared, allowing all commands to be accepted.
The ID codes are 7-byte data stored consecutively, starting with the first byte, into addresses 0FFFDFh,
0FFFE3h, 0FFFEBh, 0FFFEFh, 0FFFF3h, 0FFFF7h, and 0FFFFBh. The flash memory must have a program
with the ID codes set in these addresses.
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ROM Code Protect Control Address
22. Flash Memory Version
(5)
b7 b6 b5 b4 b3 b2 b1 b0
1 1 1 1 1 1
Symbol
ROMCP
Address
0FFFFFh
Bit Symbol
—
(b5-b0)
ROMCP1
Factory Setting
FFh (4)
Bit Name
Reserved Bit
Function
Set to “1”
ROM Code Protect Level 1 Set b7 b6
00:
Bit (1, 2, 3, 4)
01:
ROM code protection active
10:
1 1 : ROM code protection inactive
RW
RW
RW
NOTES :
1. When the ROM code protection is active by the ROMCP1 bit setting, the flash memory is protected against reading or
rew riting in parallel I/O mode.
2. Set the bit 5 to bit 0 to “111111b” w hen the ROMCP1 bit is set to a value other than “11b”.
If the bit 5 to bit 0 are set to values other than “111111b”, the ROM code protection may not become active by setting
the ROMCP1 bit to a value other than “11b”.
3. To make the ROM code protection inactive, erase a block including the ROMCP address in standard serial I/O mode
or CPU rew rite mode.
4. The ROMCP address is set to “FFh” w hen a block, including the ROMCP address, is erased.
5. When a value of the ROMCP address is “00h” or “FFh”, the ROM code protect function is disabled.
Figure 22.2
ROMCP Register
Address
0FFFDFh to 0FFFDCh
ID1
Undefined instruction vector
0FFFE3h to 0FFFE0h
ID2
Overflow vector
0FFFE7h to 0FFFE4h
BRK instruction vector
0FFFEBh to 0FFFE8h
ID3
Address match vector
0FFFEFh to 0FFFECh
ID4
Single step vector
0FFFF3h to 0FFFF0h
ID5
Watchdog timer vector
0FFFF7h to 0FFFF4h
ID6
DBC vector
0FFFFBh to 0FFFF8h
ID7
NMI vector
0FFFFFh to 0FFFFCh
ROMCP
Reset vector
4 bytes
Figure 22.3
Address for ID Code Stored
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22.3
22. Flash Memory Version
CPU Rewrite Mode
In CPU rewrite mode, the user ROM area can be rewritten when the CPU executes software commands.
The user ROM area can be rewritten with the microcomputer mounted on a board without using a parallel or serial
programmer.
In CPU rewrite mode, only the user ROM area shown in Figure 22.1 can be rewritten. The boot ROM area cannot
be rewritten. Program and the block erase command are executed only in the user ROM area.
Erase-write 0 (EW0) mode and erase-write 1 (EW1) mode are provided as CPU rewrite mode. Table 22.3 lists
differences between erase-write 0 (EW0) and erase-write 1 (EW1) modes.
Table 22.3
EW0 Mode and EW1 Mode
Item
EW0 Mode
Operating Mode
• Single-chip mod
• Memory expansion mode
• Boot mode
Space where the
• User ROM area
rewrite control
• Boot ROM area
program can be
placed
Space where the
The rewrite control program must be
rewrite control
transferred to any space other than the
program can be
flash memory (e.g., RAM) before being
executed
executed (2)
Space which can be User ROM area
rewritten
Software Command
Restriction
None
Mode after Program Read status register mode
or Erasing
Operating
CPU State during
Auto Write and Auto
Erase
Flash Memory State • Read the FMR00, FMR06 and FMR07
Detection
bits in the FMR0 register by program
• Execute the read status register
command to read the SR7, SR5 and
SR4 bits in the status register.
EW1 Mode
• Single-chip mode
• User ROM area
The rewrite control program can be
executed in the user ROM area
User ROM area
However, this excludes blocks with the
rewrite control program
• Program and block erase commands
cannot be executed in a block having
the rewrite control program.
• Erase all unlocked block command
cannot be executed when the lock bit
in a block having the rewrite control
program is set to “1” (unlocked) or
when the FMR02 bit in the FMR0
register is set to “1” (lock bit disabled).
• Read status register command cannot
be used.
Read array mode
Maintains hold state (I/O ports maintains
the state before the command was
executed) (1)
Read the FMR00, FMR06 and FMR07
bits in the FMR0 register by program
NOTES:
1. Do not generate an interrupt (except NMI interrupt) or DMA transfer.
2. 2. When in CPU rewrite mode, the PM10 and PM13 bits in the PM1 register are set to “1”. The
rewrite control program can only be executed in the internal RAM or in an external area that is
enabled for use when the PM13 bit = 1. When the PM13 bit = 0 and the flash memory is used in 4Mbyte mode, the extended accessible area (40000h to BFFFFh) cannot be used.
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22.3.1
22. Flash Memory Version
EW0 Mode
The microcomputer enters CPU rewrite mode by setting the FMR01 bit in the FMR0 register to “1” (CPU
rewrite mode enabled) and is ready to accept commands. EW0 mode is selected by setting the FMR11 bit in the
FMR1 register to “0”. To set the FMR01 bit to “1”, set to “1” after first writing “0”.
The software commands control programming and erasing. The FMR0 register or the status register indicates
whether a program or erase operation is completed as expected or not.
22.3.2
EW1 Mode
EW1 mode is selected by setting the FMR11 bit to “1” after the FMR01 bit is set to “1”. (Both bits must be set
to “0” first before setting to “1”.)
The FMR0 register indicates whether or not a program or erase operation has been completed as expected. The
status register cannot be read in EW1 mode.
When an erase/program operation is initiated the CPU halts all program execution until the operation is
completed or erase-suspend is requested.
22.3.3
Flash memory Control Register (FIDR, FMR0 and FMR1 registers)
Figure 22.4 to Figure 22.6 show the FIDR, FMR0 and FMR1 Registers.
Flash Identification Register (1)
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
FIDR
Bit Symbol
FIDR0
Address
01B4h
Bit Name
Flash Module Type
Identification Value
FIDR1
—
(b7-b2)
After Reset
XXXXXX00b
Function
b1 b0
0 0 : M16C/62N, M3062GF8N type flash module
1 0 : M16C/62P type flash module
1 1 : M16C/62M, M16C/62A type flash
Nothing is assigned. When w rite, set to “0”.
When read, their contents are indeterminate.
RW
RO
RO
—
NOTES :
1. This register identifies on-chip flash module type of M16C/62 Group. Note, how ever, no chip version is know n by
this register. Follow the procedure described below for the identification.
(a) Write “FFh” to FIDR register,
(b) Read FIDR register, and
(c) Check tw o low -order bits of read value.
Make sure no access to external memories or other SFRs or no interrupts or DMA transfers w ill occur betw een the
above tw o instructions (a) and (b).
Figure 22.4
FIDR Register
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22. Flash Memory Version
Flash Memory Control Register 0
b7 b6 b5 b4 b3 b2 b1 b0
0
Symbol
FMR0
Address
01B7h
Bit Symbol
Bit Name
___
FMR00
FMR01
FMR02
FMR05
FMR06
FMR07
Function
RW
RY/BY Status Flag
0 : Busy (being w ritten or erased)
1 : Ready
RO
CPU Rew rite Mode Select
Bit (1)
0 : Disables CPU rew rite mode
1 : Enables CPU rew rite mode
RW
Lock Bit Disable Select Bit (2)
0 : Enables lock bit
1 : Disables lock bit
RW
Flash Memory Stop Bit (3, 5)
0 : Enables flash memory operation
1 : Stops flash memory operation
(placed in low pow er mode, flash memory
initialized)
RW
FMSTP
—
(b4)
After Reset
00000001b
Reserved Bit
Set to “0”
User ROM Area Select Bit (3)
(Effective in Only Boot Mode)
0 : Boot ROM area is accessed
1 : User ROM area is accessed
RW
Program Status Flag (4)
0 : Terminated normally
1 : Terminated in error
RO
Erase Status Flag (4)
0 : Terminated normally
1 : Terminated in error
RO
RW
NOTES :
1. To set this bit to “1,” w rite “0” and then “1” in succession. Make sure no interrupts or DMA transfers w ill occur
before w riting “1” after w ____
riting “0”.
Write to this bit w hen the NMI pin is in the high state. Also, w hile in EW0 mode, w rite to this bit from a program in
than the flash memory.
Enter read array mode and set this bit to “0”.
2. To set this bit to “1,” w rite “0” and then “1” in succession w hen the FMR01 bit = 1. Make sure no interrupts or no
DMA transfers w ill occur before w riting “1” after w riting “0”.
3. Write to this bit from a program in other than the flash memory.
4. This flag is cleared to “0” by executing the Clear Status command.
5. Effective w hen the FMR01 bit = 1 (CPU rew rite mode). If the FMR01 bit = 0, although the FMR03 bit can be set to “1”
by w riting “1” in a program, the flash memory is neither placed in low pow er mode nor initialized.
6. This status includes w riting or reading w ith the Lock Bit Program or Read Lock Bit Status command.
Figure 22.5
FMR0 Register
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22. Flash Memory Version
Flash Memory Control Register 1
b7 b6 b5 b4 b3 b2 b1 b0
0
0 0
0
Symbol
FMR1
Address
01B5h
After Reset
0X00XX0Xb
Bit Symbol
Bit Name
Function
Reserved Bit
The value in this bit w hen read is indeterminate
EW1 Mode Select Bit (1)
0: EW0 mode
1: EW1 mode
—
(b3-b2)
Reserved Bit
The value in this bit w hen read is indeterminate
—
(b5-b4)
Reserved Bit
Set to “0”
Lock Bit Status Flag
0: Lock
1: Unlock
Reserved Bit
Set to “0”
—
(b0)
FMR11
FMR16
—
(b7)
RW
RO
RW
RO
RW
RO
RW
NOTES :
1. To set this bit to “1,” w rite “0” and then “1” in succession w hen the FMR01 bit = 1. Make sure no interrupts or DMA
transfers w ill occur before
w riting “1” after w riting “0”.
____
Write to this bit w hen the NMI pin is in the high state.
The FMR01 and FMR11 bits both are cleared to “0” by setting the FMR01 bit to “0”.
Figure 22.6
FMR1 Register
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22.3.3.1
22. Flash Memory Version
FMR00 Bit
This bit indicates the flash memory operating state. It is set to “0” while the program, block erase, erase all
unlocked block, lock bit program, or read lock bit status command is being executed; otherwise, it is set to “1”.
22.3.3.2
FMR01 Bit
The microcomputer can accept commands when the FMR01 bit is set to “1” (CPU rewrite mode). Set the
FMR05 bit to “1” (user ROM area access) as well if in boot mode.
22.3.3.3
FMR02 Bit
The lock bit is disabled by setting the FMR02 bit to “1” (lock bit disabled). (Refer to 22.3.6 Data Protect
Function.) The lock bit is enabled by setting the FMR02 bit to “0” (lock bit enabled).
The FMR02 bit does not change the lock bit status but disables the lock bit function. If the block erase or erase
all unlocked block command is executed when the FMR02 bit is set to “1”, the lock bit status changes “0”
(locked) to “1” (unlocked) after command execution is completed.
22.3.3.4
FMSTP Bit
The FMSTP bit resets the flash memory control circuits and minimizes power consumption in the flash
memory. Access to the flash memory is disabled when the FMSTP bit is set to “1”. Set the FMSTP bit by
program in a space other than the flash memory.
• Set the FMSTP bit to “1” if one of the followings occurs: A flash memory access error occurs while erasing
or programming in EW0 mode (FMR00 bit does not switch back to “1” (ready)).
• Low-power consumption mode or on-chip oscillator low-power consumption mode is entered
Use the following the procedure to change the FMSTP bit setting.
(1) Set the FMSTP bit to “1”
(2) Set tps (the wait time to stabilize flash memory circuit)
(3) Set the FMSTP bit to “0”
(4) Set tps (the wait time to stabilize flash memory circuit)
Figure 22.9 shows a Flow Chart Illustrating How To Start and Stop the Flash Memory Processing Before and
After Low Power Dissipation Mode or On-chip Oscillator Low-Power Consumption Mode. Follow the
procedure on this flow chart.
When entering stop or wait mode, the flash memory is automatically turned off. When exiting stop or wait
mode, the flash memory is turned back on. The FMR0 register does not need to be set.
22.3.3.5
FMR05 Bit
This bit selects the boot ROM or user ROM area in boot mode. Set to “0” to access (read) the boot ROM area or
to “1” (user ROM access) to access (read, write or erase) the user ROM area.
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22.3.3.6
22. Flash Memory Version
FMR06 Bit
This is a read-only bit indicating an auto program operation state. The FMR06 bit is set to “1” when a program
error occurs; otherwise, it is set to “0”. Refer to 22.3.8 Full Status Check.
22.3.3.7
FMR07 Bit
This is a read-only bit indicating the auto erase operation status. The FMR07 bit is set to “1” when an erase
error occurs; otherwise, it is set to “0”. For details, refer to 22.3.8 Full Status Check.
Figure 22.7 shows Setting and Resetting of EW0 Mode. Figure 22.8 show Setting and Resetting of EW1 Mode.
22.3.3.8
FMR11 Bit
EW0 mode is entered by setting the FMR11 bit to “0” (EW0 mode).
EW1 mode is entered by setting the FMR11 bit to “1” (EW1 mode).
22.3.3.9
FMR16 Bit
This is a read-only bit indicating the execution result of the read lock bit status command.
When the block, where the read lock bit status command is executed, is locked, the FMR16 bit is set to “0”.
When the block, where the read lock bit status command is executed, is unlocked, the FMR16 bit is set to “1”.
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22. Flash Memory Version
Procedure to Enter EW0 Mode
Rewrite control program
Single-chip mode, memory expansion
mode or boot mode
Transfer the rewrite control program in CPU
rewrite mode to a space other than the flash
memory (5)
In boot mode only
Set the FMR05 bit to “1” (user ROM area accessed)
Set the FMR01 bit to “1” (CPU rewrite mode
enabled) after writing “0” (2)
Execute the software commands
Set CM0, CM1 and PM1 registers (1)
Execute the read array command (3)
Jump to the rewrite control program transferred to a
space other than the flash memory. (In the following
steps, use the rewrite control program in a space
other than the flash memory)
Set the FMR01 bit to “0”
(CPU rewrite mode disabled)
In boot mode only
Set the FMR05 bit to “0”
(boot ROM area accessed)
(4)
Jump to a desired address in the flash memory
NOTES :
1. In CPU rewrite mode, set the CM06 bit in the CM0 register and CM17 to 6 bits in the CM1 register to CPU
clock frequency of 10.0 MHz or less. Set the PM17 bit in the PM1 register to “1” (with wait state).
2. Set the FMR01 bit to “1” immmediately after setting it to “0” Do not generate an interrupt or a DMA transfer
between setting the bit to “0” and setting it to “1”. Set the bit to “0”. Set this in a space other than flash
memory while the NMI pin is held “H”.
3. Exit CPU rewrite mode after executing the read array command.
4. When CPU rewrite mode is exited while FMR05 bit is set to “1”, the user ROM area can be accessed.
5.When in CPU rewrite mode, the PM10 and PM13 bits in the PM1 register are set to “1”. The rewrite control
program can only be executed in the internal RAM or in an external area that is enabled for use when the
PM13 bit = 1. When the PM13 bit = 0 and the flash memory is used in 4M-byte mode, the extended
accessible area (40000h to BFFFFh) cannot be used.
Figure 22.7
Setting and Resetting of EW0 Mode
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22. Flash Memory Version
Procedure to Enter EW1 Mode
Program in the ROM
Single-chip mode
(1)
Set the CM0, CM1, PM1 registers
(2)
Set the FMR01 bit to “1” (CPU rewrite mode enabled)
after writing “0”
Set the FMR11 bit to “1” (EW1 mode) after writing
“0” (EW1 mode) (3)
Execute the software commands
Set the FMR01 bit to 0
(CPU rewrite mode disabled)
NOTES:
1. In EW1 mode, do not enter memory expansion or boot mode.
2. In CPU rewrite mode, set the CM06 bit in the CM0 register and the CM17 to 6 bits in the
CM1 register to CPU clock frequency of 10.0 MHz or less. Set the PM17 bit in the PM1
register to “1” (with wait state).
3. Set the FMR01 bit to “1” immediately after setting it to “0”. Do not generate an interrupt or a
DMA transfer between setting the bit to “0” and setting it to “1”.
Set the FMR11 bit to “1” immediately after setting it to “0” while the FMR01 bit is set to “1”.
Do not generate an interrupt or a DMA transfer between setting the FMR11 bit to 0 and
setting it to “1”.
Set the FMR01 and FMR11 bits while “H” is applied to the NMI pin.
Figure 22.8
Setting and Resetting of EW1 Mode
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Transfer the low-power consumption mode or
on-chip oscillator low-power consumption mode
program to a space other than the flash memory
22. Flash Memory Version
Low-power consumption mode or
on-chip oscillator low-power
consumption mode program
Jump to the low-power consumption mode or
on-chip oscillator low-power consumption mode
program transferred to a space other than the
flash memory. (In the following steps, use the
low-power consumption mode or on-chip oscillator
low-power consumption mode program in a space
other than the flash memory.)
Set the FMR01 bit to “1” after setting it to “0”
(CPU rewrite mode enabled)
Set the FMSTP bit to “1” (The flash memory stops
operating. It is in a low-power consumption state) (1)
Switch clock source of the CPU clock.
The main clock stops.(2)
Process in low-power consumption mode or
on-chip oscillator low-power consumption mode
Start main
clock
oscillation
NOTES:
1. Set the FMSTP bit to “1” after the FMR01 bit is set to “1”
(CPU rewrite mode enabled).
2. Wait until clock stabilizes to switch clock source of
the CPU clock to the main clock or sub clock.
3. Add tps µs wait time by program. Do not access the
flash memory during this wait time.
4. Before entering wait mode or stop mode, be sure
to set the FMR01 bit to “0”.
Wait until
oscillation
stabilizes
(4)
Switch clock
source of the
CPU clock (2)
Set the FMSTP bit to “0” (flash memory operation)
Set the FMR01 bit to “0”
(CPU rewrite mode disabled)
Wait until the flash memory stabilizes (tps µs) (3)
Jump to a desired address in the flash memory
Figure 22.9
Processing Before and After Low Power Dissipation Mode or On-chip Oscillator LowPower Consumption Mode
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22.3.4
22. Flash Memory Version
Precautions on CPU Rewrite Mode
22.3.4.1
Operating Speed
Set the CM06 bit in the CM0 register and the CM17 to CM16 bits in the CM1 register to a CPU clock frequency
of 10 MHz or less before entering CPU rewrite mode (EW0 or EW1 mode). Also, set the PM17 bit in the PM1
register to “1” (wait state).
22.3.4.2
Prohibited Instructions
The following instructions cannot be used in EW0 mode because the CPU tries to read data in the flash
memory: the UND instruction, INTO instruction, JMPS instruction, JSRS instruction, and BRK instruction.
22.3.4.3
Interrupts (EW0 mode)
• To use interrupts having vectors in a relocatable vector table, the vectors must be relocated to the RAM
area.
• The NMI and watchdog timer interrupts are available since the FMR0 and FMR1 registers are forcibly reset
when either interrupt occurs. Allocate the jump addresses for each interrupt service routines to the fixed
vector table. Flash memory rewrite operation is suspended when the NMI or watchdog timer interrupt
occurs. Execute the rewrite program again after exiting the interrupt routine.
• The address match interrupt is not available since the CPU tries to read data in the flash memory.
22.3.4.4
Interrupts (EW1 mode)
• Do not acknowledge any interrupts with vectors in the relocatable vector table or address match interrupt
during the auto program or auto erase period.
• Do not use the watchdog timer interrupt.
• The NMI interrupt is available since the FMR0 and FMR1 registers are forcibly reset when the interrupt
occurs. Allocate the jump address for the interrupt service routine to the fixed vector table. Flash memory
rewrite operation is suspended when the NMI interrupt occurs. Execute the rewrite program again after
exiting the interrupt service routine.
22.3.4.5
22.3.4.5 How to Access
To set the FMR01, FMR02 or FMR11 bit to “1”, write “1” after first setting the bit to “0”. Do not generate an
interrupt or a DMA transfer between the instruction to set the bit to “0” and the instruction to set the bit to “1”.
Set the bit while an “H” signal is applied to the NMI pin.
22.3.4.6
22.3.4.6 Rewriting in the User ROM Area (EW0 mode)
If the supply voltage drops while rewriting the block where the rewrite control program is stored, the flash
memory cannot be rewritten because the rewrite control program is not correctly rewritten. If this error occurs,
rewrite the user ROM area while in standard serial I/O mode or parallel I/O mode.
22.3.4.7
22.3.4.7 Rewriting in the User ROM Area (EW1 mode)
Avoid rewriting any block in which the rewrite control program is stored.
22.3.4.8
22.3.4.8 DMA Transfer
In EW1 mode, do not perform a DMA transfer while the FMR00 bit in the FMR0 register is set to “0” (auto
programming or auto erasing).
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22.3.4.9
22. Flash Memory Version
Writing Command and Data
Write commands and data to even addresses in the user ROM area.
22.3.4.10 Wait Mode
When entering wait mode, set the FMR01 bit to “0” (CPU rewrite mode disabled) before executing the WAIT
instruction.
22.3.4.11 Stop Mode
When entering stop mode, the following settings are required:
• Set the FMR01 bit to “0” (CPU rewrite mode disabled). Disable DMA transfer before setting the CM10 bit
to “1” (stop mode).
22.3.4.12 Low-Power Consumption Mode and On-chip Oscillator Low-power
Consumption Mode
If the CM05 bit is set to “1” (main clock stopped), do not execute the following commands:
• Program
• Block erase
• Erase all unlocked blocks
• Lock bit program
• Read lock bit status
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22.3.5
22. Flash Memory Version
Software Commands
Software commands are described below. The command code and data must be read and written in 16-bit units,
to and from even addresses in the user ROM area. When writing command code, the 8 high-order bits (D15 to
D8) are ignored.
Table 22.4
Software Commands
First Bus Cycle
Command
Read Array
Read Status Register
Clear Status Register
Program
Block Erase
Erase All Unlocked Block
Lock Bit Program
Read Lock Bit Status
Mode
Address
Write
Write
Write
Write
Write
Write
Write
Write
X
X
X
WA
X
X
BA
X
Second Bus Cycle
Data
(D0 to D7)
xxFFh
xx70h
xx50h
xx40h
xx20h
xxA7h
xx77h
xx71h
Mode
Address
Data
(D0 to D7)
Read
X
SRD
Write
Write
Write
Write
Write
WA
BA
X
BA
BA
WD
xxD0h
xxD0h
xxD0h
xxD0h
NOTES:
1. Blocks 0 to 12 can be erased by the erase all unlocked block command.
Block A cannot be erased. The block erase command must be used to erase the block A.
SRD: Data in the SRD register (D7 to D0)
WA: Address to be written (The address specified in the first bus cycle is the same even
address as the address specified in the second bus cycle.)
WD: 16-bit write data
BA: Highest-order block address (must be an even address)
X:
Any even address in the user ROM space
xx:
8 high-order bits of command code (ignored)
22.3.5.1
Read Array Command (FFh)
The read array command reads the flash memory.
By writing command code “xxFFh” in the first bus cycle, read array mode is entered. Content of a specified
address can be read in 16-bit units after the next bus cycle.
The microcomputer remains in read array mode until another command is written. Therefore, contents from
multiple addresses can be read consecutively.
22.3.5.2
Read Status Register Command (70h)
The read status register command reads the status register (refer to 22.3.7 Status Register for detail).
By writing command code “xx70h” in the first bus cycle, the status register can be read in the second bus cycle.
Read an even address in the user ROM area.
Do not execute this command in EW1 mode.
22.3.5.3
Clear Status Register Command (50h)
The clear status register command clears the status register. By writing “xx50h” in the first bus cycle, the
FMR07 to FMR06 bits in the FMR0 register are set to “00b” and the SR5 to SR4 bits in the status register are
set to “00b”.
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22.3.5.4
22. Flash Memory Version
Program Command (40h)
The program command writes 2-byte data to the flash memory. By writing “xx40h” in the first bus cycle and
data to the write address in the second bus cycle, an auto program operation (data program and verify) will start.
The address value specified in the first bus cycle must be the same even address as the write address specified in
the second bus cycle.
The FMR00 bit in the FMR0 register indicates whether an auto program operation has been completed. The
FMR00 bit is set to “0” (busy) during auto program and to “1” (ready) when an auto program operation is
completed.
After the completion of an auto program operation, the FMR06 bit in the FMR0 register indicates whether or
not the auto program operation has been completed as expected. (Refer to 22.3.8 Full Status Check.)
An address that is already written cannot be altered or rewritten.
Figure 22.10 shows a Flow Chart of the Program Command Programming.
The lock bit protects each block from being programmed inadvertently. (Refer to 22.3.6 Data Protect
Function.)
In EW1 mode, do not execute this command on the block where the rewrite control program is allocated.
In EW0 mode, the microcomputer enters read status register mode as soon as an auto program operation starts.
The status register can be read. The SR7 bit in the status register is set to “0” at the same time an auto program
operation starts. It is set to “1” when auto program operation is completed. The microcomputer remains in read
status register mode until the read array command is written. After completion of an auto program operation,
the status register indicates whether or not the auto program operation has been completed as expected.
Start
Write the command code “xx40h”
to an address to be written
Write data to an
address to be written
FMR00=1?
NO
YES
Full status check
Program operation is
completed
NOTES:
1. Write the command code and data to even addresses.
Figure 22.10
Program Command
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22.3.5.5
22. Flash Memory Version
Block Erase Command
The block erase command erases each block.
By writing “xx20h” in the first bus cycle and “xxD0h” to the highest-order even address of a block in the
second bus cycle, an auto erase operation (erase and verify) will start in the specified block.
The FMR00 bit in the FMR0 register indicates whether an auto erase operation has been completed.
The FMR00 bit is set to “0” (busy) during auto erase and to “1” (ready) when the auto erase operation is
completed.
After the completion of an auto erase operation, the FMR07 bit in the FMR0 register indicates whether or not
the auto erase operation has been completed as expected. (Refer to 22.3.8 Full Status Check.)
Figure 22.11 shows a Flow Chart of the Block Erase Command Programming.
The lock bit protects each block from being programmed inadvertently. (Refer to 22.3.6 Data Protect
Function.)
In EW1 mode, do not execute this command on the block where the rewrite control program is allocated. In
EW0 mode, the microcomputer enters read status register mode as soon as an auto erase operation starts. The
status register can be read. The SR7 bit in the status register is set to “0” at the same time an auto erase
operation starts. It is set to “1” when an auto erase operation is completed. The microcomputer remains in read
status register mode until the read array command or read lock bit status command is written. Also execute the
clear status register command and block erase command at least 3 times until an erase error is not generated
when an erase error is generated.
Start
Write the command code “xx20h” (1)
Write “xxD0h” to the highest-order
block address
FMR00=1?
NO
YES
Full status check (2, 3)
Block erase operation is
completed
NOTES:
1. Write the command code and data to even addresses.
2. Refer to “Figure 22.14 Full Status Check and Handling Procedure
for Each Error”.
3. Execute the clear status register command and block erase
command at least 3 times until an erase error is not generated when
an erase error is generated.
Figure 22.11
Block Erase Command
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22.3.5.6
22. Flash Memory Version
Erase All Unlocked Block
The erase all unlocked block command erases all blocks except the block A.
By writing “xxA7h” in the first bus cycle and “xxD0h” in the second bus cycle, an auto erase (erase and verify)
operation will run continuously in all blocks except the block A.
The FMR00 bit in the FMR0 register indicates whether an auto erase operation has been completed.
After the completion of an auto erase operation, the FMR07 bit in the FMR0 register indicates whether or not
the auto erase operation has been completed as expected.
The lock bit can protect each block from being programmed inadvertently. (Refer to 22.3.6 Data Protect
Function.)
In EW1 mode, do not execute this command when the lock bit for any block storing the rewrite control program
is set to “1” (unlocked) or when the FMR02 bit in the FMR0 register is set to “1” (lock bit disabled).
In EW0 mode, the microcomputer enters read status register mode as soon as an auto erase operation starts. The
status register can be read. The SR7 bit in the status register is set to “0” (busy) at the same time an auto erase
operation starts. It is set to “1” (ready) when an auto erase operation is completed. The microcomputer remains
in read status register mode until the read array command or read lock bit status command is written.
Only blocks 0 to 12 can be erased by the erase all unlocked block command. The block A cannot be erased. Use
the block erase command to erase the block A.
22.3.5.7
Lock Bit Program Command
The lock bit program command sets the lock bit for a specified block to “0” (locked).
By writing “xx77h” in the first bus cycle and “xxD0h” to the highest-order even address of a block in the
second bus cycle, the lock bit for the specified block is set to “0”. The address value specified in the first bus
cycle must be the same highest-order even address of a block specified in the second bus cycle.
Figure 22.12 shows a Flow Chart of the Lock Bit Program Command Programming. Execute read lock bit
status command to read lock bit state (lock bit data).
The FMR00 bit in the FMR0 register indicates whether a lock bit program operation is completed.
Refer to 22.3.6 Data Protect Function for details on lock bit functions and how to set it to “1” (unlocked).
Start
Write the command code “xx77h” to
the highest-order block address
Write “xxD0h” to the highest-order
block address
NO
FMR00=1?
YES
Full status check
Lock bit program operation
is completed
NOTES:
1. Write the command code and data to even addresses.
Figure 22.12
Lock Bit Program Command
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M16C/62P Group (M16C/62P, M16C/62PT)
22.3.5.8
22. Flash Memory Version
Read Lock Bit Status Command (71h)
The read lock bit status command reads the lock bit state of a specified block.
By writing “xx71h” in the first bus cycle and “xxD0h” to the highest-order even address of a block in the
second bus cycle, the FMR16 bit in the FMR1 register stores information on whether or not the lock bit of a
specified block is locked. Read the FMR16 bit after the FMR00 bit in the FMR0 register is set to “1” (ready).
Figure 22.13 shows a Flow Chart of the Read Lock Bit Status Command Programming.
Start
Write the command code “xx71h”
Write “xxD0h” to the highest-order
block address
NO
FMR00=1?
YES
FMR16=0?
NO
YES
Block is locked
Block is not locked
NOTES:
1. Write the command code and data to even addresses.
Figure 22.13
Read Lock Bit Status Command
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M16C/62P Group (M16C/62P, M16C/62PT)
22.3.6
22. Flash Memory Version
Data Protect Function
Each block in the flash memory has a nonvolatile lock bit. The lock bit is enabled by setting the FMR02 bit to
“0” (lock bit enabled). The lock bit allows each block to be individually protected (locked) against program and
erase. This helps prevent data from being inadvertently written to or erased from the flash memory.
• When the lock bit status is set to “0”, the block is locked (block is protected against program and erase).
• When the lock bit status is set to “1”, the block is not locked (block can be programmed or erased).
The lock bit status is set to “0” (locked) by executing the lock bit program command and to “1” (unlocked) by
erasing the block. The lock bit status cannot be set to “1” by any commands.
The lock bit status can be read by the read lock bit status command.
The lock bit function is disabled by setting the FMR02 bit to “1”. All blocks are unlocked. However, individual
lock bit status remains unchanged. The lock bit function is enabled by setting the FMR02 bit to “0”. Lock bit
status is retained.
If the block erase or erase all unlocked block command is executed while the FMR02 bit is set to “1”, the target
block or all blocks are erased regardless of lock bit status. The lock bit status of each block are set to “1” after
an erase operation is completed.
Refer to 22.3.5 Software Commands for details on each command.
22.3.7
Status Register
The status register indicates the flash memory operation state and whether or not an erase or program operation
is completed as expected. The FMR00, FMR06 and FMR07 bits in the FMR0 register indicate status register
states.
Table 22.5 shows the Status Register.
In EW0 mode, the status register can be read when the followings occur.
• Any even address in the user ROM area is read after writing the read status register command.
• Any even address in the user ROM area is read from when the program, block erase, erase all unlocked
block, or lock bit program command is executed until when the read array command is executed.
22.3.7.1
Sequence Status (SR7 and FMR00 Bits)
The sequence status indicates the flash memory operation state. It is set to “0” while the program, block erase,
erase all unlocked block, lock bit program, or read lock bit status command is being executed; otherwise, it is
set to “1”.
22.3.7.2
Erase Status (SR5 and FMR07 Bits)
Refer to 22.3.8 Full Status Check.
22.3.7.3
Program Status (SR4 and FMR06 Bits)
Refer to 22.3.8 Full Status Check.
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M16C/62P Group (M16C/62P, M16C/62PT)
22. Flash Memory Version
Table 22.5
Status Register
Bits in Status Bit in FMR0
Definition
Value after
Status name
Register
Register
“0”
“1”
Reset
−
Reserved
−
−
−
SR0 (D0)
SR1 (D1)
−
Reserved
−
−
−
SR2 (D2)
−
Reserved
−
−
−
SR3 (D3)
−
Reserved
−
−
−
SR4 (D4)
FMR06
Program status Terminated normally Terminated in error
0
SR5 (D5)
FMR07
Erase status
Terminated normally Terminated in error
0
−
Reserved
−
−
−
SR6 (D6)
SR7 (D7)
FMR00
Sequencer status
Busy
Ready
1
• D0 to D7: These data buses are read when the read status register command is executed.
• The FMR07 bit (SR5) and FMR06 bit (SR4) are set to “0” by executing the clear status register
command.
• When the FMR07 bit (SR5) or FMR06 bit (SR4) is set to “1,” the program, block erase, erase all
unlocked block and lock bit program commands are not accepted.
Rev.2.41 Jan 10, 2006
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M16C/62P Group (M16C/62P, M16C/62PT)
22.3.8
22. Flash Memory Version
Full Status Check
If an error occurs when a program or erase operation is completed, the FMR06 to FMR07 bits in the FMR0
register are set to “1”, indicating a specific error. Therefore, execution results can be confirmed by checking
these bits (full status check).
Table 22.6 lists Errors and FMR0 Register State. Figure 22.14 shows a flow chart of the Full Status Check and
Handling Procedure for Each Error.
Table 22.6
Errors and FMR0 Register State
FMR00 Register
(Status Register) State
Error
Error Occurrence Conditions
FMR07 bit
FMR06 bit
(SR5 bit)
(SR4 bit)
Command
• Command is written incorrectly
Sequence error • A value other than “xxD0h” or “xxFFh” is written in the
1
1
second bus cycle of the lock bit program, block erase or
erase all unlocked block command (1)
Erase error
• The block erase command is executed on a locked block
• The block erase or erase all unlocked block command is
1
0
executed on an unlock block and auto erase operation is
not completed as expected (2)
Program error
• The program command is executed on locked blocks
• The program command is executed on unlocked blocks
but program operation is not completed as expected
0
1
• The lock bit program command is executed but program
operation is not completed as expected (2)
NOTES:
1. The flash memory enters read array mode by writing command code “xxFFh” in the second bus
cycle of these commands. The command code written in the first bus cycle becomes invalid.
2. When the FMR02 bit is set to “1” (lock bit disabled), no error occurs even under the conditions
above.
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M16C/62P Group (M16C/62P, M16C/62PT)
22. Flash Memory Version
F u ll s ta tu s c h e c k
FM R06 =1
and
FM R 07=1?
YES
C om m and
s e q u e n c e e rro r
( 1 ) E x e c u te th e c le a r s ta tu s re g is te r c o m m a n d a n d s e t th e S R 4 a n d S R 5
b its to “0 ” (c o m p le te d a s e x p e c te d ) .
( 2 ) R e w r ite c o m m a n d a n d e x e c u te a g a in .
NO
NO
FM R 07=0?
E ra s e e rro r
YES
(1 ) E x e c u te th e c le a r s ta tu s re g is te r c o m m a n d a n d s e t th e S R 5 b it to “0 ”.
(2 ) E x e c u te th e lo c k b it re a d s ta tu s c o m m a n d . S e t th e F M R 0 2 b it to “1 ”
( lo c k b it d is a b le d ) if th e lo c k b it in th e b lo c k w h e re th e e rro r o c c u r re d is
s e t to “0 ” (lo c k e d ).
(3 ) E x e c u te th e b lo c k e ra s e o r e ra s e a ll u n lo c k e d b lo c k c o m m a n d a g a in .
(4 ) E x e c u te (1 ), ( 2 ) a n d ( 3 ) a t le a s t 3 tim e s u n til a n e ra s e e rro r is n o t
g e n e ra te d .
N O T E : If s im ila r e rro r o c c u rs , th a t b lo c k c a n n o t b e u s e d .
If th e lo c k b it is s e t to “ 1 ” (u n lo c k e d ) in ( 2 ) a b o v e , th a t b lo c k
cannot be used.
NO
FM R 06=0?
P ro g ra m e rro r
YES
[W h e n a p r o g ra m o p e r a tio n is e x e c u te d ]
(1 ) E x e c u te th e c le a r s ta tu s re g is te r c o m m a n d a n d s e t th e S R 4 b it to “0 ”
( c o m p le te d a s e x p e c te d ) .
(2 ) E x e c u te th e re a d lo c k b it s ta tu s c o m m a n d a n d s e t th e F M R 0 2 b it to “1 ”
if th e lo c k b it in th e b lo c k w h e re th e e r ro r o c c u rr e d is s e t to 0 .
(3 ) E x e c u te th e p ro g r a m c o m m a n d a g a in .
N O T E : W h e n a s im ila r e rro r o c c u r s , th a t b lo c k c a n n o t b e u s e d .
If th e lo c k b it is s e t to “ 1 ” in (2 ) a b o v e , th a t b lo c k c a n n o t b e u s e d .
[W h e n a lo c k b it p ro g r a m o p e ra tio n is e x e c u te d ]
(1 ) E x e c u te th e c le a r s ta tu s r e g is te r c o m m a n d a n d s e t th e S R 4 b it to “0 ”.
(2 ) S e t th e F M R 0 2 b it in th e F M R 0 re g is te r to “1 ”.
(3 ) E x e c u te th e b lo c k e ra s e c o m m a n d to e ra s e th e b lo c k w h e re th e e rro r
o c c u rre d .
(4 ) E x e c u te th e lo c k b it p ro g r a m c o m m a n d a g a in .
N O T E : If s im ila r e rr o r o c c u rs , th a t b lo c k c a n n o t b e u s e d .
F u ll s ta tu s c h e c k c o m p le te d
N O T E : W h e n e ith e r F M R 0 6 o r F M R 0 7 b it is s e t to “1 ” (te rm in a te d b y e rro r ) , th e p ro g ra m , b lo c k e ra s e , e r a s e a ll u n lo c k e d b lo c k ,
lo c k b it p ro g ra m a n d re a d lo c k b it s ta tu s c o m m a n d s c a n n o t b e a c c e p te d .
E x e c u te th e c le a r s ta tu s re g is te r c o m m a n d b e fo re e a c h c o m m a n d .
Figure 22.14
Full Status Check and Handling Procedure for Each Error
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M16C/62P Group (M16C/62P, M16C/62PT)
22.4
22. Flash Memory Version
Standard Serial I/O Mode
In standard serial I/O mode, the serial programmer supporting the M16C/62P Group (M16C/62P, M16C/62PT) can
be used to rewrite the flash memory user ROM area in the microcomputer mounted on a board.
For more information about the serial programmer, contact your serial programmer manufacturer. Refer to the
user's manual included with your serial programmer for instructions.
Table 22.7 lists Pin Functions (Flash Memory Standard Serial I/O Mode). Figure 22.15 to Figure 22.18 show Pin
Connections in Serial I/O Mode.
22.4.1
ID Code Check Function
The ID code check function determines whether the ID codes sent from the serial programmer matches those
written in the flash memory. (Refer to 22.2 Functions To Prevent Flash Memory from Rewriting.)
Rev.2.41 Jan 10, 2006
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M16C/62P Group (M16C/62P, M16C/62PT)
Table 22.7
22. Flash Memory Version
Pin Functions (Flash Memory Standard Serial I/O Mode)
VCC1, VCC2,
VSS
Power Input
CNVSS
RESET
CNVSS
Reset Input
I
I
XIN
XOUT
Clock Input
Clock Output
I
O
BYTE
AVCC, AVSS
BYTE
Analog Power Supply
Input
Reference Voltage Input
Input Port P0
Input Port P1
Input Port P2
Input Port P3
Input Port P4
Input Port P5
I
I
I
I
I
I
I
I
Power
Description
Supply
−
Apply the Flash Program, Erase Voltage to VCC1 pin
and VCC2 to the VCC2 pin. The VCC apply condition is
that VCC2 ≤ VCC1. Apply 0 V to VSS pin.
VCC1 Connect to VCC1 pin.
VCC1 Reset input pin. While RESET pin is “L” level, input a 20
cycle or longer clock to XIN pin.
VCC1 Connect a ceramic resonator or crystal oscillator
VCC1 between XIN and XOUT pins. To input an externally
generated clock, input it to XIN pin and open XOUT pin.
VCC1 Connect this pin to VCC1 or VSS.
Connect AVSS to VSS and AVCC to VCC1,
respectively.
Enter the reference voltage for A/D from this pin.
VCC2 Input “H” or “L” level signal or open.
VCC2 Input “H” or “L” level signal or open.
VCC2 Input “H” or “L” level signal or open.
VCC2 Input “H” or “L” level signal or open.
VCC2 Input “H” or “L” level signal or open.
VCC2 Input “H” or “L” level signal or open.
CE Input
EPM Input
Input Port P6
BUSY Output
I
I
I
O
VCC2
VCC2
VCC1
VCC1
P6_5/CLK1
SCLK Input
I
VCC1
P6_6/RXD1
P6_7/TXD1
P7_0 to P7_7
P8_0 to P8_3,
P8_6, P8_7
P8_4
P8_5/NMI
P9_0 to P9_7
P10_0 to P10_7
P11_0 to P11_7
P12_0 to P12_7
P13_0 to P13_7
P14_0, P14_1
RXD Input
TXD Input
Input Port P7
Input Port P8
I
O
I
I
VCC1
VCC1
VCC1
VCC1
P8_4 input
NMI Input
Input Port P9
Input Port P10
Input Port P11
Input Port P12
Input Port P13
Input Port P14
I
VCC1 Input “L” level signal. (3)
I
I
I
I
I
I
I
VCC1
VCC1
VCC1
VCC1
VCC2
VCC2
VCC1
Pin
VREF
P0_0 to P0_7
P1_0 to P1_7
P2_0 to P2_7
P3_0 to P3_7
P4_0 to P4_7
P5_1 to P5_4,
P5_6, P5_7
P5_0
P5_5
P6_0 to P6_3
P6_4/RTS1
Name
I/O
Input “H” level signal.
Input “L” level signal.
Input “H” or “L” level signal or open.
Standard serial I/O mode 1: BUSY signal output pin
Standard serial I/O mode 2: Monitors the boot program
operation check signal output pin.
Standard serial I/O mode 1: Serial clock input pin
Standard serial I/O mode 2: Input “L”.
Serial data input pin.
Serial data output pin. (2)
Input “H” or “L” level signal or open.
Input “H” or “L” level signal or open.
Connect this pin to VCC1.
Input “H” or “L” level signal or open.
Input “H” or “L” level signal or open.
Input “H” or “L” level signal or open. (1)
Input “H” or “L” level signal or open. (1)
Input “H” or “L” level signal or open. (1)
Input “H” or “L” level signal or open. (1)
NOTES:
1. Available in only the 128-pin version.
2. When using the standard serial I/O mode, the internal pull-up is enabled for the TXD1 (P6_7) pin
while the RESET pin is “L”.
3. When using the standard serial I/O mode, the P0_0 to P0_7, P1_0 to P1_7 pins may become
indeterminate while the P8_4 pin is “H” and the RESET pin is “L”. If this causes a program, apply “L”
to the P8_4 pin.
Rev.2.41 Jan 10, 2006
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22. Flash Memory Version
VCC2
M16C/62P Group (M16C/62P, M16C/62PT)
102 101 100
99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65
64
63
62
61
60
59
103
104
105
106
107
108
109
110
111
112
113
114
58
57
56
55
54
53
52
51
50
M16C/62P Group
(M16C/62P)
Flash Memory Version
115
116
117
118
CE
EPM
49
48
47
46
45
44
43
42
41
40
39
119
120
121
122
123
124
125
126
127
128
BUSY
SCLK
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38
TXD
RXD
RESET
VSS
Mode setup method
Signal
CNVSS
EPM
RESET
CE
Figure 22.15
VCC1
CNVSS
Connect
oscillator
circuit.
Pin Connections for Serial I/O Mode (1)
Rev.2.41 Jan 10, 2006
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Value
VCC1
VSS
VSS to VCC1
VCC2
Package: PLQP0128KB-A (128P6Q-A)
22. Flash Memory Version
VCC2
M16C/62P Group (M16C/62P, M16C/62PT)
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51
81
50
82
83
84
85
86
49
48
47
46
45
87
88
44
43
89
90
91
92
93
94
M16C/62P Group
(M16C/62P, M16C/62PT)
Flash Memory Version
CE
42
41
40
EPM
39
38
37
36
95
96
97
98
99
100
35
34
BUSY
33
32
31
RXD
SCLK
TXD
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
VSS
Connect
oscillator
circuit.
Mode setup method
RESET
Signal
CNVSS
EPM
RESET
CE
Value
VCC1
VSS
VSS to VCC1
VCC2
Figure 22.16
VCC1
CNVSS
Package: PRQP0100JB-A (100P6S-A)
Pin Connections for Serial I/O Mode (2)
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22. Flash Memory Version
VCC2
M16C/62P Group (M16C/62P, M16C/62PT)
75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51
76
77
50
49
48
47
46
78
79
80
81
82
83
84
85
86
87
88
89
90
91
45
44
CE
43
42
M16C/62P Group
(M16C/62P, M16C/62PT)
Flash Memory Version
92
93
94
95
96
97
98
41
40
39
38
EPM
37
36
35
34
33
32
31
30
29
BUSY
SCLK
RXD
TXD
28
27
26
99
100
1
2 3
4 5
6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25
VSS
Connect
oscillator
circuit.
Figure 22.17
VCC1
CNVSS
RESET
Mode setup method
Signal
Value
CNVSS
VCC1
EPM
VSS
RESET
VSS to VCC1
CE
VCC2
Package: PLQP0100KB-A (100P6Q-A)
Pin Connections for Serial I/O Mode (3)
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M16C/62P Group (M16C/62P, M16C/62PT)
22. Flash Memory Version
60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41
61
40
62
39
63
38
64
37
65
36
66
35
67
34
68
33
69
M16C/62P Group
(M16C/62P, M16C/62PT)
Flash Memory Version
70
71
72
73
31
30
29
28
27
75
26
76
25
77
24
78
23
79
22
2
3
4
5
6
7
8
RXD
TXD
9 10 11 12 13 14 15 16 17 18 19 20
Mode setup method
Signal
Value
CNVSS
VCC1
EPM
VSS
RESET
VSS to VCC1
CE
VCC2
VSS
RESET
CNVSS
Connect
oscillator
circuit.
VCC1
Package: PRQP0080JA-A (80P6S-A)
Pin Connections for Serial I/O Mode (4)
Rev.2.41 Jan 10, 2006
REJ09B0185-0241
BUSY
SCLK
21
1
Figure 22.18
EPM
32
74
80
CE
Page 300 of 390
M16C/62P Group (M16C/62P, M16C/62PT)
22.4.2
22. Flash Memory Version
Example of Circuit Application in the Standard Serial I/O Mode
Figure 22.19 and Figure 22.20 show example of Circuit Application in Standard Serial I/O Mode 1 and Mode 2,
respectively. Refer to the user's manual of your serial programmer to handle pins controlled by the serial
programmer.
VCC1
Microcomputer
SCLK input
VCC2
P6_5/CLK1
P5_0(CE)
VCC1
TXD output
P6_7/TXD1
P5_5(EPM)
VCC1
BUSY output
P6_4/RTS1
RXD input
P6_6/RXD1
CNVSS
VCC1
VCC1
Reset input
RESET
User reset
signal
P8_5/NMI
NOTES:
1. Control pins and external circuitry will vary according to programmer.
For more information, see the programmer manual.
2. In this example, modes are switched between single-chip mode and standard
serial input/output mode by controlling the CNVSS input with a switch.
3. If in standard serial input/output mode 1 there is a possibility that the user reset
signal will go low during serial input/output mode, break the connection between
the user reset signal and RESET pin by using, for example, a jumper switch.
Figure 22.19
Circuit Application in Standard Serial I/O Mode 1
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M16C/62P Group (M16C/62P, M16C/62PT)
22. Flash Memory Version
Microcomputer
TXD output
P6_5/CLK1
P5_0(CE)
P6_7/TXD1
P5_5(EPM)
VCC2
VCC1
Monitor output
P6_4/RTS1
RXD intput
P6_6/RXD1
CNVSS
VCC1
VCC1
Reset input
RESET
User reset
signal
P8_5/NMI
NOTES:
1. In this example, modes are switched between single-chip mode and standard
serial input/output mode by controlling the CNVSS input with a switch.
Figure 22.20
Circuit Application in Standard Serial I/o Mode 2
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M16C/62P Group (M16C/62P, M16C/62PT)
22.5
22. Flash Memory Version
Parallel I/O Mode
In parallel I/O mode, the user ROM area and the boot ROM area can be rewritten by a parallel programmer
supporting the M16C/62P Group (M16C/62P, M16C/62PT). Contact your parallel programmer manufacturer for
more information on the parallel programmer. Refer to the user's manual included with your parallel programmer
for instructions.
22.5.1
User ROM and Boot ROM Areas
An erase block operation in the boot ROM area is applied to only one 4 Kbyte block. The rewrite control
program in standard serial I/O mode is written in the boot ROM area before shipment. Do not rewrite the boot
ROM area if using the serial programmer.
In parallel I/O mode, the boot ROM area is located in addresses 0FF000h to 0FFFFFh. Rewrite this address
range only if rewriting the boot ROM area. (Do not access addresses other than addresses 0FF000h to
0FFFFFh.)
22.5.2
ROM Code Protect Function
The ROM code protect function prevents the flash memory from being read and rewritten in parallel I/O mode.
(Refer to 22.2 Functions To Prevent Flash Memory from Rewriting.)
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M16C/62P Group (M16C/62P, M16C/62PT)
23. Electrical Characteristics
23. Electrical Characteristics
23.1
Electrical Characteristics (M16C/62P)
Table 23.1
Symbol
VCC1, VCC2
VCC2
AVCC
VI
VO
Pd
Topr
Tstg
Absolute Maximum Ratings
Parameter
Supply Voltage
Supply Voltage
Analog Supply Voltage
Input Voltage
RESET, CNVSS, BYTE,
P6_0 to P6_7, P7_2 to P7_7, P8_0 to P8_7,
P9_0 to P9_7, P10_0 to P10_7,
P11_0 to P11_7, P14_0, P14_1,
VREF, XIN
P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7,
P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7,
P12_0 to P12_7, P13_0 to P13_7
P7_0, P7_1
Output Voltage P6_0 to P6_7, P7_2 to P7_7, P8_0 to P8_4,
P8_6, P8_7, P9_0 to P9_7, P10_0 to P10_7,
P11_0 to P11_7, P14_0, P14_1,
XOUT
P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7,
P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7,
P12_0 to P12_7, P13_0 to P13_7
P7_0, P7_1
Power Dissipation
Operating
When the Microcomputer is Operating
Ambient
Temperature
Flash Program Erase
Storage Temperature
Condition
VCC1=AVCC
VCC2
VCC1=AVCC
−40°C<Topr≤85°C
Rated Value
−0.3 to 6.5
−0.3 to VCC1+0.1
−0.3 to 6.5
−0.3 to VCC1+0.3 (1)
Unit
V
V
V
V
−0.3 to VCC2+0.3 (1)
V
−0.3 to 6.5
−0.3 to VCC1+0.3 (1)
V
V
−0.3 to VCC2+0.3 (1)
V
−0.3 to 6.5
300
−20 to 85 / −40 to 85
V
mW
°C
0 to 60
−65 to 150
°C
NOTES:
1. There is no external connections for port P1_0 to P1_7, P4_4 to P4_7, P7_2 to P7_5 and P9_1 in
80-pin version.
Rev.2.41 Jan 10, 2006
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M16C/62P Group (M16C/62P, M16C/62PT)
Table 23.2
Recommended Operating Conditions (1) (1)
Symbol
VCC1, VCC2
AVCC
VSS
AVSS
VIH
VIL
23. Electrical Characteristics
Parameter
Supply Voltage (VCC1 ≥ VCC2)
Analog Supply Voltage
Supply Voltage
Analog Supply Voltage
P3_1 to P3_7, P4_0 to P4_7, P5_0 to P5_7,
HIGH Input
P12_0 to P12_7, P13_0 to P13_7
Voltage
LOW Input
Voltage
Min.
2.7
Standard
Typ.
5.0
VCC1
0
0
Max.
5.5
Unit
0.8VCC2
VCC2
V
V
V
V
V
P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7, P3_0
(during single-chip mode)
0.8VCC2
VCC2
V
P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7, P3_0
(data input during memory expansion and microprocessor mode)
0.5VCC2
VCC2
V
P6_0 to P6_7, P7_2 to P7_7, P8_0 to P8_7, P9_0 to P9_7,
P10_0 to P10_7, P11_0 to P11_7, P14_0, P14_1,
XIN, RESET, CNVSS, BYTE
0.8VCC1
VCC1
V
P7_0, P7_1
0.8VCC1
0
6.5
0.2VCC2
V
V
P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7, P3_0
(during single-chip mode)
0
0.2VCC2
V
P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7, P3_0
(data input during memory expansion and microprocessor mode)
0
0.16VCC2
V
P6_0 to P6_7, P7_0 to P7_7, P8_0 to P8_7, P9_0 to P9_7,
P10_0 to P10_7, P11_0 to P11_7, P14_0, P14_1,
XIN, RESET, CNVSS, BYTE
0
0.2VCC
V
P3_1 to P3_7, P4_0 to P4_7, P5_0 to P5_7,
P12_0 to P12_7, P13_0 to P13_7
IOH(peak)
HIGH Peak
Output Current
P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7, P3_0 to P3_7,
P4_0 to P4_7, P5_0 to P5_7, P6_0 to P6_7, P7_2 to P7_7,
P8_0 to P8_4, P8_6, P8_7, P9_0 to P9_7, P10_0 to P10_7,
P11_0 to P11_7, P12_0 to P12_7, P13_0 to P13_7, P14_0, P14_1
−10.0
mA
IOH(avg)
HIGH Average
Output Current
P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7, P3_0 to P3_7,
P4_0 to P4_7, P5_0 to P5_7, P6_0 to P6_7, P7_2 to P7_7,
P8_0 to P8_4, P8_6, P8_7, P9_0 to P9_7, P10_0 to P10_7,
P11_0 to P11_7, P12_0 to P12_7, P13_0 to P13_7, P14_0, P14_1
−5.0
mA
IOL(peak)
LOW Peak
Output Current
P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7, P3_0 to P3_7,
P4_0 to P4_7, P5_0 to P5_7, P6_0 to P6_7, P7_0 to P7_7,
P8_0 to P8_4, P8_6, P8_7, P9_0 to P9_7, P10_0 to P10_7,
P11_0 to P11_7, P12_0 to P12_7, P13_0 to P13_7, P14_0, P14_1
10.0
mA
IOL(avg)
LOW Average
Output Current
P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7, P3_0 to P3_7,
P4_0 to P4_7, P5_0 to P5_7, P6_0 to P6_7, P7_0 to P7_7,
P8_0 to P8_4, P8_6, P8_7, P9_0 to P9_7, P10_0 to P10_7,
P11_0 to P11_7, P12_0 to P12_7, P13_0 to P13_7, P14_0, P14_1
5.0
mA
NOTES:
1. Referenced to VCC1 = VCC2 = 2.7 to 5.5V at Topr = −20 to 85°C / −40 to 85°C unless otherwise specified.
2. The Average Output Current is the mean value within 100ms.
3. The total IOL(peak) for ports P0, P1, P2, P8_6, P8_7, P9, P10, P11, P14_0, and P14_1 must be 80mA max. The total IOL(peak)
for ports P3, P4, P5, P6, P7, P8_0 to P8_4, P12, and P13 must be 80mA max. The total IOH(peak) for ports P0, P1, and P2
must be −40mA max. The total IOH(peak) for ports P3, P4, P5, P12, and P13 must be −40mA max. The total IOH(peak) for ports
P6, P7, and P8_0 to P8_4 must be −40mA max. The total IOH(peak) for ports P8_6, P8_7, P9, P10, P14_0, and P14_1 must be
−40mA max. Set Average Output Current to 1/2 of peak. The total IOH(peak) for ports P8_6, P8_7, P9 , P10, P11, P14_0, and
P14_1 must be −40mA max.
As for 80-pin version, the total IOL(peak) for all ports and IOH(peak) must be 80mA. max. due to one VCC and one VSS.
4. There is no external connections for port P1_0 to P1_7, P4_4 to P4_7, P7_2 to P7_5 and P9_1 in 80-pin version.
Rev.2.41 Jan 10, 2006
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M16C/62P Group (M16C/62P, M16C/62PT)
23. Electrical Characteristics
Recommended Operating Conditions (2) (1)
Table 23.3
Symbol
Parameter
Main Clock Input Oscillation Frequency (2)
f(XIN)
Min.
0
0
VCC1=3.0V to 5.5V
VCC1=2.7V to 3.0V
f(XCIN)
f(Ring)
f(PLL)
Sub-Clock Oscillation Frequency
On-chip Oscillation Frequency
PLL Clock Oscillation Frequency (2)
0.5
10
10
VCC1=3.0V to 5.5V
VCC1=2.7V to 3.0V
f(BCLK)
tSU(PLL)
CPU Operation Clock
PLL Frequency Synthesizer Stabilization
Wait Time
Standard
Typ.
32.768
1
0
VCC1=5.5V
VCC1=3.0V
Max.
16
20×VCC1
−44
50
2
24
46.67×VCC1
−116
24
20
50
NOTES:
1. Referenced to VCC1 = VCC2 = 2.7 to 5.5V at Topr = −20 to 85°C / −40 to 85°C unless otherwise specified.
2. Relationship between main clock oscillation frequency, and supply voltage.
PLL clock oscillation frequency
f(PLL) operating maximum frequency [MHz]
f(XIN) operating maximum frequency [MHz]
Main clock input oscillation frequency
20 x VCC1-44MHz
16.0
10.0
0.0
2.7
3.0
5.5
VCC1[V] (main clock: no division)
Rev.2.41 Jan 10, 2006
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46.67 x VCC1-116MHz
24.0
10.0
0.0
2.7
3.0
VCC1[V] (PLL clock oscillation)
5.5
Unit
MHz
MHz
kHz
MHz
MHz
MHz
MHz
ms
ms
M16C/62P Group (M16C/62P, M16C/62PT)
Table 23.4
A/D Conversion Characteristics (1)
Symbol
−
INL
−
−
DNL
−
−
RLADDER
tCONV
tCONV
tSAMP
VREF
VIA
23. Electrical Characteristics
Parameter
Resolution
Integral Non-Linearity
Error
Absolute Accuracy
10bit
8bit
10bit
8bit
Tolerance Level Impedance
Differential Non-Linearity Error
Offset Error
Gain Error
Ladder Resistance
10-bit Conversion Time, Sample & Hold
Available
8-bit Conversion Time, Sample & Hold
Available
Sampling Time
Reference Voltage
Analog Input Voltage
Measuring Condition
Min.
VREF=VCC1
VREF= AN0 to AN7 input,
VCC1= AN0_0 to AN0_7 input,
AN2_0 to AN2_7 input,
5V
ANEX0, ANEX1 input
External operation amp
connection mode
VREF= AN0 to AN7 input,
VCC1= AN0_0 to AN0_7 input,
AN2_0 to AN2_7 input,
3.3V
ANEX0, ANEX1 input
External operation amp
connection mode
VREF=VCC1=5V, 3.3V
VREF= AN0 to AN7 input,
VCC1= AN0_0 to AN0_7 input,
5V
AN2_0 to AN2_7 input,
ANEX0, ANEX1 input
External operation amp
connection mode
VREF= AN0 to AN7 input,
AN0_0 to AN0_7 input,
VCC1
=3.3V AN2_0 to AN2_7 input,
ANEX0, ANEX1 input
External operation amp
connection mode
VREF=VCC1=5V, 3.3V
Standard
Typ.
Max.
10
±3
10
2.75
VREF=VCC1=5V, φAD=12MHz
2.33
0.25
2.0
0
Bits
LSB
±7
LSB
±5
LSB
±7
LSB
±2
±3
LSB
LSB
±7
LSB
±5
LSB
±7
LSB
±2
LSB
kΩ
LSB
LSB
LSB
kΩ
µs
3
VREF=VCC1
VREF=VCC1=5V, φAD=12MHz
Unit
±1
±3
±3
40
µs
VCC1
VREF
µs
V
V
NOTES:
1. Referenced to VCC1=AVCC=VREF=3.3 to 5.5V, VSS=AVSS=0V at Topr = −20 to 85°C / −40 to 85°C unless otherwise specified.
2. If VCC1 > VCC2, do not use AN0_0 to AN0_7 and AN2_0 to AN2_7 as analog input pins.
3. φAD frequency must be 12 MHz or less. And divide the fAD if VCC1 is less than 4.0V, and φAD frequency into 10 MHz or less.
4. When sample & hold is disabled, φAD frequency must be 250 kHz or more, in addition to the limitation in Note 3.
When sample & hold is enabled, φAD frequency must be 1MHz or more, in addition to the limitation in Note 3.
Rev.2.41 Jan 10, 2006
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M16C/62P Group (M16C/62P, M16C/62PT)
Table 23.5
D/A Conversion Characteristics (1)
Symbol
−
−
tSU
RO
IVREF
23. Electrical Characteristics
Parameter
Resolution
Absolute Accuracy
Setup Time
Output Resistance
Reference Power Supply Input Current
Measuring Condition
Min.
4
(NOTE 2)
Standard
Typ.
10
Max.
8
1.0
3
20
1.5
Unit
Bits
%
µs
kΩ
mA
NOTES:
1. Referenced to VCC1=VREF=3.3 to 5.5V, VSS=AVSS=0V at Topr = −20 to 85°C / −40 to 85°C unless otherwise specified.
2. This applies when using one D/A converter, with the D/A register for the unused D/A converter set to “00h”. The resistor
ladder of the A/D converter is not included. Also, when D/A register contents are not “00h”, the IVREF will flow even if Vref id
disconnected by the A/D control register.
Rev.2.41 Jan 10, 2006
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M16C/62P Group (M16C/62P, M16C/62PT)
Table 23.6
Flash Memory Version Electrical Characteristics (1) for 100 cycle products (D3, D5, U3,
U5)
Symbol
−
−
−
−
−
−
−
−
tPS
−
23. Electrical Characteristics
Parameter
Program and Erase Endurance (3)
Word Program Time (VCC1=5.0V)
Lock Bit Program Time
Block Erase Time
(VCC1=5.0V)
Min.
100
200
200
4
4
4
4
4×n
15
10
Parameter
Program and Erase Endurance (3, 8, 9)
Word Program Time (VCC1=5.0V)
Lock Bit Program Time
Block Erase Time
(VCC1=5.0V)
Flash Memory Circuit Stabilization Wait Time
Data Hold Time (5)
tPS
−
Max.
Unit
cycle
µs
µs
s
s
s
s
s
µs
year
Flash Memory Version Electrical Characteristics (6) for 10,000 cycle products (D7, D9,
U7, U9) (Block A and Block 1 (7))
Symbol
−
−
−
−
25
25
0.3
0.3
0.5
0.8
4-Kbyte block
8-Kbyte block
32-Kbyte block
64-Kbyte block
Erase All Unlocked Blocks Time (2)
Flash Memory Circuit Stabilization Wait Time
Data Hold Time (5)
Table 23.7
Standard
Typ.
Min.
10,000 (4)
Standard
Typ.
Max.
cycle
µs
µs
s
25
25
0.3
4-Kbyte block
15
10
Unit
µs
year
NOTES:
1. Referenced to VCC1=4.5 to 5.5V, 3.0 to 3.6V at Topr = 0 to 60 °C (D3, D5, U3, U5) unless otherwise specified.
2. n denotes the number of block erases.
3. Program and Erase Endurance refers to the number of times a block erase can be performed.
If the program and erase endurance is n (n=100, 1,000, or 10,000), each block can be erased n times.
For example, if a 4 Kbytes block A is erased after writing 1 word data 2,048 times, each to a different address, this counts as
one program and erase endurance. Data cannot be written to the same address more than once without erasing the block.
(Rewrite prohibited)
4. Maximum number of E/W cycles for which operation is guaranteed.
5. Topr = -40 to 85 °C (D3, D7, U3, U7) / -20 to 85 °C (D5, D9, U5, U9).
6. Referenced to VCC1 = 4.5 to 5.5V, 3.0 to 3.6V at Topr = -40 to 85 °C (D7, U7) / -20 to 85 °C (D9, U9) unless otherwise specified.
7. Table 23.7 applies for block A or block 1 program and erase endurance > 1,000. Otherwise, use Table 23.6.
8. To reduce the number of program and erase endurance when working with systems requiring numerous rewrites, write to
unused word addresses within the block instead of rewrite. Erase block only after all possible addresses are used. For
example, an 8-word program can be written 256 times maximum before erase becomes necessary.
Maintaining an equal number of erasure between block A and block 1 will also improve efficiency. It is important to track the
total number of times erasure is used.
9. Should erase error occur during block erase, attempt to execute clear status register command, then block erase command
at least three times until erase error disappears.
10. Set the PM17 bit in the PM1 register to “1” (wait state) when executing more than 100 times rewrites (D7, D9, U7 and U9).
11. Customers desiring E/W failure rate information should contact their Renesas technical support representative.
Table 23.8
Flash Memory Version Program / Erase Voltage and Read Operation Voltage
Characteristics (at Topr = 0 to 60 °C(D3, D5, U3, U5), Topr = -40 to 85 °C(D7, U7) / Topr =
-20 to 85 °C(D9, U9))
Flash Program, Erase Voltage
VCC1 = 3.3 V ± 0.3 V or 5.0 V ± 0.5 V
Rev.2.41 Jan 10, 2006
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Flash Read Operation Voltage
VCC1=2.7 to 5.5 V
M16C/62P Group (M16C/62P, M16C/62PT)
Table 23.9
Low Voltage Detection Circuit Electrical Characteristics
Symbol
Vdet4
Vdet3
Vdet4-Vdet3
Vdet3s
Vdet3r
23. Electrical Characteristics
Parameter
Low Voltage Detection Voltage (1)
Reset Level Detection Voltage (1, 2)
Electric potential difference of Low Voltage
Detection and Reset Level Detection
Low Voltage Reset Retention Voltage
Low Voltage Reset Release Voltage (3)
Measuring Condition
VCC1=0.8V to 5.5V
Min.
3.3
2.2
0.3
2.2
Standard
Typ.
3.8
2.8
Max.
4.4
3.6
2.9
0.8
4.0
Unit
V
V
V
V
V
NOTES:
1. Vdet4 > Vdet3.
2. Where reset level detection voltage is less than 2.7 V, if the supply power voltage is greater than the reset level detection
voltage, the microcomputer operates with f(BCLK) ≤ 10MHz.
3. Vdet3r > Vdet3 is not guaranteed.
4. The voltage detection circuit is designed to use when VCC1 is set to 5V.
Table 23.10
Power Supply Circuit Timing Characteristics
Symbol
td(P-R)
td(R-S)
td(W-S)
td(S-R)
td(E-A)
Parameter
Time for Internal Power Supply Stabilization
During Powering-On
STOP Release Time
Low Power Dissipation Mode Wait Mode
Release Time
Brown-out Detection Reset (Hardware Reset 2)
Release Wait Time
Low Voltage Detection Circuit Operation Start
Time
NOTES:
1. When VCC1 = 5V.
Rev.2.41 Jan 10, 2006
REJ09B0185-0241
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Measuring Condition
Min.
Standard
Typ.
VCC1=2.7V to 5.5V
VCC1=Vdet3r to 5.5V
VCC1=2.7V to 5.5V
6 (1)
Max.
2
Unit
ms
150
150
µs
µs
20
ms
20
µs
M16C/62P Group (M16C/62P, M16C/62PT)
23. Electrical Characteristics
Recommended
operation voltage
td(P-R)
Time for Internal Power
Supply Stabilization During
Powering-On
VCC1
td(P-R)
CPU clock
Interrupt for
(a) Stop mode release
or
(b) Wait mode release
td(R-S)
STOP Release Time
td(W-S)
Low Power Dissipation Mode
Wait Mode Release Time
CPU clock
(a)
td(R-S)
(b)
td(W-S)
td(S-R)
Low Voltage Detection
Reset (Hardware Reset 2)
Release Wait Time
Vdet3r
VCC1
td(S-R)
CPU clock
td(E-A)
VC26, VC27
Low Voltage Detection Circuit
Operation Start Time
Low Voltage
Detection Circuit
Stop
Operate
td(E-A)
Figure 23.1
Power Supply Circuit Timing Diagram
Rev.2.41 Jan 10, 2006
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M16C/62P Group (M16C/62P, M16C/62PT)
23. Electrical Characteristics
VCC1=VCC2=5V
Table 23.11
Electrical Characteristics (1)
Symbol
VOH
VOH
(1)
Parameter
HIGH
Output
Voltage (3)
HIGH
Output
Voltage (3)
Measuring Condition
P6_0 to P6_7, P7_2 to P7_7, P8_0 to P8_4,
P8_6, P8_7, P9_0 to P9_7, P10_0 to P10_7,
P11_0 to P11_7, P14_0, P14_1
IOH=−5mA
P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7,
P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7,
P12_0 to P12_7, P13_0 to P13_7
IOH=−5mA (2)
P6_0 to P6_7, P7_2 to P7_7, P8_0 to P8_4,
P8_6, P8_7, P9_0 to P9_7, P10_0 to P10_7,
P11_0 to P11_7, P14_0, P14_1
P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7,
P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7,
P12_0 to P12_7, P13_0 to P13_7
VOH
HIGH Output Voltage
XOUT
HIGH Output Voltage
VOL
VOL
VOL
LOW
Output
Voltage (3)
LOW
Output
Voltage (3)
XCOUT
HIGHPOWER
IOH=−1mA
LOWPOWER
IOH=−0.5mA
HIGHPOWER
With no load applied
LOWPOWER
With no load applied
IOL=5mA
P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7,
P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7,
P12_0 to P12_7, P13_0 to P13_7
IOL=5mA (2)
P6_0 to P6_7, P7_0 to P7_7, P8_0 to P8_4,
P8_6, P8_7, P9_0 to P9_7, P10_0 to P10_7,
P11_0 to P11_7, P14_0, P14_1
IOL=200µA
P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7,
P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7,
P12_0 to P12_7, P13_0 to P13_7
IOL=200µA (2)
LOW Output Voltage
Hysteresis
IOH=−200µA (2)
P6_0 to P6_7, P7_0 to P7_7, P8_0 to P8_4,
P8_6, P8_7, P9_0 to P9_7, P10_0 to P10_7,
P11_0 to P11_7, P14_0, P14_1
XOUT
LOW Output Voltage
VT+-VT-
OH=−200µA
XCOUT
HIGHPOWER
IOL=1mA
LOWPOWER
IOL=0.5mA
HIGHPOWER
With no load applied
LOWPOWER
With no load applied
HOLD, RDY, TA0IN to TA4IN, TB0IN to TB5IN,
INT0 to INT5, NMI, ADTRG, CTS0 to CTS2, CLK0 to CLK4,
TA0OUT to TA4OUT, KI0 to KI3, RXD0 to RXD2,
SCL0 to SCL2, SDA0 to SDA2, SIN3, SIN4
RESET
IIH
VI=5V
P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7, P3_0 to P3_7,
P4_0 to P4_7, P5_0 to P5_7, P6_0 to P6_7, P7_0 to P7_7,
P8_0 to P8_7, P9_0 to P9_7, P10_0 to P10_7,
P11_0 to P11_7,P12_0 to P12_7, P13_0 to P13_7,
P14_0, P14_1, XIN, RESET, CNVSS, BYTE
VI=0V
P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7, P3_0 to P3_7,
P4_0 to P4_7, P5_0 to P5_7, P6_0 to P6_7, P7_2 to P7_7,
P8_0 to P8_4, P8_6, P8_7, P9_0 to P9_7, P10_0 to P10_7,
P11_0 to P11_7,P12_0 to P12_7, P13_0 to P13_7,
P14_0, P14_1
VI=0V
(3)
RfXIN
RfXCIN
VRAM
VCC1
VCC2−2.0
VCC2
VCC1−0.3
VCC1
V
V
VCC2−0.3
VCC2
VCC1−2.0
VCC1−2.0
VCC1
VCC1
2.5
1.6
V
V
V
2.0
2.0
0
0
V
1.0
V
0.2
2.5
V
5.0
µA
−5.0
µA
170
kΩ
30
50
1.5
15
Feedback Resistance XCIN
At stop mode
V
0.2
Feedback Resistance XIN
RAM Retention Voltage
V
0.45
P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7, P3_0 to P3_7,
P4_0 to P4_7, P5_0 to P5_7, P6_0 to P6_7, P7_0 to P7_7,
P8_0 to P8_7, P9_0 to P9_7, P10_0 to P10_7,
P11_0 to P11_7, P12_0 to P12_7, P13_0 to P13_7,
P14_0, P14_1, XIN, RESET, CNVSS, BYTE
Resistance
VCC1−2.0
Unit
0.45
HIGH Input
Current (3)
RPULLUP Pull-Up
Max.
2.0
Hysteresis
LOW Input
Current (3)
Standard
Typ.
2.0
VT+-VT-
IIL
Min.
2.0
MΩ
MΩ
V
NOTES:
1. Referenced to VCC1=VCC2=4.2 to 5.5V, VSS = 0V at Topr = −20 to 85°C / −40 to 85°C, f(BCLK)=24MHz unless otherwise
specified.
2. Where the product is used at VCC1 = 5 V and VCC2 = 3 V, refer to the 3 V version value for the pin specified value on VCC2 port
side.
3. There is no external connections for port P1_0 to P1_7, P4_4 to P4_7, P7_2 to P7_5 and P9_1 in 80-pin version.
Rev.2.41 Jan 10, 2006
REJ09B0185-0241
Page 312 of 390
M16C/62P Group (M16C/62P, M16C/62PT)
Table 23.12
Electrical Characteristics (2) (1)
Symbol
ICC
23. Electrical Characteristics
Parameter
Measuring Condition
In single-chip
Power Supply Current
(VCC1=VCC2=4.0V to 5.5V) mode, the output
pins are open and
other pins are VSS
Mask ROM
f(BCLK)=24MHz
No division, PLL operation
No division,
On-chip oscillation
Flash
Memory
Flash Memory
Program
Flash Memory
Erase
Mask ROM
Flash Memory
Idet4
Idet3
(4)
Low Voltage Detection Dissipation Current
Reset Area Detection Dissipation Current (4)
Standard
Typ. Max.
14
20
1
Page 313 of 390
mA
mA
18
No division,
On-chip oscillation
1.8
mA
f(BCLK)=10MHz,
VCC1=5.0V
15
mA
f(BCLK)=10MHz,
VCC1=5.0V
25
mA
f(XCIN)=32kHz
Low power dissipation
mode, ROM (3)
25
µA
f(BCLK)=32kHz
Low power dissipation
mode, RAM (3)
25
µA
420
µA
On-chip oscillation,
Wait mode
50
µA
f(BCLK)=32kHz
Wait mode (2),
Oscillation capability High
7.5
µA
f(BCLK)=32kHz
Wait mode (2),
Oscillation capability Low
2.0
µA
Stop mode
Topr =25°C
0.8
3.0
µA
0.7
1.2
4
8
µA
µA
27
NOTES:
1. Referenced to VCC1=VCC2=4.2 to 5.5V, VSS = 0V at Topr = −20 to 85°C / −40 to 85°C, f(BCLK)=24MHz unless otherwise
specified.
2. With one timer operated using fC32.
3. This indicates the memory in which the program to be executed exists.
4. Idet is dissipation current when the following bit is set to “1” (detection circuit enabled).
Idet4: VC27 bit in the VCR2 register
Idet3: VC26 bit in the VCR2 register
Rev.2.41 Jan 10, 2006
REJ09B0185-0241
Unit
f(BCLK)=24MHz,
No division, PLL operation
f(BCLK)=32kHz
Low power dissipation
mode, Flash Memory (3)
Mask ROM
Flash Memory
Min.
mA
M16C/62P Group (M16C/62P, M16C/62PT)
23. Electrical Characteristics
VCC1=VCC2=5V
Timing Requirements
(VCC1 = VCC2 = 5V, VSS = 0V, at Topr = −20 to 85°C / −40 to 85°C unless otherwise specified)
Table 23.13
External Clock Input (XIN input) (1)
Symbol
Parameter
External Clock Input Cycle Time
External Clock Input HIGH Pulse Width
External Clock Input LOW Pulse Width
External Clock Rise Time
External Clock Fall Time
tc
tw(H)
tw(L)
tr
tf
Standard
Min.
62.5
25
25
Max.
15
15
Unit
ns
ns
ns
ns
ns
NOTES:
1. The condition is VCC1=VCC2=3.0 to 5.0V.
Table 23.14
Memory Expansion Mode and Microprocessor Mode
Symbol
tac1(RD-DB)
tac2(RD-DB)
tac3(RD-DB)
tsu(DB-RD)
tsu(RDY-BCLK)
tsu(HOLD-BCLK)
th(RD-DB)
th(BCLK-RDY)
th(BCLK-HOLD)
Parameter
Data Input Access Time (for setting with no wait)
Data Input Access Time (for setting with wait)
Data Input Access Time (when accessing multiplex bus area)
Data Input Setup Time
RDY Input Setup Time
HOLD Input Setup Time
Data Input Hold Time
RDY Input Hold Time
HOLD Input Hold Time
Standard
Min.
Max.
(NOTE 1)
(NOTE 2)
(NOTE 3)
40
30
40
0
0
0
NOTES:
1. Calculated according to the BCLK frequency as follows:
9
0.5x10
------------------------ – 45 [ ns ]
f ( BCLK )
2. Calculated according to the BCLK frequency as follows:
9
( n – 0.5 ) x 10
------------------------------------- – 45 [ ns ]
f ( BCLK )
n is ”2” for 1-wait setting, “3” for 2-wait setting and “4” for 3-wait setting.
3. Calculated according to the BCLK frequency as follows:
9
( n – 0.5 ) x 10
------------------------------------- – 45 [ ns ]
f ( BCLK )
Rev.2.41 Jan 10, 2006
REJ09B0185-0241
n is “2” for 2-wait setting, “3” for 3-wait setting.
Page 314 of 390
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
M16C/62P Group (M16C/62P, M16C/62PT)
23. Electrical Characteristics
VCC1=VCC2=5V
Timing Requirements
(VCC1 = VCC2 = 5V, VSS = 0V, at Topr = −20 to 85°C / −40 to 85°C unless otherwise specified)
Table 23.15
Timer A Input (Counter Input in Event Counter Mode)
Symbol
tc(TA)
tw(TAH)
tw(TAL)
Table 23.16
Parameter
TAiIN Input Cycle Time
TAiIN Input HIGH Pulse Width
TAiIN Input LOW Pulse Width
Table 23.17
Parameter
TAiIN Input Cycle Time
TAiIN Input HIGH Pulse Width
TAiIN Input LOW Pulse Width
Table 23.18
Parameter
TAiIN Input Cycle Time
TAiIN Input HIGH Pulse Width
TAiIN Input LOW Pulse Width
Table 23.19
Parameter
TAiIN Input HIGH Pulse Width
TAiIN Input LOW Pulse Width
Standard
Min.
400
200
200
Unit
ns
ns
ns
Standard
Min.
200
100
100
Max.
Unit
ns
ns
ns
Standard
Min.
100
100
Parameter
Max.
Unit
ns
ns
Standard
tc(UP)
TAiOUT Input Cycle Time
Min.
2000
tw(UPH)
tw(UPL)
tsu(UP-TIN)
th(TIN-UP)
TAiOUT Input HIGH Pulse Width
TAiOUT Input LOW Pulse Width
TAiOUT Input Setup Time
TAiOUT Input Hold Time
1000
1000
400
400
Max.
Unit
ns
ns
ns
ns
ns
Timer A Input (Two-phase Pulse Input in Event Counter Mode)
Symbol
tc(TA)
tsu(TAIN-TAOUT)
tsu(TAOUT-TAIN)
Max.
Timer A Input (Counter Increment/Decrement Input in Event Counter Mode)
Symbol
Table 23.20
ns
ns
ns
Timer A Input (External Trigger Input in Pulse Width Modulation Mode)
Symbol
tw(TAH)
tw(TAL)
Unit
Timer A Input (External Trigger Input in One-shot Timer Mode)
Symbol
tc(TA)
tw(TAH)
tw(TAL)
Max.
Timer A Input (Gating Input in Timer Mode)
Symbol
tc(TA)
tw(TAH)
tw(TAL)
Standard
Min.
100
40
40
Parameter
TAiIN Input Cycle Time
TAiOUT Input Setup Time
TAiIN Input Setup Time
Rev.2.41 Jan 10, 2006
REJ09B0185-0241
Page 315 of 390
Standard
Min.
800
200
200
Max.
Unit
ns
ns
ns
M16C/62P Group (M16C/62P, M16C/62PT)
23. Electrical Characteristics
VCC1=VCC2=5V
Timing Requirements
(VCC1 = VCC2 = 5V, VSS = 0V, at Topr = −20 to 85°C / −40 to 85°C unless otherwise specified)
Table 23.21
Timer B Input (Counter Input in Event Counter Mode)
Symbol
tc(TB)
tw(TBH)
tw(TBL)
tc(TB)
tw(TBH)
tw(TBL)
Table 23.22
Parameter
TBiIN Input Cycle Time (counted on one edge)
TBiIN Input HIGH Pulse Width (counted on one edge)
TBiIN Input LOW Pulse Width (counted on one edge)
TBiIN Input Cycle Time (counted on both edges)
TBiIN Input HIGH Pulse Width (counted on both edges)
TBiIN Input LOW Pulse Width (counted on both edges)
Table 23.23
Parameter
TBiIN Input Cycle Time
TBiIN Input HIGH Pulse Width
TBiIN Input LOW Pulse Width
Table 23.24
Parameter
TBiIN Input Cycle Time
TBiIN Input HIGH Pulse Width
TBiIN Input LOW Pulse Width
Standard
Min.
400
200
200
Parameter
tw(ADL)
ADTRG input LOW Pulse Width
125
Unit
ns
ns
ns
Max.
Unit
ns
ns
Serial Interface
Symbol
Parameter
CLKi Input Cycle Time
CLKi Input HIGH Pulse Width
CLKi Input LOW Pulse Width
TXDi Output Delay Time
TXDi Hold Time
RXDi Input Setup Time
RXDi Input Hold Time
Standard
Min.
200
100
100
Max.
80
0
70
90
Unit
ns
ns
ns
ns
ns
ns
ns
External Interrupt INTi Input
Symbol
tw(INL)
Max.
Standard
ADTRG Input Cycle Time
tw(INH)
Unit
ns
ns
ns
Standard
tc(AD)
Table 23.26
Max.
Min.
400
200
200
Min.
1000
tc(CK)
tw(CKH)
tw(CKL)
td(C-Q)
th(C-Q)
tsu(D-C)
th(C-D)
ns
ns
ns
ns
ns
ns
A/D Trigger Input
Symbol
Table 23.25
Unit
Timer B Input (Pulse Width Measurement Mode)
Symbol
tc(TB)
tw(TBH)
tw(TBL)
Max.
Timer B Input (Pulse Period Measurement Mode)
Symbol
tc(TB)
tw(TBH)
tw(TBL)
Standard
Min.
100
40
40
200
80
80
Parameter
Standard
INTi Input HIGH Pulse Width
Min.
250
INTi Input LOW Pulse Width
250
Rev.2.41 Jan 10, 2006
REJ09B0185-0241
Page 316 of 390
Max.
Unit
ns
ns
M16C/62P Group (M16C/62P, M16C/62PT)
23. Electrical Characteristics
VCC1=VCC2=5V
Switching Characteristics
(VCC1 = VCC2 = 5V, VSS = 0V, at Topr = −20 to 85°C / −40 to 85°C unless otherwise specified)
Table 23.27
Memory Expansion and Microprocessor Modes (for setting with no wait)
Symbol
td(BCLK-AD)
th(BCLK-AD)
th(RD-AD)
th(WR-AD)
td(BCLK-CS)
th(BCLK-CS)
td(BCLK-ALE)
th(BCLK-ALE)
td(BCLK-RD)
th(BCLK-RD)
td(BCLK-WR)
th(BCLK-WR)
td(BCLK-DB)
th(BCLK-DB)
td(DB-WR)
th(WR-DB)
td(BCLK-HLDA)
Parameter
Address Output Delay Time
Address Output Hold Time (in relation to BCLK)
Address Output Hold Time (in relation to RD)
Address Output Hold Time (in relation to WR)
Chip Select Output Delay Time
Chip Select Output Hold Time (in relation to BCLK)
ALE Signal Output Delay Time
ALE Signal Output Hold Time
RD Signal Output Delay Time
RD Signal Output Hold Time
WR Signal Output Delay Time
WR Signal Output Hold Time
Data Output Delay Time (in relation to BCLK)
Data Output Hold Time (in relation to BCLK) (3)
Data Output Delay Time (in relation to WR)
Data Output Hold Time (in relation to WR) (3)
HLDA Output Delay Time
See
Figure 23.2
Standard
Min.
Max.
25
4
0
(NOTE 2)
25
4
15
−4
25
0
25
0
40
4
(NOTE 1)
(NOTE 2)
40
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
NOTES:
1. Calculated according to the BCLK frequency as follows:
9
0.5x10
f(BCLK) is 12.5MHz or less.
------------------------ – 40 [ ns ]
f ( BCLK )
2. Calculated according to the BCLK frequency as follows:
9
0.5x10
------------------------ – 10 [ ns ]
f ( BCLK )
3. This standard value shows the timing when the output is off, and
does not show hold time of data bus.
Hold time of data bus varies with capacitor volume and pull-up
(pull-down) resistance value.
Hold time of data bus is expressed in
t = −CR X ln (1−VOL / VCC2)
by a circuit of the right figure.
For example, when VOL = 0.2VCC2, C = 30pF, R = 1kΩ, hold time
of output ”L” level is
t = −30pF X 1k Ω X In(1−0.2VCC2 / VCC2)
= 6.7ns.
P0
P1
P2
P3
P4
P5
P6
P7
P8
P9
P10
P11
P12
P13
P14
Figure 23.2
Ports P0 to P14 Measurement Circuit
Rev.2.41 Jan 10, 2006
REJ09B0185-0241
Page 317 of 390
R
DBi
C
30pF
M16C/62P Group (M16C/62P, M16C/62PT)
23. Electrical Characteristics
VCC1=VCC2=5V
Switching Characteristics
(VCC1 = VCC2 = 5V, VSS = 0V, at Topr = −20 to 85°C / −40 to 85°C unless otherwise specified)
Table 23.28
Memory Expansion and Microprocessor Modes (for 1- to 3-wait setting and external
area access)
Symbol
Standard
Min.
Max.
25
4
0
Parameter
td(BCLK-AD)
th(BCLK-AD)
th(RD-AD)
Address Output Delay Time
Address Output Hold Time (in relation to BCLK)
Address Output Hold Time (in relation to RD)
th(WR-AD)
td(BCLK-CS)
th(BCLK-CS)
td(BCLK-ALE)
th(BCLK-ALE)
td(BCLK-RD)
th(BCLK-RD)
td(BCLK-WR)
th(BCLK-WR)
td(BCLK-DB)
th(BCLK-DB)
td(DB-WR)
th(WR-DB)
td(BCLK-HLDA)
Address Output Hold Time (in relation to WR)
Chip Select Output Delay Time
Chip Select Output Hold Time (in relation to BCLK)
ALE Signal Output Delay Time
ALE Signal Output Hold Time
RD Signal Output Delay Time
RD Signal Output Hold Time
WR Signal Output Delay Time
WR Signal Output Hold Time
Data Output Delay Time (in relation to BCLK)
Data Output Hold Time (in relation to BCLK) (3)
Data Output Delay Time (in relation to WR)
Data Output Hold Time (in relation to WR)(3)
HLDA Output Delay Time
Unit
ns
ns
ns
(NOTE 2)
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
25
4
15
See
Figure 23.2
-4
25
0
25
0
40
4
(NOTE 1)
(NOTE 2)
40
NOTES:
1. Calculated according to the BCLK frequency as follows:
9
( n – 0.5 )x10
------------------------------------ – 40 [ ns ]
f ( BCLK )
n is “1” for 1-wait setting, “2” for 2-wait setting
and “3” for 3-wait setting.
(BCLK) is 12.5MHz or less.
2. Calculated according to the BCLK frequency as follows:
9
0.5x10
------------------------ – 10 [ ns ]
f ( BCLK )
3. This standard value shows the timing when the output is off, and
does not show hold time of data bus.
Hold time of data bus varies with capacitor volume and pull-up
(pull-down) resistance value.
Hold time of data bus is expressed in
t = −CR X ln (1−VOL / VCC2)
by a circuit of the right figure.
For example, when VOL = 0.2VCC2, C = 30pF, R = 1kΩ, hold time
of output ”L” level is
t = −30pF X 1kΩ X In(1−0.2VCC2 / VCC2)
= 6.7ns.
Rev.2.41 Jan 10, 2006
REJ09B0185-0241
Page 318 of 390
R
DBi
C
M16C/62P Group (M16C/62P, M16C/62PT)
23. Electrical Characteristics
VCC1=VCC2=5V
Switching Characteristics
(VCC1 = VCC2 = 5V, VSS = 0V, at Topr = −20 to 85°C / −40 to 85°C unless otherwise specified)
Table 23.29
Memory Expansion and Microprocessor Modes (for 2- to 3-wait setting, external area
access and multiplex bus selection)
Symbol
Standard
Min.
Max.
25
4
(NOTE 1)
Parameter
td(BCLK-AD)
th(BCLK-AD)
th(RD-AD)
Address Output Delay Time
Address Output Hold Time (in relation to BCLK)
Address Output Hold Time (in relation to RD)
th(WR-AD)
td(BCLK-CS)
th(BCLK-CS)
th(RD-CS)
th(WR-CS)
td(BCLK-RD)
th(BCLK-RD)
td(BCLK-WR)
th(BCLK-WR)
td(BCLK-DB)
th(BCLK-DB)
td(DB-WR)
th(WR-DB)
td(BCLK-HLDA)
td(BCLK-ALE)
th(BCLK-ALE)
td(AD-ALE)
th(AD-ALE)
td(AD-RD)
td(AD-WR)
tdz(RD-AD)
Address Output Hold Time (in relation to WR)
Chip Select Output Delay Time
Chip Select Output Hold Time (in relation to BCLK)
Chip Select Output Hold Time (in relation to RD)
Chip Select Output Hold Time (in relation to WR)
RD Signal Output Delay Time
RD Signal Output Hold Time
WR Signal Output Delay Time
WR Signal Output Hold Time
Data Output Delay Time (in relation to BCLK)
Data Output Hold Time (in relation to BCLK)
Data Output Delay Time (in relation to WR)
Data Output Hold Time (in relation to WR)
HLDA Output Delay Time
ALE Signal Output Delay Time (in relation to BCLK)
ALE Signal Output Hold Time (in relation to BCLK)
ALE Signal Output Delay Time (in relation to Address)
ALE Signal Output Hold Time (in relation to Address)
RD Signal Output Delay From the End of Address
WR Signal Output Delay From the End of Address
Address Output Floating Start Time
(NOTE 1)
25
4
(NOTE 1)
(NOTE 1)
25
0
25
See
Figure 23.2
NOTES:
1. Calculated according to the BCLK frequency as follows:
9
0.5x10
------------------------ – 10 [ ns ]
f ( BCLK )
2. Calculated according to the BCLK frequency as follows:
9
( n – 0.5 )x10
------------------------------------ – 40 [ ns ]
f ( BCLK )
n is “2” for 2-wait setting, “3” for 3-wait setting.
3. Calculated according to the BCLK frequency as follows:
9
0.5x10
------------------------ – 25 [ ns ]
f ( BCLK )
4. Calculated according to the BCLK frequency as follows:
9
0.5x10
------------------------ – 15 [ ns ]
f ( BCLK )
Rev.2.41 Jan 10, 2006
REJ09B0185-0241
Page 319 of 390
0
40
4
(NOTE 2)
(NOTE 1)
40
15
−4
(NOTE 3)
(NOTE 4)
0
0
8
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
M16C/62P Group (M16C/62P, M16C/62PT)
23. Electrical Characteristics
VCC1=VCC2=5V
XIN input
tw(H)
tr
tf
tw(L)
tc
tc(TA)
tw(TAH)
TAiIN input
tw(TAL)
tc(UP)
tw(UPH)
TAiOUT input
tw(UPL)
TAiOUT input
(Up/down input)
During event counter mode
TAiIN input
(When count on falling
edge is selected)
TAiIN input
(When count on rising
edge is selected)
th(TIN-UP) tsu(UP-TIN)
Two-phase pulse input in
event counter mode
tc(TA)
TAiIN input
tsu(TAIN-TAOUT)
tsu(TAIN-TAOUT)
tsu(TAOUT-TAIN)
TAiOUT input
tsu(TAOUT-TAIN)
tc(TB)
tw(TBH)
TBiIN input
tw(TBL)
tc(AD)
tw(ADL)
ADTRG input
Figure 23.3
Timing Diagram (1)
Rev.2.41 Jan 10, 2006
REJ09B0185-0241
Page 320 of 390
M16C/62P Group (M16C/62P, M16C/62PT)
23. Electrical Characteristics
VCC1=VCC2=5V
tc(CK)
tw(CKH)
CLKi
tw(CKL)
th(C-Q)
TXDi
tsu(D-C)
td(C-Q)
RXDi
tw(INL)
INTi input
tw(INH)
Figure 23.4
Timing Diagram (2)
Rev.2.41 Jan 10, 2006
REJ09B0185-0241
Page 321 of 390
th(C-D)
M16C/62P Group (M16C/62P, M16C/62PT)
23. Electrical Characteristics
VCC1=VCC2=5V
Memory Expansion Mode, Microprocessor Mode
(Effective for setting with wait)
BCLK
RD
(Separate bus)
WR, WRL, WRH
(Separate bus)
RD
(Multiplexed bus)
WR, WRL, WRH
(Multiplexed bus)
RDY input
tsu(RDY−BCLK)
th(BCLK−RDY)
(Common to setting with wait and setting without wait)
BCLK
th(BCLK−HOLD)
tsu(HOLD−BCLK)
HOLD input
HLDA input
td(BCLK−HLDA)
P0, P1, P2,
P3, P4,
P5_0 to P5_2
td(BCLK−HLDA)
Hi−Z
(1)
NOTES:
1. These pins are set to high-impedance regardless of the input level of the
BYTE pin, PM06 bit in PM0 register and PM11 bit in PM1 register.
· Measuring conditions :
· VCC1=VCC2=5V
· Input timing voltage : Determined with VIL=1.0V, VIH=4.0V
· Output timing voltage : Determined with VOL=2.5V, VOH=2.5V
Figure 23.5
Timing Diagram (3)
Rev.2.41 Jan 10, 2006
REJ09B0185-0241
Page 322 of 390
M16C/62P Group (M16C/62P, M16C/62PT)
23. Electrical Characteristics
VCC1=VCC2=5V
Memory Expansion Mode, Microprocessor Mode
(For setting with no wait)
Read timing
BCLK
td(BCLK-CS)
th(BCLK-CS)
25ns.max
4ns.min
CSi
tcyc
td(BCLK-AD)
th(BCLK-AD)
25ns.max
4ns.min
ADi
BHE
td(BCLK-ALE)
th(BCLK-ALE)
-4ns.min
25ns.max
th(RD-AD)
0ns.min
ALE
td(BCLK-RD)
25ns.max
th(BCLK-RD)
0ns.min
RD
tac1(RD-DB)
(0.5 × tcyc-45)ns.max
Hi-Z
DBi
tsu(DB-RD)
th(RD-DB)
40ns.min
0ns.min
Write timing
BCLK
td(BCLK-CS)
th(BCLK-CS)
25ns.max
4ns.min
CSi
tcyc
td(BCLK-AD)
th(BCLK-AD)
25ns.max
4ns.min
ADi
BHE
td(BCLK-ALE)
th(BCLK-ALE)
25ns.max
th(WR-AD)
(0.5 × tcyc-10)ns.min
-4ns.min
ALE
td(BCLK-WR)
25ns.max
th(BCLK-WR)
0ns.min
WR, WRL,
WRH
td(BCLK-DB)
th(BCLK-DB)
40ns.max
4ns.min
Hi-Z
DBi
tcyc=
td(DB-WR)
(0.5 × tcyc-40)ns.min
1
f(BCLK)
Measuring conditions
· VCC1=VCC2=5V
· Input timing voltage : VIL=0.8V, VIH=2.0V
· Output timing voltage : VOL=0.4V, VOH=2.4V
Figure 23.6
Timing Diagram (4)
Rev.2.41 Jan 10, 2006
REJ09B0185-0241
Page 323 of 390
th(WR-DB)
(0.5 × tcyc-10)ns.min
M16C/62P Group (M16C/62P, M16C/62PT)
23. Electrical Characteristics
VCC1=VCC2=5V
Memory Expansion Mode, Microprocessor Mode
(for 1-wait setting and external area access)
Read timing
BCLK
td(BCLK-CS)
th(BCLK-CS)
25ns.max
4ns.min
CSi
tcyc
td(BCLK-AD)
th(BCLK-AD)
25ns.max
4ns.min
ADi
BHE
td(BCLK-ALE)
th(RD-AD)
0ns.min
th(BCLK-ALE)
25ns.max
-4ns.min
ALE
td(BCLK-RD)
th(BCLK-RD)
0ns.min
25ns.max
RD
tac2(RD-DB)
(1.5 × tcyc-45)ns.max
Hi-Z
DBi
th(RD-DB)
tsu(DB-RD)
0ns.min
40ns.min
Write timing
BCLK
td(BCLK-CS)
th(BCLK-CS)
25ns.max
4ns.min
CSi
tcyc
td(BCLK-AD)
th(BCLK-AD)
25ns.max
4ns.min
ADi
BHE
td(BCLK-ALE)
th(BCLK-ALE)
25ns.max
th(WR-AD)
(0.5 × tcyc-10)ns.min
-4ns.min
ALE
td(BCLK-WR)
25ns.max
th(BCLK-WR)
0ns.min
WR, WRL,
WRH
td(BCLK-DB)
th(BCLK-DB)
4ns.min
40ns.max
Hi-Z
DBi
td(DB-WR)
tcyc=
(0.5 × tcyc-40)ns.min
1
f(BCLK)
Measuring conditions
· VCC1=VCC2=5V
· Input timing voltage : VIL=0.8V, VIH=2.0V
· Output timing voltage : VOL=0.4V, VOH=2.4V
Figure 23.7
Timing Diagram (5)
Rev.2.41 Jan 10, 2006
REJ09B0185-0241
Page 324 of 390
th(WR-DB)
(0.5 × tcyc-10)ns.min
M16C/62P Group (M16C/62P, M16C/62PT)
23. Electrical Characteristics
VCC1=VCC2=5V
Memory Expansion Mode, Microprocessor Mode
(for 2-wait setting and external area access)
Read timing
tcyc
BCLK
th(BCLK-CS)
4ns.min
td(BCLK-CS)
25ns.max
CSi
td(BCLK-AD)
25ns.max
th(BCLK-AD)
4ns.min
ADi
BHE
td(BCLK-ALE)
25ns.max
th(RD-AD)
th(BCLK-ALE)
0ns.min
-4ns.min
ALE
th(BCLK-RD)
0ns.min
td(BCLK-RD)
25ns.max
RD
tac2(RD-DB)
(2.5×tcyc-45)ns.max
DBi
Hi-Z
tsu(DB-RD)
40ns.min
th(RD-DB)
0ns.min
Write timing
tcyc
BCLK
td(BCLK-CS)
25ns.max
th(BCLK-CS)
td(BCLK-AD)
25ns.max
th(BCLK-AD)
4ns.min
4ns.min
CSi
ADi
BHE
td(BCLK-ALE)
25ns.max
th(WR-AD)
th(BCLK-ALE)
(0.5×tcyc-10)ns.min
-4ns.min
ALE
td(BCLK-WR)
25ns.max
th(BCLK-WR)
0ns.min
WR, WRL
WRH
td(BCLK-DB)
40ns.max
Hi-Z
DBi
td(DB-WR)
(1.5×tcyc-40)ns.min
Tcyc=
1
f(BCLK)
Measuring conditions
· VCC1=VCC2=5V
· Input timing voltage : V IL=0.8V, VIH=2.0V
· Output timing voltage : V OL=0.4V, VOH=2.4V
Figure 23.8
th(BCLK-DB)
4ns.min
Timing Diagram (6)
Rev.2.41 Jan 10, 2006
REJ09B0185-0241
Page 325 of 390
th(WR-DB)
(0.5×tcyc-10)ns.min
M16C/62P Group (M16C/62P, M16C/62PT)
23. Electrical Characteristics
VCC1=VCC2=5V
Memory Expansion Mode, Microprocessor Mode
(for 3-wait setting and external area access)
Read timing
tcyc
BCLK
th(BCLK-CS)
td(BCLK-CS)
25ns.max
4ns.min
CSi
th(BCLK-AD)
4ns.min
td(BCLK-AD)
25ns.max
ADi
BHE
td(BCLK-ALE)
th(RD-AD)
th(BCLK-ALE)
25ns.max
0ns.min
-4ns.min
ALE
th(BCLK-RD)
td(BCLK-RD)
25ns.max
0ns.min
RD
tac2(RD-DB)
(3.5×tcyc-45)ns.max
Hi-Z
DBi
tsu(DB-RD)
th(RD-DB)
40ns.min
0ns.min
Write timing
tcyc
BCLK
td(BCLK-CS)
25ns.max
th(BCLK-CS)
td(BCLK-AD)
th(BCLK-AD)
4ns.min
CSi
4ns.min
25ns.max
ADi
BHE
td(BCLK-ALE)
25ns.max
th(WR-AD)
th(BCLK-ALE)
(0.5×tcyc-10)ns.min
-4ns.min
ALE
td(BCLK-WR)
25ns.max
th(BCLK-WR)
0ns.min
WR, WRL
WRH
td(BCLK-DB)
th(BCLK-DB)
4ns.min
40ns.max
Hi-Z
DBi
td(DB-WR)
(2.5×tcyc-40)ns.min
tcyc=
1
f(BCLK)
Measuring conditions
· VCC1=VCC2=5V
· Input timing voltage : V IL=0.8V, VIH=2.0V
· Output timing voltage : V OL=0.4V, VOH=2.4V
Figure 23.9
Timing Diagram (7)
Rev.2.41 Jan 10, 2006
REJ09B0185-0241
Page 326 of 390
th(WR-DB)
(0.5×tcyc-10)ns.min
M16C/62P Group (M16C/62P, M16C/62PT)
23. Electrical Characteristics
VCC1=VCC2=5V
Memory Expansion Mode, Microprocessor Mode
(For 1- or 2-wait setting, external area access and multiplex bus selection )
Read timing
BCLK
td(BCLK-CS)
th(BCLK-CS)
th(RD-CS)
(0.5×tcyc-10)ns.min
tcyc
25ns.max
4ns.min
CSi
td(AD-ALE)
th(ALE-AD)
(0.5×tcyc-25)ns.min
(0.5×tcyc-15)ns.min
ADi
/DBi
Address
8ns.max
Address
Data input
tdZ(RD-AD)
tac3(RD-DB)
(1.5×tcyc-45)ns.max
tsu(DB-RD)
th(RD-DB)
0ns.min
40ns.min
td(AD-RD)
0ns.min
td(BCLK-AD)
th(BCLK-AD)
4ns.min
25ns.max
ADi
BHE
td(BCLK-ALE)
th(RD-AD)
(0.5×tcyc-10)ns.min
th(BCLK-ALE)
−4ns.min
25ns.max
ALE
td(BCLK-RD)
th(BCLK-RD)
25ns.max
0ns.min
RD
Write timing
BCLK
th(BCLK-CS)
th(WR-CS)
tcyc
td(BCLK-CS)
4ns.min
(0.5×tcyc-10)ns.min
25ns.max
CSi
th(BCLK-DB)
td(BCLK-DB)
4ns.min
40ns.max
ADi
/DBi
Address
Address
Data output
td(DB-WR)
(1.5×tcyc-40)ns.min
td(AD-ALE)
(0.5×tcyc-25)ns.min
th(WR-DB)
(0.5×tcyc-10)ns.min
td(BCLK-AD)
th(BCLK-AD)
4ns.min
25ns.max
ADi
BHE
td(BCLK-ALE)
25ns.max
th(BCLK-ALE)
td(AD-WR)
−4ns.min
0ns.min
th(WR-AD)
(0.5×tcyc-10)ns.min
ALE
td(BCLK-WR)
25ns.max
WR,WRL,
WRH
Measuring conditions
· VCC1=VCC2=5V
· Input timing voltage : V IL=0.8V, VIH=2.0V
· Output timing voltage : V OL=0.4V, VOH=2.4V
Figure 23.10
Timing Diagram (8)
Rev.2.41 Jan 10, 2006
REJ09B0185-0241
Page 327 of 390
th(BCLK-WR)
0ns.min
M16C/62P Group (M16C/62P, M16C/62PT)
23. Electrical Characteristics
VCC1=VCC2=5V
Memory Expansion Mode, Microprocessor Mode
(For 3-wait setting, external area access and multiplex bus selection )
Read timing
tcyc
BCLK
th(RD-CS)
(0.5×tcyc-10)ns.min
td(BCLK-CS)
th(BCLK-CS)
4ns.min
25ns.max
CSi
td(AD-ALE)
th(ALE-AD)
(0.5×tcyc-25)ns.min
ADi
/DBi
(0.5×tcyc-15)ns.min
Address
Data input
th(RD-DB)
tdZ(RD-AD)
td(BCLK-AD)
8ns.max
td(AD-RD)
25ns.max
(2.5×tcyc-45)ns.max
0ns.min
ADi
BHE
tac3(RD-DB)
tsu(DB-RD)
0ns.min
th(BCLK-AD)
4ns.min
40ns.min
(no multiplex)
td(BCLK-ALE)
25ns.max
th(RD-AD)
th(BCLK-ALE)
(0.5×tcyc-10)ns.min
-4ns.min
ALE
th(BCLK-RD)
td(BCLK-RD)
0ns.min
25ns.max
RD
Write timing
tcyc
BCLK
th(WR-CS)
(0.5×tcyc-10)ns.min
td(BCLK-CS)
th(BCLK-CS)
4ns.min
25ns.max
CSi
ADi
/DBi
td(BCLK-DB)
th(BCLK-DB)
40ns.max
4ns.min
Address
Data output
td(AD-ALE)
(0.5×tcyc-25)ns.min
td(DB-WR)
(2.5×tcyc-40)ns.min
th(WR-DB)
(0.5×tcyc-10)ns.min
td(BCLK-AD)
th(BCLK-AD)
25ns.max
4ns.min
ADi
BHE
(no multiplex)
td(BCLK-ALE)
25ns.max
th(BCLK-ALE)
th(WR-AD)
-4ns.min
td(AD-WR)
(0.5×tcyc-10)ns.min
0ns.min
ALE
th(BCLK-WR)
td(BCLK-WR)
25ns.max
WR, WRL
WRH
tcyc=
1
f(BCLK)
Measuring conditions
· VCC1=VCC2=5V
· Input timing voltage : V IL=0.8V, VIH=2.0V
· Output timing voltage : V OL=0.4V, VOH=2.4V
Figure 23.11
Timing Diagram (9)
Rev.2.41 Jan 10, 2006
REJ09B0185-0241
Page 328 of 390
0ns.min
M16C/62P Group (M16C/62P, M16C/62PT)
23. Electrical Characteristics
VCC1=VCC2=3V
Table 23.30
Electrical Characteristics (1)
Symbol
VOH
VOH
Parameter
HIGH Output
Voltage (3)
IOH=−1mA
P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7,
P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7,
P12_0 to P12_7, P13_0 to P13_7
IOH=−1mA (2)
HIGH Output Voltage
VOL
LOW Output
Voltage (3)
XOUT
XCOUT
IOH=−0.1mA
LOWPOWER
IOH=−50µA
HIGHPOWER
With no load applied
LOWPOWER
With no load applied
IOL=1mA
P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7,
P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7,
P12_0 to P12_7, P13_0 to P13_7
IOL=1mA (2)
LOW Output Voltage
Hysteresis
HIGHPOWER
P6_0 to P6_7, P7_0 to P7_7, P8_0 to P8_4,
P8_6, P8_7, P9_0 to P9_7, P10_0 to P10_7,
P11_0 to P11_7, P14_0, P14_1
XOUT
LOW Output Voltage
VT+-VT-
Measuring Condition
P6_0 to P6_7, P7_2 to P7_7, P8_0 to P8_4,
P8_6, P8_7, P9_0 to P9_7, P10_0 to P10_7,
P11_0 to P11_7, P14_0, P14_1
HIGH Output Voltage
VOL
(1)
XCOUT
HIGHPOWER
IOL=0.1mA
LOWPOWER
IOL=50µA
HIGHPOWER
With no load applied
LOWPOWER
With no load applied
HOLD, RDY, TA0IN to TA4IN,
TB0IN to TB5IN, INT0 to INT5, NMI,
ADTRG, CTS0 to CTS2, CLK0 to CLK4,
TA0OUT to TA4OUT, KI0 to KI3, RXD0 to RXD2,
SCL0 to SCL2, SDA0 to SDA2, SIN3, SIN4
RESET
HIGH Input
Current (3)
P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7,
P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7,
P6_0 to P6_7, P7_0 to P7_7, P8_0 to P8_7,
P9_0 to P9_7, P10_0 to P10_7, P11_0 to P11_7,
P12_0 to P12_7, P13_0 to P13_7, P14_0, P14_1,
XIN, RESET, CNVSS, BYTE
VI=3V
P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7,
P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7,
P6_0 to P6_7, P7_0 to P7_7, P8_0 to P8_7,
P9_0 to P9_7, P10_0 to P10_7, P11_0 to P11_7,
P12_0 to P12_7, P13_0 to P13_7, P14_0, P14_1,
XIN, RESET, CNVSS, BYTE
VI=0V
Resistance
(3)
RfXIN
RfXCIN
VRAM
VCC1−0.5
VCC1
VCC2−0.5
VCC2
VCC1−0.5
VCC1−0.5
VCC1
VCC1
2.5
1.6
V
0.5
0.5
0
0
50
(0.7)
100
Feedback Resistance XCIN
At stop mode
0.8
V
1.8
V
4.0
µA
−4.0
µA
500
kΩ
2.0
NOTES:
1. Referenced to VCC1 = VCC2 = 2.7 to 3.3V, VSS = 0V at Topr = −20 to 85°C / −40 to 85°C, f(XIN)=10MHz no wait unless
otherwise specified.
2. VCC1 for the port P6 to P11 and P14, and VCC2 for the port P0 to P5 and P12 to P13
3. There is no external connections for port P1_0 to P1_7, P4_4 to P4_7, P7_2 to P7_5 and P9_1 in 80-pin version.
Page 329 of 390
V
V
3.0
25
Feedback Resistance XIN
Rev.2.41 Jan 10, 2006
REJ09B0185-0241
V
V
0.2
P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7, P3_0 VI=0V
to P3_7, P4_0 to P4_7, P5_0 to P5_7, P6_0 to
P6_7, P7_2 to P7_7, P8_0 to P8_4, P8_6, P8_7,
P9_0 to P9_7, P10_0 to P10_7,
P11_0 to P11_7,P12_0 to P12_7, P13_0 to P13_7,
P14_0, P14_1
RAM Retention Voltage
Unit
V
0.2
IIH
RPULLUP Pull-Up
Max.
0.5
Hysteresis
LOW Input
Current (3)
Standard
Typ.
0.5
VT+-VT-
IIL
Min.
MΩ
MΩ
V
M16C/62P Group (M16C/62P, M16C/62PT)
Table 23.31
Electrical Characteristics (2) (1)
Symbol
ICC
23. Electrical Characteristics
Parameter
Measuring Condition
In single-chip
Power Supply Current
(VCC1=VCC2=2.7V to 3.6V) mode, the output
pins are open and
other pins are VSS
Mask ROM
Flash
Memory
Flash Memory
Program
Flash Memory
Erase
Mask ROM
Flash Memory
Idet4
Idet3
(4)
Low Voltage Detection Dissipation Current
Reset Area Detection Dissipation Current (4)
Standard
Typ. Max.
8
No division,
On-chip oscillation
1
f(BCLK)=10MHz,
No division
8
No division,
On-chip oscillation
1.8
mA
f(BCLK)=10MHz,
VCC1=3.0V
12
mA
f(BCLK)=10MHz,
VCC1=3.0V
22
mA
f(XCIN)=32kHz
Low power dissipation
mode, ROM (3)
25
µA
f(BCLK)=32kHz
Low power dissipation
mode, RAM (3)
25
µA
420
µA
On-chip oscillation,
Wait mode
45
µA
f(BCLK)=32kHz
Wait mode (2),
Oscillation capability High
6.0
µA
f(BCLK)=32kHz
Wait mode (2),
Oscillation capability Low
1.8
µA
Stop mode
Topr =25°C
0.7
3.0
µA
0.6
0.4
4
2
µA
µA
11
Page 330 of 390
mA
mA
13
NOTES:
1. Referenced to VCC1=VCC2=2.7 to 3.3V, VSS = 0V at Topr = −20 to 85°C / −40 to 85°C, f(BCLK)=10MHz unless otherwise
specified.
2. With one timer operated using fC32.
3. This indicates the memory in which the program to be executed exists.
4. Idet is dissipation current when the following bit is set to “1” (detection circuit enabled).
Idet4: VC27 bit in the VCR2 register
Idet3: VC26 bit in the VCR2 register
Rev.2.41 Jan 10, 2006
REJ09B0185-0241
Unit
f(BCLK)=10MHz
No division
f(BCLK)=32kHz
Low power dissipation
mode, Flash Memory (3)
Mask ROM
Flash Memory
Min.
mA
M16C/62P Group (M16C/62P, M16C/62PT)
23. Electrical Characteristics
VCC1=VCC2=3V
Timing Requirements
(VCC1 = VCC2 = 3V, VSS = 0V, at Topr = −20 to 85°C / −40 to 85°C unless otherwise specified)
Table 23.32
External Clock Input (XIN input)(1)
Symbol
Parameter
External Clock Input Cycle Time
External Clock Input HIGH Pulse Width
External Clock Input LOW Pulse Width
External Clock Rise Time
External Clock Fall Time
tc
tw(H)
tw(L)
tr
tf
Standard
Min.
Max.
(NOTE 2)
(NOTE 3)
(NOTE 3)
(NOTE 4)
(NOTE 4)
Unit
ns
ns
ns
ns
ns
NOTES:
1. The condition is VCC1=VCC2=2.7 to 3.0V.
2. Calculated according to the VCC1 voltage as follows:
10 –6
---------------------------------------- [ns]
20 × V C C2 – 44
3. Calculated according to the VCC1 voltage as follows:
–6
10
---------------------------------------- × 0.4 [ns]
20 × V C C1 – 44
4. Calculated according to the VCC1 voltage as follows:
– 10 × V C C1 + 45 [ns]
Table 23.33
Memory Expansion Mode and Microprocessor Mode
Symbol
tac1(RD-DB)
tac2(RD-DB)
tac3(RD-DB)
tsu(DB-RD)
tsu(RDY-BCLK)
tsu(HOLD-BCLK)
th(RD-DB)
th(BCLK-RDY)
th(BCLK-HOLD)
Parameter
Data Input Access Time (for setting with no wait)
Data Input Access Time (for setting with wait)
Data Input Access Time (when accessing multiplex bus area)
Data Input Setup Time
RDY Input Setup Time
HOLD Input Setup Time
Data Input Hold Time
RDY Input Hold Time
HOLD Input Hold Time
Standard
Min.
Max.
(NOTE 1)
(NOTE 2)
(NOTE 3)
50
40
50
0
0
0
NOTES:
1. Calculated according to the BCLK frequency as follows:
9
0.5x10
------------------------ – 60 [ ns ]
f ( BCLK )
2. Calculated according to the BCLK frequency as follows:
9
( n – 0.5 )x10
------------------------------------ – 60 [ ns ]
f ( BCLK )
n is ”2” for 1-wait setting, “3” for 2-wait setting and “4” for 3-wait setting.
3. Calculated according to the BCLK frequency as follows:
9
( n – 0.5 )x10
------------------------------------ – 60 [ ns ]
f ( BCLK )
Rev.2.41 Jan 10, 2006
REJ09B0185-0241
n is “2” for 2-wait setting, “3” for 3-wait setting.
Page 331 of 390
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
M16C/62P Group (M16C/62P, M16C/62PT)
23. Electrical Characteristics
VCC1=VCC2=3V
Timing Requirements
(VCC1 = VCC2 = 3V, VSS = 0V, at Topr = −20 to 85°C / −40 to 85°C unless otherwise specified)
Table 23.34
Timer A Input (Counter Input in Event Counter Mode)
Symbol
tc(TA)
tw(TAH)
tw(TAL)
Table 23.35
Parameter
TAiIN Input Cycle Time
TAiIN Input HIGH Pulse Width
TAiIN Input LOW Pulse Width
Table 23.36
Parameter
TAiIN Input Cycle Time
TAiIN Input HIGH Pulse Width
TAiIN Input LOW Pulse Width
Table 23.37
Parameter
TAiIN Input Cycle Time
TAiIN Input HIGH Pulse Width
TAiIN Input LOW Pulse Width
Table 23.38
Parameter
TAiIN Input HIGH Pulse Width
TAiIN Input LOW Pulse Width
Standard
Min.
600
300
300
Unit
ns
ns
ns
Standard
Min.
300
150
150
Max.
Unit
ns
ns
ns
Standard
Min.
150
150
Parameter
Max.
Unit
ns
ns
Standard
tc(UP)
TAiOUT Input Cycle Time
Min.
3000
tw(UPH)
tw(UPL)
tsu(UP-TIN)
th(TIN-UP)
TAiOUT Input HIGH Pulse Width
TAiOUT Input LOW Pulse Width
TAiOUT Input Setup Time
TAiOUT Input Hold Time
1500
1500
600
600
Max.
Unit
ns
ns
ns
ns
ns
Timer A Input (Two-phase Pulse Input in Event Counter Mode)
Symbol
tc(TA)
tsu(TAIN-TAOUT)
tsu(TAOUT-TAIN)
Max.
Timer A Input (Counter Increment/Decrement Input in Event Counter Mode)
Symbol
Table 23.39
ns
ns
ns
Timer A Input (External Trigger Input in Pulse Width Modulation Mode)
Symbol
tw(TAH)
tw(TAL)
Unit
Timer A Input (External Trigger Input in One-shot Timer Mode)
Symbol
tc(TA)
tw(TAH)
tw(TAL)
Max.
Timer A Input (Gating Input in Timer Mode)
Symbol
tc(TA)
tw(TAH)
tw(TAL)
Standard
Min.
150
60
60
Parameter
TAiIN Input Cycle Time
TAiOUT Input Setup Time
TAiIN Input Setup Time
Rev.2.41 Jan 10, 2006
REJ09B0185-0241
Page 332 of 390
Standard
Min.
2
500
500
Max.
Unit
µs
ns
ns
M16C/62P Group (M16C/62P, M16C/62PT)
23. Electrical Characteristics
VCC1=VCC2=3V
Timing Requirements
(VCC1 = VCC2 = 3V, VSS = 0V, at Topr = −20 to 85°C / −40 to 85°C unless otherwise specified)
Table 23.40
Timer B Input (Counter Input in Event Counter Mode)
Symbol
Parameter
Standard
tc(TB)
tw(TBH)
tw(TBL)
tc(TB)
TBiIN Input Cycle Time (counted on one edge)
TBiIN Input HIGH Pulse Width (counted on one edge)
TBiIN Input LOW Pulse Width (counted on one edge)
TBiIN Input Cycle Time (counted on both edges)
Min.
150
60
60
300
tw(TBH)
tw(TBL)
TBiIN Input HIGH Pulse Width (counted on both edges)
TBiIN Input LOW Pulse Width (counted on both edges)
120
120
Table 23.41
Table 23.42
Parameter
TBiIN Input Cycle Time
TBiIN Input HIGH Pulse Width
TBiIN Input LOW Pulse Width
Table 23.43
Parameter
TBiIN Input Cycle Time
TBiIN Input HIGH Pulse Width
TBiIN Input LOW Pulse Width
tc(AD)
Table 23.44
Parameter
Table 23.45
tw(INL)
Max.
Unit
ns
ns
ns
Standard
Min.
600
300
300
Max.
Unit
ns
ns
ns
Standard
ADTRG Input Cycle Time
ADTRG Input LOW Pulse Width
200
Max.
Unit
ns
ns
Serial Interface
Parameter
CLKi Input Cycle Time
CLKi Input HIGH Pulse Width
CLKi Input LOW Pulse Width
TXDi Output Delay Time
TXDi Hold Time
RXDi Input Setup Time
RXDi Input Hold Time
Standard
Min.
300
150
150
Max.
160
0
100
90
Unit
ns
ns
ns
ns
ns
ns
ns
External Interrupt INTi Input
Symbol
tw(INH)
Standard
Min.
600
300
300
Min.
1500
Symbol
tc(CK)
tw(CKH)
tw(CKL)
td(C-Q)
th(C-Q)
tsu(D-C)
th(C-D)
ns
ns
A/D Trigger Input
Symbol
tw(ADL)
ns
ns
ns
ns
Timer B Input (Pulse Width Measurement Mode)
Symbol
tc(TB)
tw(TBH)
tw(TBL)
Unit
Timer B Input (Pulse Period Measurement Mode)
Symbol
tc(TB)
tw(TBH)
tw(TBL)
Max.
Parameter
Standard
INTi Input HIGH Pulse Width
Min.
380
INTi Input LOW Pulse Width
380
Rev.2.41 Jan 10, 2006
REJ09B0185-0241
Page 333 of 390
Max.
Unit
ns
ns
M16C/62P Group (M16C/62P, M16C/62PT)
23. Electrical Characteristics
VCC1=VCC2=3V
Switching Characteristics
(VCC1 = VCC2 = 3V, VSS = 0V, at Topr = −20 to 85°C / −40 to 85°C unless otherwise specified)
Table 23.46
Memory Expansion and Microprocessor Modes (for setting with no wait)
Symbol
td(BCLK-AD)
th(BCLK-AD)
th(RD-AD)
th(WR-AD)
td(BCLK-CS)
th(BCLK-CS)
td(BCLK-ALE)
th(BCLK-ALE)
td(BCLK-RD)
th(BCLK-RD)
td(BCLK-WR)
th(BCLK-WR)
td(BCLK-DB)
th(BCLK-DB)
td(DB-WR)
th(WR-DB)
td(BCLK-HLDA)
Parameter
Address Output Delay Time
Address Output Hold Time (in relation to BCLK)
Address Output Hold Time (in relation to RD)
Address Output Hold Time (in relation to WR)
Chip Select Output Delay Time
Chip Select Output Hold Time (in relation to BCLK)
ALE Signal Output Delay Time
ALE Signal Output Hold Time
RD Signal Output Delay Time
RD Signal Output Hold Time
WR Signal Output Delay Time
WR Signal Output Hold Time
Data Output Delay Time (in relation to BCLK)
Data Output Hold Time (in relation to BCLK) (3)
Data Output Delay Time (in relation to WR)
Data Output Hold Time (in relation to WR) (3)
HLDA Output Delay Time
See
Figure 23.12
Standard
Min.
Max.
30
4
0
(NOTE 2)
30
4
25
−4
30
0
30
0
40
4
(NOTE 1)
(NOTE 2)
40
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
NOTES:
1. Calculated according to the BCLK frequency as follows:
9
0.5x10
f(BCLK) is 12.5MHz or less.
------------------------ – 40 [ ns ]
f ( BCLK )
2. Calculated according to the BCLK frequency as follows:
9
0.5x10
------------------------ – 10 [ ns ]
f ( BCLK )
3. This standard value shows the timing when the output is off, and
does not show hold time of data bus.
Hold time of data bus varies with capacitor volume and pull-up
(pull-down) resistance value.
Hold time of data bus is expressed in
t = −CR X ln (1−VOL / VCC2)
by a circuit of the right figure.
For example, when VOL = 0.2VCC2, C = 30pF, R = 1kΩ, hold time
of output ”L” level is
t = −30pF X 1k Ω X In(1−0.2VCC2 / VCC2)
= 6.7ns.
P0
P1
P2
P3
P4
P5
P6
P7
P8
P9
P10
P11
P12
P13
P14
Figure 23.12
Ports P0 to P14 Measurement Circuit
Rev.2.41 Jan 10, 2006
REJ09B0185-0241
Page 334 of 390
R
DBi
C
30pF
M16C/62P Group (M16C/62P, M16C/62PT)
23. Electrical Characteristics
VCC1=VCC2=3V
Switching Characteristics
(VCC1 = VCC2 = 5V, VSS = 0V, at Topr = −20 to 85°C / −40 to 85°C unless otherwise specified)
Table 23.47
Memory Expansion and Microprocessor Modes (for 1- to 3-wait setting and external
area access)
Symbol
Standard
Min.
Max.
30
4
0
Parameter
td(BCLK-AD)
th(BCLK-AD)
th(RD-AD)
Address Output Delay Time
Address Output Hold Time (in relation to BCLK)
Address Output Hold Time (in relation to RD)
th(WR-AD)
td(BCLK-CS)
th(BCLK-CS)
td(BCLK-ALE)
th(BCLK-ALE)
td(BCLK-RD)
th(BCLK-RD)
td(BCLK-WR)
th(BCLK-WR)
td(BCLK-DB)
th(BCLK-DB)
td(DB-WR)
th(WR-DB)
td(BCLK-HLDA)
Address Output Hold Time (in relation to WR)
Chip Select Output Delay Time
Chip Select Output Hold Time (in relation to BCLK)
ALE Signal Output Delay Time
ALE Signal Output Hold Time
RD Signal Output Delay Time
RD Signal Output Hold Time
WR Signal Output Delay Time
WR Signal Output Hold Time
Data Output Delay Time (in relation to BCLK)
Data Output Hold Time (in relation to BCLK) (3)
Data Output Delay Time (in relation to WR)
Data Output Hold Time (in relation to WR)(3)
HLDA Output Delay Time
Unit
ns
ns
ns
(NOTE 2)
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
30
4
25
See
Figure 23.12
-4
30
0
30
0
40
4
(NOTE 1)
(NOTE 2)
40
NOTES:
1. Calculated according to the BCLK frequency as follows:
9
( n – 0.5 )x10
------------------------------------ – 40 [ ns ]
f ( BCLK )
n is “1” for 1-wait setting, “2” for 2-wait setting
and “3” for 3-wait setting.
(BCLK) is 12.5MHz or less.
2. Calculated according to the BCLK frequency as follows:
9
0.5x10
------------------------ – 10 [ ns ]
f ( BCLK )
3. This standard value shows the timing when the output is off, and
does not show hold time of data bus.
Hold time of data bus varies with capacitor volume and pull-up
(pull-down) resistance value.
Hold time of data bus is expressed in
t = −CR X ln (1−VOL / VCC2)
by a circuit of the right figure.
For example, when VOL = 0.2VCC2, C = 30pF, R = 1kΩ, hold time
of output ”L” level is
t = −30pF X 1kΩ X In(1−0.2VCC2 / VCC2)
= 6.7ns.
Rev.2.41 Jan 10, 2006
REJ09B0185-0241
Page 335 of 390
R
DBi
C
M16C/62P Group (M16C/62P, M16C/62PT)
23. Electrical Characteristics
VCC1=VCC2=3V
Switching Characteristics
(VCC1 = VCC2 = 5V, VSS = 0V, at Topr = −20 to 85°C / −40 to 85°C unless otherwise specified)
Table 23.48
Memory Expansion and Microprocessor Modes (for 2- to 3-wait setting, external area
access and multiplex bus selection)
Symbol
Standard
Min.
Max.
50
4
(NOTE 1)
Parameter
td(BCLK-AD)
th(BCLK-AD)
th(RD-AD)
Address Output Delay Time
Address Output Hold Time (in relation to BCLK)
Address Output Hold Time (in relation to RD)
th(WR-AD)
td(BCLK-CS)
th(BCLK-CS)
th(RD-CS)
th(WR-CS)
td(BCLK-RD)
th(BCLK-RD)
td(BCLK-WR)
th(BCLK-WR)
td(BCLK-DB)
th(BCLK-DB)
td(DB-WR)
th(WR-DB)
td(BCLK-HLDA)
td(BCLK-ALE)
th(BCLK-ALE)
td(AD-ALE)
th(AD-ALE)
td(AD-RD)
td(AD-WR)
tdz(RD-AD)
Address Output Hold Time (in relation to WR)
Chip Select Output Delay Time
Chip Select Output Hold Time (in relation to BCLK)
Chip Select Output Hold Time (in relation to RD)
Chip Select Output Hold Time (in relation to WR)
RD Signal Output Delay Time
RD Signal Output Hold Time
WR Signal Output Delay Time
WR Signal Output Hold Time
Data Output Delay Time (in relation to BCLK)
Data Output Hold Time (in relation to BCLK)
Data Output Delay Time (in relation to WR)
Data Output Hold Time (in relation to WR)
HLDA Output Delay Time
ALE Signal Output Delay Time (in relation to BCLK)
ALE Signal Output Hold Time (in relation to BCLK)
ALE Signal Output Delay Time (in relation to Address)
ALE Signal Output Hold Time (in relation to Address)
RD Signal Output Delay From the End of Address
WR Signal Output Delay From the End of Address
Address Output Floating Start Time
(NOTE 1)
50
4
(NOTE 1)
(NOTE 1)
40
0
40
See
Figure 23.12
NOTES:
1. Calculated according to the BCLK frequency as follows:
9
0.5x10
------------------------ – 10 [ ns ]
f ( BCLK )
2. Calculated according to the BCLK frequency as follows:
9
0.5x10
------------------------ – 50 [ ns ]
f ( BCLK )
n is “2” for 2-wait setting, “3” for 3-wait setting.
3. Calculated according to the BCLK frequency as follows:
9
0.5x10
------------------------ – 40 [ ns ]
f ( BCLK )
4. Calculated according to the BCLK frequency as follows:
9
0.5x10
------------------------ – 15 [ ns ]
f ( BCLK )
Rev.2.41 Jan 10, 2006
REJ09B0185-0241
Page 336 of 390
0
50
4
(NOTE 2)
(NOTE 1)
40
25
−4
(NOTE 3)
(NOTE 4)
0
0
8
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
M16C/62P Group (M16C/62P, M16C/62PT)
23. Electrical Characteristics
VCC1=VCC2=3V
XIN input
tw(H)
tr
tf
tw(L)
tc
tc(TA)
tw(TAH)
TAiIN input
tw(TAL)
tc(UP)
tw(UPH)
TAiOUT input
tw(UPL)
TAiOUT input
(Up/down input)
During Event Counter Mode
TAiIN input
(When count on falling
edge is selected)
th(TIN-UP) tsu(UP-TIN)
TAiIN input
(When count on rising
edge is selected)
Two-Phase Pulse Input in
Event Counter Mode
tc(TA)
TAiIN input
tsu(TAIN-TAOUT)
tsu(TAIN-TAOUT)
tsu(TAOUT-TAIN)
TAiOUT input
tsu(TAOUT-TAIN)
tc(TB)
tw(TBH)
TBiIN input
tw(TBL)
tc(AD)
tw(ADL)
ADTRG input
Figure 23.13
Timing Diagram (1)
Rev.2.41 Jan 10, 2006
REJ09B0185-0241
Page 337 of 390
M16C/62P Group (M16C/62P, M16C/62PT)
23. Electrical Characteristics
VCC1=VCC2=3V
tc(CK)
tw(CKH)
CLKi
tw(CKL)
th(C-Q)
TXDi
tsu(D-C)
td(C-Q)
RXDi
tw(INL)
INTi input
tw(INH)
Figure 23.14
Timing Diagram (2)
Rev.2.41 Jan 10, 2006
REJ09B0185-0241
Page 338 of 390
th(C-D)
M16C/62P Group (M16C/62P, M16C/62PT)
23. Electrical Characteristics
Memory Expansion Mode, Microprocessor Mode
VCC1=VCC2=3V
(Effective for setting with wait)
BCLK
RD
(Separate bus)
WR, WRL, WRH
(Separate bus)
RD
(Multiplexed bus)
WR, WRL, WRH
(Multiplexed bus)
RDY input
tsu(RDY−BCLK)
th(BCLK−RDY)
(Common to setting with wait and setting without wait)
BCLK
th(BCLK−HOLD)
tsu(HOLD−BCLK)
HOLD input
HLDA output
td(BCLK−HLDA)
P0, P1, P2,
P3, P4,
P5_0 to P5_2 (1)
td(BCLK−HLDA)
Hi−Z
NOTES:
1. These pins are set to high-impedance regardless of the input level of the
BYTE pin, PM06 bit in PM0 register and PM11 bit in PM1 register.
Measuring conditions :
· VCC1=VCC2=3V
· Input timing voltage : Determined with V IL=0.6V, VIH=2.4V
· Output timing voltage : Determined with V OL=1.5V, VOH=1.5V
Figure 23.15
Timing Diagram (3)
Rev.2.41 Jan 10, 2006
REJ09B0185-0241
Page 339 of 390
M16C/62P Group (M16C/62P, M16C/62PT)
23. Electrical Characteristics
VCC1=VCC2=3V
Memory Expansion Mode, Microprocessor Mode
(for setting with no wait)
Read timing
BCLK
td(BCLK-CS)
th(BCLK-CS)
30ns.max
4ns.min
CSi
tcyc
td(BCLK-AD)
th(BCLK-AD)
30ns.max
4ns.min
ADi
BHE
td(BCLK-ALE)
th(BCLK-ALE)
-4ns.min
30ns.max
th(RD-AD)
0ns.min
ALE
td(BCLK-RD)
30ns.max
th(BCLK-RD)
0ns.min
RD
tac1(RD-DB)
(0.5 × tcyc-60)ns.max
Hi-Z
DBi
tsu(DB-RD)
50ns.min
th(RD-DB)
0ns.min
Write timing
BCLK
td(BCLK-CS)
th(BCLK-CS)
30ns.max
4ns.min
CSi
tcyc
td(BCLK-AD)
th(BCLK-AD)
30ns.max
4ns.min
ADi
BHE
td(BCLK-ALE)
th(BCLK-ALE)
th(WR-AD)
(0.5 × tcyc-10)ns.min
-4ns.min
30ns.max
ALE
td(BCLK-WR)
30ns.max
th(BCLK-WR)
0ns.min
WR, WRL,
WRH
td(BCLK-DB)
th(BCLK-DB)
40ns.max
4ns.min
Hi-Z
DBi
tcyc=
td(DB-WR)
(0.5 × tcyc-40)ns.min
1
f(BCLK)
Measuring conditions
· VCC1=VCC2=3V
· Input timing voltage : V IL=0.6V, VIH=2.4V
· Output timing voltage : V OL=1.5V, VOH=1.5V
Figure 23.16
Timing Diagram (4)
Rev.2.41 Jan 10, 2006
REJ09B0185-0241
Page 340 of 390
th(WR-DB)
(0.5 × tcyc-10)ns.min
M16C/62P Group (M16C/62P, M16C/62PT)
23. Electrical Characteristics
VCC1=VCC2=3V
Memory Expansion Mode, Microprocessor Mode
(for 1-wait setting and external area access)
Read timing
BCLK
td(BCLK−CS)
th(BCLK−CS)
30ns.max
4ns.min
CSi
tcyc
td(BCLK−AD)
th(BCLK−AD)
30ns.max
4ns.min
ADi
BHE
td(BCLK−ALE)
th(RD−AD)
th(BCLK−ALE)
0ns.min
−4ns.min
30ns.max
ALE
td(BCLK−RD)
th(BCLK−RD)
30ns.max
0ns.min
RD
tac2(RD−DB)
(1.5 × tcyc−60)ns.max
Hi−Z
DBi
th(RD−DB)
tsu(DB−RD)
0ns.min
50ns.min
Write timing
BCLK
td(BCLK−CS)
th(BCLK−CS)
30ns.max
4ns.min
CSi
tcyc
td(BCLK−AD)
th(BCLK−AD)
30ns.max
4ns.min
ADi
BHE
td(BCLK−ALE)
th(BCLK−ALE)
th(WR−AD)
(0.5 × tcyc−10)ns.min
−4ns.min
30ns.max
ALE
td(BCLK−WR)
30ns.max
th(BCLK−WR)
0ns.min
WR,WRL,
WRH
td(BCLK−DB)
th(BCLK−DB)
40ns.max
4ns.min
Hi−Z
DBi
td(DB−WR)
(0.5 × tcyc−40)ns.min
1
tcyc=
f(BCLK)
Measuring conditions
· VCC1=VCC2=3V
· Input timing voltage : V IL=0.6V, VIH=2.4V
· Output timing voltage : V OL=1.5V, VOH=1.5V
Figure 23.17
Timing Diagram (5)
Rev.2.41 Jan 10, 2006
REJ09B0185-0241
Page 341 of 390
th(WR−DB)
(0.5 × tcyc−10)ns.min
M16C/62P Group (M16C/62P, M16C/62PT)
23. Electrical Characteristics
VCC1=VCC2=3V
Memory Expansion Mode, Microprocessor Mode
(for 2-wait setting and external area access )
Read timing
tcyc
BCLK
th(BCLK-CS)
4ns.min
td(BCLK-CS)
30ns.max
CSi
th(BCLK-AD)
4ns.min
td(BCLK-AD)
30ns.max
ADi
BHE
td(BCLK-ALE)
30ns.max
th(RD-AD)
0ns.min
th(BCLK-ALE)
-4ns.min
ALE
th(BCLK-RD)
0ns.min
td(BCLK-RD)
30ns.max
RD
tac2(RD-DB)
(2.5 × tcyc-60)ns.max
Hi-Z
DBi
tsu(DB-RD)
50ns.min
th(RD-DB)
0ns.min
Write timing
tcyc
BCLK
td(BCLK-CS)
30ns.max
th(BCLK-CS)
4ns.min
td(BCLK-AD)
30ns.max
th(BCLK-AD)
4ns.min
CSi
ADi
BHE
td(BCLK-ALE)
30ns.max
th(WR-AD)
(0.5 × tcyc-10)ns.min
th(BCLK-ALE)
-4ns.min
ALE
td(BCLK-WR)
30ns.max
th(BCLK-WR)
0ns.min
WR, WRL
WRH
td(BCLK-DB)
40ns.max
Hi-Z
DBi
td(DB-WR)
(1.5 × tcyc-40)ns.min
tcyc=
1
f(BCLK)
Measuring conditions
· VCC1=VCC2=3V
· Input timing voltage : V IL=0.6V, VIH=2.4V
· Output timing voltage : V OL=1.5V, VOH=1.5V
Figure 23.18
th(BCLK-DB)
4ns.min
Timing Diagram (6)
Rev.2.41 Jan 10, 2006
REJ09B0185-0241
Page 342 of 390
th(WR-DB)
(0.5 × tcyc-10)ns.min
M16C/62P Group (M16C/62P, M16C/62PT)
23. Electrical Characteristics
VCC1 = VCC2 = 3V
Memory Expansion Mode, Microprocessor Mode
(for 3-wait setting and external area access)
Read timing
tcyc
BCLK
th(BCLK-CS)
td(BCLK-CS)
4ns.min
30ns.max
CSi
th(BCLK-AD)
td(BCLK-AD)
4ns.min
30ns.max
ADi
BHE
td(BCLK-ALE)
th(RD-AD)
th(BCLK-ALE)
30ns.max
0ns.min
-4ns.min
ALE
th(BCLK-RD)
td(BCLK-RD)
0ns.min
30ns.max
RD
tac2(RD-DB)
(3.5 × tcyc-60)ns.max
Hi-Z
DBi
tsu(DB-RD)
th(RD-DB)
50ns.min
0ns.min
Write timing
tcyc
BCLK
th(BCLK-CS)
td(BCLK-CS)
4ns.min
30ns.max
CSi
th(BCLK-AD)
td(BCLK-AD)
4ns.min
30ns.max
ADi
BHE
td(BCLK-ALE)
30ns.max
th(WR-AD)
th(BCLK-ALE)
(0.5 × tcyc-10)ns.min
-4ns.min
ALE
th(BCLK-WR)
td(BCLK-WR)
0ns.min
30ns.max
WR, WRL
WRH
td(BCLK-DB)
th(BCLK-DB)
40ns.max
4ns.min
Hi-Z
DBi
td(DB-WR)
(2.5 × tcyc-40)ns.min
tcyc=
1
f(BCLK)
Measuring conditions
· VCC1=VCC2=3V
· Input timing voltage : V IL=0.6V, VIH=2.4V
· Output timing voltage : V OL=1.5V, VOH=1.5V
Figure 23.19
Timing Diagram (7)
Rev.2.41 Jan 10, 2006
REJ09B0185-0241
Page 343 of 390
th(WR-DB)
(0.5 × tcyc-10)ns.min
M16C/62P Group (M16C/62P, M16C/62PT)
23. Electrical Characteristics
Memory Expansion Mode, Microprocessor Mode
VCC1=VCC2=3V
(For 2-wait setting, external area access and multiplex bus selection)
Read timing
BCLK
td(BCLK-CS)
th(BCLK-CS)
th(RD-CS)
(0.5×tcyc-10)ns.min
tcyc
40ns.max
4ns.min
CSi
td(AD-ALE)
(0.5×tcyc-40)ns.min
ADi
/DBi
th(ALE-AD)
(0.5×tcyc-15)ns.min
Address
8ns.max
Address
Data input
tdZ(RD-AD)
tac3(RD-DB)
(1.5×tcyc-60)ns.max
tsu(DB-RD)
th(RD-DB)
0ns.min
50ns.min
td(AD-RD)
0ns.min
td(BCLK-AD)
th(BCLK-AD)
4ns.min
40ns.max
ADi
BHE
td(BCLK-ALE)
th(BCLK-ALE)
40ns.max
th(RD-AD)
(0.5×tcyc-10)ns.min
-4ns.min
ALE
td(BCLK-RD)
th(BCLK-RD)
40ns.max
0ns.min
RD
Write timing
BCLK
tcyc
td(BCLK-CS)
th(BCLK-CS)
th(WR-CS)
(0.5×tcyc-10)ns.min
40ns.max
4ns.min
CSi
th(BCLK-DB)
td(BCLK-DB)
4ns.min
50ns.max
ADi
/DBi
Address
Address
Data output
td(DB-WR)
(1.5×tcyc-50)ns.min
td(AD-ALE)
(0.5×tcyc-40)ns.min
th(WR-DB)
(0.5×tcyc-10)ns.min
td(BCLK-AD)
th(BCLK-AD)
4ns.min
40ns.max
ADi
BHE
td(BCLK-ALE)
40ns.max
td(AD-WR)
th(BCLK-ALE)
-4ns.min
0ns.min
th(WR-AD)
(0.5×tcyc-10)ns.min
ALE
td(BCLK-WR)
40ns.max
WR,WRL,
WRH
tcyc=
1
f(BCLK)
Measuring conditions
· VCC1=VCC2=3V
· Input timing voltage : V IL=0.6V, VIH=2.4V
· Output timing voltage : V OL=1.5V, VOH=1.5V
Figure 23.20
Timing Diagram (8)
Rev.2.41 Jan 10, 2006
REJ09B0185-0241
Page 344 of 390
th(BCLK-WR)
0ns.min
M16C/62P Group (M16C/62P, M16C/62PT)
23. Electrical Characteristics
VCC1=VCC2=3V
Memory Expansion Mode, Microprocessor Mode
(For 3-wait setting, external area access and multiplex bus selection)
Read timing
tcyc
BCLK
th(RD-CS)
(0.5×tcyc-10)ns.min
td(BCLK-CS)
th(BCLK-CS)
6ns.min
40ns.max
CSi
td(AD-ALE)
(0.5×tcyc-40)ns.min
th(ALE-AD)
(0.5×tcyc-15)ns.min
ADi
/DBi
Data input
Address
td(BCLK-AD)
40ns.max
8ns.max
td(AD-RD)
tac3(RD-DB)
(2.5×tcyc-60)ns.max
0ns.min
ADi
BHE
th(RD-DB)
tdZ(RD-AD)
tsu(DB-RD)
0ns.min
th(BCLK-AD)
50ns.min
4ns.min
(No multiplex)
td(BCLK-ALE)
40ns.max
th(RD-AD)
th(BCLK-ALE)
(0.5×tcyc-10)ns.min
-4ns.min
ALE
th(BCLK-RD)
td(BCLK-RD)
0ns.min
40ns.max
RD
Write timing
tcyc
BCLK
th(WR-CS)
(0.5×tcyc-10)ns.min
td(BCLK-CS)
th(BCLK-CS)
4ns.min
40ns.max
CSi
th(BCLK-DB)
td(BCLK-DB)
4ns.min
50ns.max
ADi
/DBi
Address
Data output
td(AD-ALE)
(0.5×tcyc-40)ns.min
td(DB-WR)
(2.5×tcyc-50)ns.min
th(WR-DB)
(0.5×tcyc-10)ns.min
td(BCLK-AD)
th(BCLK-AD)
40ns.max
4ns.min
ADi
BHE
(No multiplex)
td(BCLK-ALE)
th(BCLK-ALE)
40ns.max
-4ns.min
th(WR-AD)
td(AD-WR)
(0.5×tcyc-10)ns.min
0ns.min
ALE
th(BCLK-WR)
td(BCLK-WR)
40ns.max
WR, WRL
WRH
tcyc=
1
f(BCLK)
Measuring conditions
· VCC1=VCC2=3V
· Input timing voltage : V IL=0.6V, VIH=2.4V
· Output timing voltage : V OL=1.5V, VOH=1.5V
Figure 23.21
Timing Diagram (9)
Rev.2.41 Jan 10, 2006
REJ09B0185-0241
Page 345 of 390
0ns.min
M16C/62P Group (M16C/62P, M16C/62PT)
23.2
Electrical Characteristics (M16C/62PT)
Table 23.49
Symbol
VCC1, VCC2
AVCC
VI
VO
Pd
Topr
Tstg
23. Electrical Characteristics
Absolute Maximum Ratings
Parameter
Supply Voltage
Analog Supply Voltage
Input Voltage
RESET, CNVSS, BYTE,
P6_0 to P6_7, P7_2 to P7_7, P8_0 to P8_7,
P9_0 to P9_7, P10_0 to P10_7,
P11_0 to P11_7, P14_0, P14_1,
VREF, XIN
P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7,
P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7,
P12_0 to P12_7, P13_0 to P13_7
P7_0, P7_1
Output Voltage P6_0 to P6_7, P7_2 to P7_7, P8_0 to P8_4,
P8_6, P8_7, P9_0 to P9_7, P10_0 to P10_7,
P11_0 to P11_7, P14_0, P14_1,
XOUT
P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7,
P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7,
P12_0 to P12_7, P13_0 to P13_7
P7_0, P7_1
Power Dissipation
Operating
Ambient
Temperature
When the Microcomputer is Operating
Flash Program Erase
Storage Temperature
Condition
VCC1=VCC2=AVCC
VCC1=VCC2=AVCC
−40°C<Topr≤85°C
85°C<Topr≤125°C
Rated Value
−0.3 to 6.5
−0.3 to 6.5
Unit
V
V
−0.3 to VCC1+0.3 (1)
V
−0.3 to VCC2+0.3 (1)
V
−0.3 to 6.5
V
−0.3 to VCC1+0.3 (1)
V
−0.3 to VCC2+0.3 (1)
V
−0.3 to 6.5
300
200
−40 to 85 / −40 to 125
V
mW
(2)
°C
0 to 60
−65 to 150
°C
NOTES:
1. There is no external connections for port P1_0 to P1_7, P4_4 to P4_7, P7_2 to P7_5 and P9_1 in
80-pin version.
2. T version = −40 to 85 °C, V version= −40 to 125 °C.
Rev.2.41 Jan 10, 2006
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M16C/62P Group (M16C/62P, M16C/62PT)
Table 23.50
Recommended Operating Conditions (1) (1)
Symbol
VCC1, VCC2
AVCC
VSS
AVSS
VIH
VIL
IOH(peak)
Parameter
Supply Voltage (VCC1 = VCC2)
Analog Supply Voltage
Supply Voltage
Analog Supply Voltage
P3_1 to P3_7, P4_0 to P4_7, P5_0 to P5_7,
HIGH Input
P12_0 to P12_7, P13_0 to P13_7
Voltage (4)
LOW Input
Voltage (4)
HIGH Peak
Output Current
(4)
IOH(avg)
HIGH Average
Output Current
(4)
IOL(peak)
LOW Peak
Output Current
(4)
IOL(avg)
LOW Average
Output Current
(4)
f(XIN)
f(XCIN)
f(Ring)
f(PLL)
f(BCLK)
tSU(PLL)
23. Electrical Characteristics
Min.
4.0
Standard
Typ.
5.0
VCC1
0
0
Max.
5.5
Unit
0.8VCC2
VCC2
V
V
V
V
V
P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7, P3_0
(during single-chip mode)
0.8VCC2
VCC2
V
P6_0 to P6_7, P7_2 to P7_7, P8_0 to P8_7, P9_0 to P9_7,
P10_0 to P10_7, P11_0 to P11_7, P14_0, P14_1,
XIN, RESET, CNVSS, BYTE
0.8VCC1
VCC1
V
P7_0, P7_1
0.8VCC1
0
6.5
0.2VCC2
V
V
P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7, P3_0
(during single-chip mode)
0
0.2VCC2
V
P6_0 to P6_7, P7_0 to P7_7, P8_0 to P8_7, P9_0 to P9_7,
P10_0 to P10_7, P11_0 to P11_7, P14_0, P14_1,
XIN, RESET, CNVSS, BYTE
0
0.2VCC
V
P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7, P3_0 to P3_7,
P4_0 to P4_7, P5_0 to P5_7, P6_0 to P6_7, P7_2 to P7_7,
P8_0 to P8_4, P8_6, P8_7, P9_0 to P9_7, P10_0 to P10_7,
P11_0 to P11_7, P12_0 to P12_7, P13_0 to P13_7, P14_0, P14_1
−10.0
mA
P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7, P3_0 to P3_7,
P4_0 to P4_7, P5_0 to P5_7, P6_0 to P6_7, P7_2 to P7_7,
P8_0 to P8_4, P8_6, P8_7, P9_0 to P9_7, P10_0 to P10_7,
P11_0 to P11_7, P12_0 to P12_7, P13_0 to P13_7, P14_0, P14_1
−5.0
mA
P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7, P3_0 to P3_7,
P4_0 to P4_7, P5_0 to P5_7, P6_0 to P6_7, P7_0 to P7_7,
P8_0 to P8_4, P8_6, P8_7, P9_0 to P9_7, P10_0 to P10_7,
P11_0 to P11_7, P12_0 to P12_7, P13_0 to P13_7, P14_0, P14_1
10.0
mA
P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7, P3_0 to P3_7,
P4_0 to P4_7, P5_0 to P5_7, P6_0 to P6_7, P7_0 to P7_7,
P8_0 to P8_4, P8_6, P8_7, P9_0 to P9_7, P10_0 to P10_7,
P11_0 to P11_7, P12_0 to P12_7, P13_0 to P13_7, P14_0, P14_1
5.0
mA
16
50
2
24
24
20
MHz
kHz
MHz
MHz
MHz
ms
P3_1 to P3_7, P4_0 to P4_7, P5_0 to P5_7,
P12_0 to P12_7, P13_0 to P13_7
Main Clock Input Oscillation Frequency
Sub-Clock Oscillation Frequency
On-chip Oscillation Frequency
PLL Clock Oscillation Frequency
CPU Operation Clock
PLL Frequency Synthesizer Stabilization
Wait Time
VCC1=4.0V to 5.5V
VCC1=4.0V to 5.5V
VCC1=5.5V
0
0.5
10
0
32.768
1
NOTES:
1. Referenced to VCC1 = VCC2 = 4.7 to 5.5V at Topr = −40 to 85°C / −40 to 125°C unless otherwise specified.
T version = −40 to 85 °C, V version= −40 to 125 °C.
2. The Average Output Current is the mean value within 100ms.
3. The total IOL(peak) for ports P0, P1, P2, P8_6, P8_7, P9, P10 P1, P14_0 and P14_1 must be 80mA max. The total IOL(peak) for
ports P3, P4, P5, P6, P7, P8_0 to P8_4, P12, and P13 must be 80mA max. The total IOH(peak) for ports P0, P1, and P2 must
be −40mA max. The total IOH(peak) for ports P3, P4, P5, P12, and P13 must be −40mA max. The total IOH(peak) for ports P6,
P7, and P8_0 to P8_4 must be −40mA max. The total IOH(peak) for ports P8_6, P8_7, P9 , P10, P11, P14_0, and P14_1 must
be −40mA max.
As for 80-pin version, the total IOL(peak) for all ports and IOH(peak) must be 80mA. max. due to one VCC and one VSS.
4. There is no external connections for port P1_0 to P1_7, P4_4 to P4_7, P7_2 to P7_5 and P9_1 in 80-pin version.
Rev.2.41 Jan 10, 2006
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M16C/62P Group (M16C/62P, M16C/62PT)
Table 23.51
A/D Conversion Characteristics (1)
Symbol
−
INL
−
Parameter
Resolution
Integral Non-Linearity
Error
Absolute Accuracy
−
DNL
−
−
RLADDER
tCONV
tCONV
tSAMP
VREF
VIA
23. Electrical Characteristics
10bit
8bit
10bit
8bit
Tolerance Level Impedance
Differential Non-Linearity Error
Offset Error
Gain Error
Ladder Resistance
10-bit Conversion Time, Sample & Hold
Function Available
8-bit Conversion Time, Sample & Hold
Function Available
Sampling Time
Reference Voltage
Analog Input Voltage
Measuring Condition
Min.
VREF=VCC1
VREF= AN0 to AN7 input,
VCC1= AN0_0 to AN0_7 input,
AN2_0 to AN2_7 input,
5V
ANEX0, ANEX1 input
External operation amp
connection mode
VREF=VCC1=5V
VREF= AN0 to AN7 input,
VCC1= AN0_0 to AN0_7 input,
AN2_0 to AN2_7 input,
5V
ANEX0, ANEX1 input
External operation amp
connection mode
VREF=VCC1=5V
Standard
Typ.
Max.
10
±3
10
2.75
VREF=VCC1=5V, φAD=12MHz
2.33
Bits
LSB
±7
LSB
±2
±3
LSB
LSB
±7
LSB
±2
LSB
kΩ
LSB
LSB
LSB
kΩ
µs
3
VREF=VCC1
VREF=VCC1=5V, φAD=12MHz
Unit
±1
±3
±3
40
µs
0.25
2.0
0
VCC1
VREF
µs
V
V
NOTES:
1. Referenced to VCC1=AVCC=VREF=4.0 to 5.5V, VSS=AVSS=0V at Topr = −40 to 85°C / −40 to 125°C unless otherwise specified.
T version = −40 to 85°C, V version =−40 to 125°C
2. φAD frequency must be 12 MHz or less.
3. When sample & hold is disabled, φAD frequency must be 250 kHz or more, in addition to the limitation in Note 2.
When sample & hold is enabled, φAD frequency must be 1MHz or more, in addition to the limitation in Note 2.
Table 23.52
D/A Conversion Characteristics (1)
Symbol
−
−
tSU
RO
IVREF
Parameter
Resolution
Absolute Accuracy
Setup Time
Output Resistance
Reference Power Supply Input Current
Measuring Condition
Min.
4
(NOTE 2)
Standard
Typ.
10
Max.
8
1.0
3
20
1.5
Unit
Bits
%
µs
kΩ
mA
NOTES:
1. Referenced to VCC1=VREF=4.0 to 5.5V, VSS=AVSS=0V at Topr = −40 to 85°C / −40 to 125°C unless otherwise specified. T
version = −40 to 85°C, V version =−40 to 125°C
2. This applies when using one D/A converter, with the D/A register for the unused D/A converter set to “00h”. The resistor
ladder of the A/D converter is not included. Also, when D/A register contents are not “00h”, the IVREF will flow even if Vref id
disconnected by the A/D control register.
Rev.2.41 Jan 10, 2006
REJ09B0185-0241
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M16C/62P Group (M16C/62P, M16C/62PT)
Table 23.53
23. Electrical Characteristics
Flash Memory Version Electrical Characteristics (1) for 100 cycle products (B, U)
Symbol
Parameter
−
−
−
−
−
−
−
−
tPS
−
Program and Erase Endurance (3)
Word Program Time (VCC1=5.0V)
Lock Bit Program Time
Block Erase Time
(VCC1=5.0V)
Min.
100
4-Kbyte block
8-Kbyte block
32-Kbyte block
64-Kbyte block
Erase All Unlocked Blocks Time (2)
Flash Memory Circuit Stabilization Wait Time
Data Hold Time (5)
Table 23.54
4
200
200
4
4
4
4
4×n
15
20
Parameter
Program and Erase Endurance (3, 8, 9)
Word Program Time (VCC1=5.0V)
Lock Bit Program Time
Block Erase Time
(VCC1=5.0V)
Flash Memory Circuit Stabilization Wait Time
Data Hold Time (5)
tPS
−
25
25
0.3
0.3
0.5
0.8
Max.
Unit
cycle
µs
µs
s
s
s
s
s
µs
year
Flash Memory Version Electrical Characteristics (6) for 10,000 cycle products (B7, U7)
(Block A and Block 1 (7))
Symbol
−
−
−
−
Standard
Typ.
Min.
10,000 (4)
4-Kbyte block
Standard
Typ.
4
Max.
cycle
µs
µs
s
25
25
0.3
15
20
Unit
µs
year
NOTES:
1. Referenced to VCC1=4.5 to 5.5V at Topr = 0 to 60 °C unless otherwise specified.
2. n denotes the number of block erases.
3. Program and Erase Endurance refers to the number of times a block erase can be performed.
If the program and erase endurance is n (n=100, 1,000, or 10,000), each block can be erased n times.
For example, if a 4 Kbytes block A is erased after writing 1 word data 2,048 times, each to a different address, this counts as
one program and erase endurance. Data cannot be written to the same address more than once without erasing the block.
(Rewrite prohibited)
4. Maximum number of E/W cycles for which operation is guaranteed.
5. Ta (ambient temperature)=55 °C. As to the data hold time except Ta=55 °C, please contact Renesas Technology Corp. or an
authorized Renesas Technology Corp. product distributor.
6. Referenced to VCC1 = 4.5 to 5.5V at Topr = −40 to 85 °C (B7, U7 (T version)) / −40 to 125 °C (B7, U7 (V version)) unless
otherwise specified.
7. Table 23.54 applies for block A or block 1 program and erase endurance > 1,000. Otherwise, use Table 23.53.
8. To reduce the number of program and erase endurance when working with systems requiring numerous rewrites, write to
unused word addresses within the block instead of rewrite. Erase block only after all possible addresses are used. For
example, an 8-word program can be written 256 times maximum before erase becomes necessary.
Maintaining an equal number of erasure between block A and block 1 will also improve efficiency. It is important to track the
total number of times erasure is used.
9. Should erase error occur during block erase, attempt to execute clear status register command, then block erase command
at least three times until erase error disappears.
10. Set the PM17 bit in the PM1 register to “1” (wait state) when executing more than 100 times rewrites (B7 and U7).
11. Customers desiring E/W failure rate information should contact their Renesas technical support representative.
Table 23.55
Flash Memory Version Program/Erase Voltage and Read Operation Voltage
Characteristics (at Topr = 0 to 60 °C(B, U), Topr = −40 to 85 °C (B7, U7 (T version)) / −40
to 125 °C (B7, U7 (V version))
Flash Program, Erase Voltage
VCC1 = 5.0 V ± 0.5 V
Rev.2.41 Jan 10, 2006
REJ09B0185-0241
Page 349 of 390
Flash Read Operation Voltage
VCC1=4.0 to 5.5 V
M16C/62P Group (M16C/62P, M16C/62PT)
Table 23.56
Power Supply Circuit Timing Characteristics
Symbol
td(P-R)
td(R-S)
td(W-S)
23. Electrical Characteristics
Parameter
Measuring Condition
Time for Internal Power Supply Stabilization
During Powering-On
STOP Release Time
Low Power Dissipation Mode Wait Mode
Release Time
Standard
Typ.
VCC1=4.0V to 5.5V
Time for Internal Power
Supply Stabilization During
Powering-On
VCC1
td(P-R)
CPU clock
Interrupt for
(a) Stop mode release
or
(b)Wait mode release
td(R-S)
STOP Release Time
td(W-S)
Low Power Dissipation
Mode Wait Mode Release
Time
CPU clock
(a)
(b)
Power Supply Circuit Timing Diagram
Rev.2.41 Jan 10, 2006
REJ09B0185-0241
Page 350 of 390
Max.
2
150
150
Recommended
operation voltage
td(P-R)
Figure 23.22
Min.
td(R-S)
td(W-S)
Unit
ms
µs
µs
M16C/62P Group (M16C/62P, M16C/62PT)
23. Electrical Characteristics
VCC1=VCC2=5V
Table 23.57
Electrical Characteristics (1)
Symbol
VOH
VOH
(1)
Parameter
HIGH
Output
Voltage (2)
HIGH
Output
Voltage (2)
Measuring Condition
P6_0 to P6_7, P7_2 to P7_7, P8_0 to P8_4,
P8_6, P8_7, P9_0 to P9_7, P10_0 to P10_7,
P11_0 to P11_7, P14_0, P14_1
IOH=−5mA
P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7,
P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7,
P12_0 to P12_7, P13_0 to P13_7
IOH=−5mA
P6_0 to P6_7, P7_2 to P7_7, P8_0 to P8_4,
P8_6, P8_7, P9_0 to P9_7, P10_0 to P10_7,
P11_0 to P11_7, P14_0, P14_1
P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7,
P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7,
P12_0 to P12_7, P13_0 to P13_7
VOH
HIGH Output Voltage
XOUT
HIGH Output Voltage
VOL
VOL
VOL
LOW
Output
Voltage (2)
LOW
Output
Voltage (2)
XCOUT
HIGHPOWER
IOH=−1mA
LOWPOWER
IOH=−0.5mA
HIGHPOWER
With no load applied
LOWPOWER
With no load applied
IOL=5mA
P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7,
P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7,
P12_0 to P12_7, P13_0 to P13_7
IOL=5mA
P6_0 to P6_7, P7_0 to P7_7, P8_0 to P8_4,
P8_6, P8_7, P9_0 to P9_7, P10_0 to P10_7,
P11_0 to P11_7, P14_0, P14_1
IOL=200µA
P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7,
P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7,
P12_0 to P12_7, P13_0 to P13_7
IOL=200µA
LOW Output Voltage
Hysteresis
IOH=−200µA
P6_0 to P6_7, P7_0 to P7_7, P8_0 to P8_4,
P8_6, P8_7, P9_0 to P9_7, P10_0 to P10_7,
P11_0 to P11_7, P14_0, P14_1
XOUT
LOW Output Voltage
VT+-VT-
OH=−200µA
XCOUT
HIGHPOWER
IOL=1mA
LOWPOWER
IOL=0.5mA
HIGHPOWER
With no load applied
LOWPOWER
With no load applied
HOLD, RDY, TA0IN to TA4IN, TB0IN to TB5IN,
INT0 to INT5, NMI, ADTRG, CTS0 to CTS2, CLK0 to CLK4,
TA0OUT to TA4OUT, KI0 to KI3, RXD0 to RXD2,
SCL0 to SCL2, SDA0 to SDA2, SIN3, SIN4
RESET
P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7, P3_0 to P3_7,
P4_0 to P4_7, P5_0 to P5_7, P6_0 to P6_7, P7_0 to P7_7,
P8_0 to P8_7, P9_0 to P9_7, P10_0 to P10_7,
P11_0 to P11_7, P12_0 to P12_7, P13_0 to P13_7,
P14_0, P14_1, XIN, RESET, CNVSS, BYTE
VI=5V
P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7, P3_0 to P3_7,
P4_0 to P4_7, P5_0 to P5_7, P6_0 to P6_7, P7_0 to P7_7,
P8_0 to P8_7, P9_0 to P9_7, P10_0 to P10_7,
P11_0 to P11_7,P12_0 to P12_7, P13_0 to P13_7,
P14_0, P14_1, XIN, RESET, CNVSS, BYTE
VI=0V
P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7, P3_0 to P3_7,
P4_0 to P4_7, P5_0 to P5_7, P6_0 to P6_7, P7_2 to P7_7,
P8_0 to P8_4, P8_6, P8_7, P9_0 to P9_7, P10_0 to P10_7,
P11_0 to P11_7,P12_0 to P12_7, P13_0 to P13_7,
P14_0, P14_1
VI=0V
(2)
RfXIN
RfXCIN
VRAM
VCC1
VCC2−2.0
VCC2
VCC1−0.3
VCC1
V
V
VCC2−0.3
VCC2
VCC1−2.0
VCC1−2.0
VCC1
VCC1
2.5
1.6
V
V
V
2.0
2.0
V
0.2
1.0
V
0.2
2.5
V
5.0
µA
−5.0
µA
170
kΩ
30
50
1.5
15
Feedback Resistance XCIN
At stop mode
V
0
0
Feedback Resistance XIN
RAM Retention Voltage
V
0.45
HIGH Input
Current (2)
Resistance
VCC1−2.0
Unit
0.45
IIH
RPULLUP Pull-Up
Max.
2.0
Hysteresis
LOW Input
Current (2)
Standard
Typ.
2.0
VT+-VT-
IIL
Min.
2.0
MΩ
MΩ
V
NOTES:
1. Referenced to VCC1=VCC2=4.0 to 5.5V, VSS = 0V at Topr = −40 to 85°C / −40 to 125°C, f(BCLK)=24MHz unless otherwise
specified. T version = −40 to 85°C, V version =−40 to 125°C.
2. There is no external connections for port P1_0 to P1_7, P4_4 to P4_7, P7_2 to P7_5 and P9_1 in 80-pin version.
Rev.2.41 Jan 10, 2006
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M16C/62P Group (M16C/62P, M16C/62PT)
Table 23.58
Electrical Characteristics (2) (1)
Symbol
ICC
23. Electrical Characteristics
Parameter
In single-chip
Power Supply Current
(VCC1=VCC2=4.0V to 5.5V) mode, the output
pins are open and
other pins are VSS
Measuring Condition
Mask ROM
f(BCLK)=24MHz
No division, PLL operation
No division,
On-chip oscillation
Flash
Memory
Flash Memory
Program
Flash Memory
Erase
Mask ROM
Flash Memory
Standard
Typ. Max.
14
20
1
Unit
mA
mA
f(BCLK)=24MHz,
No division, PLL operation
18
No division,
On-chip oscillation
1.8
mA
f(BCLK)=10MHz,
VCC1=5.0V
15
mA
f(BCLK)=10MHz,
VCC1=5.0V
25
mA
f(XCIN)=32kHz
Low power dissipation
mode, ROM (3)
25
µA
f(BCLK)=32kHz
Low power dissipation
mode, RAM (3)
25
µA
420
µA
On-chip oscillation,
Wait mode
50
µA
f(BCLK)=32kHz
Wait mode (2),
Oscillation capability High
7.5
µA
f(BCLK)=32kHz
Wait mode (2),
Oscillation capability Low
2.0
µA
Stop mode
Topr =25°C
2.0
f(BCLK)=32kHz
Low power dissipation
mode, Flash Memory (3)
Mask ROM
Flash Memory
Min.
27
mA
6.0
µA
Stop mode
Topr =85°C
20
µA
Stop mode
Topr =125°C
TBD
µA
NOTES:
1. Referenced to VCC1=VCC2=4.0 to 5.5V, VSS = 0V at Topr = −40 to 85°C / −40 to 125°C, f(BCLK)=24MHz unless otherwise
specified. T version = −40 to 85°C, V version =−40 to 125°C.
2. With one timer operated using fC32.
3. This indicates the memory in which the program to be executed exists.
Rev.2.41 Jan 10, 2006
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M16C/62P Group (M16C/62P, M16C/62PT)
23. Electrical Characteristics
VCC1=VCC2=5V
Timing Requirements
(VCC1 = VCC2 = 5V, VSS = 0V, at Topr = −40 to 85°C (T version) / −40 to 125°C (V version) unless otherwise
specified)
Table 23.59
External Clock Input (XIN input)
Symbol
tc
tw(H)
tw(L)
tr
tf
Parameter
External Clock Input Cycle Time
External Clock Input HIGH Pulse Width
External Clock Input LOW Pulse Width
External Clock Rise Time
External Clock Fall Time
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Standard
Min.
62.5
25
25
Max.
15
15
Unit
ns
ns
ns
ns
ns
M16C/62P Group (M16C/62P, M16C/62PT)
23. Electrical Characteristics
VCC1=VCC2=5V
Timing Requirements
(VCC1 = VCC2 = 5V, VSS = 0V, at Topr = −40 to 85°C (T version) / −40 to 125°C (V version) unless otherwise
specified)
Table 23.60
Timer A Input (Counter Input in Event Counter Mode)
Symbol
tc(TA)
tw(TAH)
tw(TAL)
Table 23.61
Parameter
TAiIN Input Cycle Time
TAiIN Input HIGH Pulse Width
TAiIN Input LOW Pulse Width
Table 23.62
Parameter
TAiIN Input Cycle Time
TAiIN Input HIGH Pulse Width
TAiIN Input LOW Pulse Width
Table 23.63
Parameter
TAiIN Input Cycle Time
TAiIN Input HIGH Pulse Width
TAiIN Input LOW Pulse Width
Table 23.64
Parameter
TAiIN Input HIGH Pulse Width
TAiIN Input LOW Pulse Width
Table 23.65
Parameter
TAiOUT Input Cycle Time
TAiOUT Input HIGH Pulse Width
TAiOUT Input LOW Pulse Width
TAiOUT Input Setup Time
TAiOUT Input Hold Time
Max.
Unit
ns
ns
ns
Standard
Min.
200
100
100
Max.
Unit
ns
ns
ns
Standard
Min.
100
100
Max.
Unit
ns
ns
Standard
Min.
Max.
2000
1000
1000
400
400
Unit
ns
ns
ns
ns
ns
Timer A Input (Two-phase Pulse Input in Event Counter Mode)
Symbol
tc(TA)
tsu(TAIN-TAOUT)
tsu(TAOUT-TAIN)
Standard
Min.
400
200
200
Timer A Input (Counter Increment/Decrement Input in Event Counter Mode)
Symbol
tc(UP)
tw(UPH)
tw(UPL)
tsu(UP-TIN)
th(TIN-UP)
ns
ns
ns
Timer A Input (External Trigger Input in Pulse Width Modulation Mode)
Symbol
tw(TAH)
tw(TAL)
Unit
Timer A Input (External Trigger Input in One-shot Timer Mode)
Symbol
tc(TA)
tw(TAH)
tw(TAL)
Max.
Timer A Input (Gating Input in Timer Mode)
Symbol
tc(TA)
tw(TAH)
tw(TAL)
Standard
Min.
100
40
40
Parameter
TAiIN Input Cycle Time
TAiOUT Input Setup Time
TAiIN Input Setup Time
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Standard
Min.
800
200
200
Max.
Unit
ns
ns
ns
M16C/62P Group (M16C/62P, M16C/62PT)
23. Electrical Characteristics
VCC1=VCC2=5V
Timing Requirements
(VCC1 = VCC2 = 5V, VSS = 0V, at Topr = −40 to 85°C (T version) / −40 to 125°C (V version) unless otherwise
specified)
Table 23.66
Timer B Input (Counter Input in Event Counter Mode)
Symbol
tc(TB)
tw(TBH)
tw(TBL)
tc(TB)
tw(TBH)
tw(TBL)
Table 23.67
Parameter
TBiIN Input Cycle Time (counted on one edge)
TBiIN Input HIGH Pulse Width (counted on one edge)
TBiIN Input LOW Pulse Width (counted on one edge)
TBiIN Input Cycle Time (counted on both edges)
TBiIN Input HIGH Pulse Width (counted on both edges)
TBiIN Input LOW Pulse Width (counted on both edges)
Table 23.68
Parameter
TBiIN Input Cycle Time
TBiIN Input HIGH Pulse Width
TBiIN Input LOW Pulse Width
Table 23.69
Parameter
TBiIN Input Cycle Time
TBiIN Input HIGH Pulse Width
TBiIN Input LOW Pulse Width
Standard
Min.
400
200
200
Parameter
tw(ADL)
ADTRG input LOW Pulse Width
125
Unit
ns
ns
ns
Max.
Unit
ns
ns
Serial Interface
Symbol
Parameter
CLKi Input Cycle Time
CLKi Input HIGH Pulse Width
CLKi Input LOW Pulse Width
TXDi Output Delay Time
TXDi Hold Time
RXDi Input Setup Time
RXDi Input Hold Time
Standard
Min.
200
100
100
Max.
80
0
70
90
Unit
ns
ns
ns
ns
ns
ns
ns
External Interrupt INTi Input
Symbol
tw(INL)
Max.
Standard
ADTRG Input Cycle Time
tw(INH)
Unit
ns
ns
ns
Standard
tc(AD)
Table 23.71
Max.
Min.
400
200
200
Min.
1000
tc(CK)
tw(CKH)
tw(CKL)
td(C-Q)
th(C-Q)
tsu(D-C)
th(C-D)
ns
ns
ns
ns
ns
ns
A/D Trigger Input
Symbol
Table 23.70
Unit
Timer B Input (Pulse Width Measurement Mode)
Symbol
tc(TB)
tw(TBH)
tw(TBL)
Max.
Timer B Input (Pulse Period Measurement Mode)
Symbol
tc(TB)
tw(TBH)
tw(TBL)
Standard
Min.
100
40
40
200
80
80
Parameter
Standard
INTi Input HIGH Pulse Width
Min.
250
INTi Input LOW Pulse Width
250
Rev.2.41 Jan 10, 2006
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Max.
Unit
ns
ns
M16C/62P Group (M16C/62P, M16C/62PT)
23. Electrical Characteristics
VCC1=VCC2=5V
Switching Characteristics
(VCC1 = VCC2 = 5V, VSS = 0V, at Topr = −40 to 85°C (T version) / −40 to 125°C (V version) unless otherwise
specified)
P0
P1
P2
P3
P4
P5
P6
P7
P8
P9
P10
Figure 23.23
Ports P0 to P10 Measurement Circuit
Rev.2.41 Jan 10, 2006
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30pF
M16C/62P Group (M16C/62P, M16C/62PT)
23. Electrical Characteristics
VCC1=VCC2=5V
XIN input
tw(H)
tr
tf
tw(L)
tc
tc(TA)
tw(TAH)
TAiIN input
tw(TAL)
tc(UP)
tw(UPH)
TAiOUT input
tw(UPL)
TAiOUT input
(Up/down input)
During event counter mode
TAiIN input
(When count on falling
edge is selected)
TAiIN input
(When count on rising
edge is selected)
th(TIN-UP) tsu(UP-TIN)
Two-phase pulse input in
event counter mode
tc(TA)
TAiIN input
tsu(TAIN-TAOUT)
tsu(TAIN-TAOUT)
tsu(TAOUT-TAIN)
TAiOUT input
tsu(TAOUT-TAIN)
tc(TB)
tw(TBH)
TBiIN input
tw(TBL)
tc(AD)
tw(ADL)
ADTRG input
Figure 23.24
Timing Diagram (1)
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M16C/62P Group (M16C/62P, M16C/62PT)
23. Electrical Characteristics
VCC1=VCC2=5V
tc(CK)
tw(CKH)
CLKi
tw(CKL)
th(C-Q)
TXDi
tsu(D-C)
td(C-Q)
RXDi
tw(INL)
INTi input
tw(INH)
Figure 23.25
Timing Diagram (2)
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th(C-D)
M16C/62P Group (M16C/62P, M16C/62PT)
24. Precautions
24. Precautions
24.1
SFR
24.1.1
Register Settings
Table Table 24.1 Registers with Write-only Bits which can only be written to. Set these registers with
immediate values. When establishing the next value by altering the present value, write the present value to the
RAM as well as to the register. Transfer the next value to the register after making changes in the RAM.
Table 24.1
Registers with Write-only Bits
Register
Watchdog timer start register
Timer A1-1 register
Timer A2-1 register
Timer A4-1 register
Short-circuit preventionTimer
Timer B2 Interrupt Generating Frequency Set Counter
SI/03 bit rate register
SI/04 bit rateregister
UART0 bit rateregister
UART1 bit rateregister
UART2 bit rate register
UART0 Transmit buffer register
UART1 Transmit buffer register
UART2 Transmit buffer register
Ups and downs flag
Timer 0 register
Timer 1 register
Timer 2 register
Timer 3 register
Timer 4 register
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Page 359 of 390
Symbol
WDC
TA11
TA21
TA41
DTT
ICTB2
S3BRG
S4BRG
U0BRG
U1BRG
U2BRG
U0TB
U1TB
U2TB
UDF
TA0
TA1
TA2
TA3
TA4
Address
000E
0343 to 0342
0345 to 0344
0347 to 0346
034C
034D
0363
0367
03A1
03A9
0379
03A3 to 03A2
03AB to 03AA
037B to 037A
0384
0387 to 0386
0389 to 0388
038B to 038A
038D to 038C
038F to 038E
M16C/62P Group (M16C/62P, M16C/62PT)
24.2
24. Precautions
Reset
When supplying power to the microcomputer, the power supply voltage applied to the VCC1 pin must meet the
conditions of SVCC.
Symbol
Parameter
SVCC
Power supply rising gradient (VCC1)(Voltage range 0 to 2.0)
Min.
0.05
Standard
Typ.
Max.
V/ms
Voltage
SVCC
Power supply rising
gradient (VCC1)
2.0V
SVCC
0V
Figure 24.1
Timing of SVCC
Rev.2.41 Jan 10, 2006
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Unit
Time
M16C/62P Group (M16C/62P, M16C/62PT)
24.3
24. Precautions
Bus
• The ROMless version can operate only in the microprocessor mode, connect the CNVSS pin to VCC1.
• When resetting CNVSS pin with “H” input, contents of internal ROM cannot be read out.
Rev.2.41 Jan 10, 2006
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M16C/62P Group (M16C/62P, M16C/62PT)
24.4
24. Precautions
PLL Frequency Synthesizer
Stabilize supply voltage so that the standard of the power supply ripple is met.
Symbol
f(ripple)
VP-P(ripple)
VCC(|∆V /∆T|)
Parameter
Min.
Power supply ripple allowable frequency (VCC1)
Power supply ripple allowable
(VCC1=5V)
amplitude voltage
(VCC1=3V)
Power supply ripple rising / falling
(VCC1=5V)
gradient
(VCC1=3V)
f(ripple)
Standard
Typ.
Max.
10
0.5
0.3
0.3
0.3
Unit
kHz
V
V
V/ms
V/ms
f(ripple)
Power supply ripple allowable frequency
(VCC1)
Vp-p(ripple)
Power supply ripple allowable
amplitude voltage
Figure 24.2
VCC1
Timing of Voltage Fluctuation
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Vp-p(ripple)
M16C/62P Group (M16C/62P, M16C/62PT)
24.5
24. Precautions
Power Control
• When exiting stop mode by hardware reset, set RESET pin to “L” until a main clock oscillation is stabilized.
• Set the MR0 bit in the TAiMR register (i=0 to 4) to “0” (pulse is not output) to use the timer A to exit stop
mode.
• When entering wait mode, insert a JMP.B instruction before a WAIT instruction. Do not execute any
instructions which can generate a write to RAM between the JMP.B and WAIT instructions. Disable the DMA
transfers, if a DMA transfer may occur between the JMP.B and WAIT instructions. After the WAIT instruction,
insert at least 4 NOP instructions. When entering wait mode, the instruction queue roadstead the instructions
following WAIT, and depending on timing, some of these may execute before the microcomputer enters wait
mode.
Program example when entering wait mode
Program Example:
JMP.B
L1
; Insert JMP.B instruction before WAIT instruction
L1:
FSET
I
;
WAIT
; Enter wait mode
NOP
; More than 4 NOP instructions
NOP
NOP
NOP
• When entering stop mode, insert a JMP.B instruction immediately after executing an instruction which sets
the CM10 bit in the CM1 register to “1”, and then insert at least 4 NOP instructions. When entering stop
mode, the instruction queue reads ahead the instructions following the instruction which sets the CM10 bit
to “1” (all clock stops), and, some of these may execute before the microcomputer enters stop mode or
before the interrupt routine for returning from stop mode.
Program example when entering stop mode
Program Example:
FSET
BSET
JMP.B
I
CM10
L2
; Enter stop mode
; Insert JMP.B instruction
L2:
NOP
NOP
NOP
NOP
; More than 4 NOP instructions
• Wait until the main clock oscillation stabilizes, before switching the clock source for CPU clock to the main
clock.
Similarly, wait until the sub clock oscillates stably before switching the clock source for CPU clock to the sub
clock.
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M16C/62P Group (M16C/62P, M16C/62PT)
24. Precautions
• Suggestions to reduce power consumption
Ports
The processor retains the state of each I/O port even when it goes to wait mode or to stop mode. A current
flows in active I/O ports. A pass current flows in input ports that high-impedance state. When entering wait
mode or stop mode, set non-used ports to input and stabilize the potential.
A/D converter
When A/D conversion is not performed, set the VCUT bit of ADiCON1 register to “0” (no VREF
connection).
When A/D conversion is performed, start the A/D conversion at least 1 µs or longer after setting the VCUT bit
to “1” (VREF connection).
D/A converter
When not performing D/A conversion, set the DAiE bit (i=0, 1) of DACON register to “0” (input inhibited)
and DAi register to “00h”.
Stopping peripheral functions
Use the CM0 register CM02 bit to stop the unnecessary peripheral functions during wait mode.
However, because the peripheral function clock (fC32) generated from the sub-clock does not stop, this
measure is not conducive to reducing the power consumption of the chip. If low speed mode or low power
dissipation mode is to be changed to wait mode, set the CM02 bit to “0” (do not peripheral function clock
stopped when in wait mode), before changing wait mode.
Switching the oscillation-driving capacity
Set the driving capacity to “LOW” when oscillation is stable.
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M16C/62P Group (M16C/62P, M16C/62PT)
24.6
24. Precautions
Protect
Set the PRC2 bit to “1” (write enabled) and then write to any address, and the PRC2 bit will be cleared to “0” (write
protected). The registers protected by the PRC2 bit should be changed in the next instruction after setting the PRC2
bit to “1”. Make sure no interrupts or DMA transfers will occur between the instruction in which the PRC2 bit is set
to “1” and the next instruction.
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M16C/62P Group (M16C/62P, M16C/62PT)
24.7
24. Precautions
Interrupt
24.7.1
Reading address 00000h
Do not read the address 00000h in a program. When a maskable interrupt request is accepted, the CPU reads
interrupt information (interrupt number and interrupt request priority level) from the address 00000h during the
interrupt sequence. At this time, the IR bit for the accepted interrupt is cleared to “0”.
If the address 00000h is read in a program, the IR bit for the interrupt which has the highest priority among the
enabled interrupts is cleared to “0”. This factors a problem that the interrupt is canceled, or an unexpected
interrupt request is generated.
24.7.2
Setting the SP
Set any value in the SP(USP, ISP) before accepting an interrupt. The SP(USP, ISP) is cleared to “0000h” after
reset. Therefore, if an interrupt is accepted before setting any value in the SP(USP, ISP), the program may go
out of control.
Especially when using NMI interrupt, set a value in the ISP at the beginning of the program. For the first and
only the first instruction after reset, all interrupts including NMI interrupt are disabled.
24.7.3
The NMI Interrupt
• The NMI interrupt cannot be disabled. If this interrupt is unused, connect the NMI pin to VCC1 via a
resistor (pull-up).
• The input level of the NMI pin can be read by accessing the P8_5 bit in the P8 register. Note that the P8_5
bit can only be read when determining the pin level in NMI interrupt routine.
• Stop mode cannot be entered into while input on the NMI pin is low. This is because while input on the
NMI pin is low the CM10 bit in the CM1 register is fixed to “0”.
• Do not go to wait mode while input on the NMI pin is low. This is because when input on the NMI pin goes
low, the CPU stops but CPU clock remains active; therefore, the current consumption in the chip does not
drop. In this case, normal condition is restored by an interrupt generated thereafter.
• The low and high level durations of the input signal to the NMI pin must each be 2 CPU clock cycles + 300
ns or more.
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M16C/62P Group (M16C/62P, M16C/62PT)
24.7.4
24. Precautions
Changing the Interrupt Generate Factor
If the interrupt generate factor is changed, the IR bit in the interrupt control register for the changed interrupt
may inadvertently be set to “1” (interrupt requested). If you changed the interrupt generate factor for an
interrupt that needs to be used, be sure to clear the IR bit for that interrupt to “0” (interrupt not requested).
Changing the interrupt generate factor refered to here means any act of changing the source, polarity or timing
of the interrupt assigned to each software interrupt number. Therefore, if a mode change of any peripheral
function involves changing the generate factor, polarity or timing of an interrupt, be sure to clear the IR bit for
that interrupt to “0” (interrupt not requested) after making such changes. Refer to the description of each
peripheral function for details about the interrupts from peripheral functions.
Figure 24.3 shows the Procedure for Changing the Interrupt Generate Factor.
Changing the interrupt source
Disable interrupts (2, 3)
Change the interrupt generate factor (including a mode change of peripheral function)
Use the MOV instruction to clear the IR bit to “0” (interrupt not requested) (3)
Enable interrupts (2, 3)
End of change
IR bit: A bit in the interrupt control register for the interrupt whose interrupt generate factor is
to be changed
NOTES :
1. The above settings must be executed individually. Do not execute two or more settings
simultaneously (using one instruction).
2. Use the I flag for the INTi interrupt (i = 0 to 5).
For the interrupts from peripheral functions other than the INTi interrupt, turn off the
peripheral function that is the source of the interrupt in order not to generate an
interrupt request before changing the interrupt generate factor. In this case, if the
maskable interrupts can all be disabled without causing a problem, use the I flag.
Otherwise, use the corresponding ILVL2 to ILVL0 bit for the interrupt whose interrupt
generate factor is to be changed.
3. Refer to 18.4.6 Rewrite the Interrupt Control Register for details about the
instructions to use and the notes to be taken for instruction execution.
Figure 24.3
24.7.5
Procedure for Changing the Interrupt Generate Factor
INT Interrupt
• Either an “L” level of at least tW(INH) or an “H” level of at least tW(INL) width is necessary for the signal
input to pins INT0 through INT5 regardless of the CPU operation clock.
• If the POL bit in the INT0IC to INT5IC registers or the IFSR7 to IFSR0 bits in the IFSR register are
changed, the IR bit may inadvertently set to “1” (interrupt requested). Be sure to clear the IR bit to “0”
interrupt not requested) after changing any of those register bits.
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24.7.6
24. Precautions
Rewrite the Interrupt Control Register
(a) The interrupt control register for any interrupt should be modified in places where no requests for that
interrupt may occur. Otherwise, disable the interrupt before rewriting the interrupt control register.
(b) To rewrite the interrupt control register for any interrupt after disabling that interrupt, be careful with the
instruction to be used.
• Changing any bit other than the IR bit
• Changing the IR bit
Depending on the instruction used, the IR bit may not always be cleared to “0” (interrupt not requested).
Therefore, be sure to use the MOV instruction to clear the IR bit.
(c) When using the I flag to disable an interrupt, refer to the sample program fragments shown below as you set
the I flag. (Refer to (b) for details about rewrite the interrupt control registers in the sample program
fragments.)
Examples 1 through 3 show how to prevent the I flag from being set to “1” (interrupts enabled) before the
interrupt control register is rewrited, owing to the effects of the internal bus and the instruction queue buffer.
Example 1:Using the NOP instruction to keep the program waiting until the interrupt control
register is modified
INT_SWITCH1:
FCLR
I
; Disable interrupts.
AND.B
#00h, 0055h
; Set the TA0IC register to “00h”.
NOP
;
NOP
FSET
I
; Enable interrupts.
The number of NOP instruction is as follows.
PM20=1(1 wait) : 2, PM20=0(2 wait) : 3, when using HOLD function : 4.
Example 2:Using the dummy read to keep the FSET instruction waiting
INT_SWITCH2:
FCLR
I
; Disable interrupts.
AND.B
#00h, 0055h
; Set the TA0IC register to “00h”.
MOV.W MEM, R0
; Dummy read.
FSET
I
; Enable interrupts.
Example 3:Using the POPC instruction to changing the I flag
INT_SWITCH3:
PUSHC FLG
FCLR
I
; Disable interrupts.
AND.B
#00h, 0055h
; Set the TA0IC register to “00h”.
POPC
FLG
; Enable interrupts.
24.7.7
Watchdog Timer Interrupt
Initialize the watchdog timer after the watchdog timer interrupt occurs.
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24.8
24. Precautions
DMAC
24.8.1
Write to DMAE Bit in DMiCON Register
When both of the conditions below are met, follow the steps below.
Conditions
• The DMAE bit is set to “1” again while it remains set (DMAi is in an active state).
• A DMA request may occur simultaneously when the DMAE bit is being written.
Steps
(1) Write “1” to the DMAE bit and DMAS bit in the DMiCON register simultaneously(1).
(2) Make sure that the DMAi is in an initial state(2) in a program.
If the DMAi is not in an initial state, the above steps should be repeated.
NOTES:
1.The DMAS bit remains unchanged even if “1” is written. However, if “0” is written to this bit, it is set to “0”
(DMA not requested). In order to prevent the DMAS bit from being modified to “0”, “1” should be written
to the DMAS bit when “1” is written to the DMAE bit. In this way the state of the DMAS bit immediately
before being written can be maintained.
Similarly, when writing to the DMAE bit with a read-modify-write instruction, “1” should be written to the
DMAS bit in order to maintain a DMA request which is generated during execution.
2.Read the TCRi register to verify whether the DMAi is in an initial state. If the read value is equal to a value
which was written to the TCRi register before DMA transfer start, the DMAi is in an initial state. (If a
DMA request occurs after writing to the DMAE bit, the value written to the TCRi register is “1”.) If the
read value is a value in the middle of transfer, the DMAi is not in an initial state.
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24.9
24. Precautions
Timers
24.9.1
Timer A
24.9.1.1
Timer A (Timer Mode)
The timer remains idle after reset. Set the mode, count source, counter value, etc. using the TAiMR (i = 0 to 4)
register and the TAi register before setting the TAiS bit in the TABSR register to “1” (count starts).
Always make sure the TAiMR register is modified while the TAiS bit remains “0” (count stops) regardless
whether after reset or not.
While counting is in progress, the counter value can be read out at any time by reading the TAi register.
However, if the counter is read at the same time it is reloaded, the value “FFFFh” is read.
Also, if the counter is read before it starts counting after a value is set in the TAi register while not counting, the
set value is read.
If a low-level signal is applied to the NMI pin when the IVPCR1 bit in the TB2SC register = 1 (three-phase
output forcible cutoff by input on NMI pin enabled), the TA1OUT, TA2OUT and TA4OUT pins go to a highimpedance state.
24.9.1.2
Timer A (Event Counter Mode)
The timer remains idle after reset. Set the mode, count source, counter value, etc. using the TAiMR (i = 0 to 4)
register, the TAi register, the UDF register, the ONSF register TAZIE, TA0TGL and TA0TGH bits and the
TRGSR register before setting the TAiS bit in the TABSR register to “1” (count starts).
Always make sure the TAiMR register, the UDF register, the TAZIE, TA0TGL and TA0TGH bits in the ONSF
register and the TRGSR register are modified while the TAiS bit remains “0” (count stops) regardless whether
after reset or not.
While counting is in progress, the counter value can be read out at any time by reading the TAi register.
However, “FFFFh” can be read in underflow, while reloading, and “0000h” in overflow. When setting TAi
register to a value during a counter stop, the setting value can be read before a counter starts counting. Also, if
the counter is read before it starts counting after a value is set in the TAi register while not counting, the set
value is read.
If a low-level signal is applied to the NMI pin when the IVPCR1 bit in the TB2SC register = 1 (three-phase
output forcible cutoff by input on NMI pin enabled), the TA1OUT, TA2OUT and TA4OUT pins go to a highimpedance state.
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24.9.1.3
24. Precautions
Timer A (One-shot Timer Mode)
The timer remains idle after reset. Set the mode, count source, counter value, etc. using the TAiMR (i = 0 to 4)
register, the TAi register, the TA0TGL and TA0TGH bits in the ONSF register and the TRGSR register before
setting the TAiS bit in the TABSR register to “1” (count starts).
Always make sure the TAiMR register, the TA0TGL and TA0TGH bits and the TRGSR register are modified
while the TAiS bit remains “0” (count stops) regardless whether after reset or not.
When setting TAiS bit to “0” (count stop), the followings occur:
• A counter stops counting and a content of reload register is reloaded.
• TAiOUT pin outputs “L”.
• After one cycle of the CPU clock, the IR bit in the TAiIC register is set to “1” (interrupt request).
Output in one-shot timer mode synchronizes with a count source internally generated. When an external trigger
has been selected, one-cycle delay of a count source as maximum occurs between a trigger input to TAiIN pin
and output in one-shot timer mode.
The IR bit is set to “1” when timer operating mode is set with any of the following procedures:
• Select one-shot timer mode after reset.
• Change an operating mode from timer mode to one-shot timer mode.
• Change an operating mode from event counter mode to one-shot timer mode.
To use the Timer Ai interrupt (the IR bit), set the IR bit to “0” after the changes listed above have been made.
When a trigger occurs, while counting, a counter reloads the reload register to continue counting after
generating a re-trigger and counting down once. To generate a trigger while counting, generate a second trigger
between occurring the previous trigger and operating longer than one cycle of a timer count source.
If a low-level signal is applied to the NMI pin when the IVPCR1 bit in the TB2SC register = 1 (three-phase
output forcible cutoff by input on NMI pin enabled), the TA1OUT, TA2OUT and TA4OUT pins go to a highimpedance state.
24.9.1.4
Timer A (Pulse Width Modulation Mode)
The timer remains idle after reset. Set the mode, count source, counter value, etc. using the TAiMR (i = 0 to 4)
register, the TAi register, the TA0TGL and TA0TGH bits in the ONSF register and the TRGSR register before
setting the TAiS bit in the TABSR register to “1” (count starts).
Always make sure the TAiMR register, TA0TGL and TA0TGH bits and the TRGSR register are modified while
the TAiS bit remains “0” (count stops) regardless whether after reset or not.
The IR bit is set to “1” when setting a timer operating mode with any of the following procedures:
• Select the PWM mode after reset.
• Change an operating mode from timer mode to PWM mode.
• Change an operating mode from event counter mode to PWM mode.
To use the Timer Ai interrupt (interrupt request bit), set the IR bit to “0” by program after the above listed
changes have been made.
When setting TAiS register to “0” (count stop) during PWM pulse output, the following action occurs:
• Stop counting.
• When TAiOUT pin is output “H”, output level is set to “L” and the IR bit is set to “1”.
• When TAiOUT pin is output “L”, both output level and the IR bit remains unchanged.
If a low-level signal is applied to the NMI pin when the IVPCR1 bit in the TB2SC register = 1 (three-phase
output forcible cutoff by input on NMI pin enabled), the TA1OUT, TA2OUT and TA4OUT pins go to a highimpedance state.
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24.9.2
24. Precautions
Timer B
24.9.2.1
Timer B (Timer Mode)
The timer remains idle after reset. Set the mode, count source, counter value, etc. using the TBiMR (i = 0 to 5)
register and TBi register before setting the TBiS bit in the TABSR or the TBSR register to “1” (count starts).
Always make sure the TBiMR register is modified while the TBiS bit remains “0” (count stops) regardless
whether after reset or not.
A value of a counter, while counting, can be read in TBi register at any time. “FFFFh” is read while reloading.
Setting value is read between setting values in TBi register at count stop and starting a counter.
24.9.2.2
Timer B (Event Counter Mode)
The timer remains idle after reset. Set the mode, count source, counter value, etc. using the TBiMR (i = 0 to 5)
register and TBi register before setting the TBiS bit in the TABSR or the TBSR register to “1” (count starts).
Always make sure the TBiMR register is modified while the TBiS bit remains “0” (count stops) regardless
whether after reset or not.
The counter value can be read out on-the-fly at any time by reading the TBi register. However, if this register is
read at the same time the counter is reloaded, the read value is always “FFFFh”. If the TBi register is read after
setting a value in it while not counting but before the counter starts counting, the read value is the one that has
been set in the register.
24.9.2.3
Timer B (Pulse Period/pulse Width Measurement Mode)
The timer remains idle after reset. Set the mode, count source, etc. using the TBiMR (i = 0 to 5) register before
setting the TBiS bit in the TABSR or the TBSR register to “1” (count starts).
Always make sure the TBiMR register is modified while the TBiS bit remains “0” (count stops) regardless
whether after reset or not. To clear the MR3 bit to “0” by writing to the TBiMR register while the TBiS bit = 1
(count starts), be sure to write the same value as previously written to the TM0D0, TM0D1, MR0, MR1, TCK0
and TCK1 bits and a 0 to the MR2 bit.
The IR bit in the TBiIC register (i=0 to 5) goes to “1” (interrupt request), when an effective edge of a
measurement pulse is input or Timer Bi is overflowed. The factor of interrupt request can be determined by use
of the MR3 bit in the TBiMR register within the interrupt routine.
If the source of interrupt cannot be identified by the MR3 bit such as when the measurement pulse input and a
timer overflow occur at the same time, use another timer to count the number of times Timer B has overflowed.
To set the MR3 bit to “0” (no overflow), set TBiMR register with setting the TBiS bit to “1” and counting the
next count source after setting the MR3 bit to “1” (overflow).
Use the IR bit to detect only overflows. Use the MR3 bit only to determine the interrupt factor.
When a count is started and the first effective edge is input, an indeterminate value is transferred to the reload
register. At this time, Timer Bi interrupt request is not generated.
A value of the counter is indeterminate at the beginning of a count. MR3 may be set to “1” and Timer Bi
interrupt request may be generated between a count start and an effective edge input.
For pulse width measurement, pulse widths are successively measured. Use program to check whether the
measurement result is an “H” level width or an “L” level width.
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24. Precautions
24.10 Serial interface
24.10.1 Clock Synchronous Serial I/O
24.10.1.1 Transmission/reception
With an external clock selected, and choosing the RTS function, the output level of the RTSi pin goes to “L”
when the data-receivable status becomes ready, which informs the transmission side that the reception has
become ready. The output level of the RTSi pin goes to “H” when reception starts. So if the RTSi pin is
connected to the CTSi pin on the transmission side, the circuit can transmission and reception data with
consistent timing. With the internal clock, the RTS function has no effect.
If a low-level signal is applied to the NMI pin when the IVPCR1 bit in the TB2SC register = 1 (three-phase
output forcible cutoff by input on NMI pin enabled), the RTS2 and CLK2 pins go to a high-impedance state.
24.10.1.2 Transmission
When an external clock is selected, the conditions must be met while if the CKPOL bit in the UiC0 register = 0
(transmit data output at the falling edge and the receive data taken in at the rising edge of the transfer clock), the
external clock is in the high state; if the CKPOL bit in the UiC0 register = 1 (transmit data output at the rising
edge and the receive data taken in at the falling edge of the transfer clock), the external clock is in the low state.
• The TE bit in the UiC1 register= 1 (transmission enabled)
• The TI bit in the UiC1 register = 0 (data present in UiTB register)
• If CTS function is selected, input on the CTSi pin = L
24.10.1.3 Reception
In operating the clock-synchronous serial I/O, operating a transmitter generates a shift clock. Fix settings for
transmission even when using the device only for reception. Dummy data is output to the outside from the
TXDi pin when receiving data.
When an internal clock is selected, set the TE bit in the UiC1 register (i = 0 to 2) to 1 (transmission enabled) and
write dummy data to the UiTB register, and the shift clock will thereby be generated.
When an external clock is selected, set the TE bit to 1 and write dummy data to the UiTB register, and the shift
clock will be generated when the external clock is fed to the CLKi input pin.
When successively receiving data, if all bits of the next receive data are prepared in the UARTi receive register
while the RE bit in the UiC1 register (i = 0 to 2) = 1 (data present in the UiRB register), an overrun error occurs
and the OER bit in the UiRB register is set to “1” (overrun error occurred). In this case, because the content of
the UiRB register is indeterminate, a corrective measure must be taken by programs on the transmit and receive
sides so that the valid data before the overrun error occurred will be retransmitted. Note that when an overrun
error occurred, the IR bit in the SiRIC register does not change state.
To receive data in succession, set dummy data in the lower-order byte of the UiTB register every time reception
is made.
When an external clock is selected, the conditions must be met while if the CKPOL bit = 0, the external clock is
in the high state; if the CKPOL bit = 1, the external clock is in the low state.
• The RE bit in the UiC1 register= 1 (reception enabled)
• The TE bit in the UiC1 register= 1 (transmission enabled)
• The TI bit in the UiC1 register= 0 (data present in the UiTB register)
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24. Precautions
24.10.2 UART
24.10.2.1 Special Mode 1(I2C Mode)
When generating start, stop and restart conditions, set the STSPSEL bit in the UiSMR4 register to “0” and wait
for more than half cycle of the transfer clock before setting each condition generate bit (STAREQ, RSTAREQ
and STPREQ) from “0” to “1”.
24.10.2.2 Special Mode 2
If a low-level signal is applied to the NMI pin when the IVPCR1 bit in the TB2SC register = 1 (three-phase
output forcible cutoff by input on NMI pin enabled), the RTS2 and CLK2 pins go to a high-impedance state.
24.10.2.3 Special Mode 4 (SIM Mode)
A transmit interrupt request is generated by setting the U2C1 register U2IRS bit to “1” (transmission complete)
and U2ERE bit to “1” (error signal output) after reset is deasserted. Therefore, when using SIM mode, be sure
to clear the IR bit to “0” (no interrupt request) after setting these bits.
24.10.3 SI/O3, SI/O4
The SOUTi default value which is set to the SOUTi pin by the SMi7 bit approximately 10ns may be output
when changing the SMi3 bit from “0” (I/O port) to “1” (SOUTi output and CLK function) while the SMi2 bit in
the SiC (i=3 and 4) to “0” (SOUTi output) and the SMi6 bit is set to “1” (internal clock). And then the SOUTi
pin is held high-impedance.
If the level which is output from the SOUTi pin is a problem when changing the SMi3 bit from “0” to “1”, set
the default value of the SOUTi pin by the SMi7 bit.
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24. Precautions
24.11 A/D Converter
Set ADCON0 (except bit 6), ADCON1 and ADCON2 registers when A/D conversion is stopped (before a trigger
occurs).
When the VCUT bit in the ADCON1 register is changed from “0” (Vref not connected) to “1” (Vref connected),
start A/D conversion after passing 1 µs or longer.
To prevent noise-induced device malfunction or latchup, as well as to reduce conversion errors, insert capacitors
between the AVCC, VREF, and analog input pins (ANi(i=0 to 7), AN0_i, AN2_i) each and the AVSS pin.
Similarly, insert a capacitor between the VCC1 pin and the VSS pin. Figure 24.4 is an example connection of each
pin.
Make sure the port direction bits for those pins that are used as analog inputs are set to “0” (input mode).
Also, if the TGR bit in the ADCON0 register = 1 (external trigger), make sure the port direction bit for the ADTRG
pin is set to “0” (input mode).
When using key input interrupts, do not use any of the four AN4 to AN7 pins as analog inputs. (A key input
interrupt request is generated when the A/D input voltage goes low.)
The φAD frequency must be 12MHz or less. Without sample-and-hold function, limit the φAD frequency to
250kHz or more. With the sample and hold function, limit the φAD frequency to 1MHz or more.
When changing an A/D operating mode, select analog input pin again in the CH2 to CH0 bits in the ADCON0
register and the SCAN1 to SCAN0 bits in the ADCON1 register.
Microcomputer
VCC1
VCC1
VCC1
AVCC
VSS
VREF
C4
C1
AVSS
VCC2
C5
C2
C3
VCC2
ANi
VSS
ANi: ANi, AN0_i and AN2_i (i=0 to 7)
NOTES :
1. C1≥0.47µF, C2≥0.47µF, C3≥100pF, C4≥0.1µF, C5≥0.1µF (reference)
2. Use thick and shortest possible wiring to connect capacitors.
Figure 24.4
Use of Capacitors to Reduce Noise
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24. Precautions
If VCC2 < VCC1, do not use AN0_0 to AN0_7 and AN2_0 to AN2_7 as analog input pins.
If the CPU reads the ADi register (i = 0 to 7) at the same time the conversion result is stored in the ADi register
after completion of A/D conversion, an incorrect value may be stored in the ADi register. This problem occurs
when a divide-by-n clock derived from the main clock or a subclock is selected for CPU clock.
• When operating in one-shot or single-sweep mode
Check to see that A/D conversion is completed before reading the target ADi register. (Check the IR bit in
the ADIC register to see if A/D conversion is completed.)
• When operating in repeat mode or repeat sweep mode 0 or 1
Use the main clock for CPU clock directly without dividing it.
If A/D conversion is forcibly terminated while in progress by setting the ADST bit in the ADCON0 register to “0”
(A/D conversion halted), the conversion result of the A/D converter is indeterminate. The contents of ADi registers
irrelevant to A/D conversion may also become indeterminate. If while A/D conversion is underway the ADST bit is
cleared to “0” in a program, ignore the values of all ADi registers.
When setting the ADST bit in the ADCON0 register to “0” in single-sweep mode during A/D conversion and
suspending A/D conversion, disable the interrupt before setting the ADST bit to “0”.
The applied intermediate potential may cause more increase in power consumption than other analog input pins
(AN0 to AN3, AN0_0 to AN0_7 and AN2_0 to AN2_7), since the AN4 to AN7 are used with the KI0 to KI3.
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24. Precautions
24.12 Programmable I/O Ports
If a low-level signal is applied to the NMI pin when the IVPCR1 bit in the TB2SC register = 1 (three-phase output
forcible cutoff by input on NMI pin enabled), the P7_2 to P7_5, P8_0 and P8_1 pins go to a high-impedance state.
Setting the SM32 bit in the S3C register to “1” causes the P9_2 pin to go to a high-impedance state.
Similarly, setting the SM42 bit in the S4C register to “1” causes the P9_6 pin to go to a high-impedance state.
The input threshold voltage of pins differs between programmable input/output ports and peripheral functions.
Therefore, if any pin is shared by a programmable input/output port and a peripheral function and the input level at
this pin is outside the range of recommended operating conditions VIH and VIL (neither “high” nor “low”), the
input level may be determined differently depending on which side-the programmable input/output port or the
peripheral function-is currently selected.
When changing the PD14_i bit (i=0 to 1) in the PC14 register from “0” (input port) to “1” (output port), follow the
procedures below.
Setting Procedure
(1) Set P14_i bit
:MOV.B #00000001b, PC14 ; P14_i bit setting
(2) Change PD14_i bit to “1” by MOV instruction
:MOV.B #00110001b, PC14 ; Change to output port
Indeterminate values are read from the P3_7 to P3_4, PD3_7 to PD3_4 bits by reading the P3 and PD3 registers
when the PM01 to PM00 bits in the PM0 register are set to “01b” (memory expansion mode) or
“11b”(microprocessor mode) and setting the PM11 bit to “1”.
Use the MOV instruction when rewriting the P3 and PD3 registers (including the case that the size specifier is “.W”
and the P2 and PD2 registers are rewritten).
When the PM01 to PM00 bits are rewritten, "L” is output from the P3_7 to P3_4 pins during 0.5 cycles of the
BCLK by setting the PM01 to PM00 bits in the PM0 register to “01b” (memory expansion mode) or “11b”
(microprocessor mode) from “00b” (single-chip mode) after setting the PM11 bit to “1”.
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24. Precautions
24.13 Electric Characteristic Differences Between Mask ROM and Flash Memory
Version Microcomputers
Flash memory version and mask ROM version may have different characteristics, operating margin, noise tolerated
dose, noise width dose in electrical characteristics due to internal ROM, different layout pattern, etc. When
switching to the mask ROM version, conduct equivalent tests as system evaluation tests conducted in the flush
memory version.
24.14 Mask ROM
When using the masked ROM version, write nothing to internal ROM area.
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24. Precautions
24.15 Flash Memory Version
24.15.1 Functions to Inhibit Rewriting Flash Memory Rewrite
ID codes are stored in addresses 0FFFDFh, 0FFFE3h, 0FFFEBh, 0FFFEFh, 0FFFF3h, 0FFFF7h, and
0FFFFBh. If wrong data are written to theses addresses, the flash memory cannot be read or written in standard
serial I/O mode.
The ROMCP register is mapped in address 0FFFFFh. If wrong data is written to this address, the flash memory
cannot be read or written in parallel I/O mode.
In the flash memory version of microcomputer, these addresses are allocated to the vector addresses (H) of
fixed vectors.
24.15.2 Stop mode
When the microcomputer enters stop mode, execute the instruction which sets the CM10 bit to “1” (stop mode)
after setting the FMR01 bit to “0” (CPU rewrite mode disabled) and disabling the DMA transfer.
24.15.3 Wait mode
When shifting to wait mode, set the FMR01 bit to “0” (CPU rewrite mode disabled) before executing the WAIT
instruction.
24.15.4 Low power dissipation mode, on-chip oscillator low power dissipation
mode
If the CM05 bit is set to “1” (main clock stop), the following commands must not be executed.
• Program
• Block erase
• Erase all unlocked blocks
• Lock bit program
24.15.5 Writing command and data
Write the command code and data at even addresses.
24.15.6 Program Command
Write “xx40h” in the first bus cycle and write data to the write address in the second bus cycle, and an auto
program operation (data program and verify) will start. Make sure the address value specified in the first bus
cycle is the same even address as the write address specified in the second bus cycle.
24.15.7 Lock Bit Program Command
Write “77h” in the first bus cycle and write “xxD0h” to the uppermost address of a block (even address,
however) in the second bus cycle, and the lock bit for the specified block is cleared to “0”. Make sure then
address value specified in the first bus cycle is the same uppermost block address that is specified in the second
bus cycle.
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24. Precautions
24.15.8 Operation speed
Before entering CPU rewrite mode (EW0 or EW1 mode), set the CM11 bit in the CM1 register to “0” (main
clock), select 10 MHz or less for CPU clock using the CM06 bit in the CM0 register and CM17 to CM16 bits in
the CM1 register. Also, set the PM17 bit in the PM1 register to “1” (with wait state).
24.15.9 Instructions inhibited against use
The following instructions cannot be used in EW0 mode because the flash memory’s internal data is referenced:
UND instruction, INTO instruction, JMPS instruction, JSRS instruction, and BRK instruction.
24.15.10 Interrupts
EW0 Mode
• Any interrupt which has a vector in the relocatable vector table can be used providing that its vector is
transferred into the RAM area.
• The NMI and watchdog timer interrupts can be used because the FMR0 register and FMR1 register are
initialized when one of those interrupts occurs. The jump addresses for those interrupt service routines
should be set in the fixed vector table.
Because the rewrite operation is halted when a NMI or watchdog timer interrupt occurs, the rewrite
program must be executed again after exiting the interrupt service routine.
• The address match interrupt cannot be used because the flash memory’s internal data is referenced.
EW1 Mode
• Make sure that any interrupt which has a vector in the variable vector table or address match interrupt will
not be accepted during the auto program or auto erase period.
• Avoid using watchdog timer interrupts.
• The NMI interrupt can be used because the FMR0 register and FMR1 register are initialized when this
interrupt occurs. The jump address for the interrupt service routine should be set in the fixed vector table.
Because the rewrite operation is halted when a NMI interrupt occurs, the rewrite program must be executed
again after exiting the interrupt service routine.
24.15.11 How to access
To set the FMR01, FMR02, or FMR11 bit to “1”, write “0” and then “1” in succession. This is necessary to
ensure that no interrupts or DMA transfers will occur before writing “1” after writing “0”. Also only when NMI
pin is “H” level.
24.15.12 Writing in the user ROM area
EW0 Mode
• If the power supply voltage drops while rewriting any block in which the rewrite control program is stored,
a problem may occur that the rewrite control program is not correctly rewritten and, consequently, the flash
memory becomes unable to be rewritten thereafter. In this case, standard serial I/O or parallel I/O mode
should be used.
EW1 Mode
• Avoid rewriting any block in which the rewrite control program is stored.
Rev.2.41 Jan 10, 2006
REJ09B0185-0241
Page 380 of 390
M16C/62P Group (M16C/62P, M16C/62PT)
24. Precautions
24.15.13 DMA transfer
In EW1 mode, make sure that no DMA transfers will occur while the FMR00 bit in the FMR0 register = 0
(during the auto program or auto erase period).
24.15.14 Regarding Programming/Erasing Endurance and Execution Time
As the number of programming/erasure times increases, so does the execution time for software commands
(Program, Block Erase, Erase All Unlock Blocks, and Lock Bit Program). Especially when the number of
programming/erasure times exceeds 1,000, the software command execution time is noticeably extended.
Therefore, the software command wait time that is set must be greater than the maximum rated value of
electrical characteristics.
The software commands are suspended by hardware reset 1, hardware reset 2, NMI interrupt, and watchdog
timer interrupt. If a software command is suspended by such reset or interrupt, the block that was in process
must be erased before reexecuting the suspended command.
Rev.2.41 Jan 10, 2006
REJ09B0185-0241
Page 381 of 390
M16C/62P Group (M16C/62P, M16C/62PT)
24. Precautions
24.16 Noise
Connect a bypass capacitor (approximately 0.1 µF) across the VCC1 and XSS pins, and VCC2 and VSS pins using
the shortest and thicker possible wiring. Figure 24.5 shows the Bypass Capacitor Connection.
Bypass Capacitor
Connecting Pattern
Connecting Pattern
VCC2
VSS
M16C/62P Group
(M16C/62P, M16C/62PT)
VSS
VCC1
Connecting Pattern
Connecting Pattern
Bypass Capacitor
Figure 24.5
Bypass Capacitor Connection
Rev.2.41 Jan 10, 2006
REJ09B0185-0241
Page 382 of 390
M16C/62P Group (M16C/62P, M16C/62PT)
25. Differences Depending on Manufacturing Period
25. Differences Depending on Manufacturing Period
Table 25.1 and Table 25.2 list the precautions are applicable or not applicable every chip version of M16C/62P flash
and ROM external versions. Contact separately about the mask ROM version.
Table 25.1
Technical Update Applicable Table of M16C/62P Flash and ROM External Versions (1)
Chip Version
TECHNICAL UPDATE
Precaution
A
B
C
Ensure that RESET must hold valid-low state during power-on.
When using a reset IC, use a CMOS type IC. When using an
open-drain type reset IC, insert a capacitor between the reset
√
−
−
input and VSS. Adjust the R-C time constant between the
capacitor and pull-up resistor at least 10 times longer than the
VCC rising time.
If UART0 or UART1 are used as a slave in the I2C mode, P6_1
or P6_5 are placed in a high-impedance state. P6_1 or P6_5
cannot be used as an output port even if the PD6_1 or PD6_5 bits √
−
−
TN-M16C-100-0309
in the PD6 register are set to “1” (output mode). Therefore, set
the PD6_1 or PD6_5 bits to “0” (Input mode).
Do not enter wait mode when the main clock or on-chip oscillator
TN-M16C-108-0309
clock is selected as the CPU clock of which division is set by the
√
−
−
Precaution 1.1
CM06 bit in the CM0 register, and the CM16 and CM17 bits in the
CM1 register.
The CM05 bit in the CM0 register is set to “0” (main clock
TN-M16C-108-0309
√
−
−
oscillation) and the CM02 bit is set to “1” (peripheral function
Precaution 1.2
clock stops in wait mode).
TN-M16C-108-0309
Do not generate an NMI interrupt after entering mode.
√
−
−
Precaution 1.3
TN-M16C-108-0309
Do not generate a voltage detection interrupt after entering
√
−
−
Precaution 1.4
mode.
I/O ports (P0 to P5) will be indeterminate until internal power
TN-M16C-114-0310
supply is stable, such as when the power is turned on, if “H” is
√
√
√
Precaution 1.1
applied to the CNVSS pin and “L” to the RESET pin while internal
power supply is unstable.
I/O ports (P6 to P14) will be indeterminate until internal power
TN-M16C-114-0310
supply is stable, such as when the power is turned on, if “H” is
√
−
−
Precaution 1.1
applied to the CNVSS pin and “L” to the RESET pin while internal
power supply is unstable.
When the RESET pin is “L” in boot mode (apply “H” to the
CNVSS pin and P5_0 (CE), and “L” to the P5_5 (EPM)), internal
TN-M16C-114-0310
√
−
−
pull-up is enabled for P10_0 to P10_3, P11_0 to P11_7, P12_5
Precaution 1.2
to P12_7, P13_0 to P13_7, P14_0 and P14_1 and so become “H”
level.
P0_0 to P0_7 and P1_0 to P1_7 may become indeterminate
when P8_4 is “H” and the RESET pin is “L” in boot mode (apply
TN-M16C-114-0310
“H” to the CNVSS pin and P5_0 (CE), and “L” to P5_5 (EPM)).
√
√
√
Precaution 1.3
P0_0 to P0_7 and P1_0 to P1_7 are in a high impedance state
when the RESET pin and P8_4 are “L”.
√ : Applies
− : Dose not apply
Rev.2.41 Jan 10, 2006
REJ09B0185-0241
Page 383 of 390
M16C/62P Group (M16C/62P, M16C/62PT)
Table 25.2
25. Differences Depending on Manufacturing Period
Technical Update Applicable Table of M16C/62P Flash and ROM External Versions (2)
Chip Version
Precaution
TECHNICAL UPDATE
A
B
C
When supplying power to the microcomputer, the power supply
voltage applied to the VCC1 pin must meet the conditions of
÷
TN-M16C-116-0311
SVCC.
Do not set the CM10 bit in the CM1 register to 1 (stop mode) with
setting the VC13 bit in the VCR1 register to 1 (VCC1≥Vdet 4)
when a low voltage detection interrupt in the voltage detection
circuit is used under the following settings:
• the VC27 bit in the VCR2 register to 1 (low voltage detection
TN-M16C-107-0309
÷
circuit enabled)
Precaution 1.1
• the D40 bit in the D4INT register to 1 (low voltage detection
interrupt enabled)
• the D41 bit to 1 (use low voltage detection interrupt to exit stop
mode)
TN-M16C-107-0309
Do not generate the NMI interrupt after setting the CM10 bit in the
÷
Precaution 1.2
CM1 register to “1” (stop mode) and entering stop mode.
Do not set the CM10 bit in the CM1 register to “1” (stop mode)
when the microcomputer is in low-speed mode under the
following settings:
TN-M16C-107-0309
÷
• the CM04 bit in the CM0 register is set to “1” (sub clock
Precaution 1.3
oscillation)
• the CM07 bit in the CM0 register is set to “1” (sub clock)
When using the sub clock (XCIN-XCOUT) as the CPU clock
(BCLK) or as the timer count source, DO NOT leave the CM03
÷
÷
TN-M16C-119A/EA
bit set to “1” (XCINXCOUT drive capacity “HIGH” ).
√ : Applies
− : Dose not apply
Rev.2.41 Jan 10, 2006
REJ09B0185-0241
Page 384 of 390
M16C/62P Group (M16C/62P, M16C/62PT)
Appendix 1. Package Dimensions
Appendix 1.Package Dimensions
JEITA Package Code
RENESAS Code
Previous Code
MASS[Typ.]
P-LQFP128-14x20-0.50
PLQP0128KB-A
128P6Q-A
0.9g
HD
*1
D
102
65
103
64
NOTE)
1. DIMENSIONS "*1" AND "*2"
DO NOT INCLUDE MOLD FLASH.
2. DIMENSION "*3" DOES NOT
INCLUDE TRIM OFFSET.
bp
c
*2
E
HE
c1
b1
Reference
Symbol
ZE
Terminal cross section
Dimension in Millimeters
Min
Nom
Max
D
19.9
20.0
20.1
E
13.9
14.0
14.1
A2
128
39
38
ZD
HD
21.8
22.0
22.2
HE
15.8
16.0
16.2
A1
0.05
0.125
0.2
bp
0.17
0.22
0.27
A
A
A2
Index mark
c
1
1.4
F
1.7
0.20
b1
A1
c
*3
y
e
DetailF
8°
0.5
0.10
x
y
0.10
ZD
0.75
ZE
0.75
L
0.35
JEITA Package Code
RENESAS Code
Previous Code
MASS[Typ.]
PRQP0100JB-A
100P6S-A
1.6g
0.5
0.65
1.0
L1
P-QFP100-14x20-0.65
0.20
0.125
e
x
0.145
0°
L1
bp
0.09
c1
L
HD
*1
D
80
51
81
50
HE
*2
E
NOTE)
1. DIMENSIONS "*1" AND "*2"
DO NOT INCLUDE MOLD FLASH.
2. DIMENSION "*3" DOES NOT
INCLUDE TRIM OFFSET.
ZE
Reference
Symbol
100
31
Dimension in Millimeters
Min
Nom
Max
D
19.8
20.0
20.2
E
13.8
14.0
HD
22.5
22.8
23.1
30
Index mark
ZD
c
F
A2
1
HE
16.5
16.8
17.1
A1
0
0.1
0.2
bp
0.25
0.3
0.4
c
0.13
0.15
A1
A
A
L
*3
e
y
3.05
0°
bp
Detail F
e
0.5
0.65
0.575
ZD
Page 385 of 390
0.8
0.10
ZE
Rev.2.41 Jan 10, 2006
REJ09B0185-0241
0.2
10°
y
L
14.2
2.8
A2
0.825
0.4
0.6
0.8
M16C/62P Group (M16C/62P, M16C/62PT)
JEITA Package Code
RENESAS Code
P-LQFP100-14x14-0.50
PLQP0100KB-A
Appendix 1. Package Dimensions
Previous Code
MASS[Typ.]
100P6Q-A / FP-100U / FP-100UV
0.6g
HD
*1
D
51
75
NOTE)
1. DIMENSIONS "*1" AND "*2"
DO NOT INCLUDE MOLD FLASH.
2. DIMENSION "*3" DOES NOT
INCLUDE TRIM OFFSET.
50
76
bp
c1
Reference
Symbol
c
E
*2
HE
b1
Terminal cross section
26
Nom
13.9
14.0
14.1
E
13.9
14.0
14.1
HD
15.8
16.0
16.2
HE
15.8
16.0
16.2
A1
0.05
0.1
0.15
bp
0.15
0.20
0.25
A2
ZE
100
Dimension in Millimeters
Min
D
1.4
A
1
25
Index mark
ZD
F
1.7
0.18
b1
0.09
c
0°
*3
e
bp
A1
e
y
0.08
0.08
1.0
ZD
Detail F
1.0
ZE
L
0.35
RENESAS Code
Previous Code
MASS[Typ.]
PRQP0080JA-A
80P6S-A
1.1g
0.5
0.65
1.0
L1
JEITA Package Code
8°
y
L1
0.20
0.5
x
L
x
P-QFP80-14x14-0.65
0.145
0.125
c1
A2
A
c
Max
HD
*1 D
60
41
61
40
HE
ZE
*2 E
NOTE)
1. DIMENSIONS "*1" AND "*2"
DO NOT INCLUDE MOLD FLASH.
2. DIMENSION "*3" DOES NOT
INCLUDE TRIM OFFSET.
Reference
Symbol
80
1
20
ZD
c
Nom
Max
D
13.8
14.0
14.2
E
13.8
14.0
14.2
A2
A2
Index mark
Dimension in Millimeters
Min
21
F
2.8
HD
16.5
16.8
17.1
HE
16.5
16.8
17.1
A1
0
0.1
0.2
bp
0.25
0.3
0.4
c
0.13
0.15
A
A1
A
L
Detail F
*3
e
y
3.05
0°
bp
e
0.5
0.65
y
0.825
ZD
Rev.2.41 Jan 10, 2006
REJ09B0185-0241
Page 386 of 390
0.8
0.10
ZE
L
0.2
10°
0.825
0.4
0.6
0.8
M16C/62P Group (M16C/62P, M16C/62PT)
Appendix 2. Difference between M16C/62P and M16C/30P
Appendix 2. Difference between M16C/62P and M16C/30P
Appendix Table 2.1 Function Difference (1)(1)
Item
M16C/62P
Shortest instruction
execution time
41.7ns (f(BCLK)=24MHz, VCC1=3.0 to 5.5V)
100ns (f(BCLK)=10MHz, VCC1=2.7 to 5.5V)
Supply voltage
VCC1=3.0 to 5.5V, VCC2=3.0V to VCC1
(f(BCLK)=24MHz)
VCC1=VCC2=2.7 to 5.5V
(f(BCLK)=10MHz)
Double (VCC1, VCC2)
80-pin, 100-pin, 128-pin plastic mold QFP
Built-in
Vdet3, Vdet4 detect
Voltage down detect interrupt
Hardware reset 2
PLL, XIN, XCIN, on-chip oscillator
When placed in low power mode, a divideby-8 value is used for these clocks. The XIN
drive capability is set to HIGH.
I/O power supply
Package
Voltage detection
circuit
Clock Generating
Circuit
System clock
protective function
Oscillation Stop,
Re-oscillation
Detection
Function
Low power
consumption
Built-in
Memory Area
Memory area expandable
(4 Mbytes)
04000h to 07FFFh(PM13=0)
08000h to 0FFFFh(PM10=0)
10000h to 26FFFh
28000h to 7FFFFh
80000h to CFFFFh(PM13=0)
D0000h to FFFFFh(Microprocessor mode)
P4_0 to P4_3 (A16 to A19), P3_4 to P3_7
(A12 to A15) : Switchable between
address bus and I/O port
External Device
Connect
Area
Upper address in
memory expansion
mode and
microprocessor mode
Access to SFR
Software wait to
external area
Protect
Watchdog timer
Address match
interrupt
Built-in
18mA (VCC1=VCC2=5V, f(BCLK)=24MHz)
8mA (VCC1=VCC2=3V, f(BCLK)=10MHz)
1.8µA (VCC1=VCC2=3V, f(XCIN)=32kHz,
when wait mode)
M16C/62A
62.5ns (f(XIN)=16MHz, VCC=4.2V to 5.5V)
100ns (f(XIN)=10MHz, VCC=2.7V to 5.5V
with software one-wait)
VCC=4.2V to 5.5V (f(XIN)=16MHz,
without software wait)
VCC=2.7V to 5.5V (f(XIN)=10MHz,
with software one-wait)
Single (VCC)
80-pin, 100-pin plastic mold QFP
None
XIN, XCIN
When placed in low power mode, the
divide-by-n value for the main clock
does not change. Nor does the XIN
drive capability change.
None
(protected by protect register)
None
32.5mA (VCC=5V, f(XIN)=16MHz)
8.5mA (VCC=3V, f(XCIN)=10MHz with
software one-wait)
0.9µA (VCC=3V, f(XCIN)=32kHz,
when wait mode)
1 Mbytes fixed
04000h to 05FFFh(PM13=0)
06000h to CFFFFh
D0000h to FFFFFh(Microprocessor mode)
P4_0 to P4_3 (A16 to A19) : Switchable
between address bus and I/O port
A12 to A15 : No switchable
Variable (1 to 2 waits)
Variable (0 to 3 waits)
1 wait fixed
Variable (0 to 1 wait)
Can be set for PM0, PM1, PM2, CM0,
CM1, CM2, PLC0, INVC0, INVC1, PD9,
S3C, S4C, TB2SC, PCLKR, VCR2, D4INT
registers
Watchdog timer interrupt or watchdog
timer reset is selected
Count source protective mode is available
4
Can be set for PM0, PM1, CM0, CM1,
PD9, S3C, S4C registers
Watchdog timer interrupt
No count source protective mode
2
NOTES:
1. About the details and the electric characteristics, refer to hardware manual.
Rev.2.41 Jan 10, 2006
REJ09B0185-0241
Page 387 of 390
M16C/62P Group (M16C/62P, M16C/62PT)
Appendix 2. Difference between M16C/62P and M16C/30P
Appendix Table 2.2 Function Difference (1)(1)
Item
M16C/62P
Timers A, B count
source
Timer A two-phase
pulse signal
processing
Timer functions for
three-phase motor
control
Serial I/O
(UART0 to UART2)
M16C/62A
Selectable: f1, f2, f8, f32, fC32
Selectable: f1, f8, f32, fC32
Function Z-phase (counter reset) input
No function Z-phase (counter reset) input
Function protect by protect register
Count source is selected:
f1, f2, f8, f32, fC32
Dead time timer count source is selected:
f1, f1 divided by 2, f2, f2 divided by 2
Three-phase output forcible shutoff function
based on NMI input is available, output
polarity change, carrier wave phase
detection.
(UART, clock synchronous, I2C bus, IEBus)
x3
Function protect by protect register
Count source is selected:
f1, f8, f32, fC32
Dead time timer count source is fixed at f1
divided by 2
(UART, clock synchronous) x 2
(UART, clock synchronous, I2C bus, IEBus)
x1
Select from f1, f8, f32
UART0 to UART2,
SI/O3, SI/O4 count
source
Select from f1SIO, f2SIO, f8SIO, f32SIO
Serial I/O RTS timing
UART0 to UART2
Overrun Error
Generation Timing
Assert low when receive buffer is read
This error occurs if the serial I/O started
receiving the next data before reading the
UiRB register (i=0 to 2) and received the 7
th bit of the next data (clock synchronous)
This error occurs if the serial I/O started
receiving the next data before reading the
UiRB register and received the bit one
before the last stop bit of the next data
(UART)
Assert low when reception is completed
This error occurs when the next data is
ready before contents of UARTi receive
buffer register are read out
CTS/RTS separate
function
UART2 data transmit
timing
Have
None
After data was written, transfer starts at the
2nd BRG overflow timing
(same as UART0 and UART1)
Serial I/O sleep
function
Serial I/O I2C mode
None
After data was written, transfer starts at the
1st BRG overflow timing
(Output starts one cycle of BRG overflow
earlier than UART0 and UART1)
Have
Serial I/O I2C mode
SDA delay
SI/O3, SI/O4 clock
polarity
A/D Converter
A/D converter
operation clock
A/D Converter Input Pin
Start condition, stop condition:
Auto-generationable
Only digital delay is selected as SDA delay
SDA digital delay count source: BRG
Selectable
10 bits X 8 channels
Expandable up to 26 channels
Selectable: fAD, fAD divided by 2, 3, 4,
6, 12
Select from ports P0, P2, P10
Start condition, stop condition:
Not auto-generationable
Analog or digital delay is selected as SDA
delay
SDA digital delay count source: 1/ f(XIN)
Fixed
10 bits X 8 channels
Expandable up to 10 channels
Selectable: fAD, fAD/2, fAD/4
Fixed at port P10
NOTES:
1. About the details and the electric characteristics, refer to hardware manual.
Rev.2.41 Jan 10, 2006
REJ09B0185-0241
Page 388 of 390
M16C/62P Group (M16C/62P, M16C/62PT)
Appendix 2. Difference between M16C/62P and M16C/30P
Appendix Table 2.3 Function Difference (1)(1)
Item
M16C/62P
User ROM blocks
Program manner
Program command
(software command)
Block status after
program function
CPU rewrite
mode
M16C/62A
14 blocks: 4 Kbytes x 3, 8 Kbytes x 3,
32 Kbytes x1, 64 Kbytes x 7
(Flash memory: max. 512 Kbytes)
Word
Page program command: none
Program command: have
(program method: in units of word, in units
of byte)
None
7 blocks: 8 Kbytes x 2, 16 Kbytes x1,
32 Kbytes x 1, 64 Kbytes x 3
(Flash memory: max. 256 Kbytes)
Page
Page program command: have
Program command: none
(program method: in units of page)
EW1 mode is available
No EW1 mode
Have
NOTES:
1. About the details and the electric characteristics, refer to hardware manual.
Rev.2.41 Jan 10, 2006
REJ09B0185-0241
Page 389 of 390
M16C/62P Group (M16C/62P, M16C/62PT)
Register Index
Register Index
A
AD0 to AD7 ............................. 237
ADCON0 ................................. 235
ADCON1 ................................. 235
ADCON2 ................................. 236
ADIC ...................................... 111
AIER ....................................... 123
AIER2 ..................................... 123
B
INT0IC to INT5IC .....................112
INVC0 .....................................167
INVC1 .....................................168
K
KUPIC ....................................111
O
ONSF .....................................142
BCNIC .................................... 111
C
CM0 ......................................... 84
CM1 ......................................... 85
CM2 ......................................... 86
CPSRF ........................... 143, 158
CRCD ..................................... 253
CRCIN .................................... 253
CSE ......................................... 68
CSR ......................................... 61
D
D4INT ....................................... 47
DA0 to DA1 ............................. 252
DACON .................................. 252
DAR0 ..................................... 131
DAR1 ..................................... 131
DBR ......................................... 73
DM0CON ................................ 130
DM0IC to DM1IC ..................... 111
DM0SL ................................... 128
DM1CON ................................ 130
DM1SL ................................... 129
DTT ........................................ 171
F
FIDR ....................................... 276
FMR0 ..................................... 277
FMR1 ..................................... 278
I
ICTB2 ..................................... 169
IDB0 ....................................... 170
IDB1 ....................................... 170
IFSR ....................................... 120
IFSR2A ................................... 120
Rev.2.41 Jan 10, 2006
REJ09B0185-0241
P
P0 to P13 ................................263
PC14 ......................................264
PCLKR .....................................87
PCR .......................................266
PD0 to PD13 ...........................262
PLC0 ........................................88
PM0 ..........................................56
PM1 ..........................................57
PM2 ..........................................87
PRCR .....................................105
PUR0 to PUR1 .........................265
PUR2 ......................................266
PUR3 ......................................264
R
RMAD0 to RMAD3 ...................123
ROMCP ..................................274
S
S0RIC to S2RIC .......................111
S0TIC to S2TIC .......................111
S3BRG to S4BRG ....................229
S3C to S4C .............................228
S3IC to S4IC ...........................112
S3TRR to S4TRR .....................229
SAR0 ......................................131
SAR1 ......................................131
T
TA0 to TA4 ..............................140
TA0IC to TA4IC ........................111
TA0MR to TA4MR ....................140
TA1 .........................................169
TA11 .......................................169
TA1MR ....................................173
Page 390 of 390
TA2 .........................................169
TA21 .......................................169
TA2MR ....................................173
TA4 .........................................169
TA41 .......................................169
TA4MR ....................................173
TABSR ....................141, 158, 172
TAiMR .....................................140
TB0 to TB5 ..............................157
TB0IC to TB5IC ........................111
TB0MR to TB5MR ....................157
TB2 .........................................171
TB2MR ...................................173
TB2SC ....................................170
TBSR ......................................158
TCR0 ......................................131
TCR1 ......................................131
TRGSR ...........................142, 171
U
U0BCNIC to U1BCNIC ..............111
U0BRG to U2BRG ....................182
U0C0 to U2C0 .........................184
U0C1 to U2C1 .........................185
U0MR to U2MR ........................183
U0RB to U2RB .........................181
U0SMR to U2SMR ...................186
U0SMR2 to U2SMR2 ................187
U0SMR3 to U2SMR3 ................187
U0SMR4 to U2SMR4 ................188
U0TB to U2TB .........................181
UCON .....................................186
UDF ........................................141
V
VCR1 ........................................46
VCR2 ........................................46
W
WDC .................................53, 125
WDTS .....................................125
REVISION HISTORY
Rev.
Date
1.0
Jan 31, 2003
M16C/62P Group (M16C/62P, M16C/62PT) Hardware Manual
Description
Page
Summary
1
Applications are partly revised.
2
Table 1.1.1 is partly revised.
5
Table 1.1.3 is partly revised.
Figure 1.1.2 is partly revised.
11
Explanation of “Memory” is partly revised.
20
Explanation of “Hardware Reset 1” is partly revised.
21
Figure 1.5.1 is partly revised.
22
Figure 1.5.2 is partly revised.
24
Figure 1.5.4 is partly revised.
25
VCR2 Register in Figure 1.5.6 is partly revised.
26
Figure 1.5.6 is partly revised.
27
Explanation of “Power Supply Down Detection Interrupt” is partly revised.
30
Figure 1.6.1 is partly revised.
31
Figure 1.6.2 is partly revised.
39
Table 1.7.5 is partly revised.
41
Table 1.7.7 is partly revised.
43
Figure 1.7.8 is partly revised.
44
Explanation of “4 Mbyte Mode” is partly revised.
53
Notes 12 and 13 in Figure 1.9.2 is partly revised.
54
Notes 2 and 5 in Figure 1.9.3 is partly revised.
55
Figure 1.9.4 is partly revised.
57
Note 4 in Figure 1.9.6 is partly revised.
60
Explanation of “PLL Clock” is partly revised.
61
Figure 1.9.9 is partly revised.
62
Explanation of “CPU Clock and BCLK” is partly revised.
63
Explanation of “Low-speed Mode” is partly revised.
Explanation of “Low Power Dissipation Mode” is partly revised.
64
Explanation of “Low Power Dissipation Mode” is partly revised.
Explanation of “On-chip Oscillator Low Power Dissipation Mode” is partly
revised.
Table 1.9.3 is partly revised.
65
Table 1.9.5 is partly revised.
68
Figure 1.9.10 is partly revised.
69
Figure 1.9.11 is partly revised.
70
Table 1.9.7 is added.
71
Explanation of “System Clock Protective Function” is partly revised.
77
Explanation of “Power Supply Down Detection Interrupt” is partly revised.
78
Table 1.11.1 is partly revised.
C-1
REVISION HISTORY
Rev.
Date
M16C/62P Group (M16C/62P, M16C/62PT) Hardware Manual
Description
Page
Summary
88
Figure 1.11.9 is partly revised.
96
WDTS Register in Figure 1.12.2 is partly revised.
99
Figure 1.13.2 is partly revised.
100
Figure 1.13.3 is partly revised.
103
Figure 1.13.5 is partly revised.
104
Table 1.13.3 is partly revised.
105
Explanation of “DMA Enable” is partly revised.
109
Figure 1.14.3 is partly revised.
115
Table 1.14.5 is partly revised.
117
Explanation of “Counter Initialization by Two-Phase Pulse Signal
Processing” is partly revised.
117
Figure 1.14.10 is partly revised.
122
Figure 1.14.14 is partly revised.
Figure 1.14.15 is partly revised.
124
Figure 1.15.3 is partly revised.
128
Figure 1.15.7 is partly revised.
128
Figure 1.15.8 is partly revised.
130
Figure 1.16.1 is partly revised.
132
Figure 1.16.3 is partly revised.
134
Note 7 is added to TAi, TAi1 Register in Figure 1.16.5.
137
Figure 1.16.8 is partly revised.
146
UiSMR2 Register in Figure 1.17.7 is partly revised.
163
Figure 1.20.1 is partly revised.
164,
165
Table 1.20.2 and Table 1.20.3 are partly revised.
169
Figure 1.20.4 is partly revised.
Explanation of “Arbitration” is partly revised.
170
Explanation of “Transfer Clock” is partly revised.
171
Explanation of “ACK and NACK” is partly revised.
179
Explanation of “Special Mode 4 (SIM Mode)” is partly revised.
Table 1.20.9 is partly revised.
184
Figure 1.21.1 is partly revised.
187
Figure 1.21.4 is partly revised.
203
Explanation of “External Operation Amp Connection Mode” is partly
revised.
205
Explanation of “Caution of Using A/D Converter” is partly revised.
Figure 1.22.11 is partly revised
206
Table 1.23.1 is partly revised.
207
Figure 1.23.3 is partly revised.
C-2
REVISION HISTORY
Rev.
Date
M16C/62P Group (M16C/62P, M16C/62PT) Hardware Manual
Description
Page
Summary
218
Figure 1.25.9 is partly revised.
223
Table 1.26.1 is partly revised.
224
Table 1.26.2 is partly revised.
225
Note 1 of Table 1.26.3 is partly revised.
Note 1 of Table 1.26.4 is partly revised.
Table 1.26.6 is partly revised.
227
Note 1 of Table 1.26.9 is partly revised.
228
Note 1 of Table 1.26.10 is partly revised.
229
Measurement conditions of timing requirements are partly revised.
Table 1.26.11 is partly revised.
230
Measurement conditions of timing requirements are partly revised.
230
Table 1.26.18 is added.
231
Measurement conditions of timing requirements are partly revised.
232
Measurement conditions of switching characteristics are partly revised.
233
Measurement conditions of switching characteristics are partly revised.
234
Measurement conditions of switching characteristics are partly revised.
235
Figure 1.26.2 is partly revised.
242
Figure 1.26.9 is partly revised.
244
Note of Table 1.26.28 is partly revised.
245
Figure 1.26.29 is partly revised.
246
Measurement conditions of timing requirements are partly revised.
Table 1.26.30 is partly revised.
247
Measurement conditions of timing requirements are partly revised.
247
Table 1.26.37 is added.
248
Measurement conditions of timing requirements are partly revised.
249
Measurement conditions of switching characteristics are partly revised.
250
Measurement conditions of switching characteristics are partly revised.
251
Measurement conditions of switching characteristics are partly revised.
252
Figure 1.26.12 is partly revised.
255
Figure 1.26.15 is partly revised.
256
Figure 1.26.16 is partly revised.
257
Figure 1.26.17 is partly revised.
258
Figure 1.26.18 is partly revised.
259
Figure 1.26.19 is partly revised.
260
Figure 1.26.20 is partly revised.
262
Explanation of “Memory Map” is partly revised.
263
Explanation of “Boot Mode” is partly revised.
264
Figure 1.27.3 is partly revised.
268
Note of FIDR Register in Figure 1.27.4 is partly revised.
C-3
REVISION HISTORY
Rev.
Date
M16C/62P Group (M16C/62P, M16C/62PT) Hardware Manual
Description
Page
Summary
271
Figure 1.27.7 is partly revised.
272
Explanation of “Interrupts” is partly revised.
Explanation of “Writing in the User ROM Space” is partly revised.
274
Table 1.27.4 is partly revised.
Explanation of “Read Array Command” is partly revised.
1.10
May 28, 2003
278
Explanation of “Program Command” is partly revised.
287
Figure 1.27.15 is partly revised.
293
Partly revised.
2
4-5
Table 1.1.1 is partly revised.
Table 1.1.2 and 1.1.3 is partly revised.
14-19 SFR is partly revised.
Note 1 is partly revised.
20
Explanation of “Hardware Reset 1” is partly revised.
23
Note 1 is added.
24
Figure 1.5.4 is partly revised.
Note 1 of Figure 1.5.5 is partly revised.
26
Figure 1.5.7 is partly revised.
27
Table 1.5.2 is partly revised.
Table 1.5.3 is partly revised.
Explanation of “1. Limitations on Stop Mode” is partly revised.
28
Explanation of “1. Limitations on WAIT instruction” is partly revised.
Figure 1.5.8 is partly revised.
31
Note is added.
33
Explanation of “Multiplexed Bus” is revised.
34
Explanation of “(2) Data Bus” is revised.
38
Explanation of “(7) Hold Signal” is revised.
Note 3 of Table 1.7.4 is added.
39
Note 4 of Table 1.7.5 is added.
40
Explanation of “(10) Software Wait” is revised.
41
Table 1.7.7 is revised.
46
Table of Figure 1.8.5 is revised.
47
Explanation is revised.
48-50 Figures 1.8.7 to 1.8.9 is partly revised.
51
Explanation of “Clock Generation Circuit” is revised.
52
Figure 1.9.1 is revised.
53
Note of Figure 1.9.2 is revised.
55
Note 12 is added.
58
Explanation of “(1) Main clock” is partly revised.
60
Explanation of “(4) PLL Clock” is partly revised.
C-4
REVISION HISTORY
Rev.
Date
M16C/62P Group (M16C/62P, M16C/62PT) Hardware Manual
Description
Page
Summary
63
Explanation of “Low power Dissipation Mode” is partly revised.
64
Explanation of “Entering Wait mode” is partly revised.
66
Explanation of “(3) Stop Mode” is partly revised.
69
Note 9 is added.
70
Table 1.9.7 is revised.
75
Figure 1.11.1 is revised.
79
Note 6 is added.
83
Note 2 is added to Figure 1.11.4.
84
Table 1.11.5 is partly revised.
85
Figure 1.11.6 is partly revised.
86
Figure 1.11.8 is partly revised.
89
Notes 1 to 2 is added to IFSR register of Figure 1.11.4.
91
Explanation of “Address Match Interrupt” is partly revised.
Figure 1. 11.12 is changed into Table 1.11.6.
93-94 Notes are deleted. (All notes are indicated in “M16C/62 GROUP (M16C/
62P) USAGE NOTES”).
93
Explanation of “Watchdog Timer” is partly revised.
94
A formula is added.
104
Explanation of “Channel Priority Transfer Timing” is partly revised.
109
TRGSR register of Figure 1.14.6 is partly revised.
116
Table 1.14.4 is partly revised.
117
Figure 1.14.12 is partly revised.
129
Figure 1.16.2 is partly revised.
130
Figure 1.16.3 is partly revised.
143
U0SMR to U2SMR of Figure 1.17.6 is partly revised.
144
U0SMR2 to U2SMR2 of Figure 1.17.7 is partly revised.
154,162, “−” of UiBRG of Tables 1.19.2, 1.20.2 and 1.20.8 is changed into “0 to 7”.
175
161
Figure 1.20.1 is partly revised.
164
Table 1.20.4 is partly revised. Notes 5 to 7 is added.
166
Explanation of “Output of Start and Stop Condition” is partly revised.
177
Note 2 is added to Table 1.20.9.
178
“−” of U2BRG of Table 1.20.10 is changed into “0 to 7”.
179
Figure 1.20.10 is revised.
183
Note of SiC register of Figure 1.21.2 is partly revised.
187
Note 2 of Table 1.22.1 is revised.
188
Figure 1.22.1 is partly revised.
190
Table of ADCON2 register of Figure 1.22.3 is partly revised.
202
The value of a capacitor of Figure 1.22.10 is changed.
C-5
REVISION HISTORY
Rev.
Date
M16C/62P Group (M16C/62P, M16C/62PT) Hardware Manual
Description
Page
Summary
202
Notes are deleted. (All notes are indicated in “M16C/62 GROUP (M16C/
62P) USAGE NOTES”).
208212
Note 1 of Figures 1.25.1 to 1.25.5 is partly revised.
218
Table 1.25.1 and 1.25.2 is revised.
219
Figure 1.25.12 is partly revised.
222
Table 1.26.3 is partly revised.
223
Table 1.26.5 is partly revised.
Table 1.26.6 is added.
224
Table 1.26.9 is partly revised.
230
Notes 1 and 2 in Table 1.26.26 is partly revised.
231
Notes 1 in Table 1.26.27 is partly revised.
230231
Note 3 is added to “Data output hold time (refers to BCLK)” in Table
1.26.26 and 1.26.27.
232
Note 4 is added to “th(ALE-AD)” in Table 1.26.28.
230232
Switching Characteristics is partly revised.
236239
th(WR-AD) and th(WR-DB) in Figure 1.26.5 to 1.5.8 is partly revised.
240241
th(ALE-AD), th(WR-CS), th(WR-DB) and th(WR-AD) in Figure 1.26.9 to
1.5.10 is partly revised.
242
Note 2 is added to Table 1.26.29.
247
Notes 1 and 2 in Table 1.26.45 is partly revised.
248
Notes 1 in Table 1.26.46 is partly revised.
247248
Note 3 is added to “Data output hold time(refers to BCLK)” in Table 1.26.45
and 1.26.46
249
Note 4 is added to “th(ALE-AD)” in Table 1.26.47.
247249
Switching Characteristics is partly revised.
253256
th(WR-AD) and th(WR-DB) in Figure 1.26.15 to 1.5.18 is partly revised.
257258
th(ALE-AD), th(WR-CS), th(WR-DB) and th(WR-AD) in Figure 1.26.19 to
1.5.20 is partly revised.
259
Table 1.27.1 is partly revised. Notes 3 and 4 is added.
260
Notes 1 and 2 is added to Table 1.27.2.
264
Note 2 is added to Table 1.27.3.
267
Notes 1 and 3 of FMR0 register of Table 1.27.4 is partly revised.
268
Figure 1.27.5 is partly revised. Note 2 is added.
270
Figure 1.27.7 is partly revised.
277
Figure 1.27.11 is partly revised.
281
Figure 1.27.12 is partly revised.
C-6
REVISION HISTORY
Rev.
Date
M16C/62P Group (M16C/62P, M16C/62PT) Hardware Manual
Description
Page
Summary
283
Table 1.27.7 is partly revised.
284286
Figures 1.27.13 to 1.27.15 is partly revised.
287288
Figures 1.27.16 and 1.27.17 is partly revised.
292293
Difference in Mask ROM Version and Flash Memory Version is revised.
294
Difference in Flash Memory Version is revised.
1.11
Jun 20, 2003
259
Number of program and erasure in Table 1.26.27 is partly revised.
1.20
Sep 11, 2003
94
Figure 1.12.2 is revised.
2.30
Sep 01, 2004
−
Since high reliability version is added, a group name is revised.
M16C/62P Group (M16C/62P) M16C/62P Group (M16C/62P, M16C/
62PT)
2-4
Table 1.1 to 1.3 are revised.
Note 3 is partly revised.
6
Figure 1.2 Note5 is deleted.
7-9
Table 1.4 to 1.7 Product List is partly revised.
11
Table 1.8 and Figure 1.4 are added.
12
Table 1.9 and Figure 1.5 are added.
13-16 Figure 1.6 to 1.9 ZP is added.
17
Table 1.10 and 1.13 ZP is added to timer A.
18, 20 Table 1.11 to 1.13 are revised.
19, 21 Table 1.12 to 1.14 are revised.
24
Figure 3.1 is partly revised.
Note 3 is added.
25
Note 6 is added.
30
After Reset of D/A register 0, 1 are revised.
31
5.2 Voltage Down Detection Reset (Hardware Reset 2) is revised.
32
Figure 5.1 is partly revised.
35
Figure 6.1 is partly revised.
36
Figure 6.2 is revised.
37
Figure 6.3 is revised.
39
Figure 6.4 is revised.
40
6.2 Limitations on Exiting Stop Mode and 6.3 Limitations on Exiting Wait
Mode are revised.
41
Note in 7. Processor is added.
44
Figure 7.2 is partly revised.
46
Note in 8. Bus is added.
8.1.2.2 When the input level on BYTE pin is low (16-bit data bus) is
revised.
C-7
REVISION HISTORY
Rev.
Date
M16C/62P Group (M16C/62P, M16C/62PT) Hardware Manual
Description
Page
Summary
46
Table 8.1 is added.
47
Note 2 in Figure 8.1 is revised.
50
Figure 8.4 is revised.
54
Table 8.8 is partly revised.
Note 5 is added.
57
Note in 9 Memory Space Expansion Function is added.
62-64 Figure 9.7 to 9.9 are revised.
79
Table 10.4 is partly revised.
81
Table 10.6 is partly revised.
82
Figure 10.10 is partly revised.
83
Note 6 in figure 10.11 is added.
88
Note in 11. Protect is added.
89
Note in 12. Interrupt is added.
108
Note 1 and 2 in figure 13.2 is revised.
109
13.2 Cold start / Warm start is added.
120
Note in 15. Timer is added.
121
Note in 15.1 Timer A is added.
126
Table 15.1 is partly revised.
127
Table 15.2 is partly revised.
131
15.1.2.1 Counter Initialization by Two-Phase Pulse Signal Processing is
partly revised.
137
Note in 15.2 Timer B is added.
140
Table 15.6 is partly revised.
144
Note in 16. Three-Phase Motor Control Timer Function is added.
146153
Figure 16.2 to 16.9 is revised.
154
Note in 17. Serial I/O is added.
Note in 17.1 UART1 is added.
155156
Figure 17.1 to 17.3 are revised.
160
Figure 17.7 is partly revised.
168
17.1.1.1 Counter Measure for Communication Error Occurs is added.
169
17.1.1.4 Continuous Receive Mode is revised.
171
17.1.1.7 CTS/RTS Function is added.
172
Note 3 in Table 17.5 is added.
176
17.1.2.1 Bit Rates is added.
177
17.1.2.2 Counter Measure for Communication Error Occurs is added.
179
17.1.2.6 CTS/RTS Function is added.
182
Note 2 in Table 17.11 is revised.
C-8
REVISION HISTORY
Rev.
Date
M16C/62P Group (M16C/62P, M16C/62PT) Hardware Manual
Description
Page
Summary
192
Note 2 in Table 17.16 is revised.
195
Note 2 in Table 17.17 is revised.
197
Note 3 in Table 17.18 is added.
202
Note in 17.2 SI/O3, SIO4 is added.
207
Table 18.1 is revised.
210
Figure 18.3 is partly revised.
222
18.2.6 Output Impedance of Sensor under A/D Conversion is added.
228
Note in 21. Programmable I/O Ports is added.
Table 21.1 is added.
229
21.3 Pull-up Control Register 0 to Pull-up Control Register 3 (PUR0 to
PUR3 Registers) is partly revised.
235
Note 3 in Figure 21.7 is partly revised.
236
Note 3 in Figure 21.8 is partly revised.
237
Note 2 in Figure 21.9 is partly revised.
240
Note 5 in Table 21.2 is added.
Note 7 in Table 21.3 is revised.
242273
Almost all pages are revised (22. Flash Memory Version).
274
Table 23.1 is revised.
275
Table 23.2 is revised.
276
Table 23.3 is revised.
Note 2 in Table 23.4 is added.
277
Table 23.5 to 23.6 is partly revised.
278
Table 23.8 is revised.
Table 23.9 is revised.
279
Table 23.10 is revised.
280
Table 23.11 is revised.
281
Table 23.13 is partly revised.
283
Table 23.24 is partly revised.
284
Figure 23.2 is partly revised.
Table 23.26 is partly revised.
285
Table 23.27 is partly revised.
286
Table 23.28 is partly revised.
287
Figure 23.3 is partly revised.
290291
Figure 23.6 to 23.7 is partly revised.
292293
Figure 23.8 to 23.9 is partly revised.
295
Figure 23.11 is Figure 23.6 to 23.7 is partly revised.
296
Table 23.29 is revised.
C-9
REVISION HISTORY
Rev.
Date
M16C/62P Group (M16C/62P, M16C/62PT) Hardware Manual
Description
Page
Summary
297
Table 23.30 is revised.
298
Table 23.32 is partly revised.
300
Table 23.43 is partly revised.
301
Figure 23.12 is partly revised.
Table 23.45 is partly revised.
2.40
Dec 15, 2005
302
Table 23.46 is partly revised.
303
Table 23.47 is partly revised.
304
Figure 23.13 is partly revised.
307308
Figure 23.16 to 23.17 is partly revised.
309310
Figure 23.18 to 23.19 is partly revised.
313339
23.2 Electrical Characteristics (M16C/62PT) is added.
340
24.1 Reset is added.
341
24.2 External Bus is partly revised.
342
Figure 24.2 is added.
343
24.4 Power Control is partly revised.
346
24.9.2.1 Special Mode (I2C mode) is added.
347
24.9.3 SI/O3, SI/O4 is added.
348349
24.10 A/D Converter is partly revised.
352
24.13 Mask ROM Version is added.
356
24.15 Noise is added.
357
25. Differences Depending on Manufacturing Period is a
2-4
voltage down detection reset -> brown-out detection Reset
Tables 1.1 to 1.3 Performance outline of M16C/62P group are partly
revised.
7
Table 1.4 Product List (1) is partly revised.
Note 1 is added.
8
Table 1.5 Product List (2) is partly revised.
Note 1 and 2 are added.
9
Table 1.6 Product List (3) is partly revised.
Note 1 and 2 are added.
10
Table 1.7 Product List (4) is partly revised.
Note 1 and 2 are added.
11
Figure 1.3 Type No., Memory Size, and Package is partly revised
12
Table 1.8 Product Code of Flash Memory version and ROMless version for
M16C/62P is partly revised.
13
Table 1.9 Product Code of Flash Memory version for M16C/62P is partly
revised.
C - 10
REVISION HISTORY
Rev.
Date
M16C/62P Group (M16C/62P, M16C/62PT) Hardware Manual
Description
Page
14
Summary
Figure 1.6 Pin Configuration (Top View) is partly revised.
15-17 Tables 1.10 to 1.12 Pin Characteristics for 128-Pin Package are added.
18-19 Figure 1.7 and 1.8 Pin Configuration (Top View) are partly revised.
20-21 Tables 1.13 to 1.14 Pin Characteristics for 100-Pin Package are added.
22
Figure 1.9 Pin Configuration (Top View) is partly revised.
23-24 Tables 1.15 to 1.16 Pin Characteristics for 80-Pin Package are added.
25-29 Tables 1.17 to 1.21 are partly revised.
34
Note 4 of Table 4.1 SFR Information is partly revised.
40-44 Change sections in Chapter 5.
42
5.2 Brown-out Detection Reset (Hardware Reset 2) is partly revised.
45
6. Voltage Detection Circuit is partly revised.
Figure 6.1 Voltage Detection Circuit Block is partly revised.
48
Figure 6.4 Typical Operation of Brown-out Detection Reset (Hardware
Reset 2) is partly revised.
49
Table 6.2 Sampling Periods is partly revised.
52-53 6.4 Cold Start-up / Warm Start-up Determine Function is added.
57
Note 7 of Figure 7.2 PM1 Register is partly revised.
64
8.2.6 RDY Signal is partly revised.
69
Table 8.8 Bit and Bus Cycle Related to Software
80
Figure 9.8 Relationship Between Address on 4-Mbyte ROM and Those on
Microcomputer (2) is partly revised.
89
Figure 10.7 Examples of Main Clock Connection Circuit is partly revised.
90
Figure 10.8 Examples of Sub Clock Connection Circuit is partly revised.
91
10.1.4 PLL Clock is partly revised.
94
10.4.1.6 On-chip Oscillator Mode is partly revised.
95
10.4.1.7 On-chip Oscillator Low Power Dissipation Mode is partly revised.
96
Table 10.4 Pin Status During Wait Mode is partly revised.
97
10.4.2.4 Exiting Wait Mode is partly revised.
98
10.4.3 Stop Mode is partly revised.
Table 10.6 Interrupts to Stop Mode and Use Conditions is added.
99
10.4.3.3 Exiting Stop Mode is partly revised.
100
Figure 10.11 State Transition in Normal Operating Mode is partly revised.
104
10.6.3 How to Use Oscillation Stop and Re-oscillation Detect Function is
partly revised.
107
12.2.2 Overflow Interrupt is partly revised.
118
12.5.8 Returning from an Interrupt Routine is partly revised.
12.5.9 Interrupt Priority is partly revised.
119
120
12.5.10 Interrupt Priority Level Select Circuit is partly revised.
Figure 12.11 IFSR and IFSR2A Registers (Interrupt Factor Select
Register) is partly revised.
C - 11
REVISION HISTORY
Rev.
Date
M16C/62P Group (M16C/62P, M16C/62PT) Hardware Manual
Description
Page
Summary
125
13.1 Cold Start / Warm Start moved to 5. Reset.
127
Table 14.1 DMAC Specifications is partly revised.
132
14.1.3 Effect of Software Wait is partly revised.
165
Table 16.1 Three-phase Motor Control Timer Functions Specifications is
partly revised.
167
Notes 5 and 7 of Figure 16.2 INVC0 Register are partly revised.
177179
Figures 17.1 to 17.3 UART Block Diagram are partly revised.
181
Note 3 of Figure 17.5 UiRB Register is added.
186
Figure 17.10 UCON and UiSMR Registers
Notes 3 is revised.
188
Table 17.1 Clock Synchronous Serial I/O Mode Specifications is partly
revised.
Note 2 is partly revised.
192
Figure 17.13 Transmit and Receive Operation is revised.
193
17.1.1.1 Counter Measure for Communication Error Occurs is partly
revised.
197
Table 17.5 UART Mode Specifications is partly revised.
Note 1 is partly revised
200
Figure 17.19 Transmit Operation is revised.
201
17.1.2.1 Bit Rate is partly revised.
Table 17.9 Example of Bit Rates and Settings is partly revised.
202
17.1.2.2 Counter Measure for Communication Error Occurs is partly
revised.
205
Table 17.10 I2C Mode Specifications is partly revised.
207
Note 4 of Table 17.11 Registers to Be Used and Settings in I2C Mode (1)
is added.
215
Table 17.15 Special Mode Specifications is partly revised.
222
Table 17.18 SIM Mode Specifications is partly revised.
224
Figure 17.34 Transmit and Receive Timing in SIM Mode is partly revised.
226
17.1.6.2 Format is partly revised.
230
Table 17.20 SI/O3 and SI/O4 Specifications is partly revised.
231
Figure 17.41 SI/Oi Operation Timing is partly revised.
Figure 17.42 Polarity of Transfer Clock is partly revised.
232
17.2.3 Functions for Settings an SOUTi Internal Value is partly revised.
249
18.2.6 Output Impedance of Sensor under A/D Conversion is partly
revised.
250
Figure 18.11 Analog Input Pin and External Sensor Equivalent Circuit is
partly revised.
251
Table 19.1 D/A Converter Performance is partly revised.
C - 12
REVISION HISTORY
Rev.
Date
M16C/62P Group (M16C/62P, M16C/62PT) Hardware Manual
Description
Page
252
Summary
Figure 19.2 DA0 and DA1 Register is partly revised.
Note 2 of Figure 19.3 D/A Converter is added.
254
Figure 20.3 CRC Calculation is partly revised.
261
Note 2 of Figure 21.6 I/O Pin is deleted.
270
Table 22.1 Flash Memory Version Specifications is partly revised.
274
Figure 22.2 ROMCP Register is partly revised.
275
Note 1 of Table 22.3 EM0 Mode and EW1 Mode is partly revised.
276
22.3.2 EW1 Mode is partly revised.
279
22.3.3.4 FMSTP Bit is partly revised.
283
Figure 22.9 Processing Before and After Low Power Dissipation mode is
partly revised.
285
22.3.4.12 Low-Power Consumption Mode and On-chip Oscillator Lowpower Consumption Mode is partly revised.
288
22.3.5.5 Block Erase Command is partly revised.
Figure 22.11 Block Erase Command is partly revised.
292
Table 22.5 Status Register is partly revised.
294
Figure 22.14 Full Status Check and Handling Procedure for Each Error is
partly revised.
297
Table 22.7 Pin Functions (Flash Memory Standard Serial I/O Mode) is
partly revised.
Note 2 is partly revised.
Note 3 is added.
297300
Figures 22.15 to 22.18 are partly revised.
301
Figure 22.19 Circuit Application in Standard I/O Mode 1 is partly revised.
302
Figure 22.20 Circuit Application in Standard I/O Mode 2 is partly revised.
307
Table 23.4 A/D Conversion Characteristics is partly revised.
309
Table 23.6 Flash Memory Version Electrical Characteristics for 100 cycle
products is partly revised.
Table 23.7 Flash Memory Version Electrical Characteristics for 10,000
cycle products is partly revised.
Table 23.8 Flash Memory Version Program / Erase Voltage and Read
Operation Voltage Characteristics is partly revised.
310
Table 23.9 Low Voltage Detection Circuit Electrical Characteristics is
partly revised.
311
Figure 23.1 Power Supply Circuit Timing Diagram is partly revised.
313
Table 23.12 Electrical Characteristics (2) is partly revised.
314
Note 1 of Table 23.13 External Clock Input (XIN input) is added.
331
Notes 1 to 4 of Table 23.32 External Clock Input (XIN input) are added.
349
Table 23.53 Flash Memory Version Electrical Characteristics for 100 cycle
products is partly revised. Standard (Min.) is partly revised.
C - 13
REVISION HISTORY
Rev.
Date
M16C/62P Group (M16C/62P, M16C/62PT) Hardware Manual
Description
Page
349
Summary
Table 23.54 Flash Memory Version Electrical Characteristics for 10,000
cycle products is partly revised. Standard (Min.) is partly revised.
Note 5 is revised.
Table 23.55 Flash Memory Version Program / Erase Voltage and Read
Operation Voltage Characteristics is partly revised.
2.41
Jan 10, 2006
352
359
Table 23.58 Electrical Characteristics is partly revised.
24.1 SFR and 24.1.1 Register Settings, Table 24.1 Registers with Writeonly Bits are added.
360
363
Figure 24.1 Timing of SVCC is revised.
24.5 Power Control is revised.
375
Figure 24.4 Use of Capacitors to Reduce Noise is partly revised.
375
24.11 A/D Converter is partly revised.
377
24.12 Programable I/O Ports is partly revised.
379
24.15.2 Stop mode is partly revised.
380
24.15.8 Operation speed is partly revised.
381
24.15.14 Regarding Programming/Erasing Endurance and Execution
Time is partly revised. (Title change.)
383
Table 25.1 Technical Update Applicable of M16C/62P Flash and ROM
External Versions is partly revised.
-
voltage down detection -> low voltage detection
99
Figure 10.10 State Transition to Stop Mode and Wait Mode is partly revised.
100
Figure 10.11 State Transition in Normal Operating Mode is partly revised.
132
14.1.3 Effect of Software Wait is partly revised.
186
Figure 17.10 UCON and UiSMR Registers
Notes 4 is added. Bit3(LSYN) is added.
252
Figure 19.3 D/A Converter Equivalent Circuit is partly revised.
C - 14
M16C/62P Group (M16C/62P, M16C/62PT) Hardware Manual
Publication Date :
Rev.2.41
Jan 10, 2006
Published by : Sales Strategic Planning Div.
Renesas Technology Corp.
© 2006. Renesas Technology Corp., All rights reserved. Printed in Japan
M16C/62P Group (M16C/62P, M16C/62PT)
Hardware Manual
2-6-2, Ote-machi, Chiyoda-ku, Tokyo, 100-0004, Japan